| 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
| 2 | |
| 3 | Copyright (C) 1988-2015 Free Software Foundation, Inc. |
| 4 | |
| 5 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
| 6 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. |
| 7 | |
| 8 | This file is part of GDB. |
| 9 | |
| 10 | This program is free software; you can redistribute it and/or modify |
| 11 | it under the terms of the GNU General Public License as published by |
| 12 | the Free Software Foundation; either version 3 of the License, or |
| 13 | (at your option) any later version. |
| 14 | |
| 15 | This program is distributed in the hope that it will be useful, |
| 16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | GNU General Public License for more details. |
| 19 | |
| 20 | You should have received a copy of the GNU General Public License |
| 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 22 | |
| 23 | #include "defs.h" |
| 24 | #include "frame.h" |
| 25 | #include "inferior.h" |
| 26 | #include "symtab.h" |
| 27 | #include "value.h" |
| 28 | #include "gdbcmd.h" |
| 29 | #include "language.h" |
| 30 | #include "gdbcore.h" |
| 31 | #include "symfile.h" |
| 32 | #include "objfiles.h" |
| 33 | #include "gdbtypes.h" |
| 34 | #include "target.h" |
| 35 | #include "arch-utils.h" |
| 36 | #include "regcache.h" |
| 37 | #include "osabi.h" |
| 38 | #include "mips-tdep.h" |
| 39 | #include "block.h" |
| 40 | #include "reggroups.h" |
| 41 | #include "opcode/mips.h" |
| 42 | #include "elf/mips.h" |
| 43 | #include "elf-bfd.h" |
| 44 | #include "symcat.h" |
| 45 | #include "sim-regno.h" |
| 46 | #include "dis-asm.h" |
| 47 | #include "frame-unwind.h" |
| 48 | #include "frame-base.h" |
| 49 | #include "trad-frame.h" |
| 50 | #include "infcall.h" |
| 51 | #include "floatformat.h" |
| 52 | #include "remote.h" |
| 53 | #include "target-descriptions.h" |
| 54 | #include "dwarf2-frame.h" |
| 55 | #include "user-regs.h" |
| 56 | #include "valprint.h" |
| 57 | #include "ax.h" |
| 58 | |
| 59 | static const struct objfile_data *mips_pdr_data; |
| 60 | |
| 61 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
| 62 | |
| 63 | static int mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, |
| 64 | ULONGEST inst); |
| 65 | static int micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32); |
| 66 | static int mips16_instruction_has_delay_slot (unsigned short inst, |
| 67 | int mustbe32); |
| 68 | |
| 69 | static int mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, |
| 70 | CORE_ADDR addr); |
| 71 | static int micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, |
| 72 | CORE_ADDR addr, int mustbe32); |
| 73 | static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, |
| 74 | CORE_ADDR addr, int mustbe32); |
| 75 | |
| 76 | static void mips_print_float_info (struct gdbarch *, struct ui_file *, |
| 77 | struct frame_info *, const char *); |
| 78 | |
| 79 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
| 80 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
| 81 | #define ST0_FR (1 << 26) |
| 82 | |
| 83 | /* The sizes of floating point registers. */ |
| 84 | |
| 85 | enum |
| 86 | { |
| 87 | MIPS_FPU_SINGLE_REGSIZE = 4, |
| 88 | MIPS_FPU_DOUBLE_REGSIZE = 8 |
| 89 | }; |
| 90 | |
| 91 | enum |
| 92 | { |
| 93 | MIPS32_REGSIZE = 4, |
| 94 | MIPS64_REGSIZE = 8 |
| 95 | }; |
| 96 | |
| 97 | static const char *mips_abi_string; |
| 98 | |
| 99 | static const char *const mips_abi_strings[] = { |
| 100 | "auto", |
| 101 | "n32", |
| 102 | "o32", |
| 103 | "n64", |
| 104 | "o64", |
| 105 | "eabi32", |
| 106 | "eabi64", |
| 107 | NULL |
| 108 | }; |
| 109 | |
| 110 | /* For backwards compatibility we default to MIPS16. This flag is |
| 111 | overridden as soon as unambiguous ELF file flags tell us the |
| 112 | compressed ISA encoding used. */ |
| 113 | static const char mips_compression_mips16[] = "mips16"; |
| 114 | static const char mips_compression_micromips[] = "micromips"; |
| 115 | static const char *const mips_compression_strings[] = |
| 116 | { |
| 117 | mips_compression_mips16, |
| 118 | mips_compression_micromips, |
| 119 | NULL |
| 120 | }; |
| 121 | |
| 122 | static const char *mips_compression_string = mips_compression_mips16; |
| 123 | |
| 124 | /* The standard register names, and all the valid aliases for them. */ |
| 125 | struct register_alias |
| 126 | { |
| 127 | const char *name; |
| 128 | int regnum; |
| 129 | }; |
| 130 | |
| 131 | /* Aliases for o32 and most other ABIs. */ |
| 132 | const struct register_alias mips_o32_aliases[] = { |
| 133 | { "ta0", 12 }, |
| 134 | { "ta1", 13 }, |
| 135 | { "ta2", 14 }, |
| 136 | { "ta3", 15 } |
| 137 | }; |
| 138 | |
| 139 | /* Aliases for n32 and n64. */ |
| 140 | const struct register_alias mips_n32_n64_aliases[] = { |
| 141 | { "ta0", 8 }, |
| 142 | { "ta1", 9 }, |
| 143 | { "ta2", 10 }, |
| 144 | { "ta3", 11 } |
| 145 | }; |
| 146 | |
| 147 | /* Aliases for ABI-independent registers. */ |
| 148 | const struct register_alias mips_register_aliases[] = { |
| 149 | /* The architecture manuals specify these ABI-independent names for |
| 150 | the GPRs. */ |
| 151 | #define R(n) { "r" #n, n } |
| 152 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), |
| 153 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), |
| 154 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), |
| 155 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), |
| 156 | #undef R |
| 157 | |
| 158 | /* k0 and k1 are sometimes called these instead (for "kernel |
| 159 | temp"). */ |
| 160 | { "kt0", 26 }, |
| 161 | { "kt1", 27 }, |
| 162 | |
| 163 | /* This is the traditional GDB name for the CP0 status register. */ |
| 164 | { "sr", MIPS_PS_REGNUM }, |
| 165 | |
| 166 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ |
| 167 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, |
| 168 | |
| 169 | /* This is the traditional GDB name for the FCSR. */ |
| 170 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } |
| 171 | }; |
| 172 | |
| 173 | const struct register_alias mips_numeric_register_aliases[] = { |
| 174 | #define R(n) { #n, n } |
| 175 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), |
| 176 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), |
| 177 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), |
| 178 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), |
| 179 | #undef R |
| 180 | }; |
| 181 | |
| 182 | #ifndef MIPS_DEFAULT_FPU_TYPE |
| 183 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE |
| 184 | #endif |
| 185 | static int mips_fpu_type_auto = 1; |
| 186 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; |
| 187 | |
| 188 | static unsigned int mips_debug = 0; |
| 189 | |
| 190 | /* Properties (for struct target_desc) describing the g/G packet |
| 191 | layout. */ |
| 192 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" |
| 193 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" |
| 194 | |
| 195 | struct target_desc *mips_tdesc_gp32; |
| 196 | struct target_desc *mips_tdesc_gp64; |
| 197 | |
| 198 | const struct mips_regnum * |
| 199 | mips_regnum (struct gdbarch *gdbarch) |
| 200 | { |
| 201 | return gdbarch_tdep (gdbarch)->regnum; |
| 202 | } |
| 203 | |
| 204 | static int |
| 205 | mips_fpa0_regnum (struct gdbarch *gdbarch) |
| 206 | { |
| 207 | return mips_regnum (gdbarch)->fp0 + 12; |
| 208 | } |
| 209 | |
| 210 | /* Return 1 if REGNUM refers to a floating-point general register, raw |
| 211 | or cooked. Otherwise return 0. */ |
| 212 | |
| 213 | static int |
| 214 | mips_float_register_p (struct gdbarch *gdbarch, int regnum) |
| 215 | { |
| 216 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
| 217 | |
| 218 | return (rawnum >= mips_regnum (gdbarch)->fp0 |
| 219 | && rawnum < mips_regnum (gdbarch)->fp0 + 32); |
| 220 | } |
| 221 | |
| 222 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
| 223 | == MIPS_ABI_EABI32 \ |
| 224 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) |
| 225 | |
| 226 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ |
| 227 | (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) |
| 228 | |
| 229 | #define MIPS_LAST_ARG_REGNUM(gdbarch) \ |
| 230 | (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) |
| 231 | |
| 232 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
| 233 | |
| 234 | /* Return the MIPS ABI associated with GDBARCH. */ |
| 235 | enum mips_abi |
| 236 | mips_abi (struct gdbarch *gdbarch) |
| 237 | { |
| 238 | return gdbarch_tdep (gdbarch)->mips_abi; |
| 239 | } |
| 240 | |
| 241 | int |
| 242 | mips_isa_regsize (struct gdbarch *gdbarch) |
| 243 | { |
| 244 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 245 | |
| 246 | /* If we know how big the registers are, use that size. */ |
| 247 | if (tdep->register_size_valid_p) |
| 248 | return tdep->register_size; |
| 249 | |
| 250 | /* Fall back to the previous behavior. */ |
| 251 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
| 252 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); |
| 253 | } |
| 254 | |
| 255 | /* Return the currently configured (or set) saved register size. */ |
| 256 | |
| 257 | unsigned int |
| 258 | mips_abi_regsize (struct gdbarch *gdbarch) |
| 259 | { |
| 260 | switch (mips_abi (gdbarch)) |
| 261 | { |
| 262 | case MIPS_ABI_EABI32: |
| 263 | case MIPS_ABI_O32: |
| 264 | return 4; |
| 265 | case MIPS_ABI_N32: |
| 266 | case MIPS_ABI_N64: |
| 267 | case MIPS_ABI_O64: |
| 268 | case MIPS_ABI_EABI64: |
| 269 | return 8; |
| 270 | case MIPS_ABI_UNKNOWN: |
| 271 | case MIPS_ABI_LAST: |
| 272 | default: |
| 273 | internal_error (__FILE__, __LINE__, _("bad switch")); |
| 274 | } |
| 275 | } |
| 276 | |
| 277 | /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here |
| 278 | are some functions to handle addresses associated with compressed |
| 279 | code including but not limited to testing, setting, or clearing |
| 280 | bit 0 of such addresses. */ |
| 281 | |
| 282 | /* Return one iff compressed code is the MIPS16 instruction set. */ |
| 283 | |
| 284 | static int |
| 285 | is_mips16_isa (struct gdbarch *gdbarch) |
| 286 | { |
| 287 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16; |
| 288 | } |
| 289 | |
| 290 | /* Return one iff compressed code is the microMIPS instruction set. */ |
| 291 | |
| 292 | static int |
| 293 | is_micromips_isa (struct gdbarch *gdbarch) |
| 294 | { |
| 295 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS; |
| 296 | } |
| 297 | |
| 298 | /* Return one iff ADDR denotes compressed code. */ |
| 299 | |
| 300 | static int |
| 301 | is_compact_addr (CORE_ADDR addr) |
| 302 | { |
| 303 | return ((addr) & 1); |
| 304 | } |
| 305 | |
| 306 | /* Return one iff ADDR denotes standard ISA code. */ |
| 307 | |
| 308 | static int |
| 309 | is_mips_addr (CORE_ADDR addr) |
| 310 | { |
| 311 | return !is_compact_addr (addr); |
| 312 | } |
| 313 | |
| 314 | /* Return one iff ADDR denotes MIPS16 code. */ |
| 315 | |
| 316 | static int |
| 317 | is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 318 | { |
| 319 | return is_compact_addr (addr) && is_mips16_isa (gdbarch); |
| 320 | } |
| 321 | |
| 322 | /* Return one iff ADDR denotes microMIPS code. */ |
| 323 | |
| 324 | static int |
| 325 | is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 326 | { |
| 327 | return is_compact_addr (addr) && is_micromips_isa (gdbarch); |
| 328 | } |
| 329 | |
| 330 | /* Strip the ISA (compression) bit off from ADDR. */ |
| 331 | |
| 332 | static CORE_ADDR |
| 333 | unmake_compact_addr (CORE_ADDR addr) |
| 334 | { |
| 335 | return ((addr) & ~(CORE_ADDR) 1); |
| 336 | } |
| 337 | |
| 338 | /* Add the ISA (compression) bit to ADDR. */ |
| 339 | |
| 340 | static CORE_ADDR |
| 341 | make_compact_addr (CORE_ADDR addr) |
| 342 | { |
| 343 | return ((addr) | (CORE_ADDR) 1); |
| 344 | } |
| 345 | |
| 346 | /* Extern version of unmake_compact_addr; we use a separate function |
| 347 | so that unmake_compact_addr can be inlined throughout this file. */ |
| 348 | |
| 349 | CORE_ADDR |
| 350 | mips_unmake_compact_addr (CORE_ADDR addr) |
| 351 | { |
| 352 | return unmake_compact_addr (addr); |
| 353 | } |
| 354 | |
| 355 | /* Functions for setting and testing a bit in a minimal symbol that |
| 356 | marks it as MIPS16 or microMIPS function. The MSB of the minimal |
| 357 | symbol's "info" field is used for this purpose. |
| 358 | |
| 359 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is |
| 360 | "special", i.e. refers to a MIPS16 or microMIPS function, and sets |
| 361 | one of the "special" bits in a minimal symbol to mark it accordingly. |
| 362 | The test checks an ELF-private flag that is valid for true function |
| 363 | symbols only; for synthetic symbols such as for PLT stubs that have |
| 364 | no ELF-private part at all the MIPS BFD backend arranges for this |
| 365 | information to be carried in the asymbol's udata field instead. |
| 366 | |
| 367 | msymbol_is_mips16 and msymbol_is_micromips test the "special" bit |
| 368 | in a minimal symbol. */ |
| 369 | |
| 370 | static void |
| 371 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
| 372 | { |
| 373 | elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
| 374 | unsigned char st_other; |
| 375 | |
| 376 | if ((sym->flags & BSF_SYNTHETIC) == 0) |
| 377 | st_other = elfsym->internal_elf_sym.st_other; |
| 378 | else if ((sym->flags & BSF_FUNCTION) != 0) |
| 379 | st_other = sym->udata.i; |
| 380 | else |
| 381 | return; |
| 382 | |
| 383 | if (ELF_ST_IS_MICROMIPS (st_other)) |
| 384 | { |
| 385 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym) = 1; |
| 386 | SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1); |
| 387 | } |
| 388 | else if (ELF_ST_IS_MIPS16 (st_other)) |
| 389 | { |
| 390 | MSYMBOL_TARGET_FLAG_MIPS16 (msym) = 1; |
| 391 | SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1); |
| 392 | } |
| 393 | } |
| 394 | |
| 395 | /* Return one iff MSYM refers to standard ISA code. */ |
| 396 | |
| 397 | static int |
| 398 | msymbol_is_mips (struct minimal_symbol *msym) |
| 399 | { |
| 400 | return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym) |
| 401 | | MSYMBOL_TARGET_FLAG_MICROMIPS (msym)); |
| 402 | } |
| 403 | |
| 404 | /* Return one iff MSYM refers to MIPS16 code. */ |
| 405 | |
| 406 | static int |
| 407 | msymbol_is_mips16 (struct minimal_symbol *msym) |
| 408 | { |
| 409 | return MSYMBOL_TARGET_FLAG_MIPS16 (msym); |
| 410 | } |
| 411 | |
| 412 | /* Return one iff MSYM refers to microMIPS code. */ |
| 413 | |
| 414 | static int |
| 415 | msymbol_is_micromips (struct minimal_symbol *msym) |
| 416 | { |
| 417 | return MSYMBOL_TARGET_FLAG_MICROMIPS (msym); |
| 418 | } |
| 419 | |
| 420 | /* Set the ISA bit in the main symbol too, complementing the corresponding |
| 421 | minimal symbol setting and reflecting the run-time value of the symbol. |
| 422 | The need for comes from the ISA bit having been cleared as code in |
| 423 | `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's |
| 424 | `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values |
| 425 | of symbols referring to compressed code different in GDB to the values |
| 426 | used by actual code. That in turn makes them evaluate incorrectly in |
| 427 | expressions, producing results different to what the same expressions |
| 428 | yield when compiled into the program being debugged. */ |
| 429 | |
| 430 | static void |
| 431 | mips_make_symbol_special (struct symbol *sym, struct objfile *objfile) |
| 432 | { |
| 433 | if (SYMBOL_CLASS (sym) == LOC_BLOCK) |
| 434 | { |
| 435 | /* We are in symbol reading so it is OK to cast away constness. */ |
| 436 | struct block *block = (struct block *) SYMBOL_BLOCK_VALUE (sym); |
| 437 | CORE_ADDR compact_block_start; |
| 438 | struct bound_minimal_symbol msym; |
| 439 | |
| 440 | compact_block_start = BLOCK_START (block) | 1; |
| 441 | msym = lookup_minimal_symbol_by_pc (compact_block_start); |
| 442 | if (msym.minsym && !msymbol_is_mips (msym.minsym)) |
| 443 | { |
| 444 | BLOCK_START (block) = compact_block_start; |
| 445 | } |
| 446 | } |
| 447 | } |
| 448 | |
| 449 | /* XFER a value from the big/little/left end of the register. |
| 450 | Depending on the size of the value it might occupy the entire |
| 451 | register or just part of it. Make an allowance for this, aligning |
| 452 | things accordingly. */ |
| 453 | |
| 454 | static void |
| 455 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
| 456 | int reg_num, int length, |
| 457 | enum bfd_endian endian, gdb_byte *in, |
| 458 | const gdb_byte *out, int buf_offset) |
| 459 | { |
| 460 | int reg_offset = 0; |
| 461 | |
| 462 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); |
| 463 | /* Need to transfer the left or right part of the register, based on |
| 464 | the targets byte order. */ |
| 465 | switch (endian) |
| 466 | { |
| 467 | case BFD_ENDIAN_BIG: |
| 468 | reg_offset = register_size (gdbarch, reg_num) - length; |
| 469 | break; |
| 470 | case BFD_ENDIAN_LITTLE: |
| 471 | reg_offset = 0; |
| 472 | break; |
| 473 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
| 474 | reg_offset = 0; |
| 475 | break; |
| 476 | default: |
| 477 | internal_error (__FILE__, __LINE__, _("bad switch")); |
| 478 | } |
| 479 | if (mips_debug) |
| 480 | fprintf_unfiltered (gdb_stderr, |
| 481 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", |
| 482 | reg_num, reg_offset, buf_offset, length); |
| 483 | if (mips_debug && out != NULL) |
| 484 | { |
| 485 | int i; |
| 486 | fprintf_unfiltered (gdb_stdlog, "out "); |
| 487 | for (i = 0; i < length; i++) |
| 488 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
| 489 | } |
| 490 | if (in != NULL) |
| 491 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
| 492 | in + buf_offset); |
| 493 | if (out != NULL) |
| 494 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
| 495 | out + buf_offset); |
| 496 | if (mips_debug && in != NULL) |
| 497 | { |
| 498 | int i; |
| 499 | fprintf_unfiltered (gdb_stdlog, "in "); |
| 500 | for (i = 0; i < length; i++) |
| 501 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
| 502 | } |
| 503 | if (mips_debug) |
| 504 | fprintf_unfiltered (gdb_stdlog, "\n"); |
| 505 | } |
| 506 | |
| 507 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
| 508 | compatiblity mode. A return value of 1 means that we have |
| 509 | physical 64-bit registers, but should treat them as 32-bit registers. */ |
| 510 | |
| 511 | static int |
| 512 | mips2_fp_compat (struct frame_info *frame) |
| 513 | { |
| 514 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 515 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
| 516 | meaningful. */ |
| 517 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
| 518 | return 0; |
| 519 | |
| 520 | #if 0 |
| 521 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, |
| 522 | in all the places we deal with FP registers. PR gdb/413. */ |
| 523 | /* Otherwise check the FR bit in the status register - it controls |
| 524 | the FP compatiblity mode. If it is clear we are in compatibility |
| 525 | mode. */ |
| 526 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
| 527 | return 1; |
| 528 | #endif |
| 529 | |
| 530 | return 0; |
| 531 | } |
| 532 | |
| 533 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
| 534 | |
| 535 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
| 536 | |
| 537 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
| 538 | |
| 539 | /* The list of available "set mips " and "show mips " commands. */ |
| 540 | |
| 541 | static struct cmd_list_element *setmipscmdlist = NULL; |
| 542 | static struct cmd_list_element *showmipscmdlist = NULL; |
| 543 | |
| 544 | /* Integer registers 0 thru 31 are handled explicitly by |
| 545 | mips_register_name(). Processor specific registers 32 and above |
| 546 | are listed in the following tables. */ |
| 547 | |
| 548 | enum |
| 549 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; |
| 550 | |
| 551 | /* Generic MIPS. */ |
| 552 | |
| 553 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
| 554 | "sr", "lo", "hi", "bad", "cause", "pc", |
| 555 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 556 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 557 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 558 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 559 | "fsr", "fir", |
| 560 | }; |
| 561 | |
| 562 | /* Names of IDT R3041 registers. */ |
| 563 | |
| 564 | static const char *mips_r3041_reg_names[] = { |
| 565 | "sr", "lo", "hi", "bad", "cause", "pc", |
| 566 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 567 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 568 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 569 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 570 | "fsr", "fir", "", /*"fp" */ "", |
| 571 | "", "", "bus", "ccfg", "", "", "", "", |
| 572 | "", "", "port", "cmp", "", "", "epc", "prid", |
| 573 | }; |
| 574 | |
| 575 | /* Names of tx39 registers. */ |
| 576 | |
| 577 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
| 578 | "sr", "lo", "hi", "bad", "cause", "pc", |
| 579 | "", "", "", "", "", "", "", "", |
| 580 | "", "", "", "", "", "", "", "", |
| 581 | "", "", "", "", "", "", "", "", |
| 582 | "", "", "", "", "", "", "", "", |
| 583 | "", "", "", "", |
| 584 | "", "", "", "", "", "", "", "", |
| 585 | "", "", "config", "cache", "debug", "depc", "epc", |
| 586 | }; |
| 587 | |
| 588 | /* Names of IRIX registers. */ |
| 589 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
| 590 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 591 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 592 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 593 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 594 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" |
| 595 | }; |
| 596 | |
| 597 | /* Names of registers with Linux kernels. */ |
| 598 | static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
| 599 | "sr", "lo", "hi", "bad", "cause", "pc", |
| 600 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 601 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 602 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 603 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 604 | "fsr", "fir" |
| 605 | }; |
| 606 | |
| 607 | |
| 608 | /* Return the name of the register corresponding to REGNO. */ |
| 609 | static const char * |
| 610 | mips_register_name (struct gdbarch *gdbarch, int regno) |
| 611 | { |
| 612 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 613 | /* GPR names for all ABIs other than n32/n64. */ |
| 614 | static char *mips_gpr_names[] = { |
| 615 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
| 616 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", |
| 617 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
| 618 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", |
| 619 | }; |
| 620 | |
| 621 | /* GPR names for n32 and n64 ABIs. */ |
| 622 | static char *mips_n32_n64_gpr_names[] = { |
| 623 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
| 624 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", |
| 625 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
| 626 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" |
| 627 | }; |
| 628 | |
| 629 | enum mips_abi abi = mips_abi (gdbarch); |
| 630 | |
| 631 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
| 632 | but then don't make the raw register names visible. This (upper) |
| 633 | range of user visible register numbers are the pseudo-registers. |
| 634 | |
| 635 | This approach was adopted accommodate the following scenario: |
| 636 | It is possible to debug a 64-bit device using a 32-bit |
| 637 | programming model. In such instances, the raw registers are |
| 638 | configured to be 64-bits wide, while the pseudo registers are |
| 639 | configured to be 32-bits wide. The registers that the user |
| 640 | sees - the pseudo registers - match the users expectations |
| 641 | given the programming model being used. */ |
| 642 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
| 643 | if (regno < gdbarch_num_regs (gdbarch)) |
| 644 | return ""; |
| 645 | |
| 646 | /* The MIPS integer registers are always mapped from 0 to 31. The |
| 647 | names of the registers (which reflects the conventions regarding |
| 648 | register use) vary depending on the ABI. */ |
| 649 | if (0 <= rawnum && rawnum < 32) |
| 650 | { |
| 651 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) |
| 652 | return mips_n32_n64_gpr_names[rawnum]; |
| 653 | else |
| 654 | return mips_gpr_names[rawnum]; |
| 655 | } |
| 656 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
| 657 | return tdesc_register_name (gdbarch, rawnum); |
| 658 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) |
| 659 | { |
| 660 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); |
| 661 | if (tdep->mips_processor_reg_names[rawnum - 32]) |
| 662 | return tdep->mips_processor_reg_names[rawnum - 32]; |
| 663 | return ""; |
| 664 | } |
| 665 | else |
| 666 | internal_error (__FILE__, __LINE__, |
| 667 | _("mips_register_name: bad register number %d"), rawnum); |
| 668 | } |
| 669 | |
| 670 | /* Return the groups that a MIPS register can be categorised into. */ |
| 671 | |
| 672 | static int |
| 673 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
| 674 | struct reggroup *reggroup) |
| 675 | { |
| 676 | int vector_p; |
| 677 | int float_p; |
| 678 | int raw_p; |
| 679 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
| 680 | int pseudo = regnum / gdbarch_num_regs (gdbarch); |
| 681 | if (reggroup == all_reggroup) |
| 682 | return pseudo; |
| 683 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); |
| 684 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; |
| 685 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs |
| 686 | (gdbarch), as not all architectures are multi-arch. */ |
| 687 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
| 688 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
| 689 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') |
| 690 | return 0; |
| 691 | if (reggroup == float_reggroup) |
| 692 | return float_p && pseudo; |
| 693 | if (reggroup == vector_reggroup) |
| 694 | return vector_p && pseudo; |
| 695 | if (reggroup == general_reggroup) |
| 696 | return (!vector_p && !float_p) && pseudo; |
| 697 | /* Save the pseudo registers. Need to make certain that any code |
| 698 | extracting register values from a saved register cache also uses |
| 699 | pseudo registers. */ |
| 700 | if (reggroup == save_reggroup) |
| 701 | return raw_p && pseudo; |
| 702 | /* Restore the same pseudo register. */ |
| 703 | if (reggroup == restore_reggroup) |
| 704 | return raw_p && pseudo; |
| 705 | return 0; |
| 706 | } |
| 707 | |
| 708 | /* Return the groups that a MIPS register can be categorised into. |
| 709 | This version is only used if we have a target description which |
| 710 | describes real registers (and their groups). */ |
| 711 | |
| 712 | static int |
| 713 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
| 714 | struct reggroup *reggroup) |
| 715 | { |
| 716 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
| 717 | int pseudo = regnum / gdbarch_num_regs (gdbarch); |
| 718 | int ret; |
| 719 | |
| 720 | /* Only save, restore, and display the pseudo registers. Need to |
| 721 | make certain that any code extracting register values from a |
| 722 | saved register cache also uses pseudo registers. |
| 723 | |
| 724 | Note: saving and restoring the pseudo registers is slightly |
| 725 | strange; if we have 64 bits, we should save and restore all |
| 726 | 64 bits. But this is hard and has little benefit. */ |
| 727 | if (!pseudo) |
| 728 | return 0; |
| 729 | |
| 730 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); |
| 731 | if (ret != -1) |
| 732 | return ret; |
| 733 | |
| 734 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); |
| 735 | } |
| 736 | |
| 737 | /* Map the symbol table registers which live in the range [1 * |
| 738 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
| 739 | registers. Take care of alignment and size problems. */ |
| 740 | |
| 741 | static enum register_status |
| 742 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
| 743 | int cookednum, gdb_byte *buf) |
| 744 | { |
| 745 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
| 746 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) |
| 747 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); |
| 748 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
| 749 | return regcache_raw_read (regcache, rawnum, buf); |
| 750 | else if (register_size (gdbarch, rawnum) > |
| 751 | register_size (gdbarch, cookednum)) |
| 752 | { |
| 753 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
| 754 | return regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
| 755 | else |
| 756 | { |
| 757 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 758 | LONGEST regval; |
| 759 | enum register_status status; |
| 760 | |
| 761 | status = regcache_raw_read_signed (regcache, rawnum, ®val); |
| 762 | if (status == REG_VALID) |
| 763 | store_signed_integer (buf, 4, byte_order, regval); |
| 764 | return status; |
| 765 | } |
| 766 | } |
| 767 | else |
| 768 | internal_error (__FILE__, __LINE__, _("bad register size")); |
| 769 | } |
| 770 | |
| 771 | static void |
| 772 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
| 773 | struct regcache *regcache, int cookednum, |
| 774 | const gdb_byte *buf) |
| 775 | { |
| 776 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
| 777 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) |
| 778 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); |
| 779 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
| 780 | regcache_raw_write (regcache, rawnum, buf); |
| 781 | else if (register_size (gdbarch, rawnum) > |
| 782 | register_size (gdbarch, cookednum)) |
| 783 | { |
| 784 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
| 785 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
| 786 | else |
| 787 | { |
| 788 | /* Sign extend the shortened version of the register prior |
| 789 | to placing it in the raw register. This is required for |
| 790 | some mips64 parts in order to avoid unpredictable behavior. */ |
| 791 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 792 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); |
| 793 | regcache_raw_write_signed (regcache, rawnum, regval); |
| 794 | } |
| 795 | } |
| 796 | else |
| 797 | internal_error (__FILE__, __LINE__, _("bad register size")); |
| 798 | } |
| 799 | |
| 800 | static int |
| 801 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, |
| 802 | struct agent_expr *ax, int reg) |
| 803 | { |
| 804 | int rawnum = reg % gdbarch_num_regs (gdbarch); |
| 805 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) |
| 806 | && reg < 2 * gdbarch_num_regs (gdbarch)); |
| 807 | |
| 808 | ax_reg_mask (ax, rawnum); |
| 809 | |
| 810 | return 0; |
| 811 | } |
| 812 | |
| 813 | static int |
| 814 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, |
| 815 | struct agent_expr *ax, int reg) |
| 816 | { |
| 817 | int rawnum = reg % gdbarch_num_regs (gdbarch); |
| 818 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) |
| 819 | && reg < 2 * gdbarch_num_regs (gdbarch)); |
| 820 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) |
| 821 | { |
| 822 | ax_reg (ax, rawnum); |
| 823 | |
| 824 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) |
| 825 | { |
| 826 | if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p |
| 827 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) |
| 828 | { |
| 829 | ax_const_l (ax, 32); |
| 830 | ax_simple (ax, aop_lsh); |
| 831 | } |
| 832 | ax_const_l (ax, 32); |
| 833 | ax_simple (ax, aop_rsh_signed); |
| 834 | } |
| 835 | } |
| 836 | else |
| 837 | internal_error (__FILE__, __LINE__, _("bad register size")); |
| 838 | |
| 839 | return 0; |
| 840 | } |
| 841 | |
| 842 | /* Table to translate 3-bit register field to actual register number. */ |
| 843 | static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
| 844 | |
| 845 | /* Heuristic_proc_start may hunt through the text section for a long |
| 846 | time across a 2400 baud serial line. Allows the user to limit this |
| 847 | search. */ |
| 848 | |
| 849 | static int heuristic_fence_post = 0; |
| 850 | |
| 851 | /* Number of bytes of storage in the actual machine representation for |
| 852 | register N. NOTE: This defines the pseudo register type so need to |
| 853 | rebuild the architecture vector. */ |
| 854 | |
| 855 | static int mips64_transfers_32bit_regs_p = 0; |
| 856 | |
| 857 | static void |
| 858 | set_mips64_transfers_32bit_regs (char *args, int from_tty, |
| 859 | struct cmd_list_element *c) |
| 860 | { |
| 861 | struct gdbarch_info info; |
| 862 | gdbarch_info_init (&info); |
| 863 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
| 864 | instead of relying on globals. Doing that would let generic code |
| 865 | handle the search for this specific architecture. */ |
| 866 | if (!gdbarch_update_p (info)) |
| 867 | { |
| 868 | mips64_transfers_32bit_regs_p = 0; |
| 869 | error (_("32-bit compatibility mode not supported")); |
| 870 | } |
| 871 | } |
| 872 | |
| 873 | /* Convert to/from a register and the corresponding memory value. */ |
| 874 | |
| 875 | /* This predicate tests for the case of an 8 byte floating point |
| 876 | value that is being transferred to or from a pair of floating point |
| 877 | registers each of which are (or are considered to be) only 4 bytes |
| 878 | wide. */ |
| 879 | static int |
| 880 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
| 881 | struct type *type) |
| 882 | { |
| 883 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
| 884 | && register_size (gdbarch, regnum) == 4 |
| 885 | && mips_float_register_p (gdbarch, regnum) |
| 886 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
| 887 | } |
| 888 | |
| 889 | /* This predicate tests for the case of a value of less than 8 |
| 890 | bytes in width that is being transfered to or from an 8 byte |
| 891 | general purpose register. */ |
| 892 | static int |
| 893 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, |
| 894 | struct type *type) |
| 895 | { |
| 896 | int num_regs = gdbarch_num_regs (gdbarch); |
| 897 | |
| 898 | return (register_size (gdbarch, regnum) == 8 |
| 899 | && regnum % num_regs > 0 && regnum % num_regs < 32 |
| 900 | && TYPE_LENGTH (type) < 8); |
| 901 | } |
| 902 | |
| 903 | static int |
| 904 | mips_convert_register_p (struct gdbarch *gdbarch, |
| 905 | int regnum, struct type *type) |
| 906 | { |
| 907 | return (mips_convert_register_float_case_p (gdbarch, regnum, type) |
| 908 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type)); |
| 909 | } |
| 910 | |
| 911 | static int |
| 912 | mips_register_to_value (struct frame_info *frame, int regnum, |
| 913 | struct type *type, gdb_byte *to, |
| 914 | int *optimizedp, int *unavailablep) |
| 915 | { |
| 916 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 917 | |
| 918 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) |
| 919 | { |
| 920 | get_frame_register (frame, regnum + 0, to + 4); |
| 921 | get_frame_register (frame, regnum + 1, to + 0); |
| 922 | |
| 923 | if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4, |
| 924 | optimizedp, unavailablep)) |
| 925 | return 0; |
| 926 | |
| 927 | if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0, |
| 928 | optimizedp, unavailablep)) |
| 929 | return 0; |
| 930 | *optimizedp = *unavailablep = 0; |
| 931 | return 1; |
| 932 | } |
| 933 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) |
| 934 | { |
| 935 | int len = TYPE_LENGTH (type); |
| 936 | CORE_ADDR offset; |
| 937 | |
| 938 | offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; |
| 939 | if (!get_frame_register_bytes (frame, regnum, offset, len, to, |
| 940 | optimizedp, unavailablep)) |
| 941 | return 0; |
| 942 | |
| 943 | *optimizedp = *unavailablep = 0; |
| 944 | return 1; |
| 945 | } |
| 946 | else |
| 947 | { |
| 948 | internal_error (__FILE__, __LINE__, |
| 949 | _("mips_register_to_value: unrecognized case")); |
| 950 | } |
| 951 | } |
| 952 | |
| 953 | static void |
| 954 | mips_value_to_register (struct frame_info *frame, int regnum, |
| 955 | struct type *type, const gdb_byte *from) |
| 956 | { |
| 957 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 958 | |
| 959 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) |
| 960 | { |
| 961 | put_frame_register (frame, regnum + 0, from + 4); |
| 962 | put_frame_register (frame, regnum + 1, from + 0); |
| 963 | } |
| 964 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) |
| 965 | { |
| 966 | gdb_byte fill[8]; |
| 967 | int len = TYPE_LENGTH (type); |
| 968 | |
| 969 | /* Sign extend values, irrespective of type, that are stored to |
| 970 | a 64-bit general purpose register. (32-bit unsigned values |
| 971 | are stored as signed quantities within a 64-bit register. |
| 972 | When performing an operation, in compiled code, that combines |
| 973 | a 32-bit unsigned value with a signed 64-bit value, a type |
| 974 | conversion is first performed that zeroes out the high 32 bits.) */ |
| 975 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 976 | { |
| 977 | if (from[0] & 0x80) |
| 978 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); |
| 979 | else |
| 980 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); |
| 981 | put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); |
| 982 | put_frame_register_bytes (frame, regnum, 8 - len, len, from); |
| 983 | } |
| 984 | else |
| 985 | { |
| 986 | if (from[len-1] & 0x80) |
| 987 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); |
| 988 | else |
| 989 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); |
| 990 | put_frame_register_bytes (frame, regnum, 0, len, from); |
| 991 | put_frame_register_bytes (frame, regnum, len, 8 - len, fill); |
| 992 | } |
| 993 | } |
| 994 | else |
| 995 | { |
| 996 | internal_error (__FILE__, __LINE__, |
| 997 | _("mips_value_to_register: unrecognized case")); |
| 998 | } |
| 999 | } |
| 1000 | |
| 1001 | /* Return the GDB type object for the "standard" data type of data in |
| 1002 | register REG. */ |
| 1003 | |
| 1004 | static struct type * |
| 1005 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
| 1006 | { |
| 1007 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
| 1008 | if (mips_float_register_p (gdbarch, regnum)) |
| 1009 | { |
| 1010 | /* The floating-point registers raw, or cooked, always match |
| 1011 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
| 1012 | if (mips_isa_regsize (gdbarch) == 4) |
| 1013 | return builtin_type (gdbarch)->builtin_float; |
| 1014 | else |
| 1015 | return builtin_type (gdbarch)->builtin_double; |
| 1016 | } |
| 1017 | else if (regnum < gdbarch_num_regs (gdbarch)) |
| 1018 | { |
| 1019 | /* The raw or ISA registers. These are all sized according to |
| 1020 | the ISA regsize. */ |
| 1021 | if (mips_isa_regsize (gdbarch) == 4) |
| 1022 | return builtin_type (gdbarch)->builtin_int32; |
| 1023 | else |
| 1024 | return builtin_type (gdbarch)->builtin_int64; |
| 1025 | } |
| 1026 | else |
| 1027 | { |
| 1028 | int rawnum = regnum - gdbarch_num_regs (gdbarch); |
| 1029 | |
| 1030 | /* The cooked or ABI registers. These are sized according to |
| 1031 | the ABI (with a few complications). */ |
| 1032 | if (rawnum == mips_regnum (gdbarch)->fp_control_status |
| 1033 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) |
| 1034 | return builtin_type (gdbarch)->builtin_int32; |
| 1035 | else if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX |
| 1036 | && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX |
| 1037 | && rawnum >= MIPS_FIRST_EMBED_REGNUM |
| 1038 | && rawnum <= MIPS_LAST_EMBED_REGNUM) |
| 1039 | /* The pseudo/cooked view of the embedded registers is always |
| 1040 | 32-bit. The raw view is handled below. */ |
| 1041 | return builtin_type (gdbarch)->builtin_int32; |
| 1042 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
| 1043 | /* The target, while possibly using a 64-bit register buffer, |
| 1044 | is only transfering 32-bits of each integer register. |
| 1045 | Reflect this in the cooked/pseudo (ABI) register value. */ |
| 1046 | return builtin_type (gdbarch)->builtin_int32; |
| 1047 | else if (mips_abi_regsize (gdbarch) == 4) |
| 1048 | /* The ABI is restricted to 32-bit registers (the ISA could be |
| 1049 | 32- or 64-bit). */ |
| 1050 | return builtin_type (gdbarch)->builtin_int32; |
| 1051 | else |
| 1052 | /* 64-bit ABI. */ |
| 1053 | return builtin_type (gdbarch)->builtin_int64; |
| 1054 | } |
| 1055 | } |
| 1056 | |
| 1057 | /* Return the GDB type for the pseudo register REGNUM, which is the |
| 1058 | ABI-level view. This function is only called if there is a target |
| 1059 | description which includes registers, so we know precisely the |
| 1060 | types of hardware registers. */ |
| 1061 | |
| 1062 | static struct type * |
| 1063 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
| 1064 | { |
| 1065 | const int num_regs = gdbarch_num_regs (gdbarch); |
| 1066 | int rawnum = regnum % num_regs; |
| 1067 | struct type *rawtype; |
| 1068 | |
| 1069 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); |
| 1070 | |
| 1071 | /* Absent registers are still absent. */ |
| 1072 | rawtype = gdbarch_register_type (gdbarch, rawnum); |
| 1073 | if (TYPE_LENGTH (rawtype) == 0) |
| 1074 | return rawtype; |
| 1075 | |
| 1076 | if (mips_float_register_p (gdbarch, rawnum)) |
| 1077 | /* Present the floating point registers however the hardware did; |
| 1078 | do not try to convert between FPU layouts. */ |
| 1079 | return rawtype; |
| 1080 | |
| 1081 | /* Use pointer types for registers if we can. For n32 we can not, |
| 1082 | since we do not have a 64-bit pointer type. */ |
| 1083 | if (mips_abi_regsize (gdbarch) |
| 1084 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) |
| 1085 | { |
| 1086 | if (rawnum == MIPS_SP_REGNUM |
| 1087 | || rawnum == mips_regnum (gdbarch)->badvaddr) |
| 1088 | return builtin_type (gdbarch)->builtin_data_ptr; |
| 1089 | else if (rawnum == mips_regnum (gdbarch)->pc) |
| 1090 | return builtin_type (gdbarch)->builtin_func_ptr; |
| 1091 | } |
| 1092 | |
| 1093 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 |
| 1094 | && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) |
| 1095 | || rawnum == mips_regnum (gdbarch)->lo |
| 1096 | || rawnum == mips_regnum (gdbarch)->hi |
| 1097 | || rawnum == mips_regnum (gdbarch)->badvaddr |
| 1098 | || rawnum == mips_regnum (gdbarch)->cause |
| 1099 | || rawnum == mips_regnum (gdbarch)->pc |
| 1100 | || (mips_regnum (gdbarch)->dspacc != -1 |
| 1101 | && rawnum >= mips_regnum (gdbarch)->dspacc |
| 1102 | && rawnum < mips_regnum (gdbarch)->dspacc + 6))) |
| 1103 | return builtin_type (gdbarch)->builtin_int32; |
| 1104 | |
| 1105 | if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX |
| 1106 | && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX |
| 1107 | && rawnum >= MIPS_EMBED_FP0_REGNUM + 32 |
| 1108 | && rawnum <= MIPS_LAST_EMBED_REGNUM) |
| 1109 | { |
| 1110 | /* The pseudo/cooked view of embedded registers is always |
| 1111 | 32-bit, even if the target transfers 64-bit values for them. |
| 1112 | New targets relying on XML descriptions should only transfer |
| 1113 | the necessary 32 bits, but older versions of GDB expected 64, |
| 1114 | so allow the target to provide 64 bits without interfering |
| 1115 | with the displayed type. */ |
| 1116 | return builtin_type (gdbarch)->builtin_int32; |
| 1117 | } |
| 1118 | |
| 1119 | /* For all other registers, pass through the hardware type. */ |
| 1120 | return rawtype; |
| 1121 | } |
| 1122 | |
| 1123 | /* Should the upper word of 64-bit addresses be zeroed? */ |
| 1124 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
| 1125 | |
| 1126 | static int |
| 1127 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
| 1128 | { |
| 1129 | switch (mask_address_var) |
| 1130 | { |
| 1131 | case AUTO_BOOLEAN_TRUE: |
| 1132 | return 1; |
| 1133 | case AUTO_BOOLEAN_FALSE: |
| 1134 | return 0; |
| 1135 | break; |
| 1136 | case AUTO_BOOLEAN_AUTO: |
| 1137 | return tdep->default_mask_address_p; |
| 1138 | default: |
| 1139 | internal_error (__FILE__, __LINE__, |
| 1140 | _("mips_mask_address_p: bad switch")); |
| 1141 | return -1; |
| 1142 | } |
| 1143 | } |
| 1144 | |
| 1145 | static void |
| 1146 | show_mask_address (struct ui_file *file, int from_tty, |
| 1147 | struct cmd_list_element *c, const char *value) |
| 1148 | { |
| 1149 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); |
| 1150 | |
| 1151 | deprecated_show_value_hack (file, from_tty, c, value); |
| 1152 | switch (mask_address_var) |
| 1153 | { |
| 1154 | case AUTO_BOOLEAN_TRUE: |
| 1155 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
| 1156 | break; |
| 1157 | case AUTO_BOOLEAN_FALSE: |
| 1158 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
| 1159 | break; |
| 1160 | case AUTO_BOOLEAN_AUTO: |
| 1161 | printf_filtered |
| 1162 | ("The 32 bit address mask is set automatically. Currently %s\n", |
| 1163 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); |
| 1164 | break; |
| 1165 | default: |
| 1166 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
| 1167 | break; |
| 1168 | } |
| 1169 | } |
| 1170 | |
| 1171 | /* Tell if the program counter value in MEMADDR is in a standard ISA |
| 1172 | function. */ |
| 1173 | |
| 1174 | int |
| 1175 | mips_pc_is_mips (CORE_ADDR memaddr) |
| 1176 | { |
| 1177 | struct bound_minimal_symbol sym; |
| 1178 | |
| 1179 | /* Flags indicating that this is a MIPS16 or microMIPS function is |
| 1180 | stored by elfread.c in the high bit of the info field. Use this |
| 1181 | to decide if the function is standard MIPS. Otherwise if bit 0 |
| 1182 | of the address is clear, then this is a standard MIPS function. */ |
| 1183 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
| 1184 | if (sym.minsym) |
| 1185 | return msymbol_is_mips (sym.minsym); |
| 1186 | else |
| 1187 | return is_mips_addr (memaddr); |
| 1188 | } |
| 1189 | |
| 1190 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
| 1191 | |
| 1192 | int |
| 1193 | mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
| 1194 | { |
| 1195 | struct bound_minimal_symbol sym; |
| 1196 | |
| 1197 | /* A flag indicating that this is a MIPS16 function is stored by |
| 1198 | elfread.c in the high bit of the info field. Use this to decide |
| 1199 | if the function is MIPS16. Otherwise if bit 0 of the address is |
| 1200 | set, then ELF file flags will tell if this is a MIPS16 function. */ |
| 1201 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
| 1202 | if (sym.minsym) |
| 1203 | return msymbol_is_mips16 (sym.minsym); |
| 1204 | else |
| 1205 | return is_mips16_addr (gdbarch, memaddr); |
| 1206 | } |
| 1207 | |
| 1208 | /* Tell if the program counter value in MEMADDR is in a microMIPS function. */ |
| 1209 | |
| 1210 | int |
| 1211 | mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
| 1212 | { |
| 1213 | struct bound_minimal_symbol sym; |
| 1214 | |
| 1215 | /* A flag indicating that this is a microMIPS function is stored by |
| 1216 | elfread.c in the high bit of the info field. Use this to decide |
| 1217 | if the function is microMIPS. Otherwise if bit 0 of the address |
| 1218 | is set, then ELF file flags will tell if this is a microMIPS |
| 1219 | function. */ |
| 1220 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
| 1221 | if (sym.minsym) |
| 1222 | return msymbol_is_micromips (sym.minsym); |
| 1223 | else |
| 1224 | return is_micromips_addr (gdbarch, memaddr); |
| 1225 | } |
| 1226 | |
| 1227 | /* Tell the ISA type of the function the program counter value in MEMADDR |
| 1228 | is in. */ |
| 1229 | |
| 1230 | static enum mips_isa |
| 1231 | mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
| 1232 | { |
| 1233 | struct bound_minimal_symbol sym; |
| 1234 | |
| 1235 | /* A flag indicating that this is a MIPS16 or a microMIPS function |
| 1236 | is stored by elfread.c in the high bit of the info field. Use |
| 1237 | this to decide if the function is MIPS16 or microMIPS or normal |
| 1238 | MIPS. Otherwise if bit 0 of the address is set, then ELF file |
| 1239 | flags will tell if this is a MIPS16 or a microMIPS function. */ |
| 1240 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
| 1241 | if (sym.minsym) |
| 1242 | { |
| 1243 | if (msymbol_is_micromips (sym.minsym)) |
| 1244 | return ISA_MICROMIPS; |
| 1245 | else if (msymbol_is_mips16 (sym.minsym)) |
| 1246 | return ISA_MIPS16; |
| 1247 | else |
| 1248 | return ISA_MIPS; |
| 1249 | } |
| 1250 | else |
| 1251 | { |
| 1252 | if (is_mips_addr (memaddr)) |
| 1253 | return ISA_MIPS; |
| 1254 | else if (is_micromips_addr (gdbarch, memaddr)) |
| 1255 | return ISA_MICROMIPS; |
| 1256 | else |
| 1257 | return ISA_MIPS16; |
| 1258 | } |
| 1259 | } |
| 1260 | |
| 1261 | /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery. |
| 1262 | The need for comes from the ISA bit having been cleared, making |
| 1263 | addresses in FDE, range records, etc. referring to compressed code |
| 1264 | different to those in line information, the symbol table and finally |
| 1265 | the PC register. That in turn confuses many operations. */ |
| 1266 | |
| 1267 | static CORE_ADDR |
| 1268 | mips_adjust_dwarf2_addr (CORE_ADDR pc) |
| 1269 | { |
| 1270 | pc = unmake_compact_addr (pc); |
| 1271 | return mips_pc_is_mips (pc) ? pc : make_compact_addr (pc); |
| 1272 | } |
| 1273 | |
| 1274 | /* Recalculate the line record requested so that the resulting PC has |
| 1275 | the ISA bit set correctly, used by DWARF-2 machinery. The need for |
| 1276 | this adjustment comes from some records associated with compressed |
| 1277 | code having the ISA bit cleared, most notably at function prologue |
| 1278 | ends. The ISA bit is in this context retrieved from the minimal |
| 1279 | symbol covering the address requested, which in turn has been |
| 1280 | constructed from the binary's symbol table rather than DWARF-2 |
| 1281 | information. The correct setting of the ISA bit is required for |
| 1282 | breakpoint addresses to correctly match against the stop PC. |
| 1283 | |
| 1284 | As line entries can specify relative address adjustments we need to |
| 1285 | keep track of the absolute value of the last line address recorded |
| 1286 | in line information, so that we can calculate the actual address to |
| 1287 | apply the ISA bit adjustment to. We use PC for this tracking and |
| 1288 | keep the original address there. |
| 1289 | |
| 1290 | As such relative address adjustments can be odd within compressed |
| 1291 | code we need to keep track of the last line address with the ISA |
| 1292 | bit adjustment applied too, as the original address may or may not |
| 1293 | have had the ISA bit set. We use ADJ_PC for this tracking and keep |
| 1294 | the adjusted address there. |
| 1295 | |
| 1296 | For relative address adjustments we then use these variables to |
| 1297 | calculate the address intended by line information, which will be |
| 1298 | PC-relative, and return an updated adjustment carrying ISA bit |
| 1299 | information, which will be ADJ_PC-relative. For absolute address |
| 1300 | adjustments we just return the same address that we store in ADJ_PC |
| 1301 | too. |
| 1302 | |
| 1303 | As the first line entry can be relative to an implied address value |
| 1304 | of 0 we need to have the initial address set up that we store in PC |
| 1305 | and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1' |
| 1306 | that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */ |
| 1307 | |
| 1308 | static CORE_ADDR |
| 1309 | mips_adjust_dwarf2_line (CORE_ADDR addr, int rel) |
| 1310 | { |
| 1311 | static CORE_ADDR adj_pc; |
| 1312 | static CORE_ADDR pc; |
| 1313 | CORE_ADDR isa_pc; |
| 1314 | |
| 1315 | pc = rel ? pc + addr : addr; |
| 1316 | isa_pc = mips_adjust_dwarf2_addr (pc); |
| 1317 | addr = rel ? isa_pc - adj_pc : isa_pc; |
| 1318 | adj_pc = isa_pc; |
| 1319 | return addr; |
| 1320 | } |
| 1321 | |
| 1322 | /* Various MIPS16 thunk (aka stub or trampoline) names. */ |
| 1323 | |
| 1324 | static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_"; |
| 1325 | static const char mips_str_mips16_ret_stub[] = "__mips16_ret_"; |
| 1326 | static const char mips_str_call_fp_stub[] = "__call_stub_fp_"; |
| 1327 | static const char mips_str_call_stub[] = "__call_stub_"; |
| 1328 | static const char mips_str_fn_stub[] = "__fn_stub_"; |
| 1329 | |
| 1330 | /* This is used as a PIC thunk prefix. */ |
| 1331 | |
| 1332 | static const char mips_str_pic[] = ".pic."; |
| 1333 | |
| 1334 | /* Return non-zero if the PC is inside a call thunk (aka stub or |
| 1335 | trampoline) that should be treated as a temporary frame. */ |
| 1336 | |
| 1337 | static int |
| 1338 | mips_in_frame_stub (CORE_ADDR pc) |
| 1339 | { |
| 1340 | CORE_ADDR start_addr; |
| 1341 | const char *name; |
| 1342 | |
| 1343 | /* Find the starting address of the function containing the PC. */ |
| 1344 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) |
| 1345 | return 0; |
| 1346 | |
| 1347 | /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */ |
| 1348 | if (startswith (name, mips_str_mips16_call_stub)) |
| 1349 | return 1; |
| 1350 | /* If the PC is in __call_stub_*, this is a call/return or a call stub. */ |
| 1351 | if (startswith (name, mips_str_call_stub)) |
| 1352 | return 1; |
| 1353 | /* If the PC is in __fn_stub_*, this is a call stub. */ |
| 1354 | if (startswith (name, mips_str_fn_stub)) |
| 1355 | return 1; |
| 1356 | |
| 1357 | return 0; /* Not a stub. */ |
| 1358 | } |
| 1359 | |
| 1360 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
| 1361 | all registers should be sign extended for simplicity? */ |
| 1362 | |
| 1363 | static CORE_ADDR |
| 1364 | mips_read_pc (struct regcache *regcache) |
| 1365 | { |
| 1366 | int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache)); |
| 1367 | LONGEST pc; |
| 1368 | |
| 1369 | regcache_cooked_read_signed (regcache, regnum, &pc); |
| 1370 | return pc; |
| 1371 | } |
| 1372 | |
| 1373 | static CORE_ADDR |
| 1374 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1375 | { |
| 1376 | CORE_ADDR pc; |
| 1377 | |
| 1378 | pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch)); |
| 1379 | /* macro/2012-04-20: This hack skips over MIPS16 call thunks as |
| 1380 | intermediate frames. In this case we can get the caller's address |
| 1381 | from $ra, or if $ra contains an address within a thunk as well, then |
| 1382 | it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10} |
| 1383 | and thus the caller's address is in $s2. */ |
| 1384 | if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc)) |
| 1385 | { |
| 1386 | pc = frame_unwind_register_signed |
| 1387 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); |
| 1388 | if (mips_in_frame_stub (pc)) |
| 1389 | pc = frame_unwind_register_signed |
| 1390 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); |
| 1391 | } |
| 1392 | return pc; |
| 1393 | } |
| 1394 | |
| 1395 | static CORE_ADDR |
| 1396 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1397 | { |
| 1398 | return frame_unwind_register_signed |
| 1399 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); |
| 1400 | } |
| 1401 | |
| 1402 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
| 1403 | dummy frame. The frame ID's base needs to match the TOS value |
| 1404 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's |
| 1405 | breakpoint. */ |
| 1406 | |
| 1407 | static struct frame_id |
| 1408 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1409 | { |
| 1410 | return frame_id_build |
| 1411 | (get_frame_register_signed (this_frame, |
| 1412 | gdbarch_num_regs (gdbarch) |
| 1413 | + MIPS_SP_REGNUM), |
| 1414 | get_frame_pc (this_frame)); |
| 1415 | } |
| 1416 | |
| 1417 | /* Implement the "write_pc" gdbarch method. */ |
| 1418 | |
| 1419 | void |
| 1420 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
| 1421 | { |
| 1422 | int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache)); |
| 1423 | |
| 1424 | regcache_cooked_write_unsigned (regcache, regnum, pc); |
| 1425 | } |
| 1426 | |
| 1427 | /* Fetch and return instruction from the specified location. Handle |
| 1428 | MIPS16/microMIPS as appropriate. */ |
| 1429 | |
| 1430 | static ULONGEST |
| 1431 | mips_fetch_instruction (struct gdbarch *gdbarch, |
| 1432 | enum mips_isa isa, CORE_ADDR addr, int *errp) |
| 1433 | { |
| 1434 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1435 | gdb_byte buf[MIPS_INSN32_SIZE]; |
| 1436 | int instlen; |
| 1437 | int err; |
| 1438 | |
| 1439 | switch (isa) |
| 1440 | { |
| 1441 | case ISA_MICROMIPS: |
| 1442 | case ISA_MIPS16: |
| 1443 | instlen = MIPS_INSN16_SIZE; |
| 1444 | addr = unmake_compact_addr (addr); |
| 1445 | break; |
| 1446 | case ISA_MIPS: |
| 1447 | instlen = MIPS_INSN32_SIZE; |
| 1448 | break; |
| 1449 | default: |
| 1450 | internal_error (__FILE__, __LINE__, _("invalid ISA")); |
| 1451 | break; |
| 1452 | } |
| 1453 | err = target_read_memory (addr, buf, instlen); |
| 1454 | if (errp != NULL) |
| 1455 | *errp = err; |
| 1456 | if (err != 0) |
| 1457 | { |
| 1458 | if (errp == NULL) |
| 1459 | memory_error (TARGET_XFER_E_IO, addr); |
| 1460 | return 0; |
| 1461 | } |
| 1462 | return extract_unsigned_integer (buf, instlen, byte_order); |
| 1463 | } |
| 1464 | |
| 1465 | /* These are the fields of 32 bit mips instructions. */ |
| 1466 | #define mips32_op(x) (x >> 26) |
| 1467 | #define itype_op(x) (x >> 26) |
| 1468 | #define itype_rs(x) ((x >> 21) & 0x1f) |
| 1469 | #define itype_rt(x) ((x >> 16) & 0x1f) |
| 1470 | #define itype_immediate(x) (x & 0xffff) |
| 1471 | |
| 1472 | #define jtype_op(x) (x >> 26) |
| 1473 | #define jtype_target(x) (x & 0x03ffffff) |
| 1474 | |
| 1475 | #define rtype_op(x) (x >> 26) |
| 1476 | #define rtype_rs(x) ((x >> 21) & 0x1f) |
| 1477 | #define rtype_rt(x) ((x >> 16) & 0x1f) |
| 1478 | #define rtype_rd(x) ((x >> 11) & 0x1f) |
| 1479 | #define rtype_shamt(x) ((x >> 6) & 0x1f) |
| 1480 | #define rtype_funct(x) (x & 0x3f) |
| 1481 | |
| 1482 | /* MicroMIPS instruction fields. */ |
| 1483 | #define micromips_op(x) ((x) >> 10) |
| 1484 | |
| 1485 | /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest |
| 1486 | bit and the size respectively of the field extracted. */ |
| 1487 | #define b0s4_imm(x) ((x) & 0xf) |
| 1488 | #define b0s5_imm(x) ((x) & 0x1f) |
| 1489 | #define b0s5_reg(x) ((x) & 0x1f) |
| 1490 | #define b0s7_imm(x) ((x) & 0x7f) |
| 1491 | #define b0s10_imm(x) ((x) & 0x3ff) |
| 1492 | #define b1s4_imm(x) (((x) >> 1) & 0xf) |
| 1493 | #define b1s9_imm(x) (((x) >> 1) & 0x1ff) |
| 1494 | #define b2s3_cc(x) (((x) >> 2) & 0x7) |
| 1495 | #define b4s2_regl(x) (((x) >> 4) & 0x3) |
| 1496 | #define b5s5_op(x) (((x) >> 5) & 0x1f) |
| 1497 | #define b5s5_reg(x) (((x) >> 5) & 0x1f) |
| 1498 | #define b6s4_op(x) (((x) >> 6) & 0xf) |
| 1499 | #define b7s3_reg(x) (((x) >> 7) & 0x7) |
| 1500 | |
| 1501 | /* 32-bit instruction formats, B and S refer to the lowest bit and the size |
| 1502 | respectively of the field extracted. */ |
| 1503 | #define b0s6_op(x) ((x) & 0x3f) |
| 1504 | #define b0s11_op(x) ((x) & 0x7ff) |
| 1505 | #define b0s12_imm(x) ((x) & 0xfff) |
| 1506 | #define b0s16_imm(x) ((x) & 0xffff) |
| 1507 | #define b0s26_imm(x) ((x) & 0x3ffffff) |
| 1508 | #define b6s10_ext(x) (((x) >> 6) & 0x3ff) |
| 1509 | #define b11s5_reg(x) (((x) >> 11) & 0x1f) |
| 1510 | #define b12s4_op(x) (((x) >> 12) & 0xf) |
| 1511 | |
| 1512 | /* Return the size in bytes of the instruction INSN encoded in the ISA |
| 1513 | instruction set. */ |
| 1514 | |
| 1515 | static int |
| 1516 | mips_insn_size (enum mips_isa isa, ULONGEST insn) |
| 1517 | { |
| 1518 | switch (isa) |
| 1519 | { |
| 1520 | case ISA_MICROMIPS: |
| 1521 | if (micromips_op (insn) == 0x1f) |
| 1522 | return 3 * MIPS_INSN16_SIZE; |
| 1523 | else if (((micromips_op (insn) & 0x4) == 0x4) |
| 1524 | || ((micromips_op (insn) & 0x7) == 0x0)) |
| 1525 | return 2 * MIPS_INSN16_SIZE; |
| 1526 | else |
| 1527 | return MIPS_INSN16_SIZE; |
| 1528 | case ISA_MIPS16: |
| 1529 | if ((insn & 0xf800) == 0xf000) |
| 1530 | return 2 * MIPS_INSN16_SIZE; |
| 1531 | else |
| 1532 | return MIPS_INSN16_SIZE; |
| 1533 | case ISA_MIPS: |
| 1534 | return MIPS_INSN32_SIZE; |
| 1535 | } |
| 1536 | internal_error (__FILE__, __LINE__, _("invalid ISA")); |
| 1537 | } |
| 1538 | |
| 1539 | static LONGEST |
| 1540 | mips32_relative_offset (ULONGEST inst) |
| 1541 | { |
| 1542 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
| 1543 | } |
| 1544 | |
| 1545 | /* Determine the address of the next instruction executed after the INST |
| 1546 | floating condition branch instruction at PC. COUNT specifies the |
| 1547 | number of the floating condition bits tested by the branch. */ |
| 1548 | |
| 1549 | static CORE_ADDR |
| 1550 | mips32_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, |
| 1551 | ULONGEST inst, CORE_ADDR pc, int count) |
| 1552 | { |
| 1553 | int fcsr = mips_regnum (gdbarch)->fp_control_status; |
| 1554 | int cnum = (itype_rt (inst) >> 2) & (count - 1); |
| 1555 | int tf = itype_rt (inst) & 1; |
| 1556 | int mask = (1 << count) - 1; |
| 1557 | ULONGEST fcs; |
| 1558 | int cond; |
| 1559 | |
| 1560 | if (fcsr == -1) |
| 1561 | /* No way to handle; it'll most likely trap anyway. */ |
| 1562 | return pc; |
| 1563 | |
| 1564 | fcs = get_frame_register_unsigned (frame, fcsr); |
| 1565 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); |
| 1566 | |
| 1567 | if (((cond >> cnum) & mask) != mask * !tf) |
| 1568 | pc += mips32_relative_offset (inst); |
| 1569 | else |
| 1570 | pc += 4; |
| 1571 | |
| 1572 | return pc; |
| 1573 | } |
| 1574 | |
| 1575 | /* Return nonzero if the gdbarch is an Octeon series. */ |
| 1576 | |
| 1577 | static int |
| 1578 | is_octeon (struct gdbarch *gdbarch) |
| 1579 | { |
| 1580 | const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch); |
| 1581 | |
| 1582 | return (info->mach == bfd_mach_mips_octeon |
| 1583 | || info->mach == bfd_mach_mips_octeonp |
| 1584 | || info->mach == bfd_mach_mips_octeon2); |
| 1585 | } |
| 1586 | |
| 1587 | /* Return true if the OP represents the Octeon's BBIT instruction. */ |
| 1588 | |
| 1589 | static int |
| 1590 | is_octeon_bbit_op (int op, struct gdbarch *gdbarch) |
| 1591 | { |
| 1592 | if (!is_octeon (gdbarch)) |
| 1593 | return 0; |
| 1594 | /* BBIT0 is encoded as LWC2: 110 010. */ |
| 1595 | /* BBIT032 is encoded as LDC2: 110 110. */ |
| 1596 | /* BBIT1 is encoded as SWC2: 111 010. */ |
| 1597 | /* BBIT132 is encoded as SDC2: 111 110. */ |
| 1598 | if (op == 50 || op == 54 || op == 58 || op == 62) |
| 1599 | return 1; |
| 1600 | return 0; |
| 1601 | } |
| 1602 | |
| 1603 | |
| 1604 | /* Determine where to set a single step breakpoint while considering |
| 1605 | branch prediction. */ |
| 1606 | |
| 1607 | static CORE_ADDR |
| 1608 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
| 1609 | { |
| 1610 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 1611 | unsigned long inst; |
| 1612 | int op; |
| 1613 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
| 1614 | op = itype_op (inst); |
| 1615 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
| 1616 | instruction. */ |
| 1617 | { |
| 1618 | if (op >> 2 == 5) |
| 1619 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
| 1620 | { |
| 1621 | switch (op & 0x03) |
| 1622 | { |
| 1623 | case 0: /* BEQL */ |
| 1624 | goto equal_branch; |
| 1625 | case 1: /* BNEL */ |
| 1626 | goto neq_branch; |
| 1627 | case 2: /* BLEZL */ |
| 1628 | goto less_branch; |
| 1629 | case 3: /* BGTZL */ |
| 1630 | goto greater_branch; |
| 1631 | default: |
| 1632 | pc += 4; |
| 1633 | } |
| 1634 | } |
| 1635 | else if (op == 17 && itype_rs (inst) == 8) |
| 1636 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
| 1637 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 1); |
| 1638 | else if (op == 17 && itype_rs (inst) == 9 |
| 1639 | && (itype_rt (inst) & 2) == 0) |
| 1640 | /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ |
| 1641 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 2); |
| 1642 | else if (op == 17 && itype_rs (inst) == 10 |
| 1643 | && (itype_rt (inst) & 2) == 0) |
| 1644 | /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ |
| 1645 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 4); |
| 1646 | else if (op == 29) |
| 1647 | /* JALX: 011101 */ |
| 1648 | /* The new PC will be alternate mode. */ |
| 1649 | { |
| 1650 | unsigned long reg; |
| 1651 | |
| 1652 | reg = jtype_target (inst) << 2; |
| 1653 | /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ |
| 1654 | pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; |
| 1655 | } |
| 1656 | else if (is_octeon_bbit_op (op, gdbarch)) |
| 1657 | { |
| 1658 | int bit, branch_if; |
| 1659 | |
| 1660 | branch_if = op == 58 || op == 62; |
| 1661 | bit = itype_rt (inst); |
| 1662 | |
| 1663 | /* Take into account the *32 instructions. */ |
| 1664 | if (op == 54 || op == 62) |
| 1665 | bit += 32; |
| 1666 | |
| 1667 | if (((get_frame_register_signed (frame, |
| 1668 | itype_rs (inst)) >> bit) & 1) |
| 1669 | == branch_if) |
| 1670 | pc += mips32_relative_offset (inst) + 4; |
| 1671 | else |
| 1672 | pc += 8; /* After the delay slot. */ |
| 1673 | } |
| 1674 | |
| 1675 | else |
| 1676 | pc += 4; /* Not a branch, next instruction is easy. */ |
| 1677 | } |
| 1678 | else |
| 1679 | { /* This gets way messy. */ |
| 1680 | |
| 1681 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
| 1682 | switch (op & 0x07) /* Extract bits 28,27,26. */ |
| 1683 | { |
| 1684 | case 0: /* SPECIAL */ |
| 1685 | op = rtype_funct (inst); |
| 1686 | switch (op) |
| 1687 | { |
| 1688 | case 8: /* JR */ |
| 1689 | case 9: /* JALR */ |
| 1690 | /* Set PC to that address. */ |
| 1691 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
| 1692 | break; |
| 1693 | case 12: /* SYSCALL */ |
| 1694 | { |
| 1695 | struct gdbarch_tdep *tdep; |
| 1696 | |
| 1697 | tdep = gdbarch_tdep (get_frame_arch (frame)); |
| 1698 | if (tdep->syscall_next_pc != NULL) |
| 1699 | pc = tdep->syscall_next_pc (frame); |
| 1700 | else |
| 1701 | pc += 4; |
| 1702 | } |
| 1703 | break; |
| 1704 | default: |
| 1705 | pc += 4; |
| 1706 | } |
| 1707 | |
| 1708 | break; /* end SPECIAL */ |
| 1709 | case 1: /* REGIMM */ |
| 1710 | { |
| 1711 | op = itype_rt (inst); /* branch condition */ |
| 1712 | switch (op) |
| 1713 | { |
| 1714 | case 0: /* BLTZ */ |
| 1715 | case 2: /* BLTZL */ |
| 1716 | case 16: /* BLTZAL */ |
| 1717 | case 18: /* BLTZALL */ |
| 1718 | less_branch: |
| 1719 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
| 1720 | pc += mips32_relative_offset (inst) + 4; |
| 1721 | else |
| 1722 | pc += 8; /* after the delay slot */ |
| 1723 | break; |
| 1724 | case 1: /* BGEZ */ |
| 1725 | case 3: /* BGEZL */ |
| 1726 | case 17: /* BGEZAL */ |
| 1727 | case 19: /* BGEZALL */ |
| 1728 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
| 1729 | pc += mips32_relative_offset (inst) + 4; |
| 1730 | else |
| 1731 | pc += 8; /* after the delay slot */ |
| 1732 | break; |
| 1733 | case 0x1c: /* BPOSGE32 */ |
| 1734 | case 0x1e: /* BPOSGE64 */ |
| 1735 | pc += 4; |
| 1736 | if (itype_rs (inst) == 0) |
| 1737 | { |
| 1738 | unsigned int pos = (op & 2) ? 64 : 32; |
| 1739 | int dspctl = mips_regnum (gdbarch)->dspctl; |
| 1740 | |
| 1741 | if (dspctl == -1) |
| 1742 | /* No way to handle; it'll most likely trap anyway. */ |
| 1743 | break; |
| 1744 | |
| 1745 | if ((get_frame_register_unsigned (frame, |
| 1746 | dspctl) & 0x7f) >= pos) |
| 1747 | pc += mips32_relative_offset (inst); |
| 1748 | else |
| 1749 | pc += 4; |
| 1750 | } |
| 1751 | break; |
| 1752 | /* All of the other instructions in the REGIMM category */ |
| 1753 | default: |
| 1754 | pc += 4; |
| 1755 | } |
| 1756 | } |
| 1757 | break; /* end REGIMM */ |
| 1758 | case 2: /* J */ |
| 1759 | case 3: /* JAL */ |
| 1760 | { |
| 1761 | unsigned long reg; |
| 1762 | reg = jtype_target (inst) << 2; |
| 1763 | /* Upper four bits get never changed... */ |
| 1764 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
| 1765 | } |
| 1766 | break; |
| 1767 | case 4: /* BEQ, BEQL */ |
| 1768 | equal_branch: |
| 1769 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
| 1770 | get_frame_register_signed (frame, itype_rt (inst))) |
| 1771 | pc += mips32_relative_offset (inst) + 4; |
| 1772 | else |
| 1773 | pc += 8; |
| 1774 | break; |
| 1775 | case 5: /* BNE, BNEL */ |
| 1776 | neq_branch: |
| 1777 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
| 1778 | get_frame_register_signed (frame, itype_rt (inst))) |
| 1779 | pc += mips32_relative_offset (inst) + 4; |
| 1780 | else |
| 1781 | pc += 8; |
| 1782 | break; |
| 1783 | case 6: /* BLEZ, BLEZL */ |
| 1784 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
| 1785 | pc += mips32_relative_offset (inst) + 4; |
| 1786 | else |
| 1787 | pc += 8; |
| 1788 | break; |
| 1789 | case 7: |
| 1790 | default: |
| 1791 | greater_branch: /* BGTZ, BGTZL */ |
| 1792 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
| 1793 | pc += mips32_relative_offset (inst) + 4; |
| 1794 | else |
| 1795 | pc += 8; |
| 1796 | break; |
| 1797 | } /* switch */ |
| 1798 | } /* else */ |
| 1799 | return pc; |
| 1800 | } /* mips32_next_pc */ |
| 1801 | |
| 1802 | /* Extract the 7-bit signed immediate offset from the microMIPS instruction |
| 1803 | INSN. */ |
| 1804 | |
| 1805 | static LONGEST |
| 1806 | micromips_relative_offset7 (ULONGEST insn) |
| 1807 | { |
| 1808 | return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1; |
| 1809 | } |
| 1810 | |
| 1811 | /* Extract the 10-bit signed immediate offset from the microMIPS instruction |
| 1812 | INSN. */ |
| 1813 | |
| 1814 | static LONGEST |
| 1815 | micromips_relative_offset10 (ULONGEST insn) |
| 1816 | { |
| 1817 | return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1; |
| 1818 | } |
| 1819 | |
| 1820 | /* Extract the 16-bit signed immediate offset from the microMIPS instruction |
| 1821 | INSN. */ |
| 1822 | |
| 1823 | static LONGEST |
| 1824 | micromips_relative_offset16 (ULONGEST insn) |
| 1825 | { |
| 1826 | return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1; |
| 1827 | } |
| 1828 | |
| 1829 | /* Return the size in bytes of the microMIPS instruction at the address PC. */ |
| 1830 | |
| 1831 | static int |
| 1832 | micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 1833 | { |
| 1834 | ULONGEST insn; |
| 1835 | |
| 1836 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); |
| 1837 | return mips_insn_size (ISA_MICROMIPS, insn); |
| 1838 | } |
| 1839 | |
| 1840 | /* Calculate the address of the next microMIPS instruction to execute |
| 1841 | after the INSN coprocessor 1 conditional branch instruction at the |
| 1842 | address PC. COUNT denotes the number of coprocessor condition bits |
| 1843 | examined by the branch. */ |
| 1844 | |
| 1845 | static CORE_ADDR |
| 1846 | micromips_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, |
| 1847 | ULONGEST insn, CORE_ADDR pc, int count) |
| 1848 | { |
| 1849 | int fcsr = mips_regnum (gdbarch)->fp_control_status; |
| 1850 | int cnum = b2s3_cc (insn >> 16) & (count - 1); |
| 1851 | int tf = b5s5_op (insn >> 16) & 1; |
| 1852 | int mask = (1 << count) - 1; |
| 1853 | ULONGEST fcs; |
| 1854 | int cond; |
| 1855 | |
| 1856 | if (fcsr == -1) |
| 1857 | /* No way to handle; it'll most likely trap anyway. */ |
| 1858 | return pc; |
| 1859 | |
| 1860 | fcs = get_frame_register_unsigned (frame, fcsr); |
| 1861 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); |
| 1862 | |
| 1863 | if (((cond >> cnum) & mask) != mask * !tf) |
| 1864 | pc += micromips_relative_offset16 (insn); |
| 1865 | else |
| 1866 | pc += micromips_pc_insn_size (gdbarch, pc); |
| 1867 | |
| 1868 | return pc; |
| 1869 | } |
| 1870 | |
| 1871 | /* Calculate the address of the next microMIPS instruction to execute |
| 1872 | after the instruction at the address PC. */ |
| 1873 | |
| 1874 | static CORE_ADDR |
| 1875 | micromips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
| 1876 | { |
| 1877 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 1878 | ULONGEST insn; |
| 1879 | |
| 1880 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); |
| 1881 | pc += MIPS_INSN16_SIZE; |
| 1882 | switch (mips_insn_size (ISA_MICROMIPS, insn)) |
| 1883 | { |
| 1884 | /* 48-bit instructions. */ |
| 1885 | case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */ |
| 1886 | /* No branch or jump instructions in this category. */ |
| 1887 | pc += 2 * MIPS_INSN16_SIZE; |
| 1888 | break; |
| 1889 | |
| 1890 | /* 32-bit instructions. */ |
| 1891 | case 2 * MIPS_INSN16_SIZE: |
| 1892 | insn <<= 16; |
| 1893 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); |
| 1894 | pc += MIPS_INSN16_SIZE; |
| 1895 | switch (micromips_op (insn >> 16)) |
| 1896 | { |
| 1897 | case 0x00: /* POOL32A: bits 000000 */ |
| 1898 | if (b0s6_op (insn) == 0x3c |
| 1899 | /* POOL32Axf: bits 000000 ... 111100 */ |
| 1900 | && (b6s10_ext (insn) & 0x2bf) == 0x3c) |
| 1901 | /* JALR, JALR.HB: 000000 000x111100 111100 */ |
| 1902 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ |
| 1903 | pc = get_frame_register_signed (frame, b0s5_reg (insn >> 16)); |
| 1904 | break; |
| 1905 | |
| 1906 | case 0x10: /* POOL32I: bits 010000 */ |
| 1907 | switch (b5s5_op (insn >> 16)) |
| 1908 | { |
| 1909 | case 0x00: /* BLTZ: bits 010000 00000 */ |
| 1910 | case 0x01: /* BLTZAL: bits 010000 00001 */ |
| 1911 | case 0x11: /* BLTZALS: bits 010000 10001 */ |
| 1912 | if (get_frame_register_signed (frame, |
| 1913 | b0s5_reg (insn >> 16)) < 0) |
| 1914 | pc += micromips_relative_offset16 (insn); |
| 1915 | else |
| 1916 | pc += micromips_pc_insn_size (gdbarch, pc); |
| 1917 | break; |
| 1918 | |
| 1919 | case 0x02: /* BGEZ: bits 010000 00010 */ |
| 1920 | case 0x03: /* BGEZAL: bits 010000 00011 */ |
| 1921 | case 0x13: /* BGEZALS: bits 010000 10011 */ |
| 1922 | if (get_frame_register_signed (frame, |
| 1923 | b0s5_reg (insn >> 16)) >= 0) |
| 1924 | pc += micromips_relative_offset16 (insn); |
| 1925 | else |
| 1926 | pc += micromips_pc_insn_size (gdbarch, pc); |
| 1927 | break; |
| 1928 | |
| 1929 | case 0x04: /* BLEZ: bits 010000 00100 */ |
| 1930 | if (get_frame_register_signed (frame, |
| 1931 | b0s5_reg (insn >> 16)) <= 0) |
| 1932 | pc += micromips_relative_offset16 (insn); |
| 1933 | else |
| 1934 | pc += micromips_pc_insn_size (gdbarch, pc); |
| 1935 | break; |
| 1936 | |
| 1937 | case 0x05: /* BNEZC: bits 010000 00101 */ |
| 1938 | if (get_frame_register_signed (frame, |
| 1939 | b0s5_reg (insn >> 16)) != 0) |
| 1940 | pc += micromips_relative_offset16 (insn); |
| 1941 | break; |
| 1942 | |
| 1943 | case 0x06: /* BGTZ: bits 010000 00110 */ |
| 1944 | if (get_frame_register_signed (frame, |
| 1945 | b0s5_reg (insn >> 16)) > 0) |
| 1946 | pc += micromips_relative_offset16 (insn); |
| 1947 | else |
| 1948 | pc += micromips_pc_insn_size (gdbarch, pc); |
| 1949 | break; |
| 1950 | |
| 1951 | case 0x07: /* BEQZC: bits 010000 00111 */ |
| 1952 | if (get_frame_register_signed (frame, |
| 1953 | b0s5_reg (insn >> 16)) == 0) |
| 1954 | pc += micromips_relative_offset16 (insn); |
| 1955 | break; |
| 1956 | |
| 1957 | case 0x14: /* BC2F: bits 010000 10100 xxx00 */ |
| 1958 | case 0x15: /* BC2T: bits 010000 10101 xxx00 */ |
| 1959 | if (((insn >> 16) & 0x3) == 0x0) |
| 1960 | /* BC2F, BC2T: don't know how to handle these. */ |
| 1961 | break; |
| 1962 | break; |
| 1963 | |
| 1964 | case 0x1a: /* BPOSGE64: bits 010000 11010 */ |
| 1965 | case 0x1b: /* BPOSGE32: bits 010000 11011 */ |
| 1966 | { |
| 1967 | unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64; |
| 1968 | int dspctl = mips_regnum (gdbarch)->dspctl; |
| 1969 | |
| 1970 | if (dspctl == -1) |
| 1971 | /* No way to handle; it'll most likely trap anyway. */ |
| 1972 | break; |
| 1973 | |
| 1974 | if ((get_frame_register_unsigned (frame, |
| 1975 | dspctl) & 0x7f) >= pos) |
| 1976 | pc += micromips_relative_offset16 (insn); |
| 1977 | else |
| 1978 | pc += micromips_pc_insn_size (gdbarch, pc); |
| 1979 | } |
| 1980 | break; |
| 1981 | |
| 1982 | case 0x1c: /* BC1F: bits 010000 11100 xxx00 */ |
| 1983 | /* BC1ANY2F: bits 010000 11100 xxx01 */ |
| 1984 | case 0x1d: /* BC1T: bits 010000 11101 xxx00 */ |
| 1985 | /* BC1ANY2T: bits 010000 11101 xxx01 */ |
| 1986 | if (((insn >> 16) & 0x2) == 0x0) |
| 1987 | pc = micromips_bc1_pc (gdbarch, frame, insn, pc, |
| 1988 | ((insn >> 16) & 0x1) + 1); |
| 1989 | break; |
| 1990 | |
| 1991 | case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */ |
| 1992 | case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */ |
| 1993 | if (((insn >> 16) & 0x3) == 0x1) |
| 1994 | pc = micromips_bc1_pc (gdbarch, frame, insn, pc, 4); |
| 1995 | break; |
| 1996 | } |
| 1997 | break; |
| 1998 | |
| 1999 | case 0x1d: /* JALS: bits 011101 */ |
| 2000 | case 0x35: /* J: bits 110101 */ |
| 2001 | case 0x3d: /* JAL: bits 111101 */ |
| 2002 | pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); |
| 2003 | break; |
| 2004 | |
| 2005 | case 0x25: /* BEQ: bits 100101 */ |
| 2006 | if (get_frame_register_signed (frame, b0s5_reg (insn >> 16)) |
| 2007 | == get_frame_register_signed (frame, b5s5_reg (insn >> 16))) |
| 2008 | pc += micromips_relative_offset16 (insn); |
| 2009 | else |
| 2010 | pc += micromips_pc_insn_size (gdbarch, pc); |
| 2011 | break; |
| 2012 | |
| 2013 | case 0x2d: /* BNE: bits 101101 */ |
| 2014 | if (get_frame_register_signed (frame, b0s5_reg (insn >> 16)) |
| 2015 | != get_frame_register_signed (frame, b5s5_reg (insn >> 16))) |
| 2016 | pc += micromips_relative_offset16 (insn); |
| 2017 | else |
| 2018 | pc += micromips_pc_insn_size (gdbarch, pc); |
| 2019 | break; |
| 2020 | |
| 2021 | case 0x3c: /* JALX: bits 111100 */ |
| 2022 | pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); |
| 2023 | break; |
| 2024 | } |
| 2025 | break; |
| 2026 | |
| 2027 | /* 16-bit instructions. */ |
| 2028 | case MIPS_INSN16_SIZE: |
| 2029 | switch (micromips_op (insn)) |
| 2030 | { |
| 2031 | case 0x11: /* POOL16C: bits 010001 */ |
| 2032 | if ((b5s5_op (insn) & 0x1c) == 0xc) |
| 2033 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ |
| 2034 | pc = get_frame_register_signed (frame, b0s5_reg (insn)); |
| 2035 | else if (b5s5_op (insn) == 0x18) |
| 2036 | /* JRADDIUSP: bits 010001 11000 */ |
| 2037 | pc = get_frame_register_signed (frame, MIPS_RA_REGNUM); |
| 2038 | break; |
| 2039 | |
| 2040 | case 0x23: /* BEQZ16: bits 100011 */ |
| 2041 | { |
| 2042 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; |
| 2043 | |
| 2044 | if (get_frame_register_signed (frame, rs) == 0) |
| 2045 | pc += micromips_relative_offset7 (insn); |
| 2046 | else |
| 2047 | pc += micromips_pc_insn_size (gdbarch, pc); |
| 2048 | } |
| 2049 | break; |
| 2050 | |
| 2051 | case 0x2b: /* BNEZ16: bits 101011 */ |
| 2052 | { |
| 2053 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; |
| 2054 | |
| 2055 | if (get_frame_register_signed (frame, rs) != 0) |
| 2056 | pc += micromips_relative_offset7 (insn); |
| 2057 | else |
| 2058 | pc += micromips_pc_insn_size (gdbarch, pc); |
| 2059 | } |
| 2060 | break; |
| 2061 | |
| 2062 | case 0x33: /* B16: bits 110011 */ |
| 2063 | pc += micromips_relative_offset10 (insn); |
| 2064 | break; |
| 2065 | } |
| 2066 | break; |
| 2067 | } |
| 2068 | |
| 2069 | return pc; |
| 2070 | } |
| 2071 | |
| 2072 | /* Decoding the next place to set a breakpoint is irregular for the |
| 2073 | mips 16 variant, but fortunately, there fewer instructions. We have |
| 2074 | to cope ith extensions for 16 bit instructions and a pair of actual |
| 2075 | 32 bit instructions. We dont want to set a single step instruction |
| 2076 | on the extend instruction either. */ |
| 2077 | |
| 2078 | /* Lots of mips16 instruction formats */ |
| 2079 | /* Predicting jumps requires itype,ritype,i8type |
| 2080 | and their extensions extItype,extritype,extI8type. */ |
| 2081 | enum mips16_inst_fmts |
| 2082 | { |
| 2083 | itype, /* 0 immediate 5,10 */ |
| 2084 | ritype, /* 1 5,3,8 */ |
| 2085 | rrtype, /* 2 5,3,3,5 */ |
| 2086 | rritype, /* 3 5,3,3,5 */ |
| 2087 | rrrtype, /* 4 5,3,3,3,2 */ |
| 2088 | rriatype, /* 5 5,3,3,1,4 */ |
| 2089 | shifttype, /* 6 5,3,3,3,2 */ |
| 2090 | i8type, /* 7 5,3,8 */ |
| 2091 | i8movtype, /* 8 5,3,3,5 */ |
| 2092 | i8mov32rtype, /* 9 5,3,5,3 */ |
| 2093 | i64type, /* 10 5,3,8 */ |
| 2094 | ri64type, /* 11 5,3,3,5 */ |
| 2095 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ |
| 2096 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ |
| 2097 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ |
| 2098 | extRRItype, /* 15 5,5,5,5,3,3,5 */ |
| 2099 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ |
| 2100 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ |
| 2101 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ |
| 2102 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ |
| 2103 | extRi64type, /* 20 5,6,5,5,3,3,5 */ |
| 2104 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ |
| 2105 | }; |
| 2106 | /* I am heaping all the fields of the formats into one structure and |
| 2107 | then, only the fields which are involved in instruction extension. */ |
| 2108 | struct upk_mips16 |
| 2109 | { |
| 2110 | CORE_ADDR offset; |
| 2111 | unsigned int regx; /* Function in i8 type. */ |
| 2112 | unsigned int regy; |
| 2113 | }; |
| 2114 | |
| 2115 | |
| 2116 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
| 2117 | for the bits which make up the immediate extension. */ |
| 2118 | |
| 2119 | static CORE_ADDR |
| 2120 | extended_offset (unsigned int extension) |
| 2121 | { |
| 2122 | CORE_ADDR value; |
| 2123 | |
| 2124 | value = (extension >> 16) & 0x1f; /* Extract 15:11. */ |
| 2125 | value = value << 6; |
| 2126 | value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ |
| 2127 | value = value << 5; |
| 2128 | value |= extension & 0x1f; /* Extract 4:0. */ |
| 2129 | |
| 2130 | return value; |
| 2131 | } |
| 2132 | |
| 2133 | /* Only call this function if you know that this is an extendable |
| 2134 | instruction. It won't malfunction, but why make excess remote memory |
| 2135 | references? If the immediate operands get sign extended or something, |
| 2136 | do it after the extension is performed. */ |
| 2137 | /* FIXME: Every one of these cases needs to worry about sign extension |
| 2138 | when the offset is to be used in relative addressing. */ |
| 2139 | |
| 2140 | static unsigned int |
| 2141 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 2142 | { |
| 2143 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2144 | gdb_byte buf[8]; |
| 2145 | |
| 2146 | pc = unmake_compact_addr (pc); /* Clear the low order bit. */ |
| 2147 | target_read_memory (pc, buf, 2); |
| 2148 | return extract_unsigned_integer (buf, 2, byte_order); |
| 2149 | } |
| 2150 | |
| 2151 | static void |
| 2152 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
| 2153 | unsigned int extension, |
| 2154 | unsigned int inst, |
| 2155 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
| 2156 | { |
| 2157 | CORE_ADDR offset; |
| 2158 | int regx; |
| 2159 | int regy; |
| 2160 | switch (insn_format) |
| 2161 | { |
| 2162 | case itype: |
| 2163 | { |
| 2164 | CORE_ADDR value; |
| 2165 | if (extension) |
| 2166 | { |
| 2167 | value = extended_offset ((extension << 16) | inst); |
| 2168 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ |
| 2169 | } |
| 2170 | else |
| 2171 | { |
| 2172 | value = inst & 0x7ff; |
| 2173 | value = (value ^ 0x400) - 0x400; /* Sign-extend. */ |
| 2174 | } |
| 2175 | offset = value; |
| 2176 | regx = -1; |
| 2177 | regy = -1; |
| 2178 | } |
| 2179 | break; |
| 2180 | case ritype: |
| 2181 | case i8type: |
| 2182 | { /* A register identifier and an offset. */ |
| 2183 | /* Most of the fields are the same as I type but the |
| 2184 | immediate value is of a different length. */ |
| 2185 | CORE_ADDR value; |
| 2186 | if (extension) |
| 2187 | { |
| 2188 | value = extended_offset ((extension << 16) | inst); |
| 2189 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ |
| 2190 | } |
| 2191 | else |
| 2192 | { |
| 2193 | value = inst & 0xff; /* 8 bits */ |
| 2194 | value = (value ^ 0x80) - 0x80; /* Sign-extend. */ |
| 2195 | } |
| 2196 | offset = value; |
| 2197 | regx = (inst >> 8) & 0x07; /* i8 funct */ |
| 2198 | regy = -1; |
| 2199 | break; |
| 2200 | } |
| 2201 | case jalxtype: |
| 2202 | { |
| 2203 | unsigned long value; |
| 2204 | unsigned int nexthalf; |
| 2205 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); |
| 2206 | value = value << 16; |
| 2207 | nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL); |
| 2208 | /* Low bit still set. */ |
| 2209 | value |= nexthalf; |
| 2210 | offset = value; |
| 2211 | regx = -1; |
| 2212 | regy = -1; |
| 2213 | break; |
| 2214 | } |
| 2215 | default: |
| 2216 | internal_error (__FILE__, __LINE__, _("bad switch")); |
| 2217 | } |
| 2218 | upk->offset = offset; |
| 2219 | upk->regx = regx; |
| 2220 | upk->regy = regy; |
| 2221 | } |
| 2222 | |
| 2223 | |
| 2224 | /* Calculate the destination of a branch whose 16-bit opcode word is at PC, |
| 2225 | and having a signed 16-bit OFFSET. */ |
| 2226 | |
| 2227 | static CORE_ADDR |
| 2228 | add_offset_16 (CORE_ADDR pc, int offset) |
| 2229 | { |
| 2230 | return pc + (offset << 1) + 2; |
| 2231 | } |
| 2232 | |
| 2233 | static CORE_ADDR |
| 2234 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
| 2235 | unsigned int extension, unsigned int insn) |
| 2236 | { |
| 2237 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2238 | int op = (insn >> 11); |
| 2239 | switch (op) |
| 2240 | { |
| 2241 | case 2: /* Branch */ |
| 2242 | { |
| 2243 | struct upk_mips16 upk; |
| 2244 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
| 2245 | pc = add_offset_16 (pc, upk.offset); |
| 2246 | break; |
| 2247 | } |
| 2248 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
| 2249 | instructions. */ |
| 2250 | { |
| 2251 | struct upk_mips16 upk; |
| 2252 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
| 2253 | pc = ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)) | (upk.offset << 2); |
| 2254 | if ((insn >> 10) & 0x01) /* Exchange mode */ |
| 2255 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
| 2256 | else |
| 2257 | pc |= 0x01; |
| 2258 | break; |
| 2259 | } |
| 2260 | case 4: /* beqz */ |
| 2261 | { |
| 2262 | struct upk_mips16 upk; |
| 2263 | int reg; |
| 2264 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
| 2265 | reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]); |
| 2266 | if (reg == 0) |
| 2267 | pc = add_offset_16 (pc, upk.offset); |
| 2268 | else |
| 2269 | pc += 2; |
| 2270 | break; |
| 2271 | } |
| 2272 | case 5: /* bnez */ |
| 2273 | { |
| 2274 | struct upk_mips16 upk; |
| 2275 | int reg; |
| 2276 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
| 2277 | reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]); |
| 2278 | if (reg != 0) |
| 2279 | pc = add_offset_16 (pc, upk.offset); |
| 2280 | else |
| 2281 | pc += 2; |
| 2282 | break; |
| 2283 | } |
| 2284 | case 12: /* I8 Formats btez btnez */ |
| 2285 | { |
| 2286 | struct upk_mips16 upk; |
| 2287 | int reg; |
| 2288 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
| 2289 | /* upk.regx contains the opcode */ |
| 2290 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
| 2291 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
| 2292 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ |
| 2293 | pc = add_offset_16 (pc, upk.offset); |
| 2294 | else |
| 2295 | pc += 2; |
| 2296 | break; |
| 2297 | } |
| 2298 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
| 2299 | { |
| 2300 | struct upk_mips16 upk; |
| 2301 | /* upk.fmt = rrtype; */ |
| 2302 | op = insn & 0x1f; |
| 2303 | if (op == 0) |
| 2304 | { |
| 2305 | int reg; |
| 2306 | upk.regx = (insn >> 8) & 0x07; |
| 2307 | upk.regy = (insn >> 5) & 0x07; |
| 2308 | if ((upk.regy & 1) == 0) |
| 2309 | reg = mips_reg3_to_reg[upk.regx]; |
| 2310 | else |
| 2311 | reg = 31; /* Function return instruction. */ |
| 2312 | pc = get_frame_register_signed (frame, reg); |
| 2313 | } |
| 2314 | else |
| 2315 | pc += 2; |
| 2316 | break; |
| 2317 | } |
| 2318 | case 30: |
| 2319 | /* This is an instruction extension. Fetch the real instruction |
| 2320 | (which follows the extension) and decode things based on |
| 2321 | that. */ |
| 2322 | { |
| 2323 | pc += 2; |
| 2324 | pc = extended_mips16_next_pc (frame, pc, insn, |
| 2325 | fetch_mips_16 (gdbarch, pc)); |
| 2326 | break; |
| 2327 | } |
| 2328 | default: |
| 2329 | { |
| 2330 | pc += 2; |
| 2331 | break; |
| 2332 | } |
| 2333 | } |
| 2334 | return pc; |
| 2335 | } |
| 2336 | |
| 2337 | static CORE_ADDR |
| 2338 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
| 2339 | { |
| 2340 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2341 | unsigned int insn = fetch_mips_16 (gdbarch, pc); |
| 2342 | return extended_mips16_next_pc (frame, pc, 0, insn); |
| 2343 | } |
| 2344 | |
| 2345 | /* The mips_next_pc function supports single_step when the remote |
| 2346 | target monitor or stub is not developed enough to do a single_step. |
| 2347 | It works by decoding the current instruction and predicting where a |
| 2348 | branch will go. This isn't hard because all the data is available. |
| 2349 | The MIPS32, MIPS16 and microMIPS variants are quite different. */ |
| 2350 | static CORE_ADDR |
| 2351 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
| 2352 | { |
| 2353 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2354 | |
| 2355 | if (mips_pc_is_mips16 (gdbarch, pc)) |
| 2356 | return mips16_next_pc (frame, pc); |
| 2357 | else if (mips_pc_is_micromips (gdbarch, pc)) |
| 2358 | return micromips_next_pc (frame, pc); |
| 2359 | else |
| 2360 | return mips32_next_pc (frame, pc); |
| 2361 | } |
| 2362 | |
| 2363 | /* Return non-zero if the MIPS16 instruction INSN is a compact branch |
| 2364 | or jump. */ |
| 2365 | |
| 2366 | static int |
| 2367 | mips16_instruction_is_compact_branch (unsigned short insn) |
| 2368 | { |
| 2369 | switch (insn & 0xf800) |
| 2370 | { |
| 2371 | case 0xe800: |
| 2372 | return (insn & 0x009f) == 0x80; /* JALRC/JRC */ |
| 2373 | case 0x6000: |
| 2374 | return (insn & 0x0600) == 0; /* BTNEZ/BTEQZ */ |
| 2375 | case 0x2800: /* BNEZ */ |
| 2376 | case 0x2000: /* BEQZ */ |
| 2377 | case 0x1000: /* B */ |
| 2378 | return 1; |
| 2379 | default: |
| 2380 | return 0; |
| 2381 | } |
| 2382 | } |
| 2383 | |
| 2384 | /* Return non-zero if the microMIPS instruction INSN is a compact branch |
| 2385 | or jump. */ |
| 2386 | |
| 2387 | static int |
| 2388 | micromips_instruction_is_compact_branch (unsigned short insn) |
| 2389 | { |
| 2390 | switch (micromips_op (insn)) |
| 2391 | { |
| 2392 | case 0x11: /* POOL16C: bits 010001 */ |
| 2393 | return (b5s5_op (insn) == 0x18 |
| 2394 | /* JRADDIUSP: bits 010001 11000 */ |
| 2395 | || b5s5_op (insn) == 0xd); |
| 2396 | /* JRC: bits 010011 01101 */ |
| 2397 | case 0x10: /* POOL32I: bits 010000 */ |
| 2398 | return (b5s5_op (insn) & 0x1d) == 0x5; |
| 2399 | /* BEQZC/BNEZC: bits 010000 001x1 */ |
| 2400 | default: |
| 2401 | return 0; |
| 2402 | } |
| 2403 | } |
| 2404 | |
| 2405 | struct mips_frame_cache |
| 2406 | { |
| 2407 | CORE_ADDR base; |
| 2408 | struct trad_frame_saved_reg *saved_regs; |
| 2409 | }; |
| 2410 | |
| 2411 | /* Set a register's saved stack address in temp_saved_regs. If an |
| 2412 | address has already been set for this register, do nothing; this |
| 2413 | way we will only recognize the first save of a given register in a |
| 2414 | function prologue. |
| 2415 | |
| 2416 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
| 2417 | [gdbarch_num_regs .. 2*gdbarch_num_regs). |
| 2418 | Strictly speaking, only the second range is used as it is only second |
| 2419 | range (the ABI instead of ISA registers) that comes into play when finding |
| 2420 | saved registers in a frame. */ |
| 2421 | |
| 2422 | static void |
| 2423 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
| 2424 | int regnum, CORE_ADDR offset) |
| 2425 | { |
| 2426 | if (this_cache != NULL |
| 2427 | && this_cache->saved_regs[regnum].addr == -1) |
| 2428 | { |
| 2429 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
| 2430 | = offset; |
| 2431 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr |
| 2432 | = offset; |
| 2433 | } |
| 2434 | } |
| 2435 | |
| 2436 | |
| 2437 | /* Fetch the immediate value from a MIPS16 instruction. |
| 2438 | If the previous instruction was an EXTEND, use it to extend |
| 2439 | the upper bits of the immediate value. This is a helper function |
| 2440 | for mips16_scan_prologue. */ |
| 2441 | |
| 2442 | static int |
| 2443 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
| 2444 | unsigned short inst, /* current instruction */ |
| 2445 | int nbits, /* number of bits in imm field */ |
| 2446 | int scale, /* scale factor to be applied to imm */ |
| 2447 | int is_signed) /* is the imm field signed? */ |
| 2448 | { |
| 2449 | int offset; |
| 2450 | |
| 2451 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
| 2452 | { |
| 2453 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); |
| 2454 | if (offset & 0x8000) /* check for negative extend */ |
| 2455 | offset = 0 - (0x10000 - (offset & 0xffff)); |
| 2456 | return offset | (inst & 0x1f); |
| 2457 | } |
| 2458 | else |
| 2459 | { |
| 2460 | int max_imm = 1 << nbits; |
| 2461 | int mask = max_imm - 1; |
| 2462 | int sign_bit = max_imm >> 1; |
| 2463 | |
| 2464 | offset = inst & mask; |
| 2465 | if (is_signed && (offset & sign_bit)) |
| 2466 | offset = 0 - (max_imm - offset); |
| 2467 | return offset * scale; |
| 2468 | } |
| 2469 | } |
| 2470 | |
| 2471 | |
| 2472 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
| 2473 | the associated FRAME_CACHE if not null. |
| 2474 | Return the address of the first instruction past the prologue. */ |
| 2475 | |
| 2476 | static CORE_ADDR |
| 2477 | mips16_scan_prologue (struct gdbarch *gdbarch, |
| 2478 | CORE_ADDR start_pc, CORE_ADDR limit_pc, |
| 2479 | struct frame_info *this_frame, |
| 2480 | struct mips_frame_cache *this_cache) |
| 2481 | { |
| 2482 | int prev_non_prologue_insn = 0; |
| 2483 | int this_non_prologue_insn; |
| 2484 | int non_prologue_insns = 0; |
| 2485 | CORE_ADDR prev_pc; |
| 2486 | CORE_ADDR cur_pc; |
| 2487 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
| 2488 | CORE_ADDR sp; |
| 2489 | long frame_offset = 0; /* Size of stack frame. */ |
| 2490 | long frame_adjust = 0; /* Offset of FP from SP. */ |
| 2491 | int frame_reg = MIPS_SP_REGNUM; |
| 2492 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
| 2493 | unsigned inst = 0; /* current instruction */ |
| 2494 | unsigned entry_inst = 0; /* the entry instruction */ |
| 2495 | unsigned save_inst = 0; /* the save instruction */ |
| 2496 | int prev_delay_slot = 0; |
| 2497 | int in_delay_slot; |
| 2498 | int reg, offset; |
| 2499 | |
| 2500 | int extend_bytes = 0; |
| 2501 | int prev_extend_bytes = 0; |
| 2502 | CORE_ADDR end_prologue_addr; |
| 2503 | |
| 2504 | /* Can be called when there's no process, and hence when there's no |
| 2505 | THIS_FRAME. */ |
| 2506 | if (this_frame != NULL) |
| 2507 | sp = get_frame_register_signed (this_frame, |
| 2508 | gdbarch_num_regs (gdbarch) |
| 2509 | + MIPS_SP_REGNUM); |
| 2510 | else |
| 2511 | sp = 0; |
| 2512 | |
| 2513 | if (limit_pc > start_pc + 200) |
| 2514 | limit_pc = start_pc + 200; |
| 2515 | prev_pc = start_pc; |
| 2516 | |
| 2517 | /* Permit at most one non-prologue non-control-transfer instruction |
| 2518 | in the middle which may have been reordered by the compiler for |
| 2519 | optimisation. */ |
| 2520 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
| 2521 | { |
| 2522 | this_non_prologue_insn = 0; |
| 2523 | in_delay_slot = 0; |
| 2524 | |
| 2525 | /* Save the previous instruction. If it's an EXTEND, we'll extract |
| 2526 | the immediate offset extension from it in mips16_get_imm. */ |
| 2527 | prev_inst = inst; |
| 2528 | |
| 2529 | /* Fetch and decode the instruction. */ |
| 2530 | inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16, |
| 2531 | cur_pc, NULL); |
| 2532 | |
| 2533 | /* Normally we ignore extend instructions. However, if it is |
| 2534 | not followed by a valid prologue instruction, then this |
| 2535 | instruction is not part of the prologue either. We must |
| 2536 | remember in this case to adjust the end_prologue_addr back |
| 2537 | over the extend. */ |
| 2538 | if ((inst & 0xf800) == 0xf000) /* extend */ |
| 2539 | { |
| 2540 | extend_bytes = MIPS_INSN16_SIZE; |
| 2541 | continue; |
| 2542 | } |
| 2543 | |
| 2544 | prev_extend_bytes = extend_bytes; |
| 2545 | extend_bytes = 0; |
| 2546 | |
| 2547 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
| 2548 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
| 2549 | { |
| 2550 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); |
| 2551 | if (offset < 0) /* Negative stack adjustment? */ |
| 2552 | frame_offset -= offset; |
| 2553 | else |
| 2554 | /* Exit loop if a positive stack adjustment is found, which |
| 2555 | usually means that the stack cleanup code in the function |
| 2556 | epilogue is reached. */ |
| 2557 | break; |
| 2558 | } |
| 2559 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
| 2560 | { |
| 2561 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); |
| 2562 | reg = mips_reg3_to_reg[(inst & 0x700) >> 8]; |
| 2563 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
| 2564 | } |
| 2565 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
| 2566 | { |
| 2567 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); |
| 2568 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
| 2569 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
| 2570 | } |
| 2571 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ |
| 2572 | { |
| 2573 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); |
| 2574 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
| 2575 | } |
| 2576 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
| 2577 | { |
| 2578 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); |
| 2579 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
| 2580 | } |
| 2581 | else if (inst == 0x673d) /* move $s1, $sp */ |
| 2582 | { |
| 2583 | frame_addr = sp; |
| 2584 | frame_reg = 17; |
| 2585 | } |
| 2586 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ |
| 2587 | { |
| 2588 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); |
| 2589 | frame_addr = sp + offset; |
| 2590 | frame_reg = 17; |
| 2591 | frame_adjust = offset; |
| 2592 | } |
| 2593 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ |
| 2594 | { |
| 2595 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); |
| 2596 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
| 2597 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
| 2598 | } |
| 2599 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ |
| 2600 | { |
| 2601 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); |
| 2602 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
| 2603 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
| 2604 | } |
| 2605 | else if ((inst & 0xf81f) == 0xe809 |
| 2606 | && (inst & 0x700) != 0x700) /* entry */ |
| 2607 | entry_inst = inst; /* Save for later processing. */ |
| 2608 | else if ((inst & 0xff80) == 0x6480) /* save */ |
| 2609 | { |
| 2610 | save_inst = inst; /* Save for later processing. */ |
| 2611 | if (prev_extend_bytes) /* extend */ |
| 2612 | save_inst |= prev_inst << 16; |
| 2613 | } |
| 2614 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
| 2615 | { |
| 2616 | /* This instruction is part of the prologue, but we don't |
| 2617 | need to do anything special to handle it. */ |
| 2618 | } |
| 2619 | else if (mips16_instruction_has_delay_slot (inst, 0)) |
| 2620 | /* JAL/JALR/JALX/JR */ |
| 2621 | { |
| 2622 | /* The instruction in the delay slot can be a part |
| 2623 | of the prologue, so move forward once more. */ |
| 2624 | in_delay_slot = 1; |
| 2625 | if (mips16_instruction_has_delay_slot (inst, 1)) |
| 2626 | /* JAL/JALX */ |
| 2627 | { |
| 2628 | prev_extend_bytes = MIPS_INSN16_SIZE; |
| 2629 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
| 2630 | } |
| 2631 | } |
| 2632 | else |
| 2633 | { |
| 2634 | this_non_prologue_insn = 1; |
| 2635 | } |
| 2636 | |
| 2637 | non_prologue_insns += this_non_prologue_insn; |
| 2638 | |
| 2639 | /* A jump or branch, or enough non-prologue insns seen? If so, |
| 2640 | then we must have reached the end of the prologue by now. */ |
| 2641 | if (prev_delay_slot || non_prologue_insns > 1 |
| 2642 | || mips16_instruction_is_compact_branch (inst)) |
| 2643 | break; |
| 2644 | |
| 2645 | prev_non_prologue_insn = this_non_prologue_insn; |
| 2646 | prev_delay_slot = in_delay_slot; |
| 2647 | prev_pc = cur_pc - prev_extend_bytes; |
| 2648 | } |
| 2649 | |
| 2650 | /* The entry instruction is typically the first instruction in a function, |
| 2651 | and it stores registers at offsets relative to the value of the old SP |
| 2652 | (before the prologue). But the value of the sp parameter to this |
| 2653 | function is the new SP (after the prologue has been executed). So we |
| 2654 | can't calculate those offsets until we've seen the entire prologue, |
| 2655 | and can calculate what the old SP must have been. */ |
| 2656 | if (entry_inst != 0) |
| 2657 | { |
| 2658 | int areg_count = (entry_inst >> 8) & 7; |
| 2659 | int sreg_count = (entry_inst >> 6) & 3; |
| 2660 | |
| 2661 | /* The entry instruction always subtracts 32 from the SP. */ |
| 2662 | frame_offset += 32; |
| 2663 | |
| 2664 | /* Now we can calculate what the SP must have been at the |
| 2665 | start of the function prologue. */ |
| 2666 | sp += frame_offset; |
| 2667 | |
| 2668 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
| 2669 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) |
| 2670 | { |
| 2671 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
| 2672 | offset += mips_abi_regsize (gdbarch); |
| 2673 | } |
| 2674 | |
| 2675 | /* Check if the ra register was pushed on the stack. */ |
| 2676 | offset = -4; |
| 2677 | if (entry_inst & 0x20) |
| 2678 | { |
| 2679 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
| 2680 | offset -= mips_abi_regsize (gdbarch); |
| 2681 | } |
| 2682 | |
| 2683 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
| 2684 | for (reg = 16; reg < sreg_count + 16; reg++) |
| 2685 | { |
| 2686 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
| 2687 | offset -= mips_abi_regsize (gdbarch); |
| 2688 | } |
| 2689 | } |
| 2690 | |
| 2691 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
| 2692 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the |
| 2693 | size of the frame is specified as an immediate field of instruction |
| 2694 | and an extended variation exists which lets additional registers and |
| 2695 | frame space to be specified. The instruction always treats registers |
| 2696 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ |
| 2697 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) |
| 2698 | { |
| 2699 | static int args_table[16] = { |
| 2700 | 0, 0, 0, 0, 1, 1, 1, 1, |
| 2701 | 2, 2, 2, 0, 3, 3, 4, -1, |
| 2702 | }; |
| 2703 | static int astatic_table[16] = { |
| 2704 | 0, 1, 2, 3, 0, 1, 2, 3, |
| 2705 | 0, 1, 2, 4, 0, 1, 0, -1, |
| 2706 | }; |
| 2707 | int aregs = (save_inst >> 16) & 0xf; |
| 2708 | int xsregs = (save_inst >> 24) & 0x7; |
| 2709 | int args = args_table[aregs]; |
| 2710 | int astatic = astatic_table[aregs]; |
| 2711 | long frame_size; |
| 2712 | |
| 2713 | if (args < 0) |
| 2714 | { |
| 2715 | warning (_("Invalid number of argument registers encoded in SAVE.")); |
| 2716 | args = 0; |
| 2717 | } |
| 2718 | if (astatic < 0) |
| 2719 | { |
| 2720 | warning (_("Invalid number of static registers encoded in SAVE.")); |
| 2721 | astatic = 0; |
| 2722 | } |
| 2723 | |
| 2724 | /* For standard SAVE the frame size of 0 means 128. */ |
| 2725 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); |
| 2726 | if (frame_size == 0 && (save_inst >> 16) == 0) |
| 2727 | frame_size = 16; |
| 2728 | frame_size *= 8; |
| 2729 | frame_offset += frame_size; |
| 2730 | |
| 2731 | /* Now we can calculate what the SP must have been at the |
| 2732 | start of the function prologue. */ |
| 2733 | sp += frame_offset; |
| 2734 | |
| 2735 | /* Check if A0-A3 were saved in the caller's argument save area. */ |
| 2736 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) |
| 2737 | { |
| 2738 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
| 2739 | offset += mips_abi_regsize (gdbarch); |
| 2740 | } |
| 2741 | |
| 2742 | offset = -4; |
| 2743 | |
| 2744 | /* Check if the RA register was pushed on the stack. */ |
| 2745 | if (save_inst & 0x40) |
| 2746 | { |
| 2747 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
| 2748 | offset -= mips_abi_regsize (gdbarch); |
| 2749 | } |
| 2750 | |
| 2751 | /* Check if the S8 register was pushed on the stack. */ |
| 2752 | if (xsregs > 6) |
| 2753 | { |
| 2754 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
| 2755 | offset -= mips_abi_regsize (gdbarch); |
| 2756 | xsregs--; |
| 2757 | } |
| 2758 | /* Check if S2-S7 were pushed on the stack. */ |
| 2759 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) |
| 2760 | { |
| 2761 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
| 2762 | offset -= mips_abi_regsize (gdbarch); |
| 2763 | } |
| 2764 | |
| 2765 | /* Check if the S1 register was pushed on the stack. */ |
| 2766 | if (save_inst & 0x10) |
| 2767 | { |
| 2768 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
| 2769 | offset -= mips_abi_regsize (gdbarch); |
| 2770 | } |
| 2771 | /* Check if the S0 register was pushed on the stack. */ |
| 2772 | if (save_inst & 0x20) |
| 2773 | { |
| 2774 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
| 2775 | offset -= mips_abi_regsize (gdbarch); |
| 2776 | } |
| 2777 | |
| 2778 | /* Check if A0-A3 were pushed on the stack. */ |
| 2779 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) |
| 2780 | { |
| 2781 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
| 2782 | offset -= mips_abi_regsize (gdbarch); |
| 2783 | } |
| 2784 | } |
| 2785 | |
| 2786 | if (this_cache != NULL) |
| 2787 | { |
| 2788 | this_cache->base = |
| 2789 | (get_frame_register_signed (this_frame, |
| 2790 | gdbarch_num_regs (gdbarch) + frame_reg) |
| 2791 | + frame_offset - frame_adjust); |
| 2792 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should |
| 2793 | be able to get rid of the assignment below, evetually. But it's |
| 2794 | still needed for now. */ |
| 2795 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
| 2796 | + mips_regnum (gdbarch)->pc] |
| 2797 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; |
| 2798 | } |
| 2799 | |
| 2800 | /* Set end_prologue_addr to the address of the instruction immediately |
| 2801 | after the last one we scanned. Unless the last one looked like a |
| 2802 | non-prologue instruction (and we looked ahead), in which case use |
| 2803 | its address instead. */ |
| 2804 | end_prologue_addr = (prev_non_prologue_insn || prev_delay_slot |
| 2805 | ? prev_pc : cur_pc - prev_extend_bytes); |
| 2806 | |
| 2807 | return end_prologue_addr; |
| 2808 | } |
| 2809 | |
| 2810 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
| 2811 | Procedures that use the 32-bit instruction set are handled by the |
| 2812 | mips_insn32 unwinder. */ |
| 2813 | |
| 2814 | static struct mips_frame_cache * |
| 2815 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 2816 | { |
| 2817 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 2818 | struct mips_frame_cache *cache; |
| 2819 | |
| 2820 | if ((*this_cache) != NULL) |
| 2821 | return (struct mips_frame_cache *) (*this_cache); |
| 2822 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
| 2823 | (*this_cache) = cache; |
| 2824 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 2825 | |
| 2826 | /* Analyze the function prologue. */ |
| 2827 | { |
| 2828 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
| 2829 | CORE_ADDR start_addr; |
| 2830 | |
| 2831 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
| 2832 | if (start_addr == 0) |
| 2833 | start_addr = heuristic_proc_start (gdbarch, pc); |
| 2834 | /* We can't analyze the prologue if we couldn't find the begining |
| 2835 | of the function. */ |
| 2836 | if (start_addr == 0) |
| 2837 | return cache; |
| 2838 | |
| 2839 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, |
| 2840 | (struct mips_frame_cache *) *this_cache); |
| 2841 | } |
| 2842 | |
| 2843 | /* gdbarch_sp_regnum contains the value and not the address. */ |
| 2844 | trad_frame_set_value (cache->saved_regs, |
| 2845 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
| 2846 | cache->base); |
| 2847 | |
| 2848 | return (struct mips_frame_cache *) (*this_cache); |
| 2849 | } |
| 2850 | |
| 2851 | static void |
| 2852 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 2853 | struct frame_id *this_id) |
| 2854 | { |
| 2855 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
| 2856 | this_cache); |
| 2857 | /* This marks the outermost frame. */ |
| 2858 | if (info->base == 0) |
| 2859 | return; |
| 2860 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
| 2861 | } |
| 2862 | |
| 2863 | static struct value * |
| 2864 | mips_insn16_frame_prev_register (struct frame_info *this_frame, |
| 2865 | void **this_cache, int regnum) |
| 2866 | { |
| 2867 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
| 2868 | this_cache); |
| 2869 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
| 2870 | } |
| 2871 | |
| 2872 | static int |
| 2873 | mips_insn16_frame_sniffer (const struct frame_unwind *self, |
| 2874 | struct frame_info *this_frame, void **this_cache) |
| 2875 | { |
| 2876 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 2877 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 2878 | if (mips_pc_is_mips16 (gdbarch, pc)) |
| 2879 | return 1; |
| 2880 | return 0; |
| 2881 | } |
| 2882 | |
| 2883 | static const struct frame_unwind mips_insn16_frame_unwind = |
| 2884 | { |
| 2885 | NORMAL_FRAME, |
| 2886 | default_frame_unwind_stop_reason, |
| 2887 | mips_insn16_frame_this_id, |
| 2888 | mips_insn16_frame_prev_register, |
| 2889 | NULL, |
| 2890 | mips_insn16_frame_sniffer |
| 2891 | }; |
| 2892 | |
| 2893 | static CORE_ADDR |
| 2894 | mips_insn16_frame_base_address (struct frame_info *this_frame, |
| 2895 | void **this_cache) |
| 2896 | { |
| 2897 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
| 2898 | this_cache); |
| 2899 | return info->base; |
| 2900 | } |
| 2901 | |
| 2902 | static const struct frame_base mips_insn16_frame_base = |
| 2903 | { |
| 2904 | &mips_insn16_frame_unwind, |
| 2905 | mips_insn16_frame_base_address, |
| 2906 | mips_insn16_frame_base_address, |
| 2907 | mips_insn16_frame_base_address |
| 2908 | }; |
| 2909 | |
| 2910 | static const struct frame_base * |
| 2911 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) |
| 2912 | { |
| 2913 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 2914 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 2915 | if (mips_pc_is_mips16 (gdbarch, pc)) |
| 2916 | return &mips_insn16_frame_base; |
| 2917 | else |
| 2918 | return NULL; |
| 2919 | } |
| 2920 | |
| 2921 | /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped |
| 2922 | to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are |
| 2923 | interpreted directly, and then multiplied by 4. */ |
| 2924 | |
| 2925 | static int |
| 2926 | micromips_decode_imm9 (int imm) |
| 2927 | { |
| 2928 | imm = (imm ^ 0x100) - 0x100; |
| 2929 | if (imm > -3 && imm < 2) |
| 2930 | imm ^= 0x100; |
| 2931 | return imm << 2; |
| 2932 | } |
| 2933 | |
| 2934 | /* Analyze the function prologue from START_PC to LIMIT_PC. Return |
| 2935 | the address of the first instruction past the prologue. */ |
| 2936 | |
| 2937 | static CORE_ADDR |
| 2938 | micromips_scan_prologue (struct gdbarch *gdbarch, |
| 2939 | CORE_ADDR start_pc, CORE_ADDR limit_pc, |
| 2940 | struct frame_info *this_frame, |
| 2941 | struct mips_frame_cache *this_cache) |
| 2942 | { |
| 2943 | CORE_ADDR end_prologue_addr; |
| 2944 | int prev_non_prologue_insn = 0; |
| 2945 | int frame_reg = MIPS_SP_REGNUM; |
| 2946 | int this_non_prologue_insn; |
| 2947 | int non_prologue_insns = 0; |
| 2948 | long frame_offset = 0; /* Size of stack frame. */ |
| 2949 | long frame_adjust = 0; /* Offset of FP from SP. */ |
| 2950 | CORE_ADDR frame_addr = 0; /* Value of $30, used as frame pointer. */ |
| 2951 | int prev_delay_slot = 0; |
| 2952 | int in_delay_slot; |
| 2953 | CORE_ADDR prev_pc; |
| 2954 | CORE_ADDR cur_pc; |
| 2955 | ULONGEST insn; /* current instruction */ |
| 2956 | CORE_ADDR sp; |
| 2957 | long offset; |
| 2958 | long sp_adj; |
| 2959 | long v1_off = 0; /* The assumption is LUI will replace it. */ |
| 2960 | int reglist; |
| 2961 | int breg; |
| 2962 | int dreg; |
| 2963 | int sreg; |
| 2964 | int treg; |
| 2965 | int loc; |
| 2966 | int op; |
| 2967 | int s; |
| 2968 | int i; |
| 2969 | |
| 2970 | /* Can be called when there's no process, and hence when there's no |
| 2971 | THIS_FRAME. */ |
| 2972 | if (this_frame != NULL) |
| 2973 | sp = get_frame_register_signed (this_frame, |
| 2974 | gdbarch_num_regs (gdbarch) |
| 2975 | + MIPS_SP_REGNUM); |
| 2976 | else |
| 2977 | sp = 0; |
| 2978 | |
| 2979 | if (limit_pc > start_pc + 200) |
| 2980 | limit_pc = start_pc + 200; |
| 2981 | prev_pc = start_pc; |
| 2982 | |
| 2983 | /* Permit at most one non-prologue non-control-transfer instruction |
| 2984 | in the middle which may have been reordered by the compiler for |
| 2985 | optimisation. */ |
| 2986 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc) |
| 2987 | { |
| 2988 | this_non_prologue_insn = 0; |
| 2989 | in_delay_slot = 0; |
| 2990 | sp_adj = 0; |
| 2991 | loc = 0; |
| 2992 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL); |
| 2993 | loc += MIPS_INSN16_SIZE; |
| 2994 | switch (mips_insn_size (ISA_MICROMIPS, insn)) |
| 2995 | { |
| 2996 | /* 48-bit instructions. */ |
| 2997 | case 3 * MIPS_INSN16_SIZE: |
| 2998 | /* No prologue instructions in this category. */ |
| 2999 | this_non_prologue_insn = 1; |
| 3000 | loc += 2 * MIPS_INSN16_SIZE; |
| 3001 | break; |
| 3002 | |
| 3003 | /* 32-bit instructions. */ |
| 3004 | case 2 * MIPS_INSN16_SIZE: |
| 3005 | insn <<= 16; |
| 3006 | insn |= mips_fetch_instruction (gdbarch, |
| 3007 | ISA_MICROMIPS, cur_pc + loc, NULL); |
| 3008 | loc += MIPS_INSN16_SIZE; |
| 3009 | switch (micromips_op (insn >> 16)) |
| 3010 | { |
| 3011 | /* Record $sp/$fp adjustment. */ |
| 3012 | /* Discard (D)ADDU $gp,$jp used for PIC code. */ |
| 3013 | case 0x0: /* POOL32A: bits 000000 */ |
| 3014 | case 0x16: /* POOL32S: bits 010110 */ |
| 3015 | op = b0s11_op (insn); |
| 3016 | sreg = b0s5_reg (insn >> 16); |
| 3017 | treg = b5s5_reg (insn >> 16); |
| 3018 | dreg = b11s5_reg (insn); |
| 3019 | if (op == 0x1d0 |
| 3020 | /* SUBU: bits 000000 00111010000 */ |
| 3021 | /* DSUBU: bits 010110 00111010000 */ |
| 3022 | && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM |
| 3023 | && treg == 3) |
| 3024 | /* (D)SUBU $sp, $v1 */ |
| 3025 | sp_adj = v1_off; |
| 3026 | else if (op != 0x150 |
| 3027 | /* ADDU: bits 000000 00101010000 */ |
| 3028 | /* DADDU: bits 010110 00101010000 */ |
| 3029 | || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM) |
| 3030 | this_non_prologue_insn = 1; |
| 3031 | break; |
| 3032 | |
| 3033 | case 0x8: /* POOL32B: bits 001000 */ |
| 3034 | op = b12s4_op (insn); |
| 3035 | breg = b0s5_reg (insn >> 16); |
| 3036 | reglist = sreg = b5s5_reg (insn >> 16); |
| 3037 | offset = (b0s12_imm (insn) ^ 0x800) - 0x800; |
| 3038 | if ((op == 0x9 || op == 0xc) |
| 3039 | /* SWP: bits 001000 1001 */ |
| 3040 | /* SDP: bits 001000 1100 */ |
| 3041 | && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM) |
| 3042 | /* S[DW]P reg,offset($sp) */ |
| 3043 | { |
| 3044 | s = 4 << ((b12s4_op (insn) & 0x4) == 0x4); |
| 3045 | set_reg_offset (gdbarch, this_cache, |
| 3046 | sreg, sp + offset); |
| 3047 | set_reg_offset (gdbarch, this_cache, |
| 3048 | sreg + 1, sp + offset + s); |
| 3049 | } |
| 3050 | else if ((op == 0xd || op == 0xf) |
| 3051 | /* SWM: bits 001000 1101 */ |
| 3052 | /* SDM: bits 001000 1111 */ |
| 3053 | && breg == MIPS_SP_REGNUM |
| 3054 | /* SWM reglist,offset($sp) */ |
| 3055 | && ((reglist >= 1 && reglist <= 9) |
| 3056 | || (reglist >= 16 && reglist <= 25))) |
| 3057 | { |
| 3058 | int sreglist = min(reglist & 0xf, 8); |
| 3059 | |
| 3060 | s = 4 << ((b12s4_op (insn) & 0x2) == 0x2); |
| 3061 | for (i = 0; i < sreglist; i++) |
| 3062 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i); |
| 3063 | if ((reglist & 0xf) > 8) |
| 3064 | set_reg_offset (gdbarch, this_cache, 30, sp + s * i++); |
| 3065 | if ((reglist & 0x10) == 0x10) |
| 3066 | set_reg_offset (gdbarch, this_cache, |
| 3067 | MIPS_RA_REGNUM, sp + s * i++); |
| 3068 | } |
| 3069 | else |
| 3070 | this_non_prologue_insn = 1; |
| 3071 | break; |
| 3072 | |
| 3073 | /* Record $sp/$fp adjustment. */ |
| 3074 | /* Discard (D)ADDIU $gp used for PIC code. */ |
| 3075 | case 0xc: /* ADDIU: bits 001100 */ |
| 3076 | case 0x17: /* DADDIU: bits 010111 */ |
| 3077 | sreg = b0s5_reg (insn >> 16); |
| 3078 | dreg = b5s5_reg (insn >> 16); |
| 3079 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; |
| 3080 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM) |
| 3081 | /* (D)ADDIU $sp, imm */ |
| 3082 | sp_adj = offset; |
| 3083 | else if (sreg == MIPS_SP_REGNUM && dreg == 30) |
| 3084 | /* (D)ADDIU $fp, $sp, imm */ |
| 3085 | { |
| 3086 | frame_addr = sp + offset; |
| 3087 | frame_adjust = offset; |
| 3088 | frame_reg = 30; |
| 3089 | } |
| 3090 | else if (sreg != 28 || dreg != 28) |
| 3091 | /* (D)ADDIU $gp, imm */ |
| 3092 | this_non_prologue_insn = 1; |
| 3093 | break; |
| 3094 | |
| 3095 | /* LUI $v1 is used for larger $sp adjustments. */ |
| 3096 | /* Discard LUI $gp used for PIC code. */ |
| 3097 | case 0x10: /* POOL32I: bits 010000 */ |
| 3098 | if (b5s5_op (insn >> 16) == 0xd |
| 3099 | /* LUI: bits 010000 001101 */ |
| 3100 | && b0s5_reg (insn >> 16) == 3) |
| 3101 | /* LUI $v1, imm */ |
| 3102 | v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000; |
| 3103 | else if (b5s5_op (insn >> 16) != 0xd |
| 3104 | /* LUI: bits 010000 001101 */ |
| 3105 | || b0s5_reg (insn >> 16) != 28) |
| 3106 | /* LUI $gp, imm */ |
| 3107 | this_non_prologue_insn = 1; |
| 3108 | break; |
| 3109 | |
| 3110 | /* ORI $v1 is used for larger $sp adjustments. */ |
| 3111 | case 0x14: /* ORI: bits 010100 */ |
| 3112 | sreg = b0s5_reg (insn >> 16); |
| 3113 | dreg = b5s5_reg (insn >> 16); |
| 3114 | if (sreg == 3 && dreg == 3) |
| 3115 | /* ORI $v1, imm */ |
| 3116 | v1_off |= b0s16_imm (insn); |
| 3117 | else |
| 3118 | this_non_prologue_insn = 1; |
| 3119 | break; |
| 3120 | |
| 3121 | case 0x26: /* SWC1: bits 100110 */ |
| 3122 | case 0x2e: /* SDC1: bits 101110 */ |
| 3123 | breg = b0s5_reg (insn >> 16); |
| 3124 | if (breg != MIPS_SP_REGNUM) |
| 3125 | /* S[DW]C1 reg,offset($sp) */ |
| 3126 | this_non_prologue_insn = 1; |
| 3127 | break; |
| 3128 | |
| 3129 | case 0x36: /* SD: bits 110110 */ |
| 3130 | case 0x3e: /* SW: bits 111110 */ |
| 3131 | breg = b0s5_reg (insn >> 16); |
| 3132 | sreg = b5s5_reg (insn >> 16); |
| 3133 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; |
| 3134 | if (breg == MIPS_SP_REGNUM) |
| 3135 | /* S[DW] reg,offset($sp) */ |
| 3136 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); |
| 3137 | else |
| 3138 | this_non_prologue_insn = 1; |
| 3139 | break; |
| 3140 | |
| 3141 | default: |
| 3142 | /* The instruction in the delay slot can be a part |
| 3143 | of the prologue, so move forward once more. */ |
| 3144 | if (micromips_instruction_has_delay_slot (insn, 0)) |
| 3145 | in_delay_slot = 1; |
| 3146 | else |
| 3147 | this_non_prologue_insn = 1; |
| 3148 | break; |
| 3149 | } |
| 3150 | insn >>= 16; |
| 3151 | break; |
| 3152 | |
| 3153 | /* 16-bit instructions. */ |
| 3154 | case MIPS_INSN16_SIZE: |
| 3155 | switch (micromips_op (insn)) |
| 3156 | { |
| 3157 | case 0x3: /* MOVE: bits 000011 */ |
| 3158 | sreg = b0s5_reg (insn); |
| 3159 | dreg = b5s5_reg (insn); |
| 3160 | if (sreg == MIPS_SP_REGNUM && dreg == 30) |
| 3161 | /* MOVE $fp, $sp */ |
| 3162 | { |
| 3163 | frame_addr = sp; |
| 3164 | frame_reg = 30; |
| 3165 | } |
| 3166 | else if ((sreg & 0x1c) != 0x4) |
| 3167 | /* MOVE reg, $a0-$a3 */ |
| 3168 | this_non_prologue_insn = 1; |
| 3169 | break; |
| 3170 | |
| 3171 | case 0x11: /* POOL16C: bits 010001 */ |
| 3172 | if (b6s4_op (insn) == 0x5) |
| 3173 | /* SWM: bits 010001 0101 */ |
| 3174 | { |
| 3175 | offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20; |
| 3176 | reglist = b4s2_regl (insn); |
| 3177 | for (i = 0; i <= reglist; i++) |
| 3178 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i); |
| 3179 | set_reg_offset (gdbarch, this_cache, |
| 3180 | MIPS_RA_REGNUM, sp + 4 * i++); |
| 3181 | } |
| 3182 | else |
| 3183 | this_non_prologue_insn = 1; |
| 3184 | break; |
| 3185 | |
| 3186 | case 0x13: /* POOL16D: bits 010011 */ |
| 3187 | if ((insn & 0x1) == 0x1) |
| 3188 | /* ADDIUSP: bits 010011 1 */ |
| 3189 | sp_adj = micromips_decode_imm9 (b1s9_imm (insn)); |
| 3190 | else if (b5s5_reg (insn) == MIPS_SP_REGNUM) |
| 3191 | /* ADDIUS5: bits 010011 0 */ |
| 3192 | /* ADDIUS5 $sp, imm */ |
| 3193 | sp_adj = (b1s4_imm (insn) ^ 8) - 8; |
| 3194 | else |
| 3195 | this_non_prologue_insn = 1; |
| 3196 | break; |
| 3197 | |
| 3198 | case 0x32: /* SWSP: bits 110010 */ |
| 3199 | offset = b0s5_imm (insn) << 2; |
| 3200 | sreg = b5s5_reg (insn); |
| 3201 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); |
| 3202 | break; |
| 3203 | |
| 3204 | default: |
| 3205 | /* The instruction in the delay slot can be a part |
| 3206 | of the prologue, so move forward once more. */ |
| 3207 | if (micromips_instruction_has_delay_slot (insn << 16, 0)) |
| 3208 | in_delay_slot = 1; |
| 3209 | else |
| 3210 | this_non_prologue_insn = 1; |
| 3211 | break; |
| 3212 | } |
| 3213 | break; |
| 3214 | } |
| 3215 | if (sp_adj < 0) |
| 3216 | frame_offset -= sp_adj; |
| 3217 | |
| 3218 | non_prologue_insns += this_non_prologue_insn; |
| 3219 | |
| 3220 | /* A jump or branch, enough non-prologue insns seen or positive |
| 3221 | stack adjustment? If so, then we must have reached the end |
| 3222 | of the prologue by now. */ |
| 3223 | if (prev_delay_slot || non_prologue_insns > 1 || sp_adj > 0 |
| 3224 | || micromips_instruction_is_compact_branch (insn)) |
| 3225 | break; |
| 3226 | |
| 3227 | prev_non_prologue_insn = this_non_prologue_insn; |
| 3228 | prev_delay_slot = in_delay_slot; |
| 3229 | prev_pc = cur_pc; |
| 3230 | } |
| 3231 | |
| 3232 | if (this_cache != NULL) |
| 3233 | { |
| 3234 | this_cache->base = |
| 3235 | (get_frame_register_signed (this_frame, |
| 3236 | gdbarch_num_regs (gdbarch) + frame_reg) |
| 3237 | + frame_offset - frame_adjust); |
| 3238 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should |
| 3239 | be able to get rid of the assignment below, evetually. But it's |
| 3240 | still needed for now. */ |
| 3241 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
| 3242 | + mips_regnum (gdbarch)->pc] |
| 3243 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; |
| 3244 | } |
| 3245 | |
| 3246 | /* Set end_prologue_addr to the address of the instruction immediately |
| 3247 | after the last one we scanned. Unless the last one looked like a |
| 3248 | non-prologue instruction (and we looked ahead), in which case use |
| 3249 | its address instead. */ |
| 3250 | end_prologue_addr |
| 3251 | = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; |
| 3252 | |
| 3253 | return end_prologue_addr; |
| 3254 | } |
| 3255 | |
| 3256 | /* Heuristic unwinder for procedures using microMIPS instructions. |
| 3257 | Procedures that use the 32-bit instruction set are handled by the |
| 3258 | mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */ |
| 3259 | |
| 3260 | static struct mips_frame_cache * |
| 3261 | mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 3262 | { |
| 3263 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 3264 | struct mips_frame_cache *cache; |
| 3265 | |
| 3266 | if ((*this_cache) != NULL) |
| 3267 | return (struct mips_frame_cache *) (*this_cache); |
| 3268 | |
| 3269 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
| 3270 | (*this_cache) = cache; |
| 3271 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 3272 | |
| 3273 | /* Analyze the function prologue. */ |
| 3274 | { |
| 3275 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
| 3276 | CORE_ADDR start_addr; |
| 3277 | |
| 3278 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
| 3279 | if (start_addr == 0) |
| 3280 | start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
| 3281 | /* We can't analyze the prologue if we couldn't find the begining |
| 3282 | of the function. */ |
| 3283 | if (start_addr == 0) |
| 3284 | return cache; |
| 3285 | |
| 3286 | micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, |
| 3287 | (struct mips_frame_cache *) *this_cache); |
| 3288 | } |
| 3289 | |
| 3290 | /* gdbarch_sp_regnum contains the value and not the address. */ |
| 3291 | trad_frame_set_value (cache->saved_regs, |
| 3292 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
| 3293 | cache->base); |
| 3294 | |
| 3295 | return (struct mips_frame_cache *) (*this_cache); |
| 3296 | } |
| 3297 | |
| 3298 | static void |
| 3299 | mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 3300 | struct frame_id *this_id) |
| 3301 | { |
| 3302 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
| 3303 | this_cache); |
| 3304 | /* This marks the outermost frame. */ |
| 3305 | if (info->base == 0) |
| 3306 | return; |
| 3307 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
| 3308 | } |
| 3309 | |
| 3310 | static struct value * |
| 3311 | mips_micro_frame_prev_register (struct frame_info *this_frame, |
| 3312 | void **this_cache, int regnum) |
| 3313 | { |
| 3314 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
| 3315 | this_cache); |
| 3316 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
| 3317 | } |
| 3318 | |
| 3319 | static int |
| 3320 | mips_micro_frame_sniffer (const struct frame_unwind *self, |
| 3321 | struct frame_info *this_frame, void **this_cache) |
| 3322 | { |
| 3323 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 3324 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 3325 | |
| 3326 | if (mips_pc_is_micromips (gdbarch, pc)) |
| 3327 | return 1; |
| 3328 | return 0; |
| 3329 | } |
| 3330 | |
| 3331 | static const struct frame_unwind mips_micro_frame_unwind = |
| 3332 | { |
| 3333 | NORMAL_FRAME, |
| 3334 | default_frame_unwind_stop_reason, |
| 3335 | mips_micro_frame_this_id, |
| 3336 | mips_micro_frame_prev_register, |
| 3337 | NULL, |
| 3338 | mips_micro_frame_sniffer |
| 3339 | }; |
| 3340 | |
| 3341 | static CORE_ADDR |
| 3342 | mips_micro_frame_base_address (struct frame_info *this_frame, |
| 3343 | void **this_cache) |
| 3344 | { |
| 3345 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
| 3346 | this_cache); |
| 3347 | return info->base; |
| 3348 | } |
| 3349 | |
| 3350 | static const struct frame_base mips_micro_frame_base = |
| 3351 | { |
| 3352 | &mips_micro_frame_unwind, |
| 3353 | mips_micro_frame_base_address, |
| 3354 | mips_micro_frame_base_address, |
| 3355 | mips_micro_frame_base_address |
| 3356 | }; |
| 3357 | |
| 3358 | static const struct frame_base * |
| 3359 | mips_micro_frame_base_sniffer (struct frame_info *this_frame) |
| 3360 | { |
| 3361 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 3362 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 3363 | |
| 3364 | if (mips_pc_is_micromips (gdbarch, pc)) |
| 3365 | return &mips_micro_frame_base; |
| 3366 | else |
| 3367 | return NULL; |
| 3368 | } |
| 3369 | |
| 3370 | /* Mark all the registers as unset in the saved_regs array |
| 3371 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ |
| 3372 | |
| 3373 | static void |
| 3374 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) |
| 3375 | { |
| 3376 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
| 3377 | return; |
| 3378 | |
| 3379 | { |
| 3380 | const int num_regs = gdbarch_num_regs (gdbarch); |
| 3381 | int i; |
| 3382 | |
| 3383 | for (i = 0; i < num_regs; i++) |
| 3384 | { |
| 3385 | this_cache->saved_regs[i].addr = -1; |
| 3386 | } |
| 3387 | } |
| 3388 | } |
| 3389 | |
| 3390 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
| 3391 | the associated FRAME_CACHE if not null. |
| 3392 | Return the address of the first instruction past the prologue. */ |
| 3393 | |
| 3394 | static CORE_ADDR |
| 3395 | mips32_scan_prologue (struct gdbarch *gdbarch, |
| 3396 | CORE_ADDR start_pc, CORE_ADDR limit_pc, |
| 3397 | struct frame_info *this_frame, |
| 3398 | struct mips_frame_cache *this_cache) |
| 3399 | { |
| 3400 | int prev_non_prologue_insn; |
| 3401 | int this_non_prologue_insn; |
| 3402 | int non_prologue_insns; |
| 3403 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
| 3404 | frame-pointer. */ |
| 3405 | int prev_delay_slot; |
| 3406 | CORE_ADDR prev_pc; |
| 3407 | CORE_ADDR cur_pc; |
| 3408 | CORE_ADDR sp; |
| 3409 | long frame_offset; |
| 3410 | int frame_reg = MIPS_SP_REGNUM; |
| 3411 | |
| 3412 | CORE_ADDR end_prologue_addr; |
| 3413 | int seen_sp_adjust = 0; |
| 3414 | int load_immediate_bytes = 0; |
| 3415 | int in_delay_slot; |
| 3416 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
| 3417 | |
| 3418 | /* Can be called when there's no process, and hence when there's no |
| 3419 | THIS_FRAME. */ |
| 3420 | if (this_frame != NULL) |
| 3421 | sp = get_frame_register_signed (this_frame, |
| 3422 | gdbarch_num_regs (gdbarch) |
| 3423 | + MIPS_SP_REGNUM); |
| 3424 | else |
| 3425 | sp = 0; |
| 3426 | |
| 3427 | if (limit_pc > start_pc + 200) |
| 3428 | limit_pc = start_pc + 200; |
| 3429 | |
| 3430 | restart: |
| 3431 | prev_non_prologue_insn = 0; |
| 3432 | non_prologue_insns = 0; |
| 3433 | prev_delay_slot = 0; |
| 3434 | prev_pc = start_pc; |
| 3435 | |
| 3436 | /* Permit at most one non-prologue non-control-transfer instruction |
| 3437 | in the middle which may have been reordered by the compiler for |
| 3438 | optimisation. */ |
| 3439 | frame_offset = 0; |
| 3440 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
| 3441 | { |
| 3442 | unsigned long inst, high_word; |
| 3443 | long offset; |
| 3444 | int reg; |
| 3445 | |
| 3446 | this_non_prologue_insn = 0; |
| 3447 | in_delay_slot = 0; |
| 3448 | |
| 3449 | /* Fetch the instruction. */ |
| 3450 | inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS, |
| 3451 | cur_pc, NULL); |
| 3452 | |
| 3453 | /* Save some code by pre-extracting some useful fields. */ |
| 3454 | high_word = (inst >> 16) & 0xffff; |
| 3455 | offset = ((inst & 0xffff) ^ 0x8000) - 0x8000; |
| 3456 | reg = high_word & 0x1f; |
| 3457 | |
| 3458 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
| 3459 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
| 3460 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ |
| 3461 | { |
| 3462 | if (offset < 0) /* Negative stack adjustment? */ |
| 3463 | frame_offset -= offset; |
| 3464 | else |
| 3465 | /* Exit loop if a positive stack adjustment is found, which |
| 3466 | usually means that the stack cleanup code in the function |
| 3467 | epilogue is reached. */ |
| 3468 | break; |
| 3469 | seen_sp_adjust = 1; |
| 3470 | } |
| 3471 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
| 3472 | && !regsize_is_64_bits) |
| 3473 | { |
| 3474 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
| 3475 | } |
| 3476 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
| 3477 | && regsize_is_64_bits) |
| 3478 | { |
| 3479 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ |
| 3480 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
| 3481 | } |
| 3482 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
| 3483 | { |
| 3484 | /* Old gcc frame, r30 is virtual frame pointer. */ |
| 3485 | if (offset != frame_offset) |
| 3486 | frame_addr = sp + offset; |
| 3487 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
| 3488 | { |
| 3489 | unsigned alloca_adjust; |
| 3490 | |
| 3491 | frame_reg = 30; |
| 3492 | frame_addr = get_frame_register_signed |
| 3493 | (this_frame, gdbarch_num_regs (gdbarch) + 30); |
| 3494 | frame_offset = 0; |
| 3495 | |
| 3496 | alloca_adjust = (unsigned) (frame_addr - (sp + offset)); |
| 3497 | if (alloca_adjust > 0) |
| 3498 | { |
| 3499 | /* FP > SP + frame_size. This may be because of |
| 3500 | an alloca or somethings similar. Fix sp to |
| 3501 | "pre-alloca" value, and try again. */ |
| 3502 | sp += alloca_adjust; |
| 3503 | /* Need to reset the status of all registers. Otherwise, |
| 3504 | we will hit a guard that prevents the new address |
| 3505 | for each register to be recomputed during the second |
| 3506 | pass. */ |
| 3507 | reset_saved_regs (gdbarch, this_cache); |
| 3508 | goto restart; |
| 3509 | } |
| 3510 | } |
| 3511 | } |
| 3512 | /* move $30,$sp. With different versions of gas this will be either |
| 3513 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. |
| 3514 | Accept any one of these. */ |
| 3515 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
| 3516 | { |
| 3517 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ |
| 3518 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
| 3519 | { |
| 3520 | unsigned alloca_adjust; |
| 3521 | |
| 3522 | frame_reg = 30; |
| 3523 | frame_addr = get_frame_register_signed |
| 3524 | (this_frame, gdbarch_num_regs (gdbarch) + 30); |
| 3525 | |
| 3526 | alloca_adjust = (unsigned) (frame_addr - sp); |
| 3527 | if (alloca_adjust > 0) |
| 3528 | { |
| 3529 | /* FP > SP + frame_size. This may be because of |
| 3530 | an alloca or somethings similar. Fix sp to |
| 3531 | "pre-alloca" value, and try again. */ |
| 3532 | sp = frame_addr; |
| 3533 | /* Need to reset the status of all registers. Otherwise, |
| 3534 | we will hit a guard that prevents the new address |
| 3535 | for each register to be recomputed during the second |
| 3536 | pass. */ |
| 3537 | reset_saved_regs (gdbarch, this_cache); |
| 3538 | goto restart; |
| 3539 | } |
| 3540 | } |
| 3541 | } |
| 3542 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
| 3543 | && !regsize_is_64_bits) |
| 3544 | { |
| 3545 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
| 3546 | } |
| 3547 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ |
| 3548 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ |
| 3549 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ |
| 3550 | || high_word == 0x3c1c /* lui $gp,n */ |
| 3551 | || high_word == 0x279c /* addiu $gp,$gp,n */ |
| 3552 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ |
| 3553 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ |
| 3554 | ) |
| 3555 | { |
| 3556 | /* These instructions are part of the prologue, but we don't |
| 3557 | need to do anything special to handle them. */ |
| 3558 | } |
| 3559 | /* The instructions below load $at or $t0 with an immediate |
| 3560 | value in preparation for a stack adjustment via |
| 3561 | subu $sp,$sp,[$at,$t0]. These instructions could also |
| 3562 | initialize a local variable, so we accept them only before |
| 3563 | a stack adjustment instruction was seen. */ |
| 3564 | else if (!seen_sp_adjust |
| 3565 | && !prev_delay_slot |
| 3566 | && (high_word == 0x3c01 /* lui $at,n */ |
| 3567 | || high_word == 0x3c08 /* lui $t0,n */ |
| 3568 | || high_word == 0x3421 /* ori $at,$at,n */ |
| 3569 | || high_word == 0x3508 /* ori $t0,$t0,n */ |
| 3570 | || high_word == 0x3401 /* ori $at,$zero,n */ |
| 3571 | || high_word == 0x3408 /* ori $t0,$zero,n */ |
| 3572 | )) |
| 3573 | { |
| 3574 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
| 3575 | } |
| 3576 | /* Check for branches and jumps. The instruction in the delay |
| 3577 | slot can be a part of the prologue, so move forward once more. */ |
| 3578 | else if (mips32_instruction_has_delay_slot (gdbarch, inst)) |
| 3579 | { |
| 3580 | in_delay_slot = 1; |
| 3581 | } |
| 3582 | /* This instruction is not an instruction typically found |
| 3583 | in a prologue, so we must have reached the end of the |
| 3584 | prologue. */ |
| 3585 | else |
| 3586 | { |
| 3587 | this_non_prologue_insn = 1; |
| 3588 | } |
| 3589 | |
| 3590 | non_prologue_insns += this_non_prologue_insn; |
| 3591 | |
| 3592 | /* A jump or branch, or enough non-prologue insns seen? If so, |
| 3593 | then we must have reached the end of the prologue by now. */ |
| 3594 | if (prev_delay_slot || non_prologue_insns > 1) |
| 3595 | break; |
| 3596 | |
| 3597 | prev_non_prologue_insn = this_non_prologue_insn; |
| 3598 | prev_delay_slot = in_delay_slot; |
| 3599 | prev_pc = cur_pc; |
| 3600 | } |
| 3601 | |
| 3602 | if (this_cache != NULL) |
| 3603 | { |
| 3604 | this_cache->base = |
| 3605 | (get_frame_register_signed (this_frame, |
| 3606 | gdbarch_num_regs (gdbarch) + frame_reg) |
| 3607 | + frame_offset); |
| 3608 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of |
| 3609 | this assignment below, eventually. But it's still needed |
| 3610 | for now. */ |
| 3611 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
| 3612 | + mips_regnum (gdbarch)->pc] |
| 3613 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
| 3614 | + MIPS_RA_REGNUM]; |
| 3615 | } |
| 3616 | |
| 3617 | /* Set end_prologue_addr to the address of the instruction immediately |
| 3618 | after the last one we scanned. Unless the last one looked like a |
| 3619 | non-prologue instruction (and we looked ahead), in which case use |
| 3620 | its address instead. */ |
| 3621 | end_prologue_addr |
| 3622 | = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; |
| 3623 | |
| 3624 | /* In a frameless function, we might have incorrectly |
| 3625 | skipped some load immediate instructions. Undo the skipping |
| 3626 | if the load immediate was not followed by a stack adjustment. */ |
| 3627 | if (load_immediate_bytes && !seen_sp_adjust) |
| 3628 | end_prologue_addr -= load_immediate_bytes; |
| 3629 | |
| 3630 | return end_prologue_addr; |
| 3631 | } |
| 3632 | |
| 3633 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
| 3634 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit |
| 3635 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 |
| 3636 | unwinder. Likewise microMIPS and the mips_micro unwinder. */ |
| 3637 | |
| 3638 | static struct mips_frame_cache * |
| 3639 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 3640 | { |
| 3641 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 3642 | struct mips_frame_cache *cache; |
| 3643 | |
| 3644 | if ((*this_cache) != NULL) |
| 3645 | return (struct mips_frame_cache *) (*this_cache); |
| 3646 | |
| 3647 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
| 3648 | (*this_cache) = cache; |
| 3649 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 3650 | |
| 3651 | /* Analyze the function prologue. */ |
| 3652 | { |
| 3653 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
| 3654 | CORE_ADDR start_addr; |
| 3655 | |
| 3656 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
| 3657 | if (start_addr == 0) |
| 3658 | start_addr = heuristic_proc_start (gdbarch, pc); |
| 3659 | /* We can't analyze the prologue if we couldn't find the begining |
| 3660 | of the function. */ |
| 3661 | if (start_addr == 0) |
| 3662 | return cache; |
| 3663 | |
| 3664 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, |
| 3665 | (struct mips_frame_cache *) *this_cache); |
| 3666 | } |
| 3667 | |
| 3668 | /* gdbarch_sp_regnum contains the value and not the address. */ |
| 3669 | trad_frame_set_value (cache->saved_regs, |
| 3670 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
| 3671 | cache->base); |
| 3672 | |
| 3673 | return (struct mips_frame_cache *) (*this_cache); |
| 3674 | } |
| 3675 | |
| 3676 | static void |
| 3677 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 3678 | struct frame_id *this_id) |
| 3679 | { |
| 3680 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
| 3681 | this_cache); |
| 3682 | /* This marks the outermost frame. */ |
| 3683 | if (info->base == 0) |
| 3684 | return; |
| 3685 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
| 3686 | } |
| 3687 | |
| 3688 | static struct value * |
| 3689 | mips_insn32_frame_prev_register (struct frame_info *this_frame, |
| 3690 | void **this_cache, int regnum) |
| 3691 | { |
| 3692 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
| 3693 | this_cache); |
| 3694 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
| 3695 | } |
| 3696 | |
| 3697 | static int |
| 3698 | mips_insn32_frame_sniffer (const struct frame_unwind *self, |
| 3699 | struct frame_info *this_frame, void **this_cache) |
| 3700 | { |
| 3701 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 3702 | if (mips_pc_is_mips (pc)) |
| 3703 | return 1; |
| 3704 | return 0; |
| 3705 | } |
| 3706 | |
| 3707 | static const struct frame_unwind mips_insn32_frame_unwind = |
| 3708 | { |
| 3709 | NORMAL_FRAME, |
| 3710 | default_frame_unwind_stop_reason, |
| 3711 | mips_insn32_frame_this_id, |
| 3712 | mips_insn32_frame_prev_register, |
| 3713 | NULL, |
| 3714 | mips_insn32_frame_sniffer |
| 3715 | }; |
| 3716 | |
| 3717 | static CORE_ADDR |
| 3718 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
| 3719 | void **this_cache) |
| 3720 | { |
| 3721 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
| 3722 | this_cache); |
| 3723 | return info->base; |
| 3724 | } |
| 3725 | |
| 3726 | static const struct frame_base mips_insn32_frame_base = |
| 3727 | { |
| 3728 | &mips_insn32_frame_unwind, |
| 3729 | mips_insn32_frame_base_address, |
| 3730 | mips_insn32_frame_base_address, |
| 3731 | mips_insn32_frame_base_address |
| 3732 | }; |
| 3733 | |
| 3734 | static const struct frame_base * |
| 3735 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
| 3736 | { |
| 3737 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 3738 | if (mips_pc_is_mips (pc)) |
| 3739 | return &mips_insn32_frame_base; |
| 3740 | else |
| 3741 | return NULL; |
| 3742 | } |
| 3743 | |
| 3744 | static struct trad_frame_cache * |
| 3745 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 3746 | { |
| 3747 | CORE_ADDR pc; |
| 3748 | CORE_ADDR start_addr; |
| 3749 | CORE_ADDR stack_addr; |
| 3750 | struct trad_frame_cache *this_trad_cache; |
| 3751 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 3752 | int num_regs = gdbarch_num_regs (gdbarch); |
| 3753 | |
| 3754 | if ((*this_cache) != NULL) |
| 3755 | return (struct trad_frame_cache *) (*this_cache); |
| 3756 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
| 3757 | (*this_cache) = this_trad_cache; |
| 3758 | |
| 3759 | /* The return address is in the link register. */ |
| 3760 | trad_frame_set_reg_realreg (this_trad_cache, |
| 3761 | gdbarch_pc_regnum (gdbarch), |
| 3762 | num_regs + MIPS_RA_REGNUM); |
| 3763 | |
| 3764 | /* Frame ID, since it's a frameless / stackless function, no stack |
| 3765 | space is allocated and SP on entry is the current SP. */ |
| 3766 | pc = get_frame_pc (this_frame); |
| 3767 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
| 3768 | stack_addr = get_frame_register_signed (this_frame, |
| 3769 | num_regs + MIPS_SP_REGNUM); |
| 3770 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
| 3771 | |
| 3772 | /* Assume that the frame's base is the same as the |
| 3773 | stack-pointer. */ |
| 3774 | trad_frame_set_this_base (this_trad_cache, stack_addr); |
| 3775 | |
| 3776 | return this_trad_cache; |
| 3777 | } |
| 3778 | |
| 3779 | static void |
| 3780 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 3781 | struct frame_id *this_id) |
| 3782 | { |
| 3783 | struct trad_frame_cache *this_trad_cache |
| 3784 | = mips_stub_frame_cache (this_frame, this_cache); |
| 3785 | trad_frame_get_id (this_trad_cache, this_id); |
| 3786 | } |
| 3787 | |
| 3788 | static struct value * |
| 3789 | mips_stub_frame_prev_register (struct frame_info *this_frame, |
| 3790 | void **this_cache, int regnum) |
| 3791 | { |
| 3792 | struct trad_frame_cache *this_trad_cache |
| 3793 | = mips_stub_frame_cache (this_frame, this_cache); |
| 3794 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); |
| 3795 | } |
| 3796 | |
| 3797 | static int |
| 3798 | mips_stub_frame_sniffer (const struct frame_unwind *self, |
| 3799 | struct frame_info *this_frame, void **this_cache) |
| 3800 | { |
| 3801 | gdb_byte dummy[4]; |
| 3802 | struct obj_section *s; |
| 3803 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
| 3804 | struct bound_minimal_symbol msym; |
| 3805 | |
| 3806 | /* Use the stub unwinder for unreadable code. */ |
| 3807 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
| 3808 | return 1; |
| 3809 | |
| 3810 | if (in_plt_section (pc) || in_mips_stubs_section (pc)) |
| 3811 | return 1; |
| 3812 | |
| 3813 | /* Calling a PIC function from a non-PIC function passes through a |
| 3814 | stub. The stub for foo is named ".pic.foo". */ |
| 3815 | msym = lookup_minimal_symbol_by_pc (pc); |
| 3816 | if (msym.minsym != NULL |
| 3817 | && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL |
| 3818 | && startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic.")) |
| 3819 | return 1; |
| 3820 | |
| 3821 | return 0; |
| 3822 | } |
| 3823 | |
| 3824 | static const struct frame_unwind mips_stub_frame_unwind = |
| 3825 | { |
| 3826 | NORMAL_FRAME, |
| 3827 | default_frame_unwind_stop_reason, |
| 3828 | mips_stub_frame_this_id, |
| 3829 | mips_stub_frame_prev_register, |
| 3830 | NULL, |
| 3831 | mips_stub_frame_sniffer |
| 3832 | }; |
| 3833 | |
| 3834 | static CORE_ADDR |
| 3835 | mips_stub_frame_base_address (struct frame_info *this_frame, |
| 3836 | void **this_cache) |
| 3837 | { |
| 3838 | struct trad_frame_cache *this_trad_cache |
| 3839 | = mips_stub_frame_cache (this_frame, this_cache); |
| 3840 | return trad_frame_get_this_base (this_trad_cache); |
| 3841 | } |
| 3842 | |
| 3843 | static const struct frame_base mips_stub_frame_base = |
| 3844 | { |
| 3845 | &mips_stub_frame_unwind, |
| 3846 | mips_stub_frame_base_address, |
| 3847 | mips_stub_frame_base_address, |
| 3848 | mips_stub_frame_base_address |
| 3849 | }; |
| 3850 | |
| 3851 | static const struct frame_base * |
| 3852 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
| 3853 | { |
| 3854 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
| 3855 | return &mips_stub_frame_base; |
| 3856 | else |
| 3857 | return NULL; |
| 3858 | } |
| 3859 | |
| 3860 | /* mips_addr_bits_remove - remove useless address bits */ |
| 3861 | |
| 3862 | static CORE_ADDR |
| 3863 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 3864 | { |
| 3865 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3866 | |
| 3867 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
| 3868 | /* This hack is a work-around for existing boards using PMON, the |
| 3869 | simulator, and any other 64-bit targets that doesn't have true |
| 3870 | 64-bit addressing. On these targets, the upper 32 bits of |
| 3871 | addresses are ignored by the hardware. Thus, the PC or SP are |
| 3872 | likely to have been sign extended to all 1s by instruction |
| 3873 | sequences that load 32-bit addresses. For example, a typical |
| 3874 | piece of code that loads an address is this: |
| 3875 | |
| 3876 | lui $r2, <upper 16 bits> |
| 3877 | ori $r2, <lower 16 bits> |
| 3878 | |
| 3879 | But the lui sign-extends the value such that the upper 32 bits |
| 3880 | may be all 1s. The workaround is simply to mask off these |
| 3881 | bits. In the future, gcc may be changed to support true 64-bit |
| 3882 | addressing, and this masking will have to be disabled. */ |
| 3883 | return addr &= 0xffffffffUL; |
| 3884 | else |
| 3885 | return addr; |
| 3886 | } |
| 3887 | |
| 3888 | |
| 3889 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD |
| 3890 | instruction and ending with a SC/SCD instruction. If such a sequence |
| 3891 | is found, attempt to step through it. A breakpoint is placed at the end of |
| 3892 | the sequence. */ |
| 3893 | |
| 3894 | /* Instructions used during single-stepping of atomic sequences, standard |
| 3895 | ISA version. */ |
| 3896 | #define LL_OPCODE 0x30 |
| 3897 | #define LLD_OPCODE 0x34 |
| 3898 | #define SC_OPCODE 0x38 |
| 3899 | #define SCD_OPCODE 0x3c |
| 3900 | |
| 3901 | static int |
| 3902 | mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, |
| 3903 | struct address_space *aspace, CORE_ADDR pc) |
| 3904 | { |
| 3905 | CORE_ADDR breaks[2] = {-1, -1}; |
| 3906 | CORE_ADDR loc = pc; |
| 3907 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ |
| 3908 | ULONGEST insn; |
| 3909 | int insn_count; |
| 3910 | int index; |
| 3911 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ |
| 3912 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ |
| 3913 | |
| 3914 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
| 3915 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
| 3916 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) |
| 3917 | return 0; |
| 3918 | |
| 3919 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" |
| 3920 | instructions. */ |
| 3921 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) |
| 3922 | { |
| 3923 | int is_branch = 0; |
| 3924 | loc += MIPS_INSN32_SIZE; |
| 3925 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
| 3926 | |
| 3927 | /* Assume that there is at most one branch in the atomic |
| 3928 | sequence. If a branch is found, put a breakpoint in its |
| 3929 | destination address. */ |
| 3930 | switch (itype_op (insn)) |
| 3931 | { |
| 3932 | case 0: /* SPECIAL */ |
| 3933 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ |
| 3934 | return 0; /* fallback to the standard single-step code. */ |
| 3935 | break; |
| 3936 | case 1: /* REGIMM */ |
| 3937 | is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ |
| 3938 | || ((itype_rt (insn) & 0x1e) == 0 |
| 3939 | && itype_rs (insn) == 0)); /* BPOSGE* */ |
| 3940 | break; |
| 3941 | case 2: /* J */ |
| 3942 | case 3: /* JAL */ |
| 3943 | return 0; /* fallback to the standard single-step code. */ |
| 3944 | case 4: /* BEQ */ |
| 3945 | case 5: /* BNE */ |
| 3946 | case 6: /* BLEZ */ |
| 3947 | case 7: /* BGTZ */ |
| 3948 | case 20: /* BEQL */ |
| 3949 | case 21: /* BNEL */ |
| 3950 | case 22: /* BLEZL */ |
| 3951 | case 23: /* BGTTL */ |
| 3952 | is_branch = 1; |
| 3953 | break; |
| 3954 | case 17: /* COP1 */ |
| 3955 | is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) |
| 3956 | && (itype_rt (insn) & 0x2) == 0); |
| 3957 | if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ |
| 3958 | break; |
| 3959 | /* Fall through. */ |
| 3960 | case 18: /* COP2 */ |
| 3961 | case 19: /* COP3 */ |
| 3962 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ |
| 3963 | break; |
| 3964 | } |
| 3965 | if (is_branch) |
| 3966 | { |
| 3967 | branch_bp = loc + mips32_relative_offset (insn) + 4; |
| 3968 | if (last_breakpoint >= 1) |
| 3969 | return 0; /* More than one branch found, fallback to the |
| 3970 | standard single-step code. */ |
| 3971 | breaks[1] = branch_bp; |
| 3972 | last_breakpoint++; |
| 3973 | } |
| 3974 | |
| 3975 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) |
| 3976 | break; |
| 3977 | } |
| 3978 | |
| 3979 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ |
| 3980 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) |
| 3981 | return 0; |
| 3982 | |
| 3983 | loc += MIPS_INSN32_SIZE; |
| 3984 | |
| 3985 | /* Insert a breakpoint right after the end of the atomic sequence. */ |
| 3986 | breaks[0] = loc; |
| 3987 | |
| 3988 | /* Check for duplicated breakpoints. Check also for a breakpoint |
| 3989 | placed (branch instruction's destination) in the atomic sequence. */ |
| 3990 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
| 3991 | last_breakpoint = 0; |
| 3992 | |
| 3993 | /* Effectively inserts the breakpoints. */ |
| 3994 | for (index = 0; index <= last_breakpoint; index++) |
| 3995 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
| 3996 | |
| 3997 | return 1; |
| 3998 | } |
| 3999 | |
| 4000 | static int |
| 4001 | micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, |
| 4002 | struct address_space *aspace, |
| 4003 | CORE_ADDR pc) |
| 4004 | { |
| 4005 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ |
| 4006 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ |
| 4007 | CORE_ADDR breaks[2] = {-1, -1}; |
| 4008 | CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's |
| 4009 | destination. */ |
| 4010 | CORE_ADDR loc = pc; |
| 4011 | int sc_found = 0; |
| 4012 | ULONGEST insn; |
| 4013 | int insn_count; |
| 4014 | int index; |
| 4015 | |
| 4016 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
| 4017 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); |
| 4018 | if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ |
| 4019 | return 0; |
| 4020 | loc += MIPS_INSN16_SIZE; |
| 4021 | insn <<= 16; |
| 4022 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); |
| 4023 | if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ |
| 4024 | return 0; |
| 4025 | loc += MIPS_INSN16_SIZE; |
| 4026 | |
| 4027 | /* Assume all atomic sequences end with an sc/scd instruction. Assume |
| 4028 | that no atomic sequence is longer than "atomic_sequence_length" |
| 4029 | instructions. */ |
| 4030 | for (insn_count = 0; |
| 4031 | !sc_found && insn_count < atomic_sequence_length; |
| 4032 | ++insn_count) |
| 4033 | { |
| 4034 | int is_branch = 0; |
| 4035 | |
| 4036 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); |
| 4037 | loc += MIPS_INSN16_SIZE; |
| 4038 | |
| 4039 | /* Assume that there is at most one conditional branch in the |
| 4040 | atomic sequence. If a branch is found, put a breakpoint in |
| 4041 | its destination address. */ |
| 4042 | switch (mips_insn_size (ISA_MICROMIPS, insn)) |
| 4043 | { |
| 4044 | /* 48-bit instructions. */ |
| 4045 | case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */ |
| 4046 | loc += 2 * MIPS_INSN16_SIZE; |
| 4047 | break; |
| 4048 | |
| 4049 | /* 32-bit instructions. */ |
| 4050 | case 2 * MIPS_INSN16_SIZE: |
| 4051 | switch (micromips_op (insn)) |
| 4052 | { |
| 4053 | case 0x10: /* POOL32I: bits 010000 */ |
| 4054 | if ((b5s5_op (insn) & 0x18) != 0x0 |
| 4055 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ |
| 4056 | /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */ |
| 4057 | && (b5s5_op (insn) & 0x1d) != 0x11 |
| 4058 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ |
| 4059 | && ((b5s5_op (insn) & 0x1e) != 0x14 |
| 4060 | || (insn & 0x3) != 0x0) |
| 4061 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ |
| 4062 | && (b5s5_op (insn) & 0x1e) != 0x1a |
| 4063 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ |
| 4064 | && ((b5s5_op (insn) & 0x1e) != 0x1c |
| 4065 | || (insn & 0x3) != 0x0) |
| 4066 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ |
| 4067 | && ((b5s5_op (insn) & 0x1c) != 0x1c |
| 4068 | || (insn & 0x3) != 0x1)) |
| 4069 | /* BC1ANY*: bits 010000 111xx xxx01 */ |
| 4070 | break; |
| 4071 | /* Fall through. */ |
| 4072 | |
| 4073 | case 0x25: /* BEQ: bits 100101 */ |
| 4074 | case 0x2d: /* BNE: bits 101101 */ |
| 4075 | insn <<= 16; |
| 4076 | insn |= mips_fetch_instruction (gdbarch, |
| 4077 | ISA_MICROMIPS, loc, NULL); |
| 4078 | branch_bp = (loc + MIPS_INSN16_SIZE |
| 4079 | + micromips_relative_offset16 (insn)); |
| 4080 | is_branch = 1; |
| 4081 | break; |
| 4082 | |
| 4083 | case 0x00: /* POOL32A: bits 000000 */ |
| 4084 | insn <<= 16; |
| 4085 | insn |= mips_fetch_instruction (gdbarch, |
| 4086 | ISA_MICROMIPS, loc, NULL); |
| 4087 | if (b0s6_op (insn) != 0x3c |
| 4088 | /* POOL32Axf: bits 000000 ... 111100 */ |
| 4089 | || (b6s10_ext (insn) & 0x2bf) != 0x3c) |
| 4090 | /* JALR, JALR.HB: 000000 000x111100 111100 */ |
| 4091 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ |
| 4092 | break; |
| 4093 | /* Fall through. */ |
| 4094 | |
| 4095 | case 0x1d: /* JALS: bits 011101 */ |
| 4096 | case 0x35: /* J: bits 110101 */ |
| 4097 | case 0x3d: /* JAL: bits 111101 */ |
| 4098 | case 0x3c: /* JALX: bits 111100 */ |
| 4099 | return 0; /* Fall back to the standard single-step code. */ |
| 4100 | |
| 4101 | case 0x18: /* POOL32C: bits 011000 */ |
| 4102 | if ((b12s4_op (insn) & 0xb) == 0xb) |
| 4103 | /* SC, SCD: bits 011000 1x11 */ |
| 4104 | sc_found = 1; |
| 4105 | break; |
| 4106 | } |
| 4107 | loc += MIPS_INSN16_SIZE; |
| 4108 | break; |
| 4109 | |
| 4110 | /* 16-bit instructions. */ |
| 4111 | case MIPS_INSN16_SIZE: |
| 4112 | switch (micromips_op (insn)) |
| 4113 | { |
| 4114 | case 0x23: /* BEQZ16: bits 100011 */ |
| 4115 | case 0x2b: /* BNEZ16: bits 101011 */ |
| 4116 | branch_bp = loc + micromips_relative_offset7 (insn); |
| 4117 | is_branch = 1; |
| 4118 | break; |
| 4119 | |
| 4120 | case 0x11: /* POOL16C: bits 010001 */ |
| 4121 | if ((b5s5_op (insn) & 0x1c) != 0xc |
| 4122 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ |
| 4123 | && b5s5_op (insn) != 0x18) |
| 4124 | /* JRADDIUSP: bits 010001 11000 */ |
| 4125 | break; |
| 4126 | return 0; /* Fall back to the standard single-step code. */ |
| 4127 | |
| 4128 | case 0x33: /* B16: bits 110011 */ |
| 4129 | return 0; /* Fall back to the standard single-step code. */ |
| 4130 | } |
| 4131 | break; |
| 4132 | } |
| 4133 | if (is_branch) |
| 4134 | { |
| 4135 | if (last_breakpoint >= 1) |
| 4136 | return 0; /* More than one branch found, fallback to the |
| 4137 | standard single-step code. */ |
| 4138 | breaks[1] = branch_bp; |
| 4139 | last_breakpoint++; |
| 4140 | } |
| 4141 | } |
| 4142 | if (!sc_found) |
| 4143 | return 0; |
| 4144 | |
| 4145 | /* Insert a breakpoint right after the end of the atomic sequence. */ |
| 4146 | breaks[0] = loc; |
| 4147 | |
| 4148 | /* Check for duplicated breakpoints. Check also for a breakpoint |
| 4149 | placed (branch instruction's destination) in the atomic sequence */ |
| 4150 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
| 4151 | last_breakpoint = 0; |
| 4152 | |
| 4153 | /* Effectively inserts the breakpoints. */ |
| 4154 | for (index = 0; index <= last_breakpoint; index++) |
| 4155 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
| 4156 | |
| 4157 | return 1; |
| 4158 | } |
| 4159 | |
| 4160 | static int |
| 4161 | deal_with_atomic_sequence (struct gdbarch *gdbarch, |
| 4162 | struct address_space *aspace, CORE_ADDR pc) |
| 4163 | { |
| 4164 | if (mips_pc_is_mips (pc)) |
| 4165 | return mips_deal_with_atomic_sequence (gdbarch, aspace, pc); |
| 4166 | else if (mips_pc_is_micromips (gdbarch, pc)) |
| 4167 | return micromips_deal_with_atomic_sequence (gdbarch, aspace, pc); |
| 4168 | else |
| 4169 | return 0; |
| 4170 | } |
| 4171 | |
| 4172 | /* mips_software_single_step() is called just before we want to resume |
| 4173 | the inferior, if we want to single-step it but there is no hardware |
| 4174 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
| 4175 | the target of the coming instruction and breakpoint it. */ |
| 4176 | |
| 4177 | int |
| 4178 | mips_software_single_step (struct frame_info *frame) |
| 4179 | { |
| 4180 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 4181 | struct address_space *aspace = get_frame_address_space (frame); |
| 4182 | CORE_ADDR pc, next_pc; |
| 4183 | |
| 4184 | pc = get_frame_pc (frame); |
| 4185 | if (deal_with_atomic_sequence (gdbarch, aspace, pc)) |
| 4186 | return 1; |
| 4187 | |
| 4188 | next_pc = mips_next_pc (frame, pc); |
| 4189 | |
| 4190 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
| 4191 | return 1; |
| 4192 | } |
| 4193 | |
| 4194 | /* Test whether the PC points to the return instruction at the |
| 4195 | end of a function. */ |
| 4196 | |
| 4197 | static int |
| 4198 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 4199 | { |
| 4200 | ULONGEST insn; |
| 4201 | ULONGEST hint; |
| 4202 | |
| 4203 | /* This used to check for MIPS16, but this piece of code is never |
| 4204 | called for MIPS16 functions. And likewise microMIPS ones. */ |
| 4205 | gdb_assert (mips_pc_is_mips (pc)); |
| 4206 | |
| 4207 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
| 4208 | hint = 0x7c0; |
| 4209 | return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */ |
| 4210 | } |
| 4211 | |
| 4212 | |
| 4213 | /* This fencepost looks highly suspicious to me. Removing it also |
| 4214 | seems suspicious as it could affect remote debugging across serial |
| 4215 | lines. */ |
| 4216 | |
| 4217 | static CORE_ADDR |
| 4218 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 4219 | { |
| 4220 | CORE_ADDR start_pc; |
| 4221 | CORE_ADDR fence; |
| 4222 | int instlen; |
| 4223 | int seen_adjsp = 0; |
| 4224 | struct inferior *inf; |
| 4225 | |
| 4226 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
| 4227 | start_pc = pc; |
| 4228 | fence = start_pc - heuristic_fence_post; |
| 4229 | if (start_pc == 0) |
| 4230 | return 0; |
| 4231 | |
| 4232 | if (heuristic_fence_post == -1 || fence < VM_MIN_ADDRESS) |
| 4233 | fence = VM_MIN_ADDRESS; |
| 4234 | |
| 4235 | instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE; |
| 4236 | |
| 4237 | inf = current_inferior (); |
| 4238 | |
| 4239 | /* Search back for previous return. */ |
| 4240 | for (start_pc -= instlen;; start_pc -= instlen) |
| 4241 | if (start_pc < fence) |
| 4242 | { |
| 4243 | /* It's not clear to me why we reach this point when |
| 4244 | stop_soon, but with this test, at least we |
| 4245 | don't print out warnings for every child forked (eg, on |
| 4246 | decstation). 22apr93 rich@cygnus.com. */ |
| 4247 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
| 4248 | { |
| 4249 | static int blurb_printed = 0; |
| 4250 | |
| 4251 | warning (_("GDB can't find the start of the function at %s."), |
| 4252 | paddress (gdbarch, pc)); |
| 4253 | |
| 4254 | if (!blurb_printed) |
| 4255 | { |
| 4256 | /* This actually happens frequently in embedded |
| 4257 | development, when you first connect to a board |
| 4258 | and your stack pointer and pc are nowhere in |
| 4259 | particular. This message needs to give people |
| 4260 | in that situation enough information to |
| 4261 | determine that it's no big deal. */ |
| 4262 | printf_filtered ("\n\ |
| 4263 | GDB is unable to find the start of the function at %s\n\ |
| 4264 | and thus can't determine the size of that function's stack frame.\n\ |
| 4265 | This means that GDB may be unable to access that stack frame, or\n\ |
| 4266 | the frames below it.\n\ |
| 4267 | This problem is most likely caused by an invalid program counter or\n\ |
| 4268 | stack pointer.\n\ |
| 4269 | However, if you think GDB should simply search farther back\n\ |
| 4270 | from %s for code which looks like the beginning of a\n\ |
| 4271 | function, you can increase the range of the search using the `set\n\ |
| 4272 | heuristic-fence-post' command.\n", |
| 4273 | paddress (gdbarch, pc), paddress (gdbarch, pc)); |
| 4274 | blurb_printed = 1; |
| 4275 | } |
| 4276 | } |
| 4277 | |
| 4278 | return 0; |
| 4279 | } |
| 4280 | else if (mips_pc_is_mips16 (gdbarch, start_pc)) |
| 4281 | { |
| 4282 | unsigned short inst; |
| 4283 | |
| 4284 | /* On MIPS16, any one of the following is likely to be the |
| 4285 | start of a function: |
| 4286 | extend save |
| 4287 | save |
| 4288 | entry |
| 4289 | addiu sp,-n |
| 4290 | daddiu sp,-n |
| 4291 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
| 4292 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL); |
| 4293 | if ((inst & 0xff80) == 0x6480) /* save */ |
| 4294 | { |
| 4295 | if (start_pc - instlen >= fence) |
| 4296 | { |
| 4297 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, |
| 4298 | start_pc - instlen, NULL); |
| 4299 | if ((inst & 0xf800) == 0xf000) /* extend */ |
| 4300 | start_pc -= instlen; |
| 4301 | } |
| 4302 | break; |
| 4303 | } |
| 4304 | else if (((inst & 0xf81f) == 0xe809 |
| 4305 | && (inst & 0x700) != 0x700) /* entry */ |
| 4306 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ |
| 4307 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ |
| 4308 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ |
| 4309 | break; |
| 4310 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
| 4311 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
| 4312 | seen_adjsp = 1; |
| 4313 | else |
| 4314 | seen_adjsp = 0; |
| 4315 | } |
| 4316 | else if (mips_pc_is_micromips (gdbarch, start_pc)) |
| 4317 | { |
| 4318 | ULONGEST insn; |
| 4319 | int stop = 0; |
| 4320 | long offset; |
| 4321 | int dreg; |
| 4322 | int sreg; |
| 4323 | |
| 4324 | /* On microMIPS, any one of the following is likely to be the |
| 4325 | start of a function: |
| 4326 | ADDIUSP -imm |
| 4327 | (D)ADDIU $sp, -imm |
| 4328 | LUI $gp, imm */ |
| 4329 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); |
| 4330 | switch (micromips_op (insn)) |
| 4331 | { |
| 4332 | case 0xc: /* ADDIU: bits 001100 */ |
| 4333 | case 0x17: /* DADDIU: bits 010111 */ |
| 4334 | sreg = b0s5_reg (insn); |
| 4335 | dreg = b5s5_reg (insn); |
| 4336 | insn <<= 16; |
| 4337 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, |
| 4338 | pc + MIPS_INSN16_SIZE, NULL); |
| 4339 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; |
| 4340 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM |
| 4341 | /* (D)ADDIU $sp, imm */ |
| 4342 | && offset < 0) |
| 4343 | stop = 1; |
| 4344 | break; |
| 4345 | |
| 4346 | case 0x10: /* POOL32I: bits 010000 */ |
| 4347 | if (b5s5_op (insn) == 0xd |
| 4348 | /* LUI: bits 010000 001101 */ |
| 4349 | && b0s5_reg (insn >> 16) == 28) |
| 4350 | /* LUI $gp, imm */ |
| 4351 | stop = 1; |
| 4352 | break; |
| 4353 | |
| 4354 | case 0x13: /* POOL16D: bits 010011 */ |
| 4355 | if ((insn & 0x1) == 0x1) |
| 4356 | /* ADDIUSP: bits 010011 1 */ |
| 4357 | { |
| 4358 | offset = micromips_decode_imm9 (b1s9_imm (insn)); |
| 4359 | if (offset < 0) |
| 4360 | /* ADDIUSP -imm */ |
| 4361 | stop = 1; |
| 4362 | } |
| 4363 | else |
| 4364 | /* ADDIUS5: bits 010011 0 */ |
| 4365 | { |
| 4366 | dreg = b5s5_reg (insn); |
| 4367 | offset = (b1s4_imm (insn) ^ 8) - 8; |
| 4368 | if (dreg == MIPS_SP_REGNUM && offset < 0) |
| 4369 | /* ADDIUS5 $sp, -imm */ |
| 4370 | stop = 1; |
| 4371 | } |
| 4372 | break; |
| 4373 | } |
| 4374 | if (stop) |
| 4375 | break; |
| 4376 | } |
| 4377 | else if (mips_about_to_return (gdbarch, start_pc)) |
| 4378 | { |
| 4379 | /* Skip return and its delay slot. */ |
| 4380 | start_pc += 2 * MIPS_INSN32_SIZE; |
| 4381 | break; |
| 4382 | } |
| 4383 | |
| 4384 | return start_pc; |
| 4385 | } |
| 4386 | |
| 4387 | struct mips_objfile_private |
| 4388 | { |
| 4389 | bfd_size_type size; |
| 4390 | char *contents; |
| 4391 | }; |
| 4392 | |
| 4393 | /* According to the current ABI, should the type be passed in a |
| 4394 | floating-point register (assuming that there is space)? When there |
| 4395 | is no FPU, FP are not even considered as possible candidates for |
| 4396 | FP registers and, consequently this returns false - forces FP |
| 4397 | arguments into integer registers. */ |
| 4398 | |
| 4399 | static int |
| 4400 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
| 4401 | struct type *arg_type) |
| 4402 | { |
| 4403 | return ((typecode == TYPE_CODE_FLT |
| 4404 | || (MIPS_EABI (gdbarch) |
| 4405 | && (typecode == TYPE_CODE_STRUCT |
| 4406 | || typecode == TYPE_CODE_UNION) |
| 4407 | && TYPE_NFIELDS (arg_type) == 1 |
| 4408 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
| 4409 | == TYPE_CODE_FLT)) |
| 4410 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
| 4411 | } |
| 4412 | |
| 4413 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
| 4414 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
| 4415 | |
| 4416 | static int |
| 4417 | mips_type_needs_double_align (struct type *type) |
| 4418 | { |
| 4419 | enum type_code typecode = TYPE_CODE (type); |
| 4420 | |
| 4421 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
| 4422 | return 1; |
| 4423 | else if (typecode == TYPE_CODE_STRUCT) |
| 4424 | { |
| 4425 | if (TYPE_NFIELDS (type) < 1) |
| 4426 | return 0; |
| 4427 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); |
| 4428 | } |
| 4429 | else if (typecode == TYPE_CODE_UNION) |
| 4430 | { |
| 4431 | int i, n; |
| 4432 | |
| 4433 | n = TYPE_NFIELDS (type); |
| 4434 | for (i = 0; i < n; i++) |
| 4435 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) |
| 4436 | return 1; |
| 4437 | return 0; |
| 4438 | } |
| 4439 | return 0; |
| 4440 | } |
| 4441 | |
| 4442 | /* Adjust the address downward (direction of stack growth) so that it |
| 4443 | is correctly aligned for a new stack frame. */ |
| 4444 | static CORE_ADDR |
| 4445 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 4446 | { |
| 4447 | return align_down (addr, 16); |
| 4448 | } |
| 4449 | |
| 4450 | /* Implement the "push_dummy_code" gdbarch method. */ |
| 4451 | |
| 4452 | static CORE_ADDR |
| 4453 | mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, |
| 4454 | CORE_ADDR funaddr, struct value **args, |
| 4455 | int nargs, struct type *value_type, |
| 4456 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
| 4457 | struct regcache *regcache) |
| 4458 | { |
| 4459 | static gdb_byte nop_insn[] = { 0, 0, 0, 0 }; |
| 4460 | CORE_ADDR nop_addr; |
| 4461 | CORE_ADDR bp_slot; |
| 4462 | |
| 4463 | /* Reserve enough room on the stack for our breakpoint instruction. */ |
| 4464 | bp_slot = sp - sizeof (nop_insn); |
| 4465 | |
| 4466 | /* Return to microMIPS mode if calling microMIPS code to avoid |
| 4467 | triggering an address error exception on processors that only |
| 4468 | support microMIPS execution. */ |
| 4469 | *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr) |
| 4470 | ? make_compact_addr (bp_slot) : bp_slot); |
| 4471 | |
| 4472 | /* The breakpoint layer automatically adjusts the address of |
| 4473 | breakpoints inserted in a branch delay slot. With enough |
| 4474 | bad luck, the 4 bytes located just before our breakpoint |
| 4475 | instruction could look like a branch instruction, and thus |
| 4476 | trigger the adjustement, and break the function call entirely. |
| 4477 | So, we reserve those 4 bytes and write a nop instruction |
| 4478 | to prevent that from happening. */ |
| 4479 | nop_addr = bp_slot - sizeof (nop_insn); |
| 4480 | write_memory (nop_addr, nop_insn, sizeof (nop_insn)); |
| 4481 | sp = mips_frame_align (gdbarch, nop_addr); |
| 4482 | |
| 4483 | /* Inferior resumes at the function entry point. */ |
| 4484 | *real_pc = funaddr; |
| 4485 | |
| 4486 | return sp; |
| 4487 | } |
| 4488 | |
| 4489 | static CORE_ADDR |
| 4490 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 4491 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 4492 | int nargs, struct value **args, CORE_ADDR sp, |
| 4493 | int struct_return, CORE_ADDR struct_addr) |
| 4494 | { |
| 4495 | int argreg; |
| 4496 | int float_argreg; |
| 4497 | int argnum; |
| 4498 | int len = 0; |
| 4499 | int stack_offset = 0; |
| 4500 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 4501 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
| 4502 | int regsize = mips_abi_regsize (gdbarch); |
| 4503 | |
| 4504 | /* For shared libraries, "t9" needs to point at the function |
| 4505 | address. */ |
| 4506 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
| 4507 | |
| 4508 | /* Set the return address register to point to the entry point of |
| 4509 | the program, where a breakpoint lies in wait. */ |
| 4510 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
| 4511 | |
| 4512 | /* First ensure that the stack and structure return address (if any) |
| 4513 | are properly aligned. The stack has to be at least 64-bit |
| 4514 | aligned even on 32-bit machines, because doubles must be 64-bit |
| 4515 | aligned. For n32 and n64, stack frames need to be 128-bit |
| 4516 | aligned, so we round to this widest known alignment. */ |
| 4517 | |
| 4518 | sp = align_down (sp, 16); |
| 4519 | struct_addr = align_down (struct_addr, 16); |
| 4520 | |
| 4521 | /* Now make space on the stack for the args. We allocate more |
| 4522 | than necessary for EABI, because the first few arguments are |
| 4523 | passed in registers, but that's OK. */ |
| 4524 | for (argnum = 0; argnum < nargs; argnum++) |
| 4525 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
| 4526 | sp -= align_up (len, 16); |
| 4527 | |
| 4528 | if (mips_debug) |
| 4529 | fprintf_unfiltered (gdb_stdlog, |
| 4530 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
| 4531 | paddress (gdbarch, sp), (long) align_up (len, 16)); |
| 4532 | |
| 4533 | /* Initialize the integer and float register pointers. */ |
| 4534 | argreg = MIPS_A0_REGNUM; |
| 4535 | float_argreg = mips_fpa0_regnum (gdbarch); |
| 4536 | |
| 4537 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
| 4538 | if (struct_return) |
| 4539 | { |
| 4540 | if (mips_debug) |
| 4541 | fprintf_unfiltered (gdb_stdlog, |
| 4542 | "mips_eabi_push_dummy_call: " |
| 4543 | "struct_return reg=%d %s\n", |
| 4544 | argreg, paddress (gdbarch, struct_addr)); |
| 4545 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
| 4546 | } |
| 4547 | |
| 4548 | /* Now load as many as possible of the first arguments into |
| 4549 | registers, and push the rest onto the stack. Loop thru args |
| 4550 | from first to last. */ |
| 4551 | for (argnum = 0; argnum < nargs; argnum++) |
| 4552 | { |
| 4553 | const gdb_byte *val; |
| 4554 | gdb_byte valbuf[MAX_REGISTER_SIZE]; |
| 4555 | struct value *arg = args[argnum]; |
| 4556 | struct type *arg_type = check_typedef (value_type (arg)); |
| 4557 | int len = TYPE_LENGTH (arg_type); |
| 4558 | enum type_code typecode = TYPE_CODE (arg_type); |
| 4559 | |
| 4560 | if (mips_debug) |
| 4561 | fprintf_unfiltered (gdb_stdlog, |
| 4562 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
| 4563 | argnum + 1, len, (int) typecode); |
| 4564 | |
| 4565 | /* The EABI passes structures that do not fit in a register by |
| 4566 | reference. */ |
| 4567 | if (len > regsize |
| 4568 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
| 4569 | { |
| 4570 | store_unsigned_integer (valbuf, regsize, byte_order, |
| 4571 | value_address (arg)); |
| 4572 | typecode = TYPE_CODE_PTR; |
| 4573 | len = regsize; |
| 4574 | val = valbuf; |
| 4575 | if (mips_debug) |
| 4576 | fprintf_unfiltered (gdb_stdlog, " push"); |
| 4577 | } |
| 4578 | else |
| 4579 | val = value_contents (arg); |
| 4580 | |
| 4581 | /* 32-bit ABIs always start floating point arguments in an |
| 4582 | even-numbered floating point register. Round the FP register |
| 4583 | up before the check to see if there are any FP registers |
| 4584 | left. Non MIPS_EABI targets also pass the FP in the integer |
| 4585 | registers so also round up normal registers. */ |
| 4586 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
| 4587 | { |
| 4588 | if ((float_argreg & 1)) |
| 4589 | float_argreg++; |
| 4590 | } |
| 4591 | |
| 4592 | /* Floating point arguments passed in registers have to be |
| 4593 | treated specially. On 32-bit architectures, doubles |
| 4594 | are passed in register pairs; the even register gets |
| 4595 | the low word, and the odd register gets the high word. |
| 4596 | On non-EABI processors, the first two floating point arguments are |
| 4597 | also copied to general registers, because MIPS16 functions |
| 4598 | don't use float registers for arguments. This duplication of |
| 4599 | arguments in general registers can't hurt non-MIPS16 functions |
| 4600 | because those registers are normally skipped. */ |
| 4601 | /* MIPS_EABI squeezes a struct that contains a single floating |
| 4602 | point value into an FP register instead of pushing it onto the |
| 4603 | stack. */ |
| 4604 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
| 4605 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) |
| 4606 | { |
| 4607 | /* EABI32 will pass doubles in consecutive registers, even on |
| 4608 | 64-bit cores. At one time, we used to check the size of |
| 4609 | `float_argreg' to determine whether or not to pass doubles |
| 4610 | in consecutive registers, but this is not sufficient for |
| 4611 | making the ABI determination. */ |
| 4612 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) |
| 4613 | { |
| 4614 | int low_offset = gdbarch_byte_order (gdbarch) |
| 4615 | == BFD_ENDIAN_BIG ? 4 : 0; |
| 4616 | long regval; |
| 4617 | |
| 4618 | /* Write the low word of the double to the even register(s). */ |
| 4619 | regval = extract_signed_integer (val + low_offset, |
| 4620 | 4, byte_order); |
| 4621 | if (mips_debug) |
| 4622 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
| 4623 | float_argreg, phex (regval, 4)); |
| 4624 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
| 4625 | |
| 4626 | /* Write the high word of the double to the odd register(s). */ |
| 4627 | regval = extract_signed_integer (val + 4 - low_offset, |
| 4628 | 4, byte_order); |
| 4629 | if (mips_debug) |
| 4630 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
| 4631 | float_argreg, phex (regval, 4)); |
| 4632 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
| 4633 | } |
| 4634 | else |
| 4635 | { |
| 4636 | /* This is a floating point value that fits entirely |
| 4637 | in a single register. */ |
| 4638 | /* On 32 bit ABI's the float_argreg is further adjusted |
| 4639 | above to ensure that it is even register aligned. */ |
| 4640 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
| 4641 | if (mips_debug) |
| 4642 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
| 4643 | float_argreg, phex (regval, len)); |
| 4644 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
| 4645 | } |
| 4646 | } |
| 4647 | else |
| 4648 | { |
| 4649 | /* Copy the argument to general registers or the stack in |
| 4650 | register-sized pieces. Large arguments are split between |
| 4651 | registers and stack. */ |
| 4652 | /* Note: structs whose size is not a multiple of regsize |
| 4653 | are treated specially: Irix cc passes |
| 4654 | them in registers where gcc sometimes puts them on the |
| 4655 | stack. For maximum compatibility, we will put them in |
| 4656 | both places. */ |
| 4657 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
| 4658 | |
| 4659 | /* Note: Floating-point values that didn't fit into an FP |
| 4660 | register are only written to memory. */ |
| 4661 | while (len > 0) |
| 4662 | { |
| 4663 | /* Remember if the argument was written to the stack. */ |
| 4664 | int stack_used_p = 0; |
| 4665 | int partial_len = (len < regsize ? len : regsize); |
| 4666 | |
| 4667 | if (mips_debug) |
| 4668 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", |
| 4669 | partial_len); |
| 4670 | |
| 4671 | /* Write this portion of the argument to the stack. */ |
| 4672 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
| 4673 | || odd_sized_struct |
| 4674 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
| 4675 | { |
| 4676 | /* Should shorter than int integer values be |
| 4677 | promoted to int before being stored? */ |
| 4678 | int longword_offset = 0; |
| 4679 | CORE_ADDR addr; |
| 4680 | stack_used_p = 1; |
| 4681 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 4682 | { |
| 4683 | if (regsize == 8 |
| 4684 | && (typecode == TYPE_CODE_INT |
| 4685 | || typecode == TYPE_CODE_PTR |
| 4686 | || typecode == TYPE_CODE_FLT) && len <= 4) |
| 4687 | longword_offset = regsize - len; |
| 4688 | else if ((typecode == TYPE_CODE_STRUCT |
| 4689 | || typecode == TYPE_CODE_UNION) |
| 4690 | && TYPE_LENGTH (arg_type) < regsize) |
| 4691 | longword_offset = regsize - len; |
| 4692 | } |
| 4693 | |
| 4694 | if (mips_debug) |
| 4695 | { |
| 4696 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
| 4697 | paddress (gdbarch, stack_offset)); |
| 4698 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", |
| 4699 | paddress (gdbarch, longword_offset)); |
| 4700 | } |
| 4701 | |
| 4702 | addr = sp + stack_offset + longword_offset; |
| 4703 | |
| 4704 | if (mips_debug) |
| 4705 | { |
| 4706 | int i; |
| 4707 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
| 4708 | paddress (gdbarch, addr)); |
| 4709 | for (i = 0; i < partial_len; i++) |
| 4710 | { |
| 4711 | fprintf_unfiltered (gdb_stdlog, "%02x", |
| 4712 | val[i] & 0xff); |
| 4713 | } |
| 4714 | } |
| 4715 | write_memory (addr, val, partial_len); |
| 4716 | } |
| 4717 | |
| 4718 | /* Note!!! This is NOT an else clause. Odd sized |
| 4719 | structs may go thru BOTH paths. Floating point |
| 4720 | arguments will not. */ |
| 4721 | /* Write this portion of the argument to a general |
| 4722 | purpose register. */ |
| 4723 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
| 4724 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) |
| 4725 | { |
| 4726 | LONGEST regval = |
| 4727 | extract_signed_integer (val, partial_len, byte_order); |
| 4728 | |
| 4729 | if (mips_debug) |
| 4730 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
| 4731 | argreg, |
| 4732 | phex (regval, regsize)); |
| 4733 | regcache_cooked_write_signed (regcache, argreg, regval); |
| 4734 | argreg++; |
| 4735 | } |
| 4736 | |
| 4737 | len -= partial_len; |
| 4738 | val += partial_len; |
| 4739 | |
| 4740 | /* Compute the offset into the stack at which we will |
| 4741 | copy the next parameter. |
| 4742 | |
| 4743 | In the new EABI (and the NABI32), the stack_offset |
| 4744 | only needs to be adjusted when it has been used. */ |
| 4745 | |
| 4746 | if (stack_used_p) |
| 4747 | stack_offset += align_up (partial_len, regsize); |
| 4748 | } |
| 4749 | } |
| 4750 | if (mips_debug) |
| 4751 | fprintf_unfiltered (gdb_stdlog, "\n"); |
| 4752 | } |
| 4753 | |
| 4754 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
| 4755 | |
| 4756 | /* Return adjusted stack pointer. */ |
| 4757 | return sp; |
| 4758 | } |
| 4759 | |
| 4760 | /* Determine the return value convention being used. */ |
| 4761 | |
| 4762 | static enum return_value_convention |
| 4763 | mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, |
| 4764 | struct type *type, struct regcache *regcache, |
| 4765 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 4766 | { |
| 4767 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 4768 | int fp_return_type = 0; |
| 4769 | int offset, regnum, xfer; |
| 4770 | |
| 4771 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
| 4772 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 4773 | |
| 4774 | /* Floating point type? */ |
| 4775 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) |
| 4776 | { |
| 4777 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
| 4778 | fp_return_type = 1; |
| 4779 | /* Structs with a single field of float type |
| 4780 | are returned in a floating point register. */ |
| 4781 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 4782 | || TYPE_CODE (type) == TYPE_CODE_UNION) |
| 4783 | && TYPE_NFIELDS (type) == 1) |
| 4784 | { |
| 4785 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); |
| 4786 | |
| 4787 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) |
| 4788 | fp_return_type = 1; |
| 4789 | } |
| 4790 | } |
| 4791 | |
| 4792 | if (fp_return_type) |
| 4793 | { |
| 4794 | /* A floating-point value belongs in the least significant part |
| 4795 | of FP0/FP1. */ |
| 4796 | if (mips_debug) |
| 4797 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); |
| 4798 | regnum = mips_regnum (gdbarch)->fp0; |
| 4799 | } |
| 4800 | else |
| 4801 | { |
| 4802 | /* An integer value goes in V0/V1. */ |
| 4803 | if (mips_debug) |
| 4804 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); |
| 4805 | regnum = MIPS_V0_REGNUM; |
| 4806 | } |
| 4807 | for (offset = 0; |
| 4808 | offset < TYPE_LENGTH (type); |
| 4809 | offset += mips_abi_regsize (gdbarch), regnum++) |
| 4810 | { |
| 4811 | xfer = mips_abi_regsize (gdbarch); |
| 4812 | if (offset + xfer > TYPE_LENGTH (type)) |
| 4813 | xfer = TYPE_LENGTH (type) - offset; |
| 4814 | mips_xfer_register (gdbarch, regcache, |
| 4815 | gdbarch_num_regs (gdbarch) + regnum, xfer, |
| 4816 | gdbarch_byte_order (gdbarch), readbuf, writebuf, |
| 4817 | offset); |
| 4818 | } |
| 4819 | |
| 4820 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 4821 | } |
| 4822 | |
| 4823 | |
| 4824 | /* N32/N64 ABI stuff. */ |
| 4825 | |
| 4826 | /* Search for a naturally aligned double at OFFSET inside a struct |
| 4827 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point |
| 4828 | registers. */ |
| 4829 | |
| 4830 | static int |
| 4831 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
| 4832 | int offset) |
| 4833 | { |
| 4834 | int i; |
| 4835 | |
| 4836 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) |
| 4837 | return 0; |
| 4838 | |
| 4839 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
| 4840 | return 0; |
| 4841 | |
| 4842 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) |
| 4843 | return 0; |
| 4844 | |
| 4845 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) |
| 4846 | { |
| 4847 | int pos; |
| 4848 | struct type *field_type; |
| 4849 | |
| 4850 | /* We're only looking at normal fields. */ |
| 4851 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
| 4852 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
| 4853 | continue; |
| 4854 | |
| 4855 | /* If we have gone past the offset, there is no double to pass. */ |
| 4856 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; |
| 4857 | if (pos > offset) |
| 4858 | return 0; |
| 4859 | |
| 4860 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); |
| 4861 | |
| 4862 | /* If this field is entirely before the requested offset, go |
| 4863 | on to the next one. */ |
| 4864 | if (pos + TYPE_LENGTH (field_type) <= offset) |
| 4865 | continue; |
| 4866 | |
| 4867 | /* If this is our special aligned double, we can stop. */ |
| 4868 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT |
| 4869 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) |
| 4870 | return 1; |
| 4871 | |
| 4872 | /* This field starts at or before the requested offset, and |
| 4873 | overlaps it. If it is a structure, recurse inwards. */ |
| 4874 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
| 4875 | } |
| 4876 | |
| 4877 | return 0; |
| 4878 | } |
| 4879 | |
| 4880 | static CORE_ADDR |
| 4881 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 4882 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 4883 | int nargs, struct value **args, CORE_ADDR sp, |
| 4884 | int struct_return, CORE_ADDR struct_addr) |
| 4885 | { |
| 4886 | int argreg; |
| 4887 | int float_argreg; |
| 4888 | int argnum; |
| 4889 | int len = 0; |
| 4890 | int stack_offset = 0; |
| 4891 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 4892 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
| 4893 | |
| 4894 | /* For shared libraries, "t9" needs to point at the function |
| 4895 | address. */ |
| 4896 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
| 4897 | |
| 4898 | /* Set the return address register to point to the entry point of |
| 4899 | the program, where a breakpoint lies in wait. */ |
| 4900 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
| 4901 | |
| 4902 | /* First ensure that the stack and structure return address (if any) |
| 4903 | are properly aligned. The stack has to be at least 64-bit |
| 4904 | aligned even on 32-bit machines, because doubles must be 64-bit |
| 4905 | aligned. For n32 and n64, stack frames need to be 128-bit |
| 4906 | aligned, so we round to this widest known alignment. */ |
| 4907 | |
| 4908 | sp = align_down (sp, 16); |
| 4909 | struct_addr = align_down (struct_addr, 16); |
| 4910 | |
| 4911 | /* Now make space on the stack for the args. */ |
| 4912 | for (argnum = 0; argnum < nargs; argnum++) |
| 4913 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
| 4914 | sp -= align_up (len, 16); |
| 4915 | |
| 4916 | if (mips_debug) |
| 4917 | fprintf_unfiltered (gdb_stdlog, |
| 4918 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
| 4919 | paddress (gdbarch, sp), (long) align_up (len, 16)); |
| 4920 | |
| 4921 | /* Initialize the integer and float register pointers. */ |
| 4922 | argreg = MIPS_A0_REGNUM; |
| 4923 | float_argreg = mips_fpa0_regnum (gdbarch); |
| 4924 | |
| 4925 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
| 4926 | if (struct_return) |
| 4927 | { |
| 4928 | if (mips_debug) |
| 4929 | fprintf_unfiltered (gdb_stdlog, |
| 4930 | "mips_n32n64_push_dummy_call: " |
| 4931 | "struct_return reg=%d %s\n", |
| 4932 | argreg, paddress (gdbarch, struct_addr)); |
| 4933 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
| 4934 | } |
| 4935 | |
| 4936 | /* Now load as many as possible of the first arguments into |
| 4937 | registers, and push the rest onto the stack. Loop thru args |
| 4938 | from first to last. */ |
| 4939 | for (argnum = 0; argnum < nargs; argnum++) |
| 4940 | { |
| 4941 | const gdb_byte *val; |
| 4942 | struct value *arg = args[argnum]; |
| 4943 | struct type *arg_type = check_typedef (value_type (arg)); |
| 4944 | int len = TYPE_LENGTH (arg_type); |
| 4945 | enum type_code typecode = TYPE_CODE (arg_type); |
| 4946 | |
| 4947 | if (mips_debug) |
| 4948 | fprintf_unfiltered (gdb_stdlog, |
| 4949 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
| 4950 | argnum + 1, len, (int) typecode); |
| 4951 | |
| 4952 | val = value_contents (arg); |
| 4953 | |
| 4954 | /* A 128-bit long double value requires an even-odd pair of |
| 4955 | floating-point registers. */ |
| 4956 | if (len == 16 |
| 4957 | && fp_register_arg_p (gdbarch, typecode, arg_type) |
| 4958 | && (float_argreg & 1)) |
| 4959 | { |
| 4960 | float_argreg++; |
| 4961 | argreg++; |
| 4962 | } |
| 4963 | |
| 4964 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
| 4965 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
| 4966 | { |
| 4967 | /* This is a floating point value that fits entirely |
| 4968 | in a single register or a pair of registers. */ |
| 4969 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
| 4970 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
| 4971 | if (mips_debug) |
| 4972 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
| 4973 | float_argreg, phex (regval, reglen)); |
| 4974 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
| 4975 | |
| 4976 | if (mips_debug) |
| 4977 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
| 4978 | argreg, phex (regval, reglen)); |
| 4979 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 4980 | float_argreg++; |
| 4981 | argreg++; |
| 4982 | if (len == 16) |
| 4983 | { |
| 4984 | regval = extract_unsigned_integer (val + reglen, |
| 4985 | reglen, byte_order); |
| 4986 | if (mips_debug) |
| 4987 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
| 4988 | float_argreg, phex (regval, reglen)); |
| 4989 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
| 4990 | |
| 4991 | if (mips_debug) |
| 4992 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
| 4993 | argreg, phex (regval, reglen)); |
| 4994 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 4995 | float_argreg++; |
| 4996 | argreg++; |
| 4997 | } |
| 4998 | } |
| 4999 | else |
| 5000 | { |
| 5001 | /* Copy the argument to general registers or the stack in |
| 5002 | register-sized pieces. Large arguments are split between |
| 5003 | registers and stack. */ |
| 5004 | /* For N32/N64, structs, unions, or other composite types are |
| 5005 | treated as a sequence of doublewords, and are passed in integer |
| 5006 | or floating point registers as though they were simple scalar |
| 5007 | parameters to the extent that they fit, with any excess on the |
| 5008 | stack packed according to the normal memory layout of the |
| 5009 | object. |
| 5010 | The caller does not reserve space for the register arguments; |
| 5011 | the callee is responsible for reserving it if required. */ |
| 5012 | /* Note: Floating-point values that didn't fit into an FP |
| 5013 | register are only written to memory. */ |
| 5014 | while (len > 0) |
| 5015 | { |
| 5016 | /* Remember if the argument was written to the stack. */ |
| 5017 | int stack_used_p = 0; |
| 5018 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
| 5019 | |
| 5020 | if (mips_debug) |
| 5021 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", |
| 5022 | partial_len); |
| 5023 | |
| 5024 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
| 5025 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); |
| 5026 | |
| 5027 | /* Write this portion of the argument to the stack. */ |
| 5028 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
| 5029 | { |
| 5030 | /* Should shorter than int integer values be |
| 5031 | promoted to int before being stored? */ |
| 5032 | int longword_offset = 0; |
| 5033 | CORE_ADDR addr; |
| 5034 | stack_used_p = 1; |
| 5035 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 5036 | { |
| 5037 | if ((typecode == TYPE_CODE_INT |
| 5038 | || typecode == TYPE_CODE_PTR) |
| 5039 | && len <= 4) |
| 5040 | longword_offset = MIPS64_REGSIZE - len; |
| 5041 | } |
| 5042 | |
| 5043 | if (mips_debug) |
| 5044 | { |
| 5045 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
| 5046 | paddress (gdbarch, stack_offset)); |
| 5047 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", |
| 5048 | paddress (gdbarch, longword_offset)); |
| 5049 | } |
| 5050 | |
| 5051 | addr = sp + stack_offset + longword_offset; |
| 5052 | |
| 5053 | if (mips_debug) |
| 5054 | { |
| 5055 | int i; |
| 5056 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
| 5057 | paddress (gdbarch, addr)); |
| 5058 | for (i = 0; i < partial_len; i++) |
| 5059 | { |
| 5060 | fprintf_unfiltered (gdb_stdlog, "%02x", |
| 5061 | val[i] & 0xff); |
| 5062 | } |
| 5063 | } |
| 5064 | write_memory (addr, val, partial_len); |
| 5065 | } |
| 5066 | |
| 5067 | /* Note!!! This is NOT an else clause. Odd sized |
| 5068 | structs may go thru BOTH paths. */ |
| 5069 | /* Write this portion of the argument to a general |
| 5070 | purpose register. */ |
| 5071 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
| 5072 | { |
| 5073 | LONGEST regval; |
| 5074 | |
| 5075 | /* Sign extend pointers, 32-bit integers and signed |
| 5076 | 16-bit and 8-bit integers; everything else is taken |
| 5077 | as is. */ |
| 5078 | |
| 5079 | if ((partial_len == 4 |
| 5080 | && (typecode == TYPE_CODE_PTR |
| 5081 | || typecode == TYPE_CODE_INT)) |
| 5082 | || (partial_len < 4 |
| 5083 | && typecode == TYPE_CODE_INT |
| 5084 | && !TYPE_UNSIGNED (arg_type))) |
| 5085 | regval = extract_signed_integer (val, partial_len, |
| 5086 | byte_order); |
| 5087 | else |
| 5088 | regval = extract_unsigned_integer (val, partial_len, |
| 5089 | byte_order); |
| 5090 | |
| 5091 | /* A non-floating-point argument being passed in a |
| 5092 | general register. If a struct or union, and if |
| 5093 | the remaining length is smaller than the register |
| 5094 | size, we have to adjust the register value on |
| 5095 | big endian targets. |
| 5096 | |
| 5097 | It does not seem to be necessary to do the |
| 5098 | same for integral types. */ |
| 5099 | |
| 5100 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
| 5101 | && partial_len < MIPS64_REGSIZE |
| 5102 | && (typecode == TYPE_CODE_STRUCT |
| 5103 | || typecode == TYPE_CODE_UNION)) |
| 5104 | regval <<= ((MIPS64_REGSIZE - partial_len) |
| 5105 | * TARGET_CHAR_BIT); |
| 5106 | |
| 5107 | if (mips_debug) |
| 5108 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
| 5109 | argreg, |
| 5110 | phex (regval, MIPS64_REGSIZE)); |
| 5111 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 5112 | |
| 5113 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
| 5114 | TYPE_LENGTH (arg_type) - len)) |
| 5115 | { |
| 5116 | if (mips_debug) |
| 5117 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", |
| 5118 | float_argreg, |
| 5119 | phex (regval, MIPS64_REGSIZE)); |
| 5120 | regcache_cooked_write_unsigned (regcache, float_argreg, |
| 5121 | regval); |
| 5122 | } |
| 5123 | |
| 5124 | float_argreg++; |
| 5125 | argreg++; |
| 5126 | } |
| 5127 | |
| 5128 | len -= partial_len; |
| 5129 | val += partial_len; |
| 5130 | |
| 5131 | /* Compute the offset into the stack at which we will |
| 5132 | copy the next parameter. |
| 5133 | |
| 5134 | In N32 (N64?), the stack_offset only needs to be |
| 5135 | adjusted when it has been used. */ |
| 5136 | |
| 5137 | if (stack_used_p) |
| 5138 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
| 5139 | } |
| 5140 | } |
| 5141 | if (mips_debug) |
| 5142 | fprintf_unfiltered (gdb_stdlog, "\n"); |
| 5143 | } |
| 5144 | |
| 5145 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
| 5146 | |
| 5147 | /* Return adjusted stack pointer. */ |
| 5148 | return sp; |
| 5149 | } |
| 5150 | |
| 5151 | static enum return_value_convention |
| 5152 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, |
| 5153 | struct type *type, struct regcache *regcache, |
| 5154 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 5155 | { |
| 5156 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 5157 | |
| 5158 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 |
| 5159 | |
| 5160 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 |
| 5161 | if needed), as appropriate for the type. Composite results (struct, |
| 5162 | union, or array) are returned in $2/$f0 and $3/$f2 according to the |
| 5163 | following rules: |
| 5164 | |
| 5165 | * A struct with only one or two floating point fields is returned in $f0 |
| 5166 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX |
| 5167 | case. |
| 5168 | |
| 5169 | * Any other composite results of at most 128 bits are returned in |
| 5170 | $2 (first 64 bits) and $3 (remainder, if necessary). |
| 5171 | |
| 5172 | * Larger composite results are handled by converting the function to a |
| 5173 | procedure with an implicit first parameter, which is a pointer to an area |
| 5174 | reserved by the caller to receive the result. [The o32-bit ABI requires |
| 5175 | that all composite results be handled by conversion to implicit first |
| 5176 | parameters. The MIPS/SGI Fortran implementation has always made a |
| 5177 | specific exception to return COMPLEX results in the floating point |
| 5178 | registers.] */ |
| 5179 | |
| 5180 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
| 5181 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 5182 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
| 5183 | && TYPE_LENGTH (type) == 16 |
| 5184 | && tdep->mips_fpu_type != MIPS_FPU_NONE) |
| 5185 | { |
| 5186 | /* A 128-bit floating-point value fills both $f0 and $f2. The |
| 5187 | two registers are used in the same as memory order, so the |
| 5188 | eight bytes with the lower memory address are in $f0. */ |
| 5189 | if (mips_debug) |
| 5190 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); |
| 5191 | mips_xfer_register (gdbarch, regcache, |
| 5192 | (gdbarch_num_regs (gdbarch) |
| 5193 | + mips_regnum (gdbarch)->fp0), |
| 5194 | 8, gdbarch_byte_order (gdbarch), |
| 5195 | readbuf, writebuf, 0); |
| 5196 | mips_xfer_register (gdbarch, regcache, |
| 5197 | (gdbarch_num_regs (gdbarch) |
| 5198 | + mips_regnum (gdbarch)->fp0 + 2), |
| 5199 | 8, gdbarch_byte_order (gdbarch), |
| 5200 | readbuf ? readbuf + 8 : readbuf, |
| 5201 | writebuf ? writebuf + 8 : writebuf, 0); |
| 5202 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 5203 | } |
| 5204 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
| 5205 | && tdep->mips_fpu_type != MIPS_FPU_NONE) |
| 5206 | { |
| 5207 | /* A single or double floating-point value that fits in FP0. */ |
| 5208 | if (mips_debug) |
| 5209 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); |
| 5210 | mips_xfer_register (gdbarch, regcache, |
| 5211 | (gdbarch_num_regs (gdbarch) |
| 5212 | + mips_regnum (gdbarch)->fp0), |
| 5213 | TYPE_LENGTH (type), |
| 5214 | gdbarch_byte_order (gdbarch), |
| 5215 | readbuf, writebuf, 0); |
| 5216 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 5217 | } |
| 5218 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 5219 | && TYPE_NFIELDS (type) <= 2 |
| 5220 | && TYPE_NFIELDS (type) >= 1 |
| 5221 | && ((TYPE_NFIELDS (type) == 1 |
| 5222 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
| 5223 | == TYPE_CODE_FLT)) |
| 5224 | || (TYPE_NFIELDS (type) == 2 |
| 5225 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
| 5226 | == TYPE_CODE_FLT) |
| 5227 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
| 5228 | == TYPE_CODE_FLT)))) |
| 5229 | { |
| 5230 | /* A struct that contains one or two floats. Each value is part |
| 5231 | in the least significant part of their floating point |
| 5232 | register (or GPR, for soft float). */ |
| 5233 | int regnum; |
| 5234 | int field; |
| 5235 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
| 5236 | ? mips_regnum (gdbarch)->fp0 |
| 5237 | : MIPS_V0_REGNUM); |
| 5238 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
| 5239 | { |
| 5240 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) |
| 5241 | / TARGET_CHAR_BIT); |
| 5242 | if (mips_debug) |
| 5243 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", |
| 5244 | offset); |
| 5245 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
| 5246 | { |
| 5247 | /* A 16-byte long double field goes in two consecutive |
| 5248 | registers. */ |
| 5249 | mips_xfer_register (gdbarch, regcache, |
| 5250 | gdbarch_num_regs (gdbarch) + regnum, |
| 5251 | 8, |
| 5252 | gdbarch_byte_order (gdbarch), |
| 5253 | readbuf, writebuf, offset); |
| 5254 | mips_xfer_register (gdbarch, regcache, |
| 5255 | gdbarch_num_regs (gdbarch) + regnum + 1, |
| 5256 | 8, |
| 5257 | gdbarch_byte_order (gdbarch), |
| 5258 | readbuf, writebuf, offset + 8); |
| 5259 | } |
| 5260 | else |
| 5261 | mips_xfer_register (gdbarch, regcache, |
| 5262 | gdbarch_num_regs (gdbarch) + regnum, |
| 5263 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
| 5264 | gdbarch_byte_order (gdbarch), |
| 5265 | readbuf, writebuf, offset); |
| 5266 | } |
| 5267 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 5268 | } |
| 5269 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 5270 | || TYPE_CODE (type) == TYPE_CODE_UNION |
| 5271 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) |
| 5272 | { |
| 5273 | /* A composite type. Extract the left justified value, |
| 5274 | regardless of the byte order. I.e. DO NOT USE |
| 5275 | mips_xfer_lower. */ |
| 5276 | int offset; |
| 5277 | int regnum; |
| 5278 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
| 5279 | offset < TYPE_LENGTH (type); |
| 5280 | offset += register_size (gdbarch, regnum), regnum++) |
| 5281 | { |
| 5282 | int xfer = register_size (gdbarch, regnum); |
| 5283 | if (offset + xfer > TYPE_LENGTH (type)) |
| 5284 | xfer = TYPE_LENGTH (type) - offset; |
| 5285 | if (mips_debug) |
| 5286 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", |
| 5287 | offset, xfer, regnum); |
| 5288 | mips_xfer_register (gdbarch, regcache, |
| 5289 | gdbarch_num_regs (gdbarch) + regnum, |
| 5290 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
| 5291 | offset); |
| 5292 | } |
| 5293 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 5294 | } |
| 5295 | else |
| 5296 | { |
| 5297 | /* A scalar extract each part but least-significant-byte |
| 5298 | justified. */ |
| 5299 | int offset; |
| 5300 | int regnum; |
| 5301 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
| 5302 | offset < TYPE_LENGTH (type); |
| 5303 | offset += register_size (gdbarch, regnum), regnum++) |
| 5304 | { |
| 5305 | int xfer = register_size (gdbarch, regnum); |
| 5306 | if (offset + xfer > TYPE_LENGTH (type)) |
| 5307 | xfer = TYPE_LENGTH (type) - offset; |
| 5308 | if (mips_debug) |
| 5309 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", |
| 5310 | offset, xfer, regnum); |
| 5311 | mips_xfer_register (gdbarch, regcache, |
| 5312 | gdbarch_num_regs (gdbarch) + regnum, |
| 5313 | xfer, gdbarch_byte_order (gdbarch), |
| 5314 | readbuf, writebuf, offset); |
| 5315 | } |
| 5316 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 5317 | } |
| 5318 | } |
| 5319 | |
| 5320 | /* Which registers to use for passing floating-point values between |
| 5321 | function calls, one of floating-point, general and both kinds of |
| 5322 | registers. O32 and O64 use different register kinds for standard |
| 5323 | MIPS and MIPS16 code; to make the handling of cases where we may |
| 5324 | not know what kind of code is being used (e.g. no debug information) |
| 5325 | easier we sometimes use both kinds. */ |
| 5326 | |
| 5327 | enum mips_fval_reg |
| 5328 | { |
| 5329 | mips_fval_fpr, |
| 5330 | mips_fval_gpr, |
| 5331 | mips_fval_both |
| 5332 | }; |
| 5333 | |
| 5334 | /* O32 ABI stuff. */ |
| 5335 | |
| 5336 | static CORE_ADDR |
| 5337 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 5338 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 5339 | int nargs, struct value **args, CORE_ADDR sp, |
| 5340 | int struct_return, CORE_ADDR struct_addr) |
| 5341 | { |
| 5342 | int argreg; |
| 5343 | int float_argreg; |
| 5344 | int argnum; |
| 5345 | int len = 0; |
| 5346 | int stack_offset = 0; |
| 5347 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 5348 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
| 5349 | |
| 5350 | /* For shared libraries, "t9" needs to point at the function |
| 5351 | address. */ |
| 5352 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
| 5353 | |
| 5354 | /* Set the return address register to point to the entry point of |
| 5355 | the program, where a breakpoint lies in wait. */ |
| 5356 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
| 5357 | |
| 5358 | /* First ensure that the stack and structure return address (if any) |
| 5359 | are properly aligned. The stack has to be at least 64-bit |
| 5360 | aligned even on 32-bit machines, because doubles must be 64-bit |
| 5361 | aligned. For n32 and n64, stack frames need to be 128-bit |
| 5362 | aligned, so we round to this widest known alignment. */ |
| 5363 | |
| 5364 | sp = align_down (sp, 16); |
| 5365 | struct_addr = align_down (struct_addr, 16); |
| 5366 | |
| 5367 | /* Now make space on the stack for the args. */ |
| 5368 | for (argnum = 0; argnum < nargs; argnum++) |
| 5369 | { |
| 5370 | struct type *arg_type = check_typedef (value_type (args[argnum])); |
| 5371 | |
| 5372 | /* Align to double-word if necessary. */ |
| 5373 | if (mips_type_needs_double_align (arg_type)) |
| 5374 | len = align_up (len, MIPS32_REGSIZE * 2); |
| 5375 | /* Allocate space on the stack. */ |
| 5376 | len += align_up (TYPE_LENGTH (arg_type), MIPS32_REGSIZE); |
| 5377 | } |
| 5378 | sp -= align_up (len, 16); |
| 5379 | |
| 5380 | if (mips_debug) |
| 5381 | fprintf_unfiltered (gdb_stdlog, |
| 5382 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
| 5383 | paddress (gdbarch, sp), (long) align_up (len, 16)); |
| 5384 | |
| 5385 | /* Initialize the integer and float register pointers. */ |
| 5386 | argreg = MIPS_A0_REGNUM; |
| 5387 | float_argreg = mips_fpa0_regnum (gdbarch); |
| 5388 | |
| 5389 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
| 5390 | if (struct_return) |
| 5391 | { |
| 5392 | if (mips_debug) |
| 5393 | fprintf_unfiltered (gdb_stdlog, |
| 5394 | "mips_o32_push_dummy_call: " |
| 5395 | "struct_return reg=%d %s\n", |
| 5396 | argreg, paddress (gdbarch, struct_addr)); |
| 5397 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
| 5398 | stack_offset += MIPS32_REGSIZE; |
| 5399 | } |
| 5400 | |
| 5401 | /* Now load as many as possible of the first arguments into |
| 5402 | registers, and push the rest onto the stack. Loop thru args |
| 5403 | from first to last. */ |
| 5404 | for (argnum = 0; argnum < nargs; argnum++) |
| 5405 | { |
| 5406 | const gdb_byte *val; |
| 5407 | struct value *arg = args[argnum]; |
| 5408 | struct type *arg_type = check_typedef (value_type (arg)); |
| 5409 | int len = TYPE_LENGTH (arg_type); |
| 5410 | enum type_code typecode = TYPE_CODE (arg_type); |
| 5411 | |
| 5412 | if (mips_debug) |
| 5413 | fprintf_unfiltered (gdb_stdlog, |
| 5414 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
| 5415 | argnum + 1, len, (int) typecode); |
| 5416 | |
| 5417 | val = value_contents (arg); |
| 5418 | |
| 5419 | /* 32-bit ABIs always start floating point arguments in an |
| 5420 | even-numbered floating point register. Round the FP register |
| 5421 | up before the check to see if there are any FP registers |
| 5422 | left. O32 targets also pass the FP in the integer registers |
| 5423 | so also round up normal registers. */ |
| 5424 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
| 5425 | { |
| 5426 | if ((float_argreg & 1)) |
| 5427 | float_argreg++; |
| 5428 | } |
| 5429 | |
| 5430 | /* Floating point arguments passed in registers have to be |
| 5431 | treated specially. On 32-bit architectures, doubles are |
| 5432 | passed in register pairs; the even FP register gets the |
| 5433 | low word, and the odd FP register gets the high word. |
| 5434 | On O32, the first two floating point arguments are also |
| 5435 | copied to general registers, following their memory order, |
| 5436 | because MIPS16 functions don't use float registers for |
| 5437 | arguments. This duplication of arguments in general |
| 5438 | registers can't hurt non-MIPS16 functions, because those |
| 5439 | registers are normally skipped. */ |
| 5440 | |
| 5441 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
| 5442 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) |
| 5443 | { |
| 5444 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
| 5445 | { |
| 5446 | int freg_offset = gdbarch_byte_order (gdbarch) |
| 5447 | == BFD_ENDIAN_BIG ? 1 : 0; |
| 5448 | unsigned long regval; |
| 5449 | |
| 5450 | /* First word. */ |
| 5451 | regval = extract_unsigned_integer (val, 4, byte_order); |
| 5452 | if (mips_debug) |
| 5453 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
| 5454 | float_argreg + freg_offset, |
| 5455 | phex (regval, 4)); |
| 5456 | regcache_cooked_write_unsigned (regcache, |
| 5457 | float_argreg++ + freg_offset, |
| 5458 | regval); |
| 5459 | if (mips_debug) |
| 5460 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
| 5461 | argreg, phex (regval, 4)); |
| 5462 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
| 5463 | |
| 5464 | /* Second word. */ |
| 5465 | regval = extract_unsigned_integer (val + 4, 4, byte_order); |
| 5466 | if (mips_debug) |
| 5467 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
| 5468 | float_argreg - freg_offset, |
| 5469 | phex (regval, 4)); |
| 5470 | regcache_cooked_write_unsigned (regcache, |
| 5471 | float_argreg++ - freg_offset, |
| 5472 | regval); |
| 5473 | if (mips_debug) |
| 5474 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
| 5475 | argreg, phex (regval, 4)); |
| 5476 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
| 5477 | } |
| 5478 | else |
| 5479 | { |
| 5480 | /* This is a floating point value that fits entirely |
| 5481 | in a single register. */ |
| 5482 | /* On 32 bit ABI's the float_argreg is further adjusted |
| 5483 | above to ensure that it is even register aligned. */ |
| 5484 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
| 5485 | if (mips_debug) |
| 5486 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
| 5487 | float_argreg, phex (regval, len)); |
| 5488 | regcache_cooked_write_unsigned (regcache, |
| 5489 | float_argreg++, regval); |
| 5490 | /* Although two FP registers are reserved for each |
| 5491 | argument, only one corresponding integer register is |
| 5492 | reserved. */ |
| 5493 | if (mips_debug) |
| 5494 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
| 5495 | argreg, phex (regval, len)); |
| 5496 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
| 5497 | } |
| 5498 | /* Reserve space for the FP register. */ |
| 5499 | stack_offset += align_up (len, MIPS32_REGSIZE); |
| 5500 | } |
| 5501 | else |
| 5502 | { |
| 5503 | /* Copy the argument to general registers or the stack in |
| 5504 | register-sized pieces. Large arguments are split between |
| 5505 | registers and stack. */ |
| 5506 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
| 5507 | are treated specially: Irix cc passes |
| 5508 | them in registers where gcc sometimes puts them on the |
| 5509 | stack. For maximum compatibility, we will put them in |
| 5510 | both places. */ |
| 5511 | int odd_sized_struct = (len > MIPS32_REGSIZE |
| 5512 | && len % MIPS32_REGSIZE != 0); |
| 5513 | /* Structures should be aligned to eight bytes (even arg registers) |
| 5514 | on MIPS_ABI_O32, if their first member has double precision. */ |
| 5515 | if (mips_type_needs_double_align (arg_type)) |
| 5516 | { |
| 5517 | if ((argreg & 1)) |
| 5518 | { |
| 5519 | argreg++; |
| 5520 | stack_offset += MIPS32_REGSIZE; |
| 5521 | } |
| 5522 | } |
| 5523 | while (len > 0) |
| 5524 | { |
| 5525 | /* Remember if the argument was written to the stack. */ |
| 5526 | int stack_used_p = 0; |
| 5527 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
| 5528 | |
| 5529 | if (mips_debug) |
| 5530 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", |
| 5531 | partial_len); |
| 5532 | |
| 5533 | /* Write this portion of the argument to the stack. */ |
| 5534 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
| 5535 | || odd_sized_struct) |
| 5536 | { |
| 5537 | /* Should shorter than int integer values be |
| 5538 | promoted to int before being stored? */ |
| 5539 | int longword_offset = 0; |
| 5540 | CORE_ADDR addr; |
| 5541 | stack_used_p = 1; |
| 5542 | |
| 5543 | if (mips_debug) |
| 5544 | { |
| 5545 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
| 5546 | paddress (gdbarch, stack_offset)); |
| 5547 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", |
| 5548 | paddress (gdbarch, longword_offset)); |
| 5549 | } |
| 5550 | |
| 5551 | addr = sp + stack_offset + longword_offset; |
| 5552 | |
| 5553 | if (mips_debug) |
| 5554 | { |
| 5555 | int i; |
| 5556 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
| 5557 | paddress (gdbarch, addr)); |
| 5558 | for (i = 0; i < partial_len; i++) |
| 5559 | { |
| 5560 | fprintf_unfiltered (gdb_stdlog, "%02x", |
| 5561 | val[i] & 0xff); |
| 5562 | } |
| 5563 | } |
| 5564 | write_memory (addr, val, partial_len); |
| 5565 | } |
| 5566 | |
| 5567 | /* Note!!! This is NOT an else clause. Odd sized |
| 5568 | structs may go thru BOTH paths. */ |
| 5569 | /* Write this portion of the argument to a general |
| 5570 | purpose register. */ |
| 5571 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
| 5572 | { |
| 5573 | LONGEST regval = extract_signed_integer (val, partial_len, |
| 5574 | byte_order); |
| 5575 | /* Value may need to be sign extended, because |
| 5576 | mips_isa_regsize() != mips_abi_regsize(). */ |
| 5577 | |
| 5578 | /* A non-floating-point argument being passed in a |
| 5579 | general register. If a struct or union, and if |
| 5580 | the remaining length is smaller than the register |
| 5581 | size, we have to adjust the register value on |
| 5582 | big endian targets. |
| 5583 | |
| 5584 | It does not seem to be necessary to do the |
| 5585 | same for integral types. |
| 5586 | |
| 5587 | Also don't do this adjustment on O64 binaries. |
| 5588 | |
| 5589 | cagney/2001-07-23: gdb/179: Also, GCC, when |
| 5590 | outputting LE O32 with sizeof (struct) < |
| 5591 | mips_abi_regsize(), generates a left shift |
| 5592 | as part of storing the argument in a register |
| 5593 | (the left shift isn't generated when |
| 5594 | sizeof (struct) >= mips_abi_regsize()). Since |
| 5595 | it is quite possible that this is GCC |
| 5596 | contradicting the LE/O32 ABI, GDB has not been |
| 5597 | adjusted to accommodate this. Either someone |
| 5598 | needs to demonstrate that the LE/O32 ABI |
| 5599 | specifies such a left shift OR this new ABI gets |
| 5600 | identified as such and GDB gets tweaked |
| 5601 | accordingly. */ |
| 5602 | |
| 5603 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
| 5604 | && partial_len < MIPS32_REGSIZE |
| 5605 | && (typecode == TYPE_CODE_STRUCT |
| 5606 | || typecode == TYPE_CODE_UNION)) |
| 5607 | regval <<= ((MIPS32_REGSIZE - partial_len) |
| 5608 | * TARGET_CHAR_BIT); |
| 5609 | |
| 5610 | if (mips_debug) |
| 5611 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
| 5612 | argreg, |
| 5613 | phex (regval, MIPS32_REGSIZE)); |
| 5614 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 5615 | argreg++; |
| 5616 | |
| 5617 | /* Prevent subsequent floating point arguments from |
| 5618 | being passed in floating point registers. */ |
| 5619 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
| 5620 | } |
| 5621 | |
| 5622 | len -= partial_len; |
| 5623 | val += partial_len; |
| 5624 | |
| 5625 | /* Compute the offset into the stack at which we will |
| 5626 | copy the next parameter. |
| 5627 | |
| 5628 | In older ABIs, the caller reserved space for |
| 5629 | registers that contained arguments. This was loosely |
| 5630 | refered to as their "home". Consequently, space is |
| 5631 | always allocated. */ |
| 5632 | |
| 5633 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
| 5634 | } |
| 5635 | } |
| 5636 | if (mips_debug) |
| 5637 | fprintf_unfiltered (gdb_stdlog, "\n"); |
| 5638 | } |
| 5639 | |
| 5640 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
| 5641 | |
| 5642 | /* Return adjusted stack pointer. */ |
| 5643 | return sp; |
| 5644 | } |
| 5645 | |
| 5646 | static enum return_value_convention |
| 5647 | mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, |
| 5648 | struct type *type, struct regcache *regcache, |
| 5649 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 5650 | { |
| 5651 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
| 5652 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
| 5653 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 5654 | enum mips_fval_reg fval_reg; |
| 5655 | |
| 5656 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
| 5657 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 5658 | || TYPE_CODE (type) == TYPE_CODE_UNION |
| 5659 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) |
| 5660 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 5661 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
| 5662 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) |
| 5663 | { |
| 5664 | /* A single-precision floating-point value. If reading in or copying, |
| 5665 | then we get it from/put it to FP0 for standard MIPS code or GPR2 |
| 5666 | for MIPS16 code. If writing out only, then we put it to both FP0 |
| 5667 | and GPR2. We do not support reading in with no function known, if |
| 5668 | this safety check ever triggers, then we'll have to try harder. */ |
| 5669 | gdb_assert (function || !readbuf); |
| 5670 | if (mips_debug) |
| 5671 | switch (fval_reg) |
| 5672 | { |
| 5673 | case mips_fval_fpr: |
| 5674 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); |
| 5675 | break; |
| 5676 | case mips_fval_gpr: |
| 5677 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); |
| 5678 | break; |
| 5679 | case mips_fval_both: |
| 5680 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); |
| 5681 | break; |
| 5682 | } |
| 5683 | if (fval_reg != mips_fval_gpr) |
| 5684 | mips_xfer_register (gdbarch, regcache, |
| 5685 | (gdbarch_num_regs (gdbarch) |
| 5686 | + mips_regnum (gdbarch)->fp0), |
| 5687 | TYPE_LENGTH (type), |
| 5688 | gdbarch_byte_order (gdbarch), |
| 5689 | readbuf, writebuf, 0); |
| 5690 | if (fval_reg != mips_fval_fpr) |
| 5691 | mips_xfer_register (gdbarch, regcache, |
| 5692 | gdbarch_num_regs (gdbarch) + 2, |
| 5693 | TYPE_LENGTH (type), |
| 5694 | gdbarch_byte_order (gdbarch), |
| 5695 | readbuf, writebuf, 0); |
| 5696 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 5697 | } |
| 5698 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
| 5699 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) |
| 5700 | { |
| 5701 | /* A double-precision floating-point value. If reading in or copying, |
| 5702 | then we get it from/put it to FP1 and FP0 for standard MIPS code or |
| 5703 | GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it |
| 5704 | to both FP1/FP0 and GPR2/GPR3. We do not support reading in with |
| 5705 | no function known, if this safety check ever triggers, then we'll |
| 5706 | have to try harder. */ |
| 5707 | gdb_assert (function || !readbuf); |
| 5708 | if (mips_debug) |
| 5709 | switch (fval_reg) |
| 5710 | { |
| 5711 | case mips_fval_fpr: |
| 5712 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); |
| 5713 | break; |
| 5714 | case mips_fval_gpr: |
| 5715 | fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n"); |
| 5716 | break; |
| 5717 | case mips_fval_both: |
| 5718 | fprintf_unfiltered (gdb_stderr, |
| 5719 | "Return float in $fp1/$fp0 and $2/$3\n"); |
| 5720 | break; |
| 5721 | } |
| 5722 | if (fval_reg != mips_fval_gpr) |
| 5723 | { |
| 5724 | /* The most significant part goes in FP1, and the least significant |
| 5725 | in FP0. */ |
| 5726 | switch (gdbarch_byte_order (gdbarch)) |
| 5727 | { |
| 5728 | case BFD_ENDIAN_LITTLE: |
| 5729 | mips_xfer_register (gdbarch, regcache, |
| 5730 | (gdbarch_num_regs (gdbarch) |
| 5731 | + mips_regnum (gdbarch)->fp0 + 0), |
| 5732 | 4, gdbarch_byte_order (gdbarch), |
| 5733 | readbuf, writebuf, 0); |
| 5734 | mips_xfer_register (gdbarch, regcache, |
| 5735 | (gdbarch_num_regs (gdbarch) |
| 5736 | + mips_regnum (gdbarch)->fp0 + 1), |
| 5737 | 4, gdbarch_byte_order (gdbarch), |
| 5738 | readbuf, writebuf, 4); |
| 5739 | break; |
| 5740 | case BFD_ENDIAN_BIG: |
| 5741 | mips_xfer_register (gdbarch, regcache, |
| 5742 | (gdbarch_num_regs (gdbarch) |
| 5743 | + mips_regnum (gdbarch)->fp0 + 1), |
| 5744 | 4, gdbarch_byte_order (gdbarch), |
| 5745 | readbuf, writebuf, 0); |
| 5746 | mips_xfer_register (gdbarch, regcache, |
| 5747 | (gdbarch_num_regs (gdbarch) |
| 5748 | + mips_regnum (gdbarch)->fp0 + 0), |
| 5749 | 4, gdbarch_byte_order (gdbarch), |
| 5750 | readbuf, writebuf, 4); |
| 5751 | break; |
| 5752 | default: |
| 5753 | internal_error (__FILE__, __LINE__, _("bad switch")); |
| 5754 | } |
| 5755 | } |
| 5756 | if (fval_reg != mips_fval_fpr) |
| 5757 | { |
| 5758 | /* The two 32-bit parts are always placed in GPR2 and GPR3 |
| 5759 | following these registers' memory order. */ |
| 5760 | mips_xfer_register (gdbarch, regcache, |
| 5761 | gdbarch_num_regs (gdbarch) + 2, |
| 5762 | 4, gdbarch_byte_order (gdbarch), |
| 5763 | readbuf, writebuf, 0); |
| 5764 | mips_xfer_register (gdbarch, regcache, |
| 5765 | gdbarch_num_regs (gdbarch) + 3, |
| 5766 | 4, gdbarch_byte_order (gdbarch), |
| 5767 | readbuf, writebuf, 4); |
| 5768 | } |
| 5769 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 5770 | } |
| 5771 | #if 0 |
| 5772 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 5773 | && TYPE_NFIELDS (type) <= 2 |
| 5774 | && TYPE_NFIELDS (type) >= 1 |
| 5775 | && ((TYPE_NFIELDS (type) == 1 |
| 5776 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) |
| 5777 | == TYPE_CODE_FLT)) |
| 5778 | || (TYPE_NFIELDS (type) == 2 |
| 5779 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) |
| 5780 | == TYPE_CODE_FLT) |
| 5781 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) |
| 5782 | == TYPE_CODE_FLT))) |
| 5783 | && tdep->mips_fpu_type != MIPS_FPU_NONE) |
| 5784 | { |
| 5785 | /* A struct that contains one or two floats. Each value is part |
| 5786 | in the least significant part of their floating point |
| 5787 | register.. */ |
| 5788 | gdb_byte reg[MAX_REGISTER_SIZE]; |
| 5789 | int regnum; |
| 5790 | int field; |
| 5791 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
| 5792 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
| 5793 | { |
| 5794 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) |
| 5795 | / TARGET_CHAR_BIT); |
| 5796 | if (mips_debug) |
| 5797 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", |
| 5798 | offset); |
| 5799 | mips_xfer_register (gdbarch, regcache, |
| 5800 | gdbarch_num_regs (gdbarch) + regnum, |
| 5801 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
| 5802 | gdbarch_byte_order (gdbarch), |
| 5803 | readbuf, writebuf, offset); |
| 5804 | } |
| 5805 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 5806 | } |
| 5807 | #endif |
| 5808 | #if 0 |
| 5809 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 5810 | || TYPE_CODE (type) == TYPE_CODE_UNION) |
| 5811 | { |
| 5812 | /* A structure or union. Extract the left justified value, |
| 5813 | regardless of the byte order. I.e. DO NOT USE |
| 5814 | mips_xfer_lower. */ |
| 5815 | int offset; |
| 5816 | int regnum; |
| 5817 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
| 5818 | offset < TYPE_LENGTH (type); |
| 5819 | offset += register_size (gdbarch, regnum), regnum++) |
| 5820 | { |
| 5821 | int xfer = register_size (gdbarch, regnum); |
| 5822 | if (offset + xfer > TYPE_LENGTH (type)) |
| 5823 | xfer = TYPE_LENGTH (type) - offset; |
| 5824 | if (mips_debug) |
| 5825 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", |
| 5826 | offset, xfer, regnum); |
| 5827 | mips_xfer_register (gdbarch, regcache, |
| 5828 | gdbarch_num_regs (gdbarch) + regnum, xfer, |
| 5829 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
| 5830 | } |
| 5831 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 5832 | } |
| 5833 | #endif |
| 5834 | else |
| 5835 | { |
| 5836 | /* A scalar extract each part but least-significant-byte |
| 5837 | justified. o32 thinks registers are 4 byte, regardless of |
| 5838 | the ISA. */ |
| 5839 | int offset; |
| 5840 | int regnum; |
| 5841 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
| 5842 | offset < TYPE_LENGTH (type); |
| 5843 | offset += MIPS32_REGSIZE, regnum++) |
| 5844 | { |
| 5845 | int xfer = MIPS32_REGSIZE; |
| 5846 | if (offset + xfer > TYPE_LENGTH (type)) |
| 5847 | xfer = TYPE_LENGTH (type) - offset; |
| 5848 | if (mips_debug) |
| 5849 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", |
| 5850 | offset, xfer, regnum); |
| 5851 | mips_xfer_register (gdbarch, regcache, |
| 5852 | gdbarch_num_regs (gdbarch) + regnum, xfer, |
| 5853 | gdbarch_byte_order (gdbarch), |
| 5854 | readbuf, writebuf, offset); |
| 5855 | } |
| 5856 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 5857 | } |
| 5858 | } |
| 5859 | |
| 5860 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 |
| 5861 | ABI. */ |
| 5862 | |
| 5863 | static CORE_ADDR |
| 5864 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 5865 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 5866 | int nargs, |
| 5867 | struct value **args, CORE_ADDR sp, |
| 5868 | int struct_return, CORE_ADDR struct_addr) |
| 5869 | { |
| 5870 | int argreg; |
| 5871 | int float_argreg; |
| 5872 | int argnum; |
| 5873 | int len = 0; |
| 5874 | int stack_offset = 0; |
| 5875 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 5876 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
| 5877 | |
| 5878 | /* For shared libraries, "t9" needs to point at the function |
| 5879 | address. */ |
| 5880 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
| 5881 | |
| 5882 | /* Set the return address register to point to the entry point of |
| 5883 | the program, where a breakpoint lies in wait. */ |
| 5884 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
| 5885 | |
| 5886 | /* First ensure that the stack and structure return address (if any) |
| 5887 | are properly aligned. The stack has to be at least 64-bit |
| 5888 | aligned even on 32-bit machines, because doubles must be 64-bit |
| 5889 | aligned. For n32 and n64, stack frames need to be 128-bit |
| 5890 | aligned, so we round to this widest known alignment. */ |
| 5891 | |
| 5892 | sp = align_down (sp, 16); |
| 5893 | struct_addr = align_down (struct_addr, 16); |
| 5894 | |
| 5895 | /* Now make space on the stack for the args. */ |
| 5896 | for (argnum = 0; argnum < nargs; argnum++) |
| 5897 | { |
| 5898 | struct type *arg_type = check_typedef (value_type (args[argnum])); |
| 5899 | |
| 5900 | /* Allocate space on the stack. */ |
| 5901 | len += align_up (TYPE_LENGTH (arg_type), MIPS64_REGSIZE); |
| 5902 | } |
| 5903 | sp -= align_up (len, 16); |
| 5904 | |
| 5905 | if (mips_debug) |
| 5906 | fprintf_unfiltered (gdb_stdlog, |
| 5907 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
| 5908 | paddress (gdbarch, sp), (long) align_up (len, 16)); |
| 5909 | |
| 5910 | /* Initialize the integer and float register pointers. */ |
| 5911 | argreg = MIPS_A0_REGNUM; |
| 5912 | float_argreg = mips_fpa0_regnum (gdbarch); |
| 5913 | |
| 5914 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
| 5915 | if (struct_return) |
| 5916 | { |
| 5917 | if (mips_debug) |
| 5918 | fprintf_unfiltered (gdb_stdlog, |
| 5919 | "mips_o64_push_dummy_call: " |
| 5920 | "struct_return reg=%d %s\n", |
| 5921 | argreg, paddress (gdbarch, struct_addr)); |
| 5922 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
| 5923 | stack_offset += MIPS64_REGSIZE; |
| 5924 | } |
| 5925 | |
| 5926 | /* Now load as many as possible of the first arguments into |
| 5927 | registers, and push the rest onto the stack. Loop thru args |
| 5928 | from first to last. */ |
| 5929 | for (argnum = 0; argnum < nargs; argnum++) |
| 5930 | { |
| 5931 | const gdb_byte *val; |
| 5932 | struct value *arg = args[argnum]; |
| 5933 | struct type *arg_type = check_typedef (value_type (arg)); |
| 5934 | int len = TYPE_LENGTH (arg_type); |
| 5935 | enum type_code typecode = TYPE_CODE (arg_type); |
| 5936 | |
| 5937 | if (mips_debug) |
| 5938 | fprintf_unfiltered (gdb_stdlog, |
| 5939 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
| 5940 | argnum + 1, len, (int) typecode); |
| 5941 | |
| 5942 | val = value_contents (arg); |
| 5943 | |
| 5944 | /* Floating point arguments passed in registers have to be |
| 5945 | treated specially. On 32-bit architectures, doubles are |
| 5946 | passed in register pairs; the even FP register gets the |
| 5947 | low word, and the odd FP register gets the high word. |
| 5948 | On O64, the first two floating point arguments are also |
| 5949 | copied to general registers, because MIPS16 functions |
| 5950 | don't use float registers for arguments. This duplication |
| 5951 | of arguments in general registers can't hurt non-MIPS16 |
| 5952 | functions because those registers are normally skipped. */ |
| 5953 | |
| 5954 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
| 5955 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) |
| 5956 | { |
| 5957 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
| 5958 | if (mips_debug) |
| 5959 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
| 5960 | float_argreg, phex (regval, len)); |
| 5961 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
| 5962 | if (mips_debug) |
| 5963 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
| 5964 | argreg, phex (regval, len)); |
| 5965 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 5966 | argreg++; |
| 5967 | /* Reserve space for the FP register. */ |
| 5968 | stack_offset += align_up (len, MIPS64_REGSIZE); |
| 5969 | } |
| 5970 | else |
| 5971 | { |
| 5972 | /* Copy the argument to general registers or the stack in |
| 5973 | register-sized pieces. Large arguments are split between |
| 5974 | registers and stack. */ |
| 5975 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
| 5976 | are treated specially: Irix cc passes them in registers |
| 5977 | where gcc sometimes puts them on the stack. For maximum |
| 5978 | compatibility, we will put them in both places. */ |
| 5979 | int odd_sized_struct = (len > MIPS64_REGSIZE |
| 5980 | && len % MIPS64_REGSIZE != 0); |
| 5981 | while (len > 0) |
| 5982 | { |
| 5983 | /* Remember if the argument was written to the stack. */ |
| 5984 | int stack_used_p = 0; |
| 5985 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
| 5986 | |
| 5987 | if (mips_debug) |
| 5988 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", |
| 5989 | partial_len); |
| 5990 | |
| 5991 | /* Write this portion of the argument to the stack. */ |
| 5992 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
| 5993 | || odd_sized_struct) |
| 5994 | { |
| 5995 | /* Should shorter than int integer values be |
| 5996 | promoted to int before being stored? */ |
| 5997 | int longword_offset = 0; |
| 5998 | CORE_ADDR addr; |
| 5999 | stack_used_p = 1; |
| 6000 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 6001 | { |
| 6002 | if ((typecode == TYPE_CODE_INT |
| 6003 | || typecode == TYPE_CODE_PTR |
| 6004 | || typecode == TYPE_CODE_FLT) |
| 6005 | && len <= 4) |
| 6006 | longword_offset = MIPS64_REGSIZE - len; |
| 6007 | } |
| 6008 | |
| 6009 | if (mips_debug) |
| 6010 | { |
| 6011 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
| 6012 | paddress (gdbarch, stack_offset)); |
| 6013 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", |
| 6014 | paddress (gdbarch, longword_offset)); |
| 6015 | } |
| 6016 | |
| 6017 | addr = sp + stack_offset + longword_offset; |
| 6018 | |
| 6019 | if (mips_debug) |
| 6020 | { |
| 6021 | int i; |
| 6022 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
| 6023 | paddress (gdbarch, addr)); |
| 6024 | for (i = 0; i < partial_len; i++) |
| 6025 | { |
| 6026 | fprintf_unfiltered (gdb_stdlog, "%02x", |
| 6027 | val[i] & 0xff); |
| 6028 | } |
| 6029 | } |
| 6030 | write_memory (addr, val, partial_len); |
| 6031 | } |
| 6032 | |
| 6033 | /* Note!!! This is NOT an else clause. Odd sized |
| 6034 | structs may go thru BOTH paths. */ |
| 6035 | /* Write this portion of the argument to a general |
| 6036 | purpose register. */ |
| 6037 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
| 6038 | { |
| 6039 | LONGEST regval = extract_signed_integer (val, partial_len, |
| 6040 | byte_order); |
| 6041 | /* Value may need to be sign extended, because |
| 6042 | mips_isa_regsize() != mips_abi_regsize(). */ |
| 6043 | |
| 6044 | /* A non-floating-point argument being passed in a |
| 6045 | general register. If a struct or union, and if |
| 6046 | the remaining length is smaller than the register |
| 6047 | size, we have to adjust the register value on |
| 6048 | big endian targets. |
| 6049 | |
| 6050 | It does not seem to be necessary to do the |
| 6051 | same for integral types. */ |
| 6052 | |
| 6053 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
| 6054 | && partial_len < MIPS64_REGSIZE |
| 6055 | && (typecode == TYPE_CODE_STRUCT |
| 6056 | || typecode == TYPE_CODE_UNION)) |
| 6057 | regval <<= ((MIPS64_REGSIZE - partial_len) |
| 6058 | * TARGET_CHAR_BIT); |
| 6059 | |
| 6060 | if (mips_debug) |
| 6061 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
| 6062 | argreg, |
| 6063 | phex (regval, MIPS64_REGSIZE)); |
| 6064 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 6065 | argreg++; |
| 6066 | |
| 6067 | /* Prevent subsequent floating point arguments from |
| 6068 | being passed in floating point registers. */ |
| 6069 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
| 6070 | } |
| 6071 | |
| 6072 | len -= partial_len; |
| 6073 | val += partial_len; |
| 6074 | |
| 6075 | /* Compute the offset into the stack at which we will |
| 6076 | copy the next parameter. |
| 6077 | |
| 6078 | In older ABIs, the caller reserved space for |
| 6079 | registers that contained arguments. This was loosely |
| 6080 | refered to as their "home". Consequently, space is |
| 6081 | always allocated. */ |
| 6082 | |
| 6083 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
| 6084 | } |
| 6085 | } |
| 6086 | if (mips_debug) |
| 6087 | fprintf_unfiltered (gdb_stdlog, "\n"); |
| 6088 | } |
| 6089 | |
| 6090 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
| 6091 | |
| 6092 | /* Return adjusted stack pointer. */ |
| 6093 | return sp; |
| 6094 | } |
| 6095 | |
| 6096 | static enum return_value_convention |
| 6097 | mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, |
| 6098 | struct type *type, struct regcache *regcache, |
| 6099 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 6100 | { |
| 6101 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
| 6102 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
| 6103 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 6104 | enum mips_fval_reg fval_reg; |
| 6105 | |
| 6106 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
| 6107 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 6108 | || TYPE_CODE (type) == TYPE_CODE_UNION |
| 6109 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) |
| 6110 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 6111 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
| 6112 | { |
| 6113 | /* A floating-point value. If reading in or copying, then we get it |
| 6114 | from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code. |
| 6115 | If writing out only, then we put it to both FP0 and GPR2. We do |
| 6116 | not support reading in with no function known, if this safety |
| 6117 | check ever triggers, then we'll have to try harder. */ |
| 6118 | gdb_assert (function || !readbuf); |
| 6119 | if (mips_debug) |
| 6120 | switch (fval_reg) |
| 6121 | { |
| 6122 | case mips_fval_fpr: |
| 6123 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); |
| 6124 | break; |
| 6125 | case mips_fval_gpr: |
| 6126 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); |
| 6127 | break; |
| 6128 | case mips_fval_both: |
| 6129 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); |
| 6130 | break; |
| 6131 | } |
| 6132 | if (fval_reg != mips_fval_gpr) |
| 6133 | mips_xfer_register (gdbarch, regcache, |
| 6134 | (gdbarch_num_regs (gdbarch) |
| 6135 | + mips_regnum (gdbarch)->fp0), |
| 6136 | TYPE_LENGTH (type), |
| 6137 | gdbarch_byte_order (gdbarch), |
| 6138 | readbuf, writebuf, 0); |
| 6139 | if (fval_reg != mips_fval_fpr) |
| 6140 | mips_xfer_register (gdbarch, regcache, |
| 6141 | gdbarch_num_regs (gdbarch) + 2, |
| 6142 | TYPE_LENGTH (type), |
| 6143 | gdbarch_byte_order (gdbarch), |
| 6144 | readbuf, writebuf, 0); |
| 6145 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 6146 | } |
| 6147 | else |
| 6148 | { |
| 6149 | /* A scalar extract each part but least-significant-byte |
| 6150 | justified. */ |
| 6151 | int offset; |
| 6152 | int regnum; |
| 6153 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
| 6154 | offset < TYPE_LENGTH (type); |
| 6155 | offset += MIPS64_REGSIZE, regnum++) |
| 6156 | { |
| 6157 | int xfer = MIPS64_REGSIZE; |
| 6158 | if (offset + xfer > TYPE_LENGTH (type)) |
| 6159 | xfer = TYPE_LENGTH (type) - offset; |
| 6160 | if (mips_debug) |
| 6161 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", |
| 6162 | offset, xfer, regnum); |
| 6163 | mips_xfer_register (gdbarch, regcache, |
| 6164 | gdbarch_num_regs (gdbarch) + regnum, |
| 6165 | xfer, gdbarch_byte_order (gdbarch), |
| 6166 | readbuf, writebuf, offset); |
| 6167 | } |
| 6168 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 6169 | } |
| 6170 | } |
| 6171 | |
| 6172 | /* Floating point register management. |
| 6173 | |
| 6174 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support |
| 6175 | 64bit operations, these early MIPS cpus treat fp register pairs |
| 6176 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp |
| 6177 | registers and offer a compatibility mode that emulates the MIPS2 fp |
| 6178 | model. When operating in MIPS2 fp compat mode, later cpu's split |
| 6179 | double precision floats into two 32-bit chunks and store them in |
| 6180 | consecutive fp regs. To display 64-bit floats stored in this |
| 6181 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. |
| 6182 | Throw in user-configurable endianness and you have a real mess. |
| 6183 | |
| 6184 | The way this works is: |
| 6185 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit |
| 6186 | double-precision value will be split across two logical registers. |
| 6187 | The lower-numbered logical register will hold the low-order bits, |
| 6188 | regardless of the processor's endianness. |
| 6189 | - If we are on a 64-bit processor, and we are looking for a |
| 6190 | single-precision value, it will be in the low ordered bits |
| 6191 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register |
| 6192 | save slot in memory. |
| 6193 | - If we are in 64-bit mode, everything is straightforward. |
| 6194 | |
| 6195 | Note that this code only deals with "live" registers at the top of the |
| 6196 | stack. We will attempt to deal with saved registers later, when |
| 6197 | the raw/cooked register interface is in place. (We need a general |
| 6198 | interface that can deal with dynamic saved register sizes -- fp |
| 6199 | regs could be 32 bits wide in one frame and 64 on the frame above |
| 6200 | and below). */ |
| 6201 | |
| 6202 | /* Copy a 32-bit single-precision value from the current frame |
| 6203 | into rare_buffer. */ |
| 6204 | |
| 6205 | static void |
| 6206 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
| 6207 | gdb_byte *rare_buffer) |
| 6208 | { |
| 6209 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 6210 | int raw_size = register_size (gdbarch, regno); |
| 6211 | gdb_byte *raw_buffer = (gdb_byte *) alloca (raw_size); |
| 6212 | |
| 6213 | if (!deprecated_frame_register_read (frame, regno, raw_buffer)) |
| 6214 | error (_("can't read register %d (%s)"), |
| 6215 | regno, gdbarch_register_name (gdbarch, regno)); |
| 6216 | if (raw_size == 8) |
| 6217 | { |
| 6218 | /* We have a 64-bit value for this register. Find the low-order |
| 6219 | 32 bits. */ |
| 6220 | int offset; |
| 6221 | |
| 6222 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 6223 | offset = 4; |
| 6224 | else |
| 6225 | offset = 0; |
| 6226 | |
| 6227 | memcpy (rare_buffer, raw_buffer + offset, 4); |
| 6228 | } |
| 6229 | else |
| 6230 | { |
| 6231 | memcpy (rare_buffer, raw_buffer, 4); |
| 6232 | } |
| 6233 | } |
| 6234 | |
| 6235 | /* Copy a 64-bit double-precision value from the current frame into |
| 6236 | rare_buffer. This may include getting half of it from the next |
| 6237 | register. */ |
| 6238 | |
| 6239 | static void |
| 6240 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
| 6241 | gdb_byte *rare_buffer) |
| 6242 | { |
| 6243 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 6244 | int raw_size = register_size (gdbarch, regno); |
| 6245 | |
| 6246 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
| 6247 | { |
| 6248 | /* We have a 64-bit value for this register, and we should use |
| 6249 | all 64 bits. */ |
| 6250 | if (!deprecated_frame_register_read (frame, regno, rare_buffer)) |
| 6251 | error (_("can't read register %d (%s)"), |
| 6252 | regno, gdbarch_register_name (gdbarch, regno)); |
| 6253 | } |
| 6254 | else |
| 6255 | { |
| 6256 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
| 6257 | |
| 6258 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
| 6259 | internal_error (__FILE__, __LINE__, |
| 6260 | _("mips_read_fp_register_double: bad access to " |
| 6261 | "odd-numbered FP register")); |
| 6262 | |
| 6263 | /* mips_read_fp_register_single will find the correct 32 bits from |
| 6264 | each register. */ |
| 6265 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 6266 | { |
| 6267 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
| 6268 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); |
| 6269 | } |
| 6270 | else |
| 6271 | { |
| 6272 | mips_read_fp_register_single (frame, regno, rare_buffer); |
| 6273 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); |
| 6274 | } |
| 6275 | } |
| 6276 | } |
| 6277 | |
| 6278 | static void |
| 6279 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
| 6280 | int regnum) |
| 6281 | { /* Do values for FP (float) regs. */ |
| 6282 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 6283 | gdb_byte *raw_buffer; |
| 6284 | double doub, flt1; /* Doubles extracted from raw hex data. */ |
| 6285 | int inv1, inv2; |
| 6286 | |
| 6287 | raw_buffer |
| 6288 | = ((gdb_byte *) |
| 6289 | alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0))); |
| 6290 | |
| 6291 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
| 6292 | fprintf_filtered (file, "%*s", |
| 6293 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
| 6294 | ""); |
| 6295 | |
| 6296 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
| 6297 | { |
| 6298 | struct value_print_options opts; |
| 6299 | |
| 6300 | /* 4-byte registers: Print hex and floating. Also print even |
| 6301 | numbered registers as doubles. */ |
| 6302 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
| 6303 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
| 6304 | raw_buffer, &inv1); |
| 6305 | |
| 6306 | get_formatted_print_options (&opts, 'x'); |
| 6307 | print_scalar_formatted (raw_buffer, |
| 6308 | builtin_type (gdbarch)->builtin_uint32, |
| 6309 | &opts, 'w', file); |
| 6310 | |
| 6311 | fprintf_filtered (file, " flt: "); |
| 6312 | if (inv1) |
| 6313 | fprintf_filtered (file, " <invalid float> "); |
| 6314 | else |
| 6315 | fprintf_filtered (file, "%-17.9g", flt1); |
| 6316 | |
| 6317 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
| 6318 | { |
| 6319 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
| 6320 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
| 6321 | raw_buffer, &inv2); |
| 6322 | |
| 6323 | fprintf_filtered (file, " dbl: "); |
| 6324 | if (inv2) |
| 6325 | fprintf_filtered (file, "<invalid double>"); |
| 6326 | else |
| 6327 | fprintf_filtered (file, "%-24.17g", doub); |
| 6328 | } |
| 6329 | } |
| 6330 | else |
| 6331 | { |
| 6332 | struct value_print_options opts; |
| 6333 | |
| 6334 | /* Eight byte registers: print each one as hex, float and double. */ |
| 6335 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
| 6336 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
| 6337 | raw_buffer, &inv1); |
| 6338 | |
| 6339 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
| 6340 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
| 6341 | raw_buffer, &inv2); |
| 6342 | |
| 6343 | get_formatted_print_options (&opts, 'x'); |
| 6344 | print_scalar_formatted (raw_buffer, |
| 6345 | builtin_type (gdbarch)->builtin_uint64, |
| 6346 | &opts, 'g', file); |
| 6347 | |
| 6348 | fprintf_filtered (file, " flt: "); |
| 6349 | if (inv1) |
| 6350 | fprintf_filtered (file, "<invalid float>"); |
| 6351 | else |
| 6352 | fprintf_filtered (file, "%-17.9g", flt1); |
| 6353 | |
| 6354 | fprintf_filtered (file, " dbl: "); |
| 6355 | if (inv2) |
| 6356 | fprintf_filtered (file, "<invalid double>"); |
| 6357 | else |
| 6358 | fprintf_filtered (file, "%-24.17g", doub); |
| 6359 | } |
| 6360 | } |
| 6361 | |
| 6362 | static void |
| 6363 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
| 6364 | int regnum) |
| 6365 | { |
| 6366 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 6367 | struct value_print_options opts; |
| 6368 | struct value *val; |
| 6369 | |
| 6370 | if (mips_float_register_p (gdbarch, regnum)) |
| 6371 | { |
| 6372 | mips_print_fp_register (file, frame, regnum); |
| 6373 | return; |
| 6374 | } |
| 6375 | |
| 6376 | val = get_frame_register_value (frame, regnum); |
| 6377 | |
| 6378 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
| 6379 | |
| 6380 | /* The problem with printing numeric register names (r26, etc.) is that |
| 6381 | the user can't use them on input. Probably the best solution is to |
| 6382 | fix it so that either the numeric or the funky (a2, etc.) names |
| 6383 | are accepted on input. */ |
| 6384 | if (regnum < MIPS_NUMREGS) |
| 6385 | fprintf_filtered (file, "(r%d): ", regnum); |
| 6386 | else |
| 6387 | fprintf_filtered (file, ": "); |
| 6388 | |
| 6389 | get_formatted_print_options (&opts, 'x'); |
| 6390 | val_print_scalar_formatted (value_type (val), |
| 6391 | value_contents_for_printing (val), |
| 6392 | value_embedded_offset (val), |
| 6393 | val, |
| 6394 | &opts, 0, file); |
| 6395 | } |
| 6396 | |
| 6397 | /* Print IEEE exception condition bits in FLAGS. */ |
| 6398 | |
| 6399 | static void |
| 6400 | print_fpu_flags (struct ui_file *file, int flags) |
| 6401 | { |
| 6402 | if (flags & (1 << 0)) |
| 6403 | fputs_filtered (" inexact", file); |
| 6404 | if (flags & (1 << 1)) |
| 6405 | fputs_filtered (" uflow", file); |
| 6406 | if (flags & (1 << 2)) |
| 6407 | fputs_filtered (" oflow", file); |
| 6408 | if (flags & (1 << 3)) |
| 6409 | fputs_filtered (" div0", file); |
| 6410 | if (flags & (1 << 4)) |
| 6411 | fputs_filtered (" inval", file); |
| 6412 | if (flags & (1 << 5)) |
| 6413 | fputs_filtered (" unimp", file); |
| 6414 | fputc_filtered ('\n', file); |
| 6415 | } |
| 6416 | |
| 6417 | /* Print interesting information about the floating point processor |
| 6418 | (if present) or emulator. */ |
| 6419 | |
| 6420 | static void |
| 6421 | mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
| 6422 | struct frame_info *frame, const char *args) |
| 6423 | { |
| 6424 | int fcsr = mips_regnum (gdbarch)->fp_control_status; |
| 6425 | enum mips_fpu_type type = MIPS_FPU_TYPE (gdbarch); |
| 6426 | ULONGEST fcs = 0; |
| 6427 | int i; |
| 6428 | |
| 6429 | if (fcsr == -1 || !read_frame_register_unsigned (frame, fcsr, &fcs)) |
| 6430 | type = MIPS_FPU_NONE; |
| 6431 | |
| 6432 | fprintf_filtered (file, "fpu type: %s\n", |
| 6433 | type == MIPS_FPU_DOUBLE ? "double-precision" |
| 6434 | : type == MIPS_FPU_SINGLE ? "single-precision" |
| 6435 | : "none / unused"); |
| 6436 | |
| 6437 | if (type == MIPS_FPU_NONE) |
| 6438 | return; |
| 6439 | |
| 6440 | fprintf_filtered (file, "reg size: %d bits\n", |
| 6441 | register_size (gdbarch, mips_regnum (gdbarch)->fp0) * 8); |
| 6442 | |
| 6443 | fputs_filtered ("cond :", file); |
| 6444 | if (fcs & (1 << 23)) |
| 6445 | fputs_filtered (" 0", file); |
| 6446 | for (i = 1; i <= 7; i++) |
| 6447 | if (fcs & (1 << (24 + i))) |
| 6448 | fprintf_filtered (file, " %d", i); |
| 6449 | fputc_filtered ('\n', file); |
| 6450 | |
| 6451 | fputs_filtered ("cause :", file); |
| 6452 | print_fpu_flags (file, (fcs >> 12) & 0x3f); |
| 6453 | fputs ("mask :", stdout); |
| 6454 | print_fpu_flags (file, (fcs >> 7) & 0x1f); |
| 6455 | fputs ("flags :", stdout); |
| 6456 | print_fpu_flags (file, (fcs >> 2) & 0x1f); |
| 6457 | |
| 6458 | fputs_filtered ("rounding: ", file); |
| 6459 | switch (fcs & 3) |
| 6460 | { |
| 6461 | case 0: fputs_filtered ("nearest\n", file); break; |
| 6462 | case 1: fputs_filtered ("zero\n", file); break; |
| 6463 | case 2: fputs_filtered ("+inf\n", file); break; |
| 6464 | case 3: fputs_filtered ("-inf\n", file); break; |
| 6465 | } |
| 6466 | |
| 6467 | fputs_filtered ("flush :", file); |
| 6468 | if (fcs & (1 << 21)) |
| 6469 | fputs_filtered (" nearest", file); |
| 6470 | if (fcs & (1 << 22)) |
| 6471 | fputs_filtered (" override", file); |
| 6472 | if (fcs & (1 << 24)) |
| 6473 | fputs_filtered (" zero", file); |
| 6474 | if ((fcs & (0xb << 21)) == 0) |
| 6475 | fputs_filtered (" no", file); |
| 6476 | fputc_filtered ('\n', file); |
| 6477 | |
| 6478 | fprintf_filtered (file, "nan2008 : %s\n", fcs & (1 << 18) ? "yes" : "no"); |
| 6479 | fprintf_filtered (file, "abs2008 : %s\n", fcs & (1 << 19) ? "yes" : "no"); |
| 6480 | fputc_filtered ('\n', file); |
| 6481 | |
| 6482 | default_print_float_info (gdbarch, file, frame, args); |
| 6483 | } |
| 6484 | |
| 6485 | /* Replacement for generic do_registers_info. |
| 6486 | Print regs in pretty columns. */ |
| 6487 | |
| 6488 | static int |
| 6489 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
| 6490 | int regnum) |
| 6491 | { |
| 6492 | fprintf_filtered (file, " "); |
| 6493 | mips_print_fp_register (file, frame, regnum); |
| 6494 | fprintf_filtered (file, "\n"); |
| 6495 | return regnum + 1; |
| 6496 | } |
| 6497 | |
| 6498 | |
| 6499 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
| 6500 | |
| 6501 | static int |
| 6502 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
| 6503 | int start_regnum) |
| 6504 | { |
| 6505 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 6506 | /* Do values for GP (int) regs. */ |
| 6507 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
| 6508 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
| 6509 | per row. */ |
| 6510 | int col, byte; |
| 6511 | int regnum; |
| 6512 | |
| 6513 | /* For GP registers, we print a separate row of names above the vals. */ |
| 6514 | for (col = 0, regnum = start_regnum; |
| 6515 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
| 6516 | + gdbarch_num_pseudo_regs (gdbarch); |
| 6517 | regnum++) |
| 6518 | { |
| 6519 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
| 6520 | continue; /* unused register */ |
| 6521 | if (mips_float_register_p (gdbarch, regnum)) |
| 6522 | break; /* End the row: reached FP register. */ |
| 6523 | /* Large registers are handled separately. */ |
| 6524 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
| 6525 | { |
| 6526 | if (col > 0) |
| 6527 | break; /* End the row before this register. */ |
| 6528 | |
| 6529 | /* Print this register on a row by itself. */ |
| 6530 | mips_print_register (file, frame, regnum); |
| 6531 | fprintf_filtered (file, "\n"); |
| 6532 | return regnum + 1; |
| 6533 | } |
| 6534 | if (col == 0) |
| 6535 | fprintf_filtered (file, " "); |
| 6536 | fprintf_filtered (file, |
| 6537 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
| 6538 | gdbarch_register_name (gdbarch, regnum)); |
| 6539 | col++; |
| 6540 | } |
| 6541 | |
| 6542 | if (col == 0) |
| 6543 | return regnum; |
| 6544 | |
| 6545 | /* Print the R0 to R31 names. */ |
| 6546 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
| 6547 | fprintf_filtered (file, "\n R%-4d", |
| 6548 | start_regnum % gdbarch_num_regs (gdbarch)); |
| 6549 | else |
| 6550 | fprintf_filtered (file, "\n "); |
| 6551 | |
| 6552 | /* Now print the values in hex, 4 or 8 to the row. */ |
| 6553 | for (col = 0, regnum = start_regnum; |
| 6554 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
| 6555 | + gdbarch_num_pseudo_regs (gdbarch); |
| 6556 | regnum++) |
| 6557 | { |
| 6558 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
| 6559 | continue; /* unused register */ |
| 6560 | if (mips_float_register_p (gdbarch, regnum)) |
| 6561 | break; /* End row: reached FP register. */ |
| 6562 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
| 6563 | break; /* End row: large register. */ |
| 6564 | |
| 6565 | /* OK: get the data in raw format. */ |
| 6566 | if (!deprecated_frame_register_read (frame, regnum, raw_buffer)) |
| 6567 | error (_("can't read register %d (%s)"), |
| 6568 | regnum, gdbarch_register_name (gdbarch, regnum)); |
| 6569 | /* pad small registers */ |
| 6570 | for (byte = 0; |
| 6571 | byte < (mips_abi_regsize (gdbarch) |
| 6572 | - register_size (gdbarch, regnum)); byte++) |
| 6573 | printf_filtered (" "); |
| 6574 | /* Now print the register value in hex, endian order. */ |
| 6575 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 6576 | for (byte = |
| 6577 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
| 6578 | byte < register_size (gdbarch, regnum); byte++) |
| 6579 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
| 6580 | else |
| 6581 | for (byte = register_size (gdbarch, regnum) - 1; |
| 6582 | byte >= 0; byte--) |
| 6583 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
| 6584 | fprintf_filtered (file, " "); |
| 6585 | col++; |
| 6586 | } |
| 6587 | if (col > 0) /* ie. if we actually printed anything... */ |
| 6588 | fprintf_filtered (file, "\n"); |
| 6589 | |
| 6590 | return regnum; |
| 6591 | } |
| 6592 | |
| 6593 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
| 6594 | |
| 6595 | static void |
| 6596 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
| 6597 | struct frame_info *frame, int regnum, int all) |
| 6598 | { |
| 6599 | if (regnum != -1) /* Do one specified register. */ |
| 6600 | { |
| 6601 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
| 6602 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') |
| 6603 | error (_("Not a valid register for the current processor type")); |
| 6604 | |
| 6605 | mips_print_register (file, frame, regnum); |
| 6606 | fprintf_filtered (file, "\n"); |
| 6607 | } |
| 6608 | else |
| 6609 | /* Do all (or most) registers. */ |
| 6610 | { |
| 6611 | regnum = gdbarch_num_regs (gdbarch); |
| 6612 | while (regnum < gdbarch_num_regs (gdbarch) |
| 6613 | + gdbarch_num_pseudo_regs (gdbarch)) |
| 6614 | { |
| 6615 | if (mips_float_register_p (gdbarch, regnum)) |
| 6616 | { |
| 6617 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
| 6618 | regnum = print_fp_register_row (file, frame, regnum); |
| 6619 | else |
| 6620 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
| 6621 | } |
| 6622 | else |
| 6623 | regnum = print_gp_register_row (file, frame, regnum); |
| 6624 | } |
| 6625 | } |
| 6626 | } |
| 6627 | |
| 6628 | static int |
| 6629 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
| 6630 | struct frame_info *frame) |
| 6631 | { |
| 6632 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 6633 | CORE_ADDR pc = get_frame_pc (frame); |
| 6634 | struct address_space *aspace; |
| 6635 | enum mips_isa isa; |
| 6636 | ULONGEST insn; |
| 6637 | int status; |
| 6638 | int size; |
| 6639 | |
| 6640 | if ((mips_pc_is_mips (pc) |
| 6641 | && !mips32_insn_at_pc_has_delay_slot (gdbarch, pc)) |
| 6642 | || (mips_pc_is_micromips (gdbarch, pc) |
| 6643 | && !micromips_insn_at_pc_has_delay_slot (gdbarch, pc, 0)) |
| 6644 | || (mips_pc_is_mips16 (gdbarch, pc) |
| 6645 | && !mips16_insn_at_pc_has_delay_slot (gdbarch, pc, 0))) |
| 6646 | return 0; |
| 6647 | |
| 6648 | isa = mips_pc_isa (gdbarch, pc); |
| 6649 | /* _has_delay_slot above will have validated the read. */ |
| 6650 | insn = mips_fetch_instruction (gdbarch, isa, pc, NULL); |
| 6651 | size = mips_insn_size (isa, insn); |
| 6652 | aspace = get_frame_address_space (frame); |
| 6653 | return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here; |
| 6654 | } |
| 6655 | |
| 6656 | /* To skip prologues, I use this predicate. Returns either PC itself |
| 6657 | if the code at PC does not look like a function prologue; otherwise |
| 6658 | returns an address that (if we're lucky) follows the prologue. If |
| 6659 | LENIENT, then we must skip everything which is involved in setting |
| 6660 | up the frame (it's OK to skip more, just so long as we don't skip |
| 6661 | anything which might clobber the registers which are being saved. |
| 6662 | We must skip more in the case where part of the prologue is in the |
| 6663 | delay slot of a non-prologue instruction). */ |
| 6664 | |
| 6665 | static CORE_ADDR |
| 6666 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 6667 | { |
| 6668 | CORE_ADDR limit_pc; |
| 6669 | CORE_ADDR func_addr; |
| 6670 | |
| 6671 | /* See if we can determine the end of the prologue via the symbol table. |
| 6672 | If so, then return either PC, or the PC after the prologue, whichever |
| 6673 | is greater. */ |
| 6674 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
| 6675 | { |
| 6676 | CORE_ADDR post_prologue_pc |
| 6677 | = skip_prologue_using_sal (gdbarch, func_addr); |
| 6678 | if (post_prologue_pc != 0) |
| 6679 | return max (pc, post_prologue_pc); |
| 6680 | } |
| 6681 | |
| 6682 | /* Can't determine prologue from the symbol table, need to examine |
| 6683 | instructions. */ |
| 6684 | |
| 6685 | /* Find an upper limit on the function prologue using the debug |
| 6686 | information. If the debug information could not be used to provide |
| 6687 | that bound, then use an arbitrary large number as the upper bound. */ |
| 6688 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
| 6689 | if (limit_pc == 0) |
| 6690 | limit_pc = pc + 100; /* Magic. */ |
| 6691 | |
| 6692 | if (mips_pc_is_mips16 (gdbarch, pc)) |
| 6693 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
| 6694 | else if (mips_pc_is_micromips (gdbarch, pc)) |
| 6695 | return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
| 6696 | else |
| 6697 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
| 6698 | } |
| 6699 | |
| 6700 | /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version). |
| 6701 | This is a helper function for mips_stack_frame_destroyed_p. */ |
| 6702 | |
| 6703 | static int |
| 6704 | mips32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 6705 | { |
| 6706 | CORE_ADDR func_addr = 0, func_end = 0; |
| 6707 | |
| 6708 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
| 6709 | { |
| 6710 | /* The MIPS epilogue is max. 12 bytes long. */ |
| 6711 | CORE_ADDR addr = func_end - 12; |
| 6712 | |
| 6713 | if (addr < func_addr + 4) |
| 6714 | addr = func_addr + 4; |
| 6715 | if (pc < addr) |
| 6716 | return 0; |
| 6717 | |
| 6718 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) |
| 6719 | { |
| 6720 | unsigned long high_word; |
| 6721 | unsigned long inst; |
| 6722 | |
| 6723 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
| 6724 | high_word = (inst >> 16) & 0xffff; |
| 6725 | |
| 6726 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ |
| 6727 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ |
| 6728 | && inst != 0x03e00008 /* jr $ra */ |
| 6729 | && inst != 0x00000000) /* nop */ |
| 6730 | return 0; |
| 6731 | } |
| 6732 | |
| 6733 | return 1; |
| 6734 | } |
| 6735 | |
| 6736 | return 0; |
| 6737 | } |
| 6738 | |
| 6739 | /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version). |
| 6740 | This is a helper function for mips_stack_frame_destroyed_p. */ |
| 6741 | |
| 6742 | static int |
| 6743 | micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 6744 | { |
| 6745 | CORE_ADDR func_addr = 0; |
| 6746 | CORE_ADDR func_end = 0; |
| 6747 | CORE_ADDR addr; |
| 6748 | ULONGEST insn; |
| 6749 | long offset; |
| 6750 | int dreg; |
| 6751 | int sreg; |
| 6752 | int loc; |
| 6753 | |
| 6754 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
| 6755 | return 0; |
| 6756 | |
| 6757 | /* The microMIPS epilogue is max. 12 bytes long. */ |
| 6758 | addr = func_end - 12; |
| 6759 | |
| 6760 | if (addr < func_addr + 2) |
| 6761 | addr = func_addr + 2; |
| 6762 | if (pc < addr) |
| 6763 | return 0; |
| 6764 | |
| 6765 | for (; pc < func_end; pc += loc) |
| 6766 | { |
| 6767 | loc = 0; |
| 6768 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); |
| 6769 | loc += MIPS_INSN16_SIZE; |
| 6770 | switch (mips_insn_size (ISA_MICROMIPS, insn)) |
| 6771 | { |
| 6772 | /* 48-bit instructions. */ |
| 6773 | case 3 * MIPS_INSN16_SIZE: |
| 6774 | /* No epilogue instructions in this category. */ |
| 6775 | return 0; |
| 6776 | |
| 6777 | /* 32-bit instructions. */ |
| 6778 | case 2 * MIPS_INSN16_SIZE: |
| 6779 | insn <<= 16; |
| 6780 | insn |= mips_fetch_instruction (gdbarch, |
| 6781 | ISA_MICROMIPS, pc + loc, NULL); |
| 6782 | loc += MIPS_INSN16_SIZE; |
| 6783 | switch (micromips_op (insn >> 16)) |
| 6784 | { |
| 6785 | case 0xc: /* ADDIU: bits 001100 */ |
| 6786 | case 0x17: /* DADDIU: bits 010111 */ |
| 6787 | sreg = b0s5_reg (insn >> 16); |
| 6788 | dreg = b5s5_reg (insn >> 16); |
| 6789 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; |
| 6790 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM |
| 6791 | /* (D)ADDIU $sp, imm */ |
| 6792 | && offset >= 0) |
| 6793 | break; |
| 6794 | return 0; |
| 6795 | |
| 6796 | default: |
| 6797 | return 0; |
| 6798 | } |
| 6799 | break; |
| 6800 | |
| 6801 | /* 16-bit instructions. */ |
| 6802 | case MIPS_INSN16_SIZE: |
| 6803 | switch (micromips_op (insn)) |
| 6804 | { |
| 6805 | case 0x3: /* MOVE: bits 000011 */ |
| 6806 | sreg = b0s5_reg (insn); |
| 6807 | dreg = b5s5_reg (insn); |
| 6808 | if (sreg == 0 && dreg == 0) |
| 6809 | /* MOVE $zero, $zero aka NOP */ |
| 6810 | break; |
| 6811 | return 0; |
| 6812 | |
| 6813 | case 0x11: /* POOL16C: bits 010001 */ |
| 6814 | if (b5s5_op (insn) == 0x18 |
| 6815 | /* JRADDIUSP: bits 010011 11000 */ |
| 6816 | || (b5s5_op (insn) == 0xd |
| 6817 | /* JRC: bits 010011 01101 */ |
| 6818 | && b0s5_reg (insn) == MIPS_RA_REGNUM)) |
| 6819 | /* JRC $ra */ |
| 6820 | break; |
| 6821 | return 0; |
| 6822 | |
| 6823 | case 0x13: /* POOL16D: bits 010011 */ |
| 6824 | offset = micromips_decode_imm9 (b1s9_imm (insn)); |
| 6825 | if ((insn & 0x1) == 0x1 |
| 6826 | /* ADDIUSP: bits 010011 1 */ |
| 6827 | && offset > 0) |
| 6828 | break; |
| 6829 | return 0; |
| 6830 | |
| 6831 | default: |
| 6832 | return 0; |
| 6833 | } |
| 6834 | } |
| 6835 | } |
| 6836 | |
| 6837 | return 1; |
| 6838 | } |
| 6839 | |
| 6840 | /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version). |
| 6841 | This is a helper function for mips_stack_frame_destroyed_p. */ |
| 6842 | |
| 6843 | static int |
| 6844 | mips16_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 6845 | { |
| 6846 | CORE_ADDR func_addr = 0, func_end = 0; |
| 6847 | |
| 6848 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
| 6849 | { |
| 6850 | /* The MIPS epilogue is max. 12 bytes long. */ |
| 6851 | CORE_ADDR addr = func_end - 12; |
| 6852 | |
| 6853 | if (addr < func_addr + 4) |
| 6854 | addr = func_addr + 4; |
| 6855 | if (pc < addr) |
| 6856 | return 0; |
| 6857 | |
| 6858 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) |
| 6859 | { |
| 6860 | unsigned short inst; |
| 6861 | |
| 6862 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL); |
| 6863 | |
| 6864 | if ((inst & 0xf800) == 0xf000) /* extend */ |
| 6865 | continue; |
| 6866 | |
| 6867 | if (inst != 0x6300 /* addiu $sp,offset */ |
| 6868 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ |
| 6869 | && inst != 0xe820 /* jr $ra */ |
| 6870 | && inst != 0xe8a0 /* jrc $ra */ |
| 6871 | && inst != 0x6500) /* nop */ |
| 6872 | return 0; |
| 6873 | } |
| 6874 | |
| 6875 | return 1; |
| 6876 | } |
| 6877 | |
| 6878 | return 0; |
| 6879 | } |
| 6880 | |
| 6881 | /* Implement the stack_frame_destroyed_p gdbarch method. |
| 6882 | |
| 6883 | The epilogue is defined here as the area at the end of a function, |
| 6884 | after an instruction which destroys the function's stack frame. */ |
| 6885 | |
| 6886 | static int |
| 6887 | mips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 6888 | { |
| 6889 | if (mips_pc_is_mips16 (gdbarch, pc)) |
| 6890 | return mips16_stack_frame_destroyed_p (gdbarch, pc); |
| 6891 | else if (mips_pc_is_micromips (gdbarch, pc)) |
| 6892 | return micromips_stack_frame_destroyed_p (gdbarch, pc); |
| 6893 | else |
| 6894 | return mips32_stack_frame_destroyed_p (gdbarch, pc); |
| 6895 | } |
| 6896 | |
| 6897 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
| 6898 | used for all MIPS-specific commands. */ |
| 6899 | |
| 6900 | static void |
| 6901 | show_mips_command (char *args, int from_tty) |
| 6902 | { |
| 6903 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); |
| 6904 | } |
| 6905 | |
| 6906 | static void |
| 6907 | set_mips_command (char *args, int from_tty) |
| 6908 | { |
| 6909 | printf_unfiltered |
| 6910 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); |
| 6911 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
| 6912 | } |
| 6913 | |
| 6914 | /* Commands to show/set the MIPS FPU type. */ |
| 6915 | |
| 6916 | static void |
| 6917 | show_mipsfpu_command (char *args, int from_tty) |
| 6918 | { |
| 6919 | char *fpu; |
| 6920 | |
| 6921 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) |
| 6922 | { |
| 6923 | printf_unfiltered |
| 6924 | ("The MIPS floating-point coprocessor is unknown " |
| 6925 | "because the current architecture is not MIPS.\n"); |
| 6926 | return; |
| 6927 | } |
| 6928 | |
| 6929 | switch (MIPS_FPU_TYPE (target_gdbarch ())) |
| 6930 | { |
| 6931 | case MIPS_FPU_SINGLE: |
| 6932 | fpu = "single-precision"; |
| 6933 | break; |
| 6934 | case MIPS_FPU_DOUBLE: |
| 6935 | fpu = "double-precision"; |
| 6936 | break; |
| 6937 | case MIPS_FPU_NONE: |
| 6938 | fpu = "absent (none)"; |
| 6939 | break; |
| 6940 | default: |
| 6941 | internal_error (__FILE__, __LINE__, _("bad switch")); |
| 6942 | } |
| 6943 | if (mips_fpu_type_auto) |
| 6944 | printf_unfiltered ("The MIPS floating-point coprocessor " |
| 6945 | "is set automatically (currently %s)\n", |
| 6946 | fpu); |
| 6947 | else |
| 6948 | printf_unfiltered |
| 6949 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); |
| 6950 | } |
| 6951 | |
| 6952 | |
| 6953 | static void |
| 6954 | set_mipsfpu_command (char *args, int from_tty) |
| 6955 | { |
| 6956 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", " |
| 6957 | "\"single\",\"none\" or \"auto\".\n"); |
| 6958 | show_mipsfpu_command (args, from_tty); |
| 6959 | } |
| 6960 | |
| 6961 | static void |
| 6962 | set_mipsfpu_single_command (char *args, int from_tty) |
| 6963 | { |
| 6964 | struct gdbarch_info info; |
| 6965 | gdbarch_info_init (&info); |
| 6966 | mips_fpu_type = MIPS_FPU_SINGLE; |
| 6967 | mips_fpu_type_auto = 0; |
| 6968 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
| 6969 | instead of relying on globals. Doing that would let generic code |
| 6970 | handle the search for this specific architecture. */ |
| 6971 | if (!gdbarch_update_p (info)) |
| 6972 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
| 6973 | } |
| 6974 | |
| 6975 | static void |
| 6976 | set_mipsfpu_double_command (char *args, int from_tty) |
| 6977 | { |
| 6978 | struct gdbarch_info info; |
| 6979 | gdbarch_info_init (&info); |
| 6980 | mips_fpu_type = MIPS_FPU_DOUBLE; |
| 6981 | mips_fpu_type_auto = 0; |
| 6982 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
| 6983 | instead of relying on globals. Doing that would let generic code |
| 6984 | handle the search for this specific architecture. */ |
| 6985 | if (!gdbarch_update_p (info)) |
| 6986 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
| 6987 | } |
| 6988 | |
| 6989 | static void |
| 6990 | set_mipsfpu_none_command (char *args, int from_tty) |
| 6991 | { |
| 6992 | struct gdbarch_info info; |
| 6993 | gdbarch_info_init (&info); |
| 6994 | mips_fpu_type = MIPS_FPU_NONE; |
| 6995 | mips_fpu_type_auto = 0; |
| 6996 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
| 6997 | instead of relying on globals. Doing that would let generic code |
| 6998 | handle the search for this specific architecture. */ |
| 6999 | if (!gdbarch_update_p (info)) |
| 7000 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
| 7001 | } |
| 7002 | |
| 7003 | static void |
| 7004 | set_mipsfpu_auto_command (char *args, int from_tty) |
| 7005 | { |
| 7006 | mips_fpu_type_auto = 1; |
| 7007 | } |
| 7008 | |
| 7009 | /* Attempt to identify the particular processor model by reading the |
| 7010 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
| 7011 | the relevant processor still exists (it dates back to '94) and |
| 7012 | secondly this is not the way to do this. The processor type should |
| 7013 | be set by forcing an architecture change. */ |
| 7014 | |
| 7015 | void |
| 7016 | deprecated_mips_set_processor_regs_hack (void) |
| 7017 | { |
| 7018 | struct regcache *regcache = get_current_regcache (); |
| 7019 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 7020 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 7021 | ULONGEST prid; |
| 7022 | |
| 7023 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
| 7024 | if ((prid & ~0xf) == 0x700) |
| 7025 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
| 7026 | } |
| 7027 | |
| 7028 | /* Just like reinit_frame_cache, but with the right arguments to be |
| 7029 | callable as an sfunc. */ |
| 7030 | |
| 7031 | static void |
| 7032 | reinit_frame_cache_sfunc (char *args, int from_tty, |
| 7033 | struct cmd_list_element *c) |
| 7034 | { |
| 7035 | reinit_frame_cache (); |
| 7036 | } |
| 7037 | |
| 7038 | static int |
| 7039 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) |
| 7040 | { |
| 7041 | struct gdbarch *gdbarch = (struct gdbarch *) info->application_data; |
| 7042 | |
| 7043 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
| 7044 | disassembler needs to be able to locally determine the ISA, and |
| 7045 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not |
| 7046 | work. */ |
| 7047 | if (mips_pc_is_mips16 (gdbarch, memaddr)) |
| 7048 | info->mach = bfd_mach_mips16; |
| 7049 | else if (mips_pc_is_micromips (gdbarch, memaddr)) |
| 7050 | info->mach = bfd_mach_mips_micromips; |
| 7051 | |
| 7052 | /* Round down the instruction address to the appropriate boundary. */ |
| 7053 | memaddr &= (info->mach == bfd_mach_mips16 |
| 7054 | || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3; |
| 7055 | |
| 7056 | /* Set the disassembler options. */ |
| 7057 | if (!info->disassembler_options) |
| 7058 | /* This string is not recognized explicitly by the disassembler, |
| 7059 | but it tells the disassembler to not try to guess the ABI from |
| 7060 | the bfd elf headers, such that, if the user overrides the ABI |
| 7061 | of a program linked as NewABI, the disassembly will follow the |
| 7062 | register naming conventions specified by the user. */ |
| 7063 | info->disassembler_options = "gpr-names=32"; |
| 7064 | |
| 7065 | /* Call the appropriate disassembler based on the target endian-ness. */ |
| 7066 | if (info->endian == BFD_ENDIAN_BIG) |
| 7067 | return print_insn_big_mips (memaddr, info); |
| 7068 | else |
| 7069 | return print_insn_little_mips (memaddr, info); |
| 7070 | } |
| 7071 | |
| 7072 | static int |
| 7073 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) |
| 7074 | { |
| 7075 | /* Set up the disassembler info, so that we get the right |
| 7076 | register names from libopcodes. */ |
| 7077 | info->disassembler_options = "gpr-names=n32"; |
| 7078 | info->flavour = bfd_target_elf_flavour; |
| 7079 | |
| 7080 | return gdb_print_insn_mips (memaddr, info); |
| 7081 | } |
| 7082 | |
| 7083 | static int |
| 7084 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) |
| 7085 | { |
| 7086 | /* Set up the disassembler info, so that we get the right |
| 7087 | register names from libopcodes. */ |
| 7088 | info->disassembler_options = "gpr-names=64"; |
| 7089 | info->flavour = bfd_target_elf_flavour; |
| 7090 | |
| 7091 | return gdb_print_insn_mips (memaddr, info); |
| 7092 | } |
| 7093 | |
| 7094 | /* This function implements gdbarch_breakpoint_from_pc. It uses the |
| 7095 | program counter value to determine whether a 16- or 32-bit breakpoint |
| 7096 | should be used. It returns a pointer to a string of bytes that encode a |
| 7097 | breakpoint instruction, stores the length of the string to *lenptr, and |
| 7098 | adjusts pc (if necessary) to point to the actual memory location where |
| 7099 | the breakpoint should be inserted. */ |
| 7100 | |
| 7101 | static const gdb_byte * |
| 7102 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, |
| 7103 | CORE_ADDR *pcptr, int *lenptr) |
| 7104 | { |
| 7105 | CORE_ADDR pc = *pcptr; |
| 7106 | |
| 7107 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 7108 | { |
| 7109 | if (mips_pc_is_mips16 (gdbarch, pc)) |
| 7110 | { |
| 7111 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
| 7112 | *pcptr = unmake_compact_addr (pc); |
| 7113 | *lenptr = sizeof (mips16_big_breakpoint); |
| 7114 | return mips16_big_breakpoint; |
| 7115 | } |
| 7116 | else if (mips_pc_is_micromips (gdbarch, pc)) |
| 7117 | { |
| 7118 | static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 }; |
| 7119 | static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 }; |
| 7120 | ULONGEST insn; |
| 7121 | int err; |
| 7122 | int size; |
| 7123 | |
| 7124 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &err); |
| 7125 | size = (err != 0 |
| 7126 | ? 2 : (mips_insn_size (ISA_MICROMIPS, insn) == 2 |
| 7127 | ? 2 : 4)); |
| 7128 | *pcptr = unmake_compact_addr (pc); |
| 7129 | *lenptr = size; |
| 7130 | return (size == 2) ? micromips16_big_breakpoint |
| 7131 | : micromips32_big_breakpoint; |
| 7132 | } |
| 7133 | else |
| 7134 | { |
| 7135 | /* The IDT board uses an unusual breakpoint value, and |
| 7136 | sometimes gets confused when it sees the usual MIPS |
| 7137 | breakpoint instruction. */ |
| 7138 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
| 7139 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; |
| 7140 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; |
| 7141 | /* Likewise, IRIX appears to expect a different breakpoint, |
| 7142 | although this is not apparent until you try to use pthreads. */ |
| 7143 | static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; |
| 7144 | |
| 7145 | *lenptr = sizeof (big_breakpoint); |
| 7146 | |
| 7147 | if (strcmp (target_shortname, "mips") == 0) |
| 7148 | return idt_big_breakpoint; |
| 7149 | else if (strcmp (target_shortname, "ddb") == 0 |
| 7150 | || strcmp (target_shortname, "pmon") == 0 |
| 7151 | || strcmp (target_shortname, "lsi") == 0) |
| 7152 | return pmon_big_breakpoint; |
| 7153 | else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) |
| 7154 | return irix_big_breakpoint; |
| 7155 | else |
| 7156 | return big_breakpoint; |
| 7157 | } |
| 7158 | } |
| 7159 | else |
| 7160 | { |
| 7161 | if (mips_pc_is_mips16 (gdbarch, pc)) |
| 7162 | { |
| 7163 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
| 7164 | *pcptr = unmake_compact_addr (pc); |
| 7165 | *lenptr = sizeof (mips16_little_breakpoint); |
| 7166 | return mips16_little_breakpoint; |
| 7167 | } |
| 7168 | else if (mips_pc_is_micromips (gdbarch, pc)) |
| 7169 | { |
| 7170 | static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 }; |
| 7171 | static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 }; |
| 7172 | ULONGEST insn; |
| 7173 | int status; |
| 7174 | int size; |
| 7175 | |
| 7176 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); |
| 7177 | size = status ? 2 |
| 7178 | : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; |
| 7179 | *pcptr = unmake_compact_addr (pc); |
| 7180 | *lenptr = size; |
| 7181 | return (size == 2) ? micromips16_little_breakpoint |
| 7182 | : micromips32_little_breakpoint; |
| 7183 | } |
| 7184 | else |
| 7185 | { |
| 7186 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
| 7187 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; |
| 7188 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; |
| 7189 | |
| 7190 | *lenptr = sizeof (little_breakpoint); |
| 7191 | |
| 7192 | if (strcmp (target_shortname, "mips") == 0) |
| 7193 | return idt_little_breakpoint; |
| 7194 | else if (strcmp (target_shortname, "ddb") == 0 |
| 7195 | || strcmp (target_shortname, "pmon") == 0 |
| 7196 | || strcmp (target_shortname, "lsi") == 0) |
| 7197 | return pmon_little_breakpoint; |
| 7198 | else |
| 7199 | return little_breakpoint; |
| 7200 | } |
| 7201 | } |
| 7202 | } |
| 7203 | |
| 7204 | /* Determine the remote breakpoint kind suitable for the PC. The following |
| 7205 | kinds are used: |
| 7206 | |
| 7207 | * 2 -- 16-bit MIPS16 mode breakpoint, |
| 7208 | |
| 7209 | * 3 -- 16-bit microMIPS mode breakpoint, |
| 7210 | |
| 7211 | * 4 -- 32-bit standard MIPS mode breakpoint, |
| 7212 | |
| 7213 | * 5 -- 32-bit microMIPS mode breakpoint. */ |
| 7214 | |
| 7215 | static void |
| 7216 | mips_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, |
| 7217 | int *kindptr) |
| 7218 | { |
| 7219 | CORE_ADDR pc = *pcptr; |
| 7220 | |
| 7221 | if (mips_pc_is_mips16 (gdbarch, pc)) |
| 7222 | { |
| 7223 | *pcptr = unmake_compact_addr (pc); |
| 7224 | *kindptr = 2; |
| 7225 | } |
| 7226 | else if (mips_pc_is_micromips (gdbarch, pc)) |
| 7227 | { |
| 7228 | ULONGEST insn; |
| 7229 | int status; |
| 7230 | int size; |
| 7231 | |
| 7232 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); |
| 7233 | size = status ? 2 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; |
| 7234 | *pcptr = unmake_compact_addr (pc); |
| 7235 | *kindptr = size | 1; |
| 7236 | } |
| 7237 | else |
| 7238 | *kindptr = 4; |
| 7239 | } |
| 7240 | |
| 7241 | /* Return non-zero if the standard MIPS instruction INST has a branch |
| 7242 | delay slot (i.e. it is a jump or branch instruction). This function |
| 7243 | is based on mips32_next_pc. */ |
| 7244 | |
| 7245 | static int |
| 7246 | mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, ULONGEST inst) |
| 7247 | { |
| 7248 | int op; |
| 7249 | int rs; |
| 7250 | int rt; |
| 7251 | |
| 7252 | op = itype_op (inst); |
| 7253 | if ((inst & 0xe0000000) != 0) |
| 7254 | { |
| 7255 | rs = itype_rs (inst); |
| 7256 | rt = itype_rt (inst); |
| 7257 | return (is_octeon_bbit_op (op, gdbarch) |
| 7258 | || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
| 7259 | || op == 29 /* JALX: bits 011101 */ |
| 7260 | || (op == 17 |
| 7261 | && (rs == 8 |
| 7262 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
| 7263 | || (rs == 9 && (rt & 0x2) == 0) |
| 7264 | /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ |
| 7265 | || (rs == 10 && (rt & 0x2) == 0)))); |
| 7266 | /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ |
| 7267 | } |
| 7268 | else |
| 7269 | switch (op & 0x07) /* extract bits 28,27,26 */ |
| 7270 | { |
| 7271 | case 0: /* SPECIAL */ |
| 7272 | op = rtype_funct (inst); |
| 7273 | return (op == 8 /* JR */ |
| 7274 | || op == 9); /* JALR */ |
| 7275 | break; /* end SPECIAL */ |
| 7276 | case 1: /* REGIMM */ |
| 7277 | rs = itype_rs (inst); |
| 7278 | rt = itype_rt (inst); /* branch condition */ |
| 7279 | return ((rt & 0xc) == 0 |
| 7280 | /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ |
| 7281 | /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ |
| 7282 | || ((rt & 0x1e) == 0x1c && rs == 0)); |
| 7283 | /* BPOSGE32, BPOSGE64: bits 1110x */ |
| 7284 | break; /* end REGIMM */ |
| 7285 | default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ |
| 7286 | return 1; |
| 7287 | break; |
| 7288 | } |
| 7289 | } |
| 7290 | |
| 7291 | /* Return non-zero if a standard MIPS instruction at ADDR has a branch |
| 7292 | delay slot (i.e. it is a jump or branch instruction). */ |
| 7293 | |
| 7294 | static int |
| 7295 | mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 7296 | { |
| 7297 | ULONGEST insn; |
| 7298 | int status; |
| 7299 | |
| 7300 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status); |
| 7301 | if (status) |
| 7302 | return 0; |
| 7303 | |
| 7304 | return mips32_instruction_has_delay_slot (gdbarch, insn); |
| 7305 | } |
| 7306 | |
| 7307 | /* Return non-zero if the microMIPS instruction INSN, comprising the |
| 7308 | 16-bit major opcode word in the high 16 bits and any second word |
| 7309 | in the low 16 bits, has a branch delay slot (i.e. it is a non-compact |
| 7310 | jump or branch instruction). The instruction must be 32-bit if |
| 7311 | MUSTBE32 is set or can be any instruction otherwise. */ |
| 7312 | |
| 7313 | static int |
| 7314 | micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32) |
| 7315 | { |
| 7316 | ULONGEST major = insn >> 16; |
| 7317 | |
| 7318 | switch (micromips_op (major)) |
| 7319 | { |
| 7320 | /* 16-bit instructions. */ |
| 7321 | case 0x33: /* B16: bits 110011 */ |
| 7322 | case 0x2b: /* BNEZ16: bits 101011 */ |
| 7323 | case 0x23: /* BEQZ16: bits 100011 */ |
| 7324 | return !mustbe32; |
| 7325 | case 0x11: /* POOL16C: bits 010001 */ |
| 7326 | return (!mustbe32 |
| 7327 | && ((b5s5_op (major) == 0xc |
| 7328 | /* JR16: bits 010001 01100 */ |
| 7329 | || (b5s5_op (major) & 0x1e) == 0xe))); |
| 7330 | /* JALR16, JALRS16: bits 010001 0111x */ |
| 7331 | /* 32-bit instructions. */ |
| 7332 | case 0x3d: /* JAL: bits 111101 */ |
| 7333 | case 0x3c: /* JALX: bits 111100 */ |
| 7334 | case 0x35: /* J: bits 110101 */ |
| 7335 | case 0x2d: /* BNE: bits 101101 */ |
| 7336 | case 0x25: /* BEQ: bits 100101 */ |
| 7337 | case 0x1d: /* JALS: bits 011101 */ |
| 7338 | return 1; |
| 7339 | case 0x10: /* POOL32I: bits 010000 */ |
| 7340 | return ((b5s5_op (major) & 0x1c) == 0x0 |
| 7341 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ |
| 7342 | || (b5s5_op (major) & 0x1d) == 0x4 |
| 7343 | /* BLEZ, BGTZ: bits 010000 001x0 */ |
| 7344 | || (b5s5_op (major) & 0x1d) == 0x11 |
| 7345 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ |
| 7346 | || ((b5s5_op (major) & 0x1e) == 0x14 |
| 7347 | && (major & 0x3) == 0x0) |
| 7348 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ |
| 7349 | || (b5s5_op (major) & 0x1e) == 0x1a |
| 7350 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ |
| 7351 | || ((b5s5_op (major) & 0x1e) == 0x1c |
| 7352 | && (major & 0x3) == 0x0) |
| 7353 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ |
| 7354 | || ((b5s5_op (major) & 0x1c) == 0x1c |
| 7355 | && (major & 0x3) == 0x1)); |
| 7356 | /* BC1ANY*: bits 010000 111xx xxx01 */ |
| 7357 | case 0x0: /* POOL32A: bits 000000 */ |
| 7358 | return (b0s6_op (insn) == 0x3c |
| 7359 | /* POOL32Axf: bits 000000 ... 111100 */ |
| 7360 | && (b6s10_ext (insn) & 0x2bf) == 0x3c); |
| 7361 | /* JALR, JALR.HB: 000000 000x111100 111100 */ |
| 7362 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ |
| 7363 | default: |
| 7364 | return 0; |
| 7365 | } |
| 7366 | } |
| 7367 | |
| 7368 | /* Return non-zero if a microMIPS instruction at ADDR has a branch delay |
| 7369 | slot (i.e. it is a non-compact jump instruction). The instruction |
| 7370 | must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ |
| 7371 | |
| 7372 | static int |
| 7373 | micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, |
| 7374 | CORE_ADDR addr, int mustbe32) |
| 7375 | { |
| 7376 | ULONGEST insn; |
| 7377 | int status; |
| 7378 | |
| 7379 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); |
| 7380 | if (status) |
| 7381 | return 0; |
| 7382 | insn <<= 16; |
| 7383 | if (mips_insn_size (ISA_MICROMIPS, insn) == 2 * MIPS_INSN16_SIZE) |
| 7384 | { |
| 7385 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); |
| 7386 | if (status) |
| 7387 | return 0; |
| 7388 | } |
| 7389 | |
| 7390 | return micromips_instruction_has_delay_slot (insn, mustbe32); |
| 7391 | } |
| 7392 | |
| 7393 | /* Return non-zero if the MIPS16 instruction INST, which must be |
| 7394 | a 32-bit instruction if MUSTBE32 is set or can be any instruction |
| 7395 | otherwise, has a branch delay slot (i.e. it is a non-compact jump |
| 7396 | instruction). This function is based on mips16_next_pc. */ |
| 7397 | |
| 7398 | static int |
| 7399 | mips16_instruction_has_delay_slot (unsigned short inst, int mustbe32) |
| 7400 | { |
| 7401 | if ((inst & 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */ |
| 7402 | return !mustbe32; |
| 7403 | return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ |
| 7404 | } |
| 7405 | |
| 7406 | /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay |
| 7407 | slot (i.e. it is a non-compact jump instruction). The instruction |
| 7408 | must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ |
| 7409 | |
| 7410 | static int |
| 7411 | mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, |
| 7412 | CORE_ADDR addr, int mustbe32) |
| 7413 | { |
| 7414 | unsigned short insn; |
| 7415 | int status; |
| 7416 | |
| 7417 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status); |
| 7418 | if (status) |
| 7419 | return 0; |
| 7420 | |
| 7421 | return mips16_instruction_has_delay_slot (insn, mustbe32); |
| 7422 | } |
| 7423 | |
| 7424 | /* Calculate the starting address of the MIPS memory segment BPADDR is in. |
| 7425 | This assumes KSSEG exists. */ |
| 7426 | |
| 7427 | static CORE_ADDR |
| 7428 | mips_segment_boundary (CORE_ADDR bpaddr) |
| 7429 | { |
| 7430 | CORE_ADDR mask = CORE_ADDR_MAX; |
| 7431 | int segsize; |
| 7432 | |
| 7433 | if (sizeof (CORE_ADDR) == 8) |
| 7434 | /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid |
| 7435 | a compiler warning produced where CORE_ADDR is a 32-bit type even |
| 7436 | though in that case this is dead code). */ |
| 7437 | switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) |
| 7438 | { |
| 7439 | case 3: |
| 7440 | if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) |
| 7441 | segsize = 29; /* 32-bit compatibility segment */ |
| 7442 | else |
| 7443 | segsize = 62; /* xkseg */ |
| 7444 | break; |
| 7445 | case 2: /* xkphys */ |
| 7446 | segsize = 59; |
| 7447 | break; |
| 7448 | default: /* xksseg (1), xkuseg/kuseg (0) */ |
| 7449 | segsize = 62; |
| 7450 | break; |
| 7451 | } |
| 7452 | else if (bpaddr & 0x80000000) /* kernel segment */ |
| 7453 | segsize = 29; |
| 7454 | else |
| 7455 | segsize = 31; /* user segment */ |
| 7456 | mask <<= segsize; |
| 7457 | return bpaddr & mask; |
| 7458 | } |
| 7459 | |
| 7460 | /* Move the breakpoint at BPADDR out of any branch delay slot by shifting |
| 7461 | it backwards if necessary. Return the address of the new location. */ |
| 7462 | |
| 7463 | static CORE_ADDR |
| 7464 | mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) |
| 7465 | { |
| 7466 | CORE_ADDR prev_addr; |
| 7467 | CORE_ADDR boundary; |
| 7468 | CORE_ADDR func_addr; |
| 7469 | |
| 7470 | /* If a breakpoint is set on the instruction in a branch delay slot, |
| 7471 | GDB gets confused. When the breakpoint is hit, the PC isn't on |
| 7472 | the instruction in the branch delay slot, the PC will point to |
| 7473 | the branch instruction. Since the PC doesn't match any known |
| 7474 | breakpoints, GDB reports a trap exception. |
| 7475 | |
| 7476 | There are two possible fixes for this problem. |
| 7477 | |
| 7478 | 1) When the breakpoint gets hit, see if the BD bit is set in the |
| 7479 | Cause register (which indicates the last exception occurred in a |
| 7480 | branch delay slot). If the BD bit is set, fix the PC to point to |
| 7481 | the instruction in the branch delay slot. |
| 7482 | |
| 7483 | 2) When the user sets the breakpoint, don't allow him to set the |
| 7484 | breakpoint on the instruction in the branch delay slot. Instead |
| 7485 | move the breakpoint to the branch instruction (which will have |
| 7486 | the same result). |
| 7487 | |
| 7488 | The problem with the first solution is that if the user then |
| 7489 | single-steps the processor, the branch instruction will get |
| 7490 | skipped (since GDB thinks the PC is on the instruction in the |
| 7491 | branch delay slot). |
| 7492 | |
| 7493 | So, we'll use the second solution. To do this we need to know if |
| 7494 | the instruction we're trying to set the breakpoint on is in the |
| 7495 | branch delay slot. */ |
| 7496 | |
| 7497 | boundary = mips_segment_boundary (bpaddr); |
| 7498 | |
| 7499 | /* Make sure we don't scan back before the beginning of the current |
| 7500 | function, since we may fetch constant data or insns that look like |
| 7501 | a jump. Of course we might do that anyway if the compiler has |
| 7502 | moved constants inline. :-( */ |
| 7503 | if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) |
| 7504 | && func_addr > boundary && func_addr <= bpaddr) |
| 7505 | boundary = func_addr; |
| 7506 | |
| 7507 | if (mips_pc_is_mips (bpaddr)) |
| 7508 | { |
| 7509 | if (bpaddr == boundary) |
| 7510 | return bpaddr; |
| 7511 | |
| 7512 | /* If the previous instruction has a branch delay slot, we have |
| 7513 | to move the breakpoint to the branch instruction. */ |
| 7514 | prev_addr = bpaddr - 4; |
| 7515 | if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr)) |
| 7516 | bpaddr = prev_addr; |
| 7517 | } |
| 7518 | else |
| 7519 | { |
| 7520 | int (*insn_at_pc_has_delay_slot) (struct gdbarch *, CORE_ADDR, int); |
| 7521 | CORE_ADDR addr, jmpaddr; |
| 7522 | int i; |
| 7523 | |
| 7524 | boundary = unmake_compact_addr (boundary); |
| 7525 | |
| 7526 | /* The only MIPS16 instructions with delay slots are JAL, JALX, |
| 7527 | JALR and JR. An absolute JAL/JALX is always 4 bytes long, |
| 7528 | so try for that first, then try the 2 byte JALR/JR. |
| 7529 | The microMIPS ASE has a whole range of jumps and branches |
| 7530 | with delay slots, some of which take 4 bytes and some take |
| 7531 | 2 bytes, so the idea is the same. |
| 7532 | FIXME: We have to assume that bpaddr is not the second half |
| 7533 | of an extended instruction. */ |
| 7534 | insn_at_pc_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr) |
| 7535 | ? micromips_insn_at_pc_has_delay_slot |
| 7536 | : mips16_insn_at_pc_has_delay_slot); |
| 7537 | |
| 7538 | jmpaddr = 0; |
| 7539 | addr = bpaddr; |
| 7540 | for (i = 1; i < 4; i++) |
| 7541 | { |
| 7542 | if (unmake_compact_addr (addr) == boundary) |
| 7543 | break; |
| 7544 | addr -= MIPS_INSN16_SIZE; |
| 7545 | if (i == 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 0)) |
| 7546 | /* Looks like a JR/JALR at [target-1], but it could be |
| 7547 | the second word of a previous JAL/JALX, so record it |
| 7548 | and check back one more. */ |
| 7549 | jmpaddr = addr; |
| 7550 | else if (i > 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 1)) |
| 7551 | { |
| 7552 | if (i == 2) |
| 7553 | /* Looks like a JAL/JALX at [target-2], but it could also |
| 7554 | be the second word of a previous JAL/JALX, record it, |
| 7555 | and check back one more. */ |
| 7556 | jmpaddr = addr; |
| 7557 | else |
| 7558 | /* Looks like a JAL/JALX at [target-3], so any previously |
| 7559 | recorded JAL/JALX or JR/JALR must be wrong, because: |
| 7560 | |
| 7561 | >-3: JAL |
| 7562 | -2: JAL-ext (can't be JAL/JALX) |
| 7563 | -1: bdslot (can't be JR/JALR) |
| 7564 | 0: target insn |
| 7565 | |
| 7566 | Of course it could be another JAL-ext which looks |
| 7567 | like a JAL, but in that case we'd have broken out |
| 7568 | of this loop at [target-2]: |
| 7569 | |
| 7570 | -4: JAL |
| 7571 | >-3: JAL-ext |
| 7572 | -2: bdslot (can't be jmp) |
| 7573 | -1: JR/JALR |
| 7574 | 0: target insn */ |
| 7575 | jmpaddr = 0; |
| 7576 | } |
| 7577 | else |
| 7578 | { |
| 7579 | /* Not a jump instruction: if we're at [target-1] this |
| 7580 | could be the second word of a JAL/JALX, so continue; |
| 7581 | otherwise we're done. */ |
| 7582 | if (i > 1) |
| 7583 | break; |
| 7584 | } |
| 7585 | } |
| 7586 | |
| 7587 | if (jmpaddr) |
| 7588 | bpaddr = jmpaddr; |
| 7589 | } |
| 7590 | |
| 7591 | return bpaddr; |
| 7592 | } |
| 7593 | |
| 7594 | /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16 |
| 7595 | call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */ |
| 7596 | |
| 7597 | static int |
| 7598 | mips_is_stub_suffix (const char *suffix, int zero) |
| 7599 | { |
| 7600 | switch (suffix[0]) |
| 7601 | { |
| 7602 | case '0': |
| 7603 | return zero && suffix[1] == '\0'; |
| 7604 | case '1': |
| 7605 | return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); |
| 7606 | case '2': |
| 7607 | case '5': |
| 7608 | case '6': |
| 7609 | case '9': |
| 7610 | return suffix[1] == '\0'; |
| 7611 | default: |
| 7612 | return 0; |
| 7613 | } |
| 7614 | } |
| 7615 | |
| 7616 | /* Return non-zero if MODE is one of the mode infixes used for MIPS16 |
| 7617 | call stubs, one of sf, df, sc, or dc. */ |
| 7618 | |
| 7619 | static int |
| 7620 | mips_is_stub_mode (const char *mode) |
| 7621 | { |
| 7622 | return ((mode[0] == 's' || mode[0] == 'd') |
| 7623 | && (mode[1] == 'f' || mode[1] == 'c')); |
| 7624 | } |
| 7625 | |
| 7626 | /* Code at PC is a compiler-generated stub. Such a stub for a function |
| 7627 | bar might have a name like __fn_stub_bar, and might look like this: |
| 7628 | |
| 7629 | mfc1 $4, $f13 |
| 7630 | mfc1 $5, $f12 |
| 7631 | mfc1 $6, $f15 |
| 7632 | mfc1 $7, $f14 |
| 7633 | |
| 7634 | followed by (or interspersed with): |
| 7635 | |
| 7636 | j bar |
| 7637 | |
| 7638 | or: |
| 7639 | |
| 7640 | lui $25, %hi(bar) |
| 7641 | addiu $25, $25, %lo(bar) |
| 7642 | jr $25 |
| 7643 | |
| 7644 | ($1 may be used in old code; for robustness we accept any register) |
| 7645 | or, in PIC code: |
| 7646 | |
| 7647 | lui $28, %hi(_gp_disp) |
| 7648 | addiu $28, $28, %lo(_gp_disp) |
| 7649 | addu $28, $28, $25 |
| 7650 | lw $25, %got(bar) |
| 7651 | addiu $25, $25, %lo(bar) |
| 7652 | jr $25 |
| 7653 | |
| 7654 | In the case of a __call_stub_bar stub, the sequence to set up |
| 7655 | arguments might look like this: |
| 7656 | |
| 7657 | mtc1 $4, $f13 |
| 7658 | mtc1 $5, $f12 |
| 7659 | mtc1 $6, $f15 |
| 7660 | mtc1 $7, $f14 |
| 7661 | |
| 7662 | followed by (or interspersed with) one of the jump sequences above. |
| 7663 | |
| 7664 | In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead |
| 7665 | of J or JR, respectively, followed by: |
| 7666 | |
| 7667 | mfc1 $2, $f0 |
| 7668 | mfc1 $3, $f1 |
| 7669 | jr $18 |
| 7670 | |
| 7671 | We are at the beginning of the stub here, and scan down and extract |
| 7672 | the target address from the jump immediate instruction or, if a jump |
| 7673 | register instruction is used, from the register referred. Return |
| 7674 | the value of PC calculated or 0 if inconclusive. |
| 7675 | |
| 7676 | The limit on the search is arbitrarily set to 20 instructions. FIXME. */ |
| 7677 | |
| 7678 | static CORE_ADDR |
| 7679 | mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc) |
| 7680 | { |
| 7681 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 7682 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 7683 | int addrreg = MIPS_ZERO_REGNUM; |
| 7684 | CORE_ADDR start_pc = pc; |
| 7685 | CORE_ADDR target_pc = 0; |
| 7686 | CORE_ADDR addr = 0; |
| 7687 | CORE_ADDR gp = 0; |
| 7688 | int status = 0; |
| 7689 | int i; |
| 7690 | |
| 7691 | for (i = 0; |
| 7692 | status == 0 && target_pc == 0 && i < 20; |
| 7693 | i++, pc += MIPS_INSN32_SIZE) |
| 7694 | { |
| 7695 | ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
| 7696 | CORE_ADDR imm; |
| 7697 | int rt; |
| 7698 | int rs; |
| 7699 | int rd; |
| 7700 | |
| 7701 | switch (itype_op (inst)) |
| 7702 | { |
| 7703 | case 0: /* SPECIAL */ |
| 7704 | switch (rtype_funct (inst)) |
| 7705 | { |
| 7706 | case 8: /* JR */ |
| 7707 | case 9: /* JALR */ |
| 7708 | rs = rtype_rs (inst); |
| 7709 | if (rs == MIPS_GP_REGNUM) |
| 7710 | target_pc = gp; /* Hmm... */ |
| 7711 | else if (rs == addrreg) |
| 7712 | target_pc = addr; |
| 7713 | break; |
| 7714 | |
| 7715 | case 0x21: /* ADDU */ |
| 7716 | rt = rtype_rt (inst); |
| 7717 | rs = rtype_rs (inst); |
| 7718 | rd = rtype_rd (inst); |
| 7719 | if (rd == MIPS_GP_REGNUM |
| 7720 | && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM) |
| 7721 | || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM))) |
| 7722 | gp += start_pc; |
| 7723 | break; |
| 7724 | } |
| 7725 | break; |
| 7726 | |
| 7727 | case 2: /* J */ |
| 7728 | case 3: /* JAL */ |
| 7729 | target_pc = jtype_target (inst) << 2; |
| 7730 | target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
| 7731 | break; |
| 7732 | |
| 7733 | case 9: /* ADDIU */ |
| 7734 | rt = itype_rt (inst); |
| 7735 | rs = itype_rs (inst); |
| 7736 | if (rt == rs) |
| 7737 | { |
| 7738 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; |
| 7739 | if (rt == MIPS_GP_REGNUM) |
| 7740 | gp += imm; |
| 7741 | else if (rt == addrreg) |
| 7742 | addr += imm; |
| 7743 | } |
| 7744 | break; |
| 7745 | |
| 7746 | case 0xf: /* LUI */ |
| 7747 | rt = itype_rt (inst); |
| 7748 | imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16; |
| 7749 | if (rt == MIPS_GP_REGNUM) |
| 7750 | gp = imm; |
| 7751 | else if (rt != MIPS_ZERO_REGNUM) |
| 7752 | { |
| 7753 | addrreg = rt; |
| 7754 | addr = imm; |
| 7755 | } |
| 7756 | break; |
| 7757 | |
| 7758 | case 0x23: /* LW */ |
| 7759 | rt = itype_rt (inst); |
| 7760 | rs = itype_rs (inst); |
| 7761 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; |
| 7762 | if (gp != 0 && rs == MIPS_GP_REGNUM) |
| 7763 | { |
| 7764 | gdb_byte buf[4]; |
| 7765 | |
| 7766 | memset (buf, 0, sizeof (buf)); |
| 7767 | status = target_read_memory (gp + imm, buf, sizeof (buf)); |
| 7768 | addrreg = rt; |
| 7769 | addr = extract_signed_integer (buf, sizeof (buf), byte_order); |
| 7770 | } |
| 7771 | break; |
| 7772 | } |
| 7773 | } |
| 7774 | |
| 7775 | return target_pc; |
| 7776 | } |
| 7777 | |
| 7778 | /* If PC is in a MIPS16 call or return stub, return the address of the |
| 7779 | target PC, which is either the callee or the caller. There are several |
| 7780 | cases which must be handled: |
| 7781 | |
| 7782 | * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
| 7783 | and the target PC is in $31 ($ra). |
| 7784 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
| 7785 | and the target PC is in $2. |
| 7786 | * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, |
| 7787 | i.e. before the JALR instruction, this is effectively a call stub |
| 7788 | and the target PC is in $2. Otherwise this is effectively |
| 7789 | a return stub and the target PC is in $18. |
| 7790 | * If the PC is at the start of __call_stub_fp_*, i.e. before the |
| 7791 | JAL or JALR instruction, this is effectively a call stub and the |
| 7792 | target PC is buried in the instruction stream. Otherwise this |
| 7793 | is effectively a return stub and the target PC is in $18. |
| 7794 | * If the PC is in __call_stub_* or in __fn_stub_*, this is a call |
| 7795 | stub and the target PC is buried in the instruction stream. |
| 7796 | |
| 7797 | See the source code for the stubs in gcc/config/mips/mips16.S, or the |
| 7798 | stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the |
| 7799 | gory details. */ |
| 7800 | |
| 7801 | static CORE_ADDR |
| 7802 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
| 7803 | { |
| 7804 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 7805 | CORE_ADDR start_addr; |
| 7806 | const char *name; |
| 7807 | size_t prefixlen; |
| 7808 | |
| 7809 | /* Find the starting address and name of the function containing the PC. */ |
| 7810 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) |
| 7811 | return 0; |
| 7812 | |
| 7813 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
| 7814 | and the target PC is in $31 ($ra). */ |
| 7815 | prefixlen = strlen (mips_str_mips16_ret_stub); |
| 7816 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 |
| 7817 | && mips_is_stub_mode (name + prefixlen) |
| 7818 | && name[prefixlen + 2] == '\0') |
| 7819 | return get_frame_register_signed |
| 7820 | (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); |
| 7821 | |
| 7822 | /* If the PC is in __mips16_call_stub_*, this is one of the call |
| 7823 | call/return stubs. */ |
| 7824 | prefixlen = strlen (mips_str_mips16_call_stub); |
| 7825 | if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0) |
| 7826 | { |
| 7827 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
| 7828 | and the target PC is in $2. */ |
| 7829 | if (mips_is_stub_suffix (name + prefixlen, 0)) |
| 7830 | return get_frame_register_signed |
| 7831 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); |
| 7832 | |
| 7833 | /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, |
| 7834 | i.e. before the JALR instruction, this is effectively a call stub |
| 7835 | and the target PC is in $2. Otherwise this is effectively |
| 7836 | a return stub and the target PC is in $18. */ |
| 7837 | else if (mips_is_stub_mode (name + prefixlen) |
| 7838 | && name[prefixlen + 2] == '_' |
| 7839 | && mips_is_stub_suffix (name + prefixlen + 3, 0)) |
| 7840 | { |
| 7841 | if (pc == start_addr) |
| 7842 | /* This is the 'call' part of a call stub. The return |
| 7843 | address is in $2. */ |
| 7844 | return get_frame_register_signed |
| 7845 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); |
| 7846 | else |
| 7847 | /* This is the 'return' part of a call stub. The return |
| 7848 | address is in $18. */ |
| 7849 | return get_frame_register_signed |
| 7850 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); |
| 7851 | } |
| 7852 | else |
| 7853 | return 0; /* Not a stub. */ |
| 7854 | } |
| 7855 | |
| 7856 | /* If the PC is in __call_stub_* or __fn_stub*, this is one of the |
| 7857 | compiler-generated call or call/return stubs. */ |
| 7858 | if (startswith (name, mips_str_fn_stub) |
| 7859 | || startswith (name, mips_str_call_stub)) |
| 7860 | { |
| 7861 | if (pc == start_addr) |
| 7862 | /* This is the 'call' part of a call stub. Call this helper |
| 7863 | to scan through this code for interesting instructions |
| 7864 | and determine the final PC. */ |
| 7865 | return mips_get_mips16_fn_stub_pc (frame, pc); |
| 7866 | else |
| 7867 | /* This is the 'return' part of a call stub. The return address |
| 7868 | is in $18. */ |
| 7869 | return get_frame_register_signed |
| 7870 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); |
| 7871 | } |
| 7872 | |
| 7873 | return 0; /* Not a stub. */ |
| 7874 | } |
| 7875 | |
| 7876 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). |
| 7877 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ |
| 7878 | |
| 7879 | static int |
| 7880 | mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) |
| 7881 | { |
| 7882 | CORE_ADDR start_addr; |
| 7883 | size_t prefixlen; |
| 7884 | |
| 7885 | /* Find the starting address of the function containing the PC. */ |
| 7886 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) |
| 7887 | return 0; |
| 7888 | |
| 7889 | /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at |
| 7890 | the start, i.e. after the JALR instruction, this is effectively |
| 7891 | a return stub. */ |
| 7892 | prefixlen = strlen (mips_str_mips16_call_stub); |
| 7893 | if (pc != start_addr |
| 7894 | && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0 |
| 7895 | && mips_is_stub_mode (name + prefixlen) |
| 7896 | && name[prefixlen + 2] == '_' |
| 7897 | && mips_is_stub_suffix (name + prefixlen + 3, 1)) |
| 7898 | return 1; |
| 7899 | |
| 7900 | /* If the PC is in __call_stub_fp_* but not at the start, i.e. after |
| 7901 | the JAL or JALR instruction, this is effectively a return stub. */ |
| 7902 | prefixlen = strlen (mips_str_call_fp_stub); |
| 7903 | if (pc != start_addr |
| 7904 | && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0) |
| 7905 | return 1; |
| 7906 | |
| 7907 | /* Consume the .pic. prefix of any PIC stub, this function must return |
| 7908 | true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub |
| 7909 | or the call stub path will trigger in handle_inferior_event causing |
| 7910 | it to go astray. */ |
| 7911 | prefixlen = strlen (mips_str_pic); |
| 7912 | if (strncmp (name, mips_str_pic, prefixlen) == 0) |
| 7913 | name += prefixlen; |
| 7914 | |
| 7915 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */ |
| 7916 | prefixlen = strlen (mips_str_mips16_ret_stub); |
| 7917 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 |
| 7918 | && mips_is_stub_mode (name + prefixlen) |
| 7919 | && name[prefixlen + 2] == '\0') |
| 7920 | return 1; |
| 7921 | |
| 7922 | return 0; /* Not a stub. */ |
| 7923 | } |
| 7924 | |
| 7925 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
| 7926 | PC of the stub target. The stub just loads $t9 and jumps to it, |
| 7927 | so that $t9 has the correct value at function entry. */ |
| 7928 | |
| 7929 | static CORE_ADDR |
| 7930 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
| 7931 | { |
| 7932 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 7933 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 7934 | struct bound_minimal_symbol msym; |
| 7935 | int i; |
| 7936 | gdb_byte stub_code[16]; |
| 7937 | int32_t stub_words[4]; |
| 7938 | |
| 7939 | /* The stub for foo is named ".pic.foo", and is either two |
| 7940 | instructions inserted before foo or a three instruction sequence |
| 7941 | which jumps to foo. */ |
| 7942 | msym = lookup_minimal_symbol_by_pc (pc); |
| 7943 | if (msym.minsym == NULL |
| 7944 | || BMSYMBOL_VALUE_ADDRESS (msym) != pc |
| 7945 | || MSYMBOL_LINKAGE_NAME (msym.minsym) == NULL |
| 7946 | || !startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic.")) |
| 7947 | return 0; |
| 7948 | |
| 7949 | /* A two-instruction header. */ |
| 7950 | if (MSYMBOL_SIZE (msym.minsym) == 8) |
| 7951 | return pc + 8; |
| 7952 | |
| 7953 | /* A three-instruction (plus delay slot) trampoline. */ |
| 7954 | if (MSYMBOL_SIZE (msym.minsym) == 16) |
| 7955 | { |
| 7956 | if (target_read_memory (pc, stub_code, 16) != 0) |
| 7957 | return 0; |
| 7958 | for (i = 0; i < 4; i++) |
| 7959 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
| 7960 | 4, byte_order); |
| 7961 | |
| 7962 | /* A stub contains these instructions: |
| 7963 | lui t9, %hi(target) |
| 7964 | j target |
| 7965 | addiu t9, t9, %lo(target) |
| 7966 | nop |
| 7967 | |
| 7968 | This works even for N64, since stubs are only generated with |
| 7969 | -msym32. */ |
| 7970 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 |
| 7971 | && (stub_words[1] & 0xfc000000U) == 0x08000000 |
| 7972 | && (stub_words[2] & 0xffff0000U) == 0x27390000 |
| 7973 | && stub_words[3] == 0x00000000) |
| 7974 | return ((((stub_words[0] & 0x0000ffff) << 16) |
| 7975 | + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; |
| 7976 | } |
| 7977 | |
| 7978 | /* Not a recognized stub. */ |
| 7979 | return 0; |
| 7980 | } |
| 7981 | |
| 7982 | static CORE_ADDR |
| 7983 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
| 7984 | { |
| 7985 | CORE_ADDR requested_pc = pc; |
| 7986 | CORE_ADDR target_pc; |
| 7987 | CORE_ADDR new_pc; |
| 7988 | |
| 7989 | do |
| 7990 | { |
| 7991 | target_pc = pc; |
| 7992 | |
| 7993 | new_pc = mips_skip_mips16_trampoline_code (frame, pc); |
| 7994 | if (new_pc) |
| 7995 | pc = new_pc; |
| 7996 | |
| 7997 | new_pc = find_solib_trampoline_target (frame, pc); |
| 7998 | if (new_pc) |
| 7999 | pc = new_pc; |
| 8000 | |
| 8001 | new_pc = mips_skip_pic_trampoline_code (frame, pc); |
| 8002 | if (new_pc) |
| 8003 | pc = new_pc; |
| 8004 | } |
| 8005 | while (pc != target_pc); |
| 8006 | |
| 8007 | return pc != requested_pc ? pc : 0; |
| 8008 | } |
| 8009 | |
| 8010 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
| 8011 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
| 8012 | |
| 8013 | static int |
| 8014 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
| 8015 | { |
| 8016 | int regnum; |
| 8017 | if (num >= 0 && num < 32) |
| 8018 | regnum = num; |
| 8019 | else if (num >= 38 && num < 70) |
| 8020 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
| 8021 | else if (num == 70) |
| 8022 | regnum = mips_regnum (gdbarch)->hi; |
| 8023 | else if (num == 71) |
| 8024 | regnum = mips_regnum (gdbarch)->lo; |
| 8025 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) |
| 8026 | regnum = num + mips_regnum (gdbarch)->dspacc - 72; |
| 8027 | else |
| 8028 | return -1; |
| 8029 | return gdbarch_num_regs (gdbarch) + regnum; |
| 8030 | } |
| 8031 | |
| 8032 | |
| 8033 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
| 8034 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
| 8035 | |
| 8036 | static int |
| 8037 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
| 8038 | { |
| 8039 | int regnum; |
| 8040 | if (num >= 0 && num < 32) |
| 8041 | regnum = num; |
| 8042 | else if (num >= 32 && num < 64) |
| 8043 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
| 8044 | else if (num == 64) |
| 8045 | regnum = mips_regnum (gdbarch)->hi; |
| 8046 | else if (num == 65) |
| 8047 | regnum = mips_regnum (gdbarch)->lo; |
| 8048 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) |
| 8049 | regnum = num + mips_regnum (gdbarch)->dspacc - 66; |
| 8050 | else |
| 8051 | return -1; |
| 8052 | return gdbarch_num_regs (gdbarch) + regnum; |
| 8053 | } |
| 8054 | |
| 8055 | static int |
| 8056 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
| 8057 | { |
| 8058 | /* Only makes sense to supply raw registers. */ |
| 8059 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
| 8060 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
| 8061 | decide if it is valid. Should instead define a standard sim/gdb |
| 8062 | register numbering scheme. */ |
| 8063 | if (gdbarch_register_name (gdbarch, |
| 8064 | gdbarch_num_regs (gdbarch) + regnum) != NULL |
| 8065 | && gdbarch_register_name (gdbarch, |
| 8066 | gdbarch_num_regs (gdbarch) |
| 8067 | + regnum)[0] != '\0') |
| 8068 | return regnum; |
| 8069 | else |
| 8070 | return LEGACY_SIM_REGNO_IGNORE; |
| 8071 | } |
| 8072 | |
| 8073 | |
| 8074 | /* Convert an integer into an address. Extracting the value signed |
| 8075 | guarantees a correctly sign extended address. */ |
| 8076 | |
| 8077 | static CORE_ADDR |
| 8078 | mips_integer_to_address (struct gdbarch *gdbarch, |
| 8079 | struct type *type, const gdb_byte *buf) |
| 8080 | { |
| 8081 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 8082 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); |
| 8083 | } |
| 8084 | |
| 8085 | /* Dummy virtual frame pointer method. This is no more or less accurate |
| 8086 | than most other architectures; we just need to be explicit about it, |
| 8087 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to |
| 8088 | an assertion failure. */ |
| 8089 | |
| 8090 | static void |
| 8091 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
| 8092 | CORE_ADDR pc, int *reg, LONGEST *offset) |
| 8093 | { |
| 8094 | *reg = MIPS_SP_REGNUM; |
| 8095 | *offset = 0; |
| 8096 | } |
| 8097 | |
| 8098 | static void |
| 8099 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) |
| 8100 | { |
| 8101 | enum mips_abi *abip = (enum mips_abi *) obj; |
| 8102 | const char *name = bfd_get_section_name (abfd, sect); |
| 8103 | |
| 8104 | if (*abip != MIPS_ABI_UNKNOWN) |
| 8105 | return; |
| 8106 | |
| 8107 | if (!startswith (name, ".mdebug.")) |
| 8108 | return; |
| 8109 | |
| 8110 | if (strcmp (name, ".mdebug.abi32") == 0) |
| 8111 | *abip = MIPS_ABI_O32; |
| 8112 | else if (strcmp (name, ".mdebug.abiN32") == 0) |
| 8113 | *abip = MIPS_ABI_N32; |
| 8114 | else if (strcmp (name, ".mdebug.abi64") == 0) |
| 8115 | *abip = MIPS_ABI_N64; |
| 8116 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
| 8117 | *abip = MIPS_ABI_O64; |
| 8118 | else if (strcmp (name, ".mdebug.eabi32") == 0) |
| 8119 | *abip = MIPS_ABI_EABI32; |
| 8120 | else if (strcmp (name, ".mdebug.eabi64") == 0) |
| 8121 | *abip = MIPS_ABI_EABI64; |
| 8122 | else |
| 8123 | warning (_("unsupported ABI %s."), name + 8); |
| 8124 | } |
| 8125 | |
| 8126 | static void |
| 8127 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) |
| 8128 | { |
| 8129 | int *lbp = (int *) obj; |
| 8130 | const char *name = bfd_get_section_name (abfd, sect); |
| 8131 | |
| 8132 | if (startswith (name, ".gcc_compiled_long32")) |
| 8133 | *lbp = 32; |
| 8134 | else if (startswith (name, ".gcc_compiled_long64")) |
| 8135 | *lbp = 64; |
| 8136 | else if (startswith (name, ".gcc_compiled_long")) |
| 8137 | warning (_("unrecognized .gcc_compiled_longXX")); |
| 8138 | } |
| 8139 | |
| 8140 | static enum mips_abi |
| 8141 | global_mips_abi (void) |
| 8142 | { |
| 8143 | int i; |
| 8144 | |
| 8145 | for (i = 0; mips_abi_strings[i] != NULL; i++) |
| 8146 | if (mips_abi_strings[i] == mips_abi_string) |
| 8147 | return (enum mips_abi) i; |
| 8148 | |
| 8149 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
| 8150 | } |
| 8151 | |
| 8152 | /* Return the default compressed instruction set, either of MIPS16 |
| 8153 | or microMIPS, selected when none could have been determined from |
| 8154 | the ELF header of the binary being executed (or no binary has been |
| 8155 | selected. */ |
| 8156 | |
| 8157 | static enum mips_isa |
| 8158 | global_mips_compression (void) |
| 8159 | { |
| 8160 | int i; |
| 8161 | |
| 8162 | for (i = 0; mips_compression_strings[i] != NULL; i++) |
| 8163 | if (mips_compression_strings[i] == mips_compression_string) |
| 8164 | return (enum mips_isa) i; |
| 8165 | |
| 8166 | internal_error (__FILE__, __LINE__, _("unknown compressed ISA string")); |
| 8167 | } |
| 8168 | |
| 8169 | static void |
| 8170 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) |
| 8171 | { |
| 8172 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
| 8173 | assume that's what we've got. */ |
| 8174 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
| 8175 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); |
| 8176 | |
| 8177 | /* If the size matches the full set of registers GDB traditionally |
| 8178 | knows about, including floating point, for either 32-bit or |
| 8179 | 64-bit, assume that's what we've got. */ |
| 8180 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
| 8181 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); |
| 8182 | |
| 8183 | /* Otherwise we don't have a useful guess. */ |
| 8184 | } |
| 8185 | |
| 8186 | static struct value * |
| 8187 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) |
| 8188 | { |
| 8189 | const int *reg_p = (const int *) baton; |
| 8190 | return value_of_register (*reg_p, frame); |
| 8191 | } |
| 8192 | |
| 8193 | static struct gdbarch * |
| 8194 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 8195 | { |
| 8196 | struct gdbarch *gdbarch; |
| 8197 | struct gdbarch_tdep *tdep; |
| 8198 | int elf_flags; |
| 8199 | enum mips_abi mips_abi, found_abi, wanted_abi; |
| 8200 | int i, num_regs; |
| 8201 | enum mips_fpu_type fpu_type; |
| 8202 | struct tdesc_arch_data *tdesc_data = NULL; |
| 8203 | int elf_fpu_type = Val_GNU_MIPS_ABI_FP_ANY; |
| 8204 | const char **reg_names; |
| 8205 | struct mips_regnum mips_regnum, *regnum; |
| 8206 | enum mips_isa mips_isa; |
| 8207 | int dspacc; |
| 8208 | int dspctl; |
| 8209 | |
| 8210 | /* Fill in the OS dependent register numbers and names. */ |
| 8211 | if (info.osabi == GDB_OSABI_IRIX) |
| 8212 | { |
| 8213 | mips_regnum.fp0 = 32; |
| 8214 | mips_regnum.pc = 64; |
| 8215 | mips_regnum.cause = 65; |
| 8216 | mips_regnum.badvaddr = 66; |
| 8217 | mips_regnum.hi = 67; |
| 8218 | mips_regnum.lo = 68; |
| 8219 | mips_regnum.fp_control_status = 69; |
| 8220 | mips_regnum.fp_implementation_revision = 70; |
| 8221 | mips_regnum.dspacc = dspacc = -1; |
| 8222 | mips_regnum.dspctl = dspctl = -1; |
| 8223 | num_regs = 71; |
| 8224 | reg_names = mips_irix_reg_names; |
| 8225 | } |
| 8226 | else if (info.osabi == GDB_OSABI_LINUX) |
| 8227 | { |
| 8228 | mips_regnum.fp0 = 38; |
| 8229 | mips_regnum.pc = 37; |
| 8230 | mips_regnum.cause = 36; |
| 8231 | mips_regnum.badvaddr = 35; |
| 8232 | mips_regnum.hi = 34; |
| 8233 | mips_regnum.lo = 33; |
| 8234 | mips_regnum.fp_control_status = 70; |
| 8235 | mips_regnum.fp_implementation_revision = 71; |
| 8236 | mips_regnum.dspacc = -1; |
| 8237 | mips_regnum.dspctl = -1; |
| 8238 | dspacc = 72; |
| 8239 | dspctl = 78; |
| 8240 | num_regs = 79; |
| 8241 | reg_names = mips_linux_reg_names; |
| 8242 | } |
| 8243 | else |
| 8244 | { |
| 8245 | mips_regnum.lo = MIPS_EMBED_LO_REGNUM; |
| 8246 | mips_regnum.hi = MIPS_EMBED_HI_REGNUM; |
| 8247 | mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; |
| 8248 | mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; |
| 8249 | mips_regnum.pc = MIPS_EMBED_PC_REGNUM; |
| 8250 | mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; |
| 8251 | mips_regnum.fp_control_status = 70; |
| 8252 | mips_regnum.fp_implementation_revision = 71; |
| 8253 | mips_regnum.dspacc = dspacc = -1; |
| 8254 | mips_regnum.dspctl = dspctl = -1; |
| 8255 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; |
| 8256 | if (info.bfd_arch_info != NULL |
| 8257 | && info.bfd_arch_info->mach == bfd_mach_mips3900) |
| 8258 | reg_names = mips_tx39_reg_names; |
| 8259 | else |
| 8260 | reg_names = mips_generic_reg_names; |
| 8261 | } |
| 8262 | |
| 8263 | /* Check any target description for validity. */ |
| 8264 | if (tdesc_has_registers (info.target_desc)) |
| 8265 | { |
| 8266 | static const char *const mips_gprs[] = { |
| 8267 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 8268 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 8269 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
| 8270 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" |
| 8271 | }; |
| 8272 | static const char *const mips_fprs[] = { |
| 8273 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 8274 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 8275 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 8276 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 8277 | }; |
| 8278 | |
| 8279 | const struct tdesc_feature *feature; |
| 8280 | int valid_p; |
| 8281 | |
| 8282 | feature = tdesc_find_feature (info.target_desc, |
| 8283 | "org.gnu.gdb.mips.cpu"); |
| 8284 | if (feature == NULL) |
| 8285 | return NULL; |
| 8286 | |
| 8287 | tdesc_data = tdesc_data_alloc (); |
| 8288 | |
| 8289 | valid_p = 1; |
| 8290 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) |
| 8291 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, |
| 8292 | mips_gprs[i]); |
| 8293 | |
| 8294 | |
| 8295 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8296 | mips_regnum.lo, "lo"); |
| 8297 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8298 | mips_regnum.hi, "hi"); |
| 8299 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8300 | mips_regnum.pc, "pc"); |
| 8301 | |
| 8302 | if (!valid_p) |
| 8303 | { |
| 8304 | tdesc_data_cleanup (tdesc_data); |
| 8305 | return NULL; |
| 8306 | } |
| 8307 | |
| 8308 | feature = tdesc_find_feature (info.target_desc, |
| 8309 | "org.gnu.gdb.mips.cp0"); |
| 8310 | if (feature == NULL) |
| 8311 | { |
| 8312 | tdesc_data_cleanup (tdesc_data); |
| 8313 | return NULL; |
| 8314 | } |
| 8315 | |
| 8316 | valid_p = 1; |
| 8317 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8318 | mips_regnum.badvaddr, "badvaddr"); |
| 8319 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8320 | MIPS_PS_REGNUM, "status"); |
| 8321 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8322 | mips_regnum.cause, "cause"); |
| 8323 | |
| 8324 | if (!valid_p) |
| 8325 | { |
| 8326 | tdesc_data_cleanup (tdesc_data); |
| 8327 | return NULL; |
| 8328 | } |
| 8329 | |
| 8330 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS |
| 8331 | backend is not prepared for that, though. */ |
| 8332 | feature = tdesc_find_feature (info.target_desc, |
| 8333 | "org.gnu.gdb.mips.fpu"); |
| 8334 | if (feature == NULL) |
| 8335 | { |
| 8336 | tdesc_data_cleanup (tdesc_data); |
| 8337 | return NULL; |
| 8338 | } |
| 8339 | |
| 8340 | valid_p = 1; |
| 8341 | for (i = 0; i < 32; i++) |
| 8342 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8343 | i + mips_regnum.fp0, mips_fprs[i]); |
| 8344 | |
| 8345 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8346 | mips_regnum.fp_control_status, |
| 8347 | "fcsr"); |
| 8348 | valid_p |
| 8349 | &= tdesc_numbered_register (feature, tdesc_data, |
| 8350 | mips_regnum.fp_implementation_revision, |
| 8351 | "fir"); |
| 8352 | |
| 8353 | if (!valid_p) |
| 8354 | { |
| 8355 | tdesc_data_cleanup (tdesc_data); |
| 8356 | return NULL; |
| 8357 | } |
| 8358 | |
| 8359 | if (dspacc >= 0) |
| 8360 | { |
| 8361 | feature = tdesc_find_feature (info.target_desc, |
| 8362 | "org.gnu.gdb.mips.dsp"); |
| 8363 | /* The DSP registers are optional; it's OK if they are absent. */ |
| 8364 | if (feature != NULL) |
| 8365 | { |
| 8366 | i = 0; |
| 8367 | valid_p = 1; |
| 8368 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8369 | dspacc + i++, "hi1"); |
| 8370 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8371 | dspacc + i++, "lo1"); |
| 8372 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8373 | dspacc + i++, "hi2"); |
| 8374 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8375 | dspacc + i++, "lo2"); |
| 8376 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8377 | dspacc + i++, "hi3"); |
| 8378 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8379 | dspacc + i++, "lo3"); |
| 8380 | |
| 8381 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8382 | dspctl, "dspctl"); |
| 8383 | |
| 8384 | if (!valid_p) |
| 8385 | { |
| 8386 | tdesc_data_cleanup (tdesc_data); |
| 8387 | return NULL; |
| 8388 | } |
| 8389 | |
| 8390 | mips_regnum.dspacc = dspacc; |
| 8391 | mips_regnum.dspctl = dspctl; |
| 8392 | } |
| 8393 | } |
| 8394 | |
| 8395 | /* It would be nice to detect an attempt to use a 64-bit ABI |
| 8396 | when only 32-bit registers are provided. */ |
| 8397 | reg_names = NULL; |
| 8398 | } |
| 8399 | |
| 8400 | /* First of all, extract the elf_flags, if available. */ |
| 8401 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) |
| 8402 | elf_flags = elf_elfheader (info.abfd)->e_flags; |
| 8403 | else if (arches != NULL) |
| 8404 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; |
| 8405 | else |
| 8406 | elf_flags = 0; |
| 8407 | if (gdbarch_debug) |
| 8408 | fprintf_unfiltered (gdb_stdlog, |
| 8409 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
| 8410 | |
| 8411 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
| 8412 | switch ((elf_flags & EF_MIPS_ABI)) |
| 8413 | { |
| 8414 | case E_MIPS_ABI_O32: |
| 8415 | found_abi = MIPS_ABI_O32; |
| 8416 | break; |
| 8417 | case E_MIPS_ABI_O64: |
| 8418 | found_abi = MIPS_ABI_O64; |
| 8419 | break; |
| 8420 | case E_MIPS_ABI_EABI32: |
| 8421 | found_abi = MIPS_ABI_EABI32; |
| 8422 | break; |
| 8423 | case E_MIPS_ABI_EABI64: |
| 8424 | found_abi = MIPS_ABI_EABI64; |
| 8425 | break; |
| 8426 | default: |
| 8427 | if ((elf_flags & EF_MIPS_ABI2)) |
| 8428 | found_abi = MIPS_ABI_N32; |
| 8429 | else |
| 8430 | found_abi = MIPS_ABI_UNKNOWN; |
| 8431 | break; |
| 8432 | } |
| 8433 | |
| 8434 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
| 8435 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
| 8436 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); |
| 8437 | |
| 8438 | /* If we have no useful BFD information, use the ABI from the last |
| 8439 | MIPS architecture (if there is one). */ |
| 8440 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) |
| 8441 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; |
| 8442 | |
| 8443 | /* Try the architecture for any hint of the correct ABI. */ |
| 8444 | if (found_abi == MIPS_ABI_UNKNOWN |
| 8445 | && info.bfd_arch_info != NULL |
| 8446 | && info.bfd_arch_info->arch == bfd_arch_mips) |
| 8447 | { |
| 8448 | switch (info.bfd_arch_info->mach) |
| 8449 | { |
| 8450 | case bfd_mach_mips3900: |
| 8451 | found_abi = MIPS_ABI_EABI32; |
| 8452 | break; |
| 8453 | case bfd_mach_mips4100: |
| 8454 | case bfd_mach_mips5000: |
| 8455 | found_abi = MIPS_ABI_EABI64; |
| 8456 | break; |
| 8457 | case bfd_mach_mips8000: |
| 8458 | case bfd_mach_mips10000: |
| 8459 | /* On Irix, ELF64 executables use the N64 ABI. The |
| 8460 | pseudo-sections which describe the ABI aren't present |
| 8461 | on IRIX. (Even for executables created by gcc.) */ |
| 8462 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
| 8463 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) |
| 8464 | found_abi = MIPS_ABI_N64; |
| 8465 | else |
| 8466 | found_abi = MIPS_ABI_N32; |
| 8467 | break; |
| 8468 | } |
| 8469 | } |
| 8470 | |
| 8471 | /* Default 64-bit objects to N64 instead of O32. */ |
| 8472 | if (found_abi == MIPS_ABI_UNKNOWN |
| 8473 | && info.abfd != NULL |
| 8474 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
| 8475 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) |
| 8476 | found_abi = MIPS_ABI_N64; |
| 8477 | |
| 8478 | if (gdbarch_debug) |
| 8479 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", |
| 8480 | found_abi); |
| 8481 | |
| 8482 | /* What has the user specified from the command line? */ |
| 8483 | wanted_abi = global_mips_abi (); |
| 8484 | if (gdbarch_debug) |
| 8485 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", |
| 8486 | wanted_abi); |
| 8487 | |
| 8488 | /* Now that we have found what the ABI for this binary would be, |
| 8489 | check whether the user is overriding it. */ |
| 8490 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
| 8491 | mips_abi = wanted_abi; |
| 8492 | else if (found_abi != MIPS_ABI_UNKNOWN) |
| 8493 | mips_abi = found_abi; |
| 8494 | else |
| 8495 | mips_abi = MIPS_ABI_O32; |
| 8496 | if (gdbarch_debug) |
| 8497 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", |
| 8498 | mips_abi); |
| 8499 | |
| 8500 | /* Determine the default compressed ISA. */ |
| 8501 | if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0 |
| 8502 | && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0) |
| 8503 | mips_isa = ISA_MICROMIPS; |
| 8504 | else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0 |
| 8505 | && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0) |
| 8506 | mips_isa = ISA_MIPS16; |
| 8507 | else |
| 8508 | mips_isa = global_mips_compression (); |
| 8509 | mips_compression_string = mips_compression_strings[mips_isa]; |
| 8510 | |
| 8511 | /* Also used when doing an architecture lookup. */ |
| 8512 | if (gdbarch_debug) |
| 8513 | fprintf_unfiltered (gdb_stdlog, |
| 8514 | "mips_gdbarch_init: " |
| 8515 | "mips64_transfers_32bit_regs_p = %d\n", |
| 8516 | mips64_transfers_32bit_regs_p); |
| 8517 | |
| 8518 | /* Determine the MIPS FPU type. */ |
| 8519 | #ifdef HAVE_ELF |
| 8520 | if (info.abfd |
| 8521 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) |
| 8522 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, |
| 8523 | Tag_GNU_MIPS_ABI_FP); |
| 8524 | #endif /* HAVE_ELF */ |
| 8525 | |
| 8526 | if (!mips_fpu_type_auto) |
| 8527 | fpu_type = mips_fpu_type; |
| 8528 | else if (elf_fpu_type != Val_GNU_MIPS_ABI_FP_ANY) |
| 8529 | { |
| 8530 | switch (elf_fpu_type) |
| 8531 | { |
| 8532 | case Val_GNU_MIPS_ABI_FP_DOUBLE: |
| 8533 | fpu_type = MIPS_FPU_DOUBLE; |
| 8534 | break; |
| 8535 | case Val_GNU_MIPS_ABI_FP_SINGLE: |
| 8536 | fpu_type = MIPS_FPU_SINGLE; |
| 8537 | break; |
| 8538 | case Val_GNU_MIPS_ABI_FP_SOFT: |
| 8539 | default: |
| 8540 | /* Soft float or unknown. */ |
| 8541 | fpu_type = MIPS_FPU_NONE; |
| 8542 | break; |
| 8543 | } |
| 8544 | } |
| 8545 | else if (info.bfd_arch_info != NULL |
| 8546 | && info.bfd_arch_info->arch == bfd_arch_mips) |
| 8547 | switch (info.bfd_arch_info->mach) |
| 8548 | { |
| 8549 | case bfd_mach_mips3900: |
| 8550 | case bfd_mach_mips4100: |
| 8551 | case bfd_mach_mips4111: |
| 8552 | case bfd_mach_mips4120: |
| 8553 | fpu_type = MIPS_FPU_NONE; |
| 8554 | break; |
| 8555 | case bfd_mach_mips4650: |
| 8556 | fpu_type = MIPS_FPU_SINGLE; |
| 8557 | break; |
| 8558 | default: |
| 8559 | fpu_type = MIPS_FPU_DOUBLE; |
| 8560 | break; |
| 8561 | } |
| 8562 | else if (arches != NULL) |
| 8563 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; |
| 8564 | else |
| 8565 | fpu_type = MIPS_FPU_DOUBLE; |
| 8566 | if (gdbarch_debug) |
| 8567 | fprintf_unfiltered (gdb_stdlog, |
| 8568 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
| 8569 | |
| 8570 | /* Check for blatant incompatibilities. */ |
| 8571 | |
| 8572 | /* If we have only 32-bit registers, then we can't debug a 64-bit |
| 8573 | ABI. */ |
| 8574 | if (info.target_desc |
| 8575 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL |
| 8576 | && mips_abi != MIPS_ABI_EABI32 |
| 8577 | && mips_abi != MIPS_ABI_O32) |
| 8578 | { |
| 8579 | if (tdesc_data != NULL) |
| 8580 | tdesc_data_cleanup (tdesc_data); |
| 8581 | return NULL; |
| 8582 | } |
| 8583 | |
| 8584 | /* Try to find a pre-existing architecture. */ |
| 8585 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
| 8586 | arches != NULL; |
| 8587 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) |
| 8588 | { |
| 8589 | /* MIPS needs to be pedantic about which ABI and the compressed |
| 8590 | ISA variation the object is using. */ |
| 8591 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
| 8592 | continue; |
| 8593 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
| 8594 | continue; |
| 8595 | if (gdbarch_tdep (arches->gdbarch)->mips_isa != mips_isa) |
| 8596 | continue; |
| 8597 | /* Need to be pedantic about which register virtual size is |
| 8598 | used. */ |
| 8599 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p |
| 8600 | != mips64_transfers_32bit_regs_p) |
| 8601 | continue; |
| 8602 | /* Be pedantic about which FPU is selected. */ |
| 8603 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) |
| 8604 | continue; |
| 8605 | |
| 8606 | if (tdesc_data != NULL) |
| 8607 | tdesc_data_cleanup (tdesc_data); |
| 8608 | return arches->gdbarch; |
| 8609 | } |
| 8610 | |
| 8611 | /* Need a new architecture. Fill in a target specific vector. */ |
| 8612 | tdep = XNEW (struct gdbarch_tdep); |
| 8613 | gdbarch = gdbarch_alloc (&info, tdep); |
| 8614 | tdep->elf_flags = elf_flags; |
| 8615 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
| 8616 | tdep->found_abi = found_abi; |
| 8617 | tdep->mips_abi = mips_abi; |
| 8618 | tdep->mips_isa = mips_isa; |
| 8619 | tdep->mips_fpu_type = fpu_type; |
| 8620 | tdep->register_size_valid_p = 0; |
| 8621 | tdep->register_size = 0; |
| 8622 | |
| 8623 | if (info.target_desc) |
| 8624 | { |
| 8625 | /* Some useful properties can be inferred from the target. */ |
| 8626 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) |
| 8627 | { |
| 8628 | tdep->register_size_valid_p = 1; |
| 8629 | tdep->register_size = 4; |
| 8630 | } |
| 8631 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) |
| 8632 | { |
| 8633 | tdep->register_size_valid_p = 1; |
| 8634 | tdep->register_size = 8; |
| 8635 | } |
| 8636 | } |
| 8637 | |
| 8638 | /* Initially set everything according to the default ABI/ISA. */ |
| 8639 | set_gdbarch_short_bit (gdbarch, 16); |
| 8640 | set_gdbarch_int_bit (gdbarch, 32); |
| 8641 | set_gdbarch_float_bit (gdbarch, 32); |
| 8642 | set_gdbarch_double_bit (gdbarch, 64); |
| 8643 | set_gdbarch_long_double_bit (gdbarch, 64); |
| 8644 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
| 8645 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); |
| 8646 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); |
| 8647 | |
| 8648 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
| 8649 | mips_ax_pseudo_register_collect); |
| 8650 | set_gdbarch_ax_pseudo_register_push_stack |
| 8651 | (gdbarch, mips_ax_pseudo_register_push_stack); |
| 8652 | |
| 8653 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
| 8654 | mips_elf_make_msymbol_special); |
| 8655 | set_gdbarch_make_symbol_special (gdbarch, mips_make_symbol_special); |
| 8656 | set_gdbarch_adjust_dwarf2_addr (gdbarch, mips_adjust_dwarf2_addr); |
| 8657 | set_gdbarch_adjust_dwarf2_line (gdbarch, mips_adjust_dwarf2_line); |
| 8658 | |
| 8659 | regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); |
| 8660 | *regnum = mips_regnum; |
| 8661 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
| 8662 | set_gdbarch_num_regs (gdbarch, num_regs); |
| 8663 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); |
| 8664 | set_gdbarch_register_name (gdbarch, mips_register_name); |
| 8665 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); |
| 8666 | tdep->mips_processor_reg_names = reg_names; |
| 8667 | tdep->regnum = regnum; |
| 8668 | |
| 8669 | switch (mips_abi) |
| 8670 | { |
| 8671 | case MIPS_ABI_O32: |
| 8672 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
| 8673 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
| 8674 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
| 8675 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
| 8676 | tdep->default_mask_address_p = 0; |
| 8677 | set_gdbarch_long_bit (gdbarch, 32); |
| 8678 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 8679 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 8680 | break; |
| 8681 | case MIPS_ABI_O64: |
| 8682 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
| 8683 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
| 8684 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
| 8685 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
| 8686 | tdep->default_mask_address_p = 0; |
| 8687 | set_gdbarch_long_bit (gdbarch, 32); |
| 8688 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 8689 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 8690 | break; |
| 8691 | case MIPS_ABI_EABI32: |
| 8692 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
| 8693 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
| 8694 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
| 8695 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
| 8696 | tdep->default_mask_address_p = 0; |
| 8697 | set_gdbarch_long_bit (gdbarch, 32); |
| 8698 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 8699 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 8700 | break; |
| 8701 | case MIPS_ABI_EABI64: |
| 8702 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
| 8703 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
| 8704 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
| 8705 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
| 8706 | tdep->default_mask_address_p = 0; |
| 8707 | set_gdbarch_long_bit (gdbarch, 64); |
| 8708 | set_gdbarch_ptr_bit (gdbarch, 64); |
| 8709 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 8710 | break; |
| 8711 | case MIPS_ABI_N32: |
| 8712 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
| 8713 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
| 8714 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
| 8715 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
| 8716 | tdep->default_mask_address_p = 0; |
| 8717 | set_gdbarch_long_bit (gdbarch, 32); |
| 8718 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 8719 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 8720 | set_gdbarch_long_double_bit (gdbarch, 128); |
| 8721 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
| 8722 | break; |
| 8723 | case MIPS_ABI_N64: |
| 8724 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
| 8725 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
| 8726 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
| 8727 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
| 8728 | tdep->default_mask_address_p = 0; |
| 8729 | set_gdbarch_long_bit (gdbarch, 64); |
| 8730 | set_gdbarch_ptr_bit (gdbarch, 64); |
| 8731 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 8732 | set_gdbarch_long_double_bit (gdbarch, 128); |
| 8733 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
| 8734 | break; |
| 8735 | default: |
| 8736 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
| 8737 | } |
| 8738 | |
| 8739 | /* GCC creates a pseudo-section whose name specifies the size of |
| 8740 | longs, since -mlong32 or -mlong64 may be used independent of |
| 8741 | other options. How those options affect pointer sizes is ABI and |
| 8742 | architecture dependent, so use them to override the default sizes |
| 8743 | set by the ABI. This table shows the relationship between ABI, |
| 8744 | -mlongXX, and size of pointers: |
| 8745 | |
| 8746 | ABI -mlongXX ptr bits |
| 8747 | --- -------- -------- |
| 8748 | o32 32 32 |
| 8749 | o32 64 32 |
| 8750 | n32 32 32 |
| 8751 | n32 64 64 |
| 8752 | o64 32 32 |
| 8753 | o64 64 64 |
| 8754 | n64 32 32 |
| 8755 | n64 64 64 |
| 8756 | eabi32 32 32 |
| 8757 | eabi32 64 32 |
| 8758 | eabi64 32 32 |
| 8759 | eabi64 64 64 |
| 8760 | |
| 8761 | Note that for o32 and eabi32, pointers are always 32 bits |
| 8762 | regardless of any -mlongXX option. For all others, pointers and |
| 8763 | longs are the same, as set by -mlongXX or set by defaults. */ |
| 8764 | |
| 8765 | if (info.abfd != NULL) |
| 8766 | { |
| 8767 | int long_bit = 0; |
| 8768 | |
| 8769 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); |
| 8770 | if (long_bit) |
| 8771 | { |
| 8772 | set_gdbarch_long_bit (gdbarch, long_bit); |
| 8773 | switch (mips_abi) |
| 8774 | { |
| 8775 | case MIPS_ABI_O32: |
| 8776 | case MIPS_ABI_EABI32: |
| 8777 | break; |
| 8778 | case MIPS_ABI_N32: |
| 8779 | case MIPS_ABI_O64: |
| 8780 | case MIPS_ABI_N64: |
| 8781 | case MIPS_ABI_EABI64: |
| 8782 | set_gdbarch_ptr_bit (gdbarch, long_bit); |
| 8783 | break; |
| 8784 | default: |
| 8785 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
| 8786 | } |
| 8787 | } |
| 8788 | } |
| 8789 | |
| 8790 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
| 8791 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the |
| 8792 | comment: |
| 8793 | |
| 8794 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE |
| 8795 | flag in object files because to do so would make it impossible to |
| 8796 | link with libraries compiled without "-gp32". This is |
| 8797 | unnecessarily restrictive. |
| 8798 | |
| 8799 | We could solve this problem by adding "-gp32" multilibs to gcc, |
| 8800 | but to set this flag before gcc is built with such multilibs will |
| 8801 | break too many systems.'' |
| 8802 | |
| 8803 | But even more unhelpfully, the default linker output target for |
| 8804 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even |
| 8805 | for 64-bit programs - you need to change the ABI to change this, |
| 8806 | and not all gcc targets support that currently. Therefore using |
| 8807 | this flag to detect 32-bit mode would do the wrong thing given |
| 8808 | the current gcc - it would make GDB treat these 64-bit programs |
| 8809 | as 32-bit programs by default. */ |
| 8810 | |
| 8811 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
| 8812 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
| 8813 | |
| 8814 | /* Add/remove bits from an address. The MIPS needs be careful to |
| 8815 | ensure that all 32 bit addresses are sign extended to 64 bits. */ |
| 8816 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
| 8817 | |
| 8818 | /* Unwind the frame. */ |
| 8819 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); |
| 8820 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
| 8821 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
| 8822 | |
| 8823 | /* Map debug register numbers onto internal register numbers. */ |
| 8824 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
| 8825 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
| 8826 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); |
| 8827 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
| 8828 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); |
| 8829 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
| 8830 | |
| 8831 | /* MIPS version of CALL_DUMMY. */ |
| 8832 | |
| 8833 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
| 8834 | set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code); |
| 8835 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
| 8836 | |
| 8837 | set_gdbarch_print_float_info (gdbarch, mips_print_float_info); |
| 8838 | |
| 8839 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
| 8840 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); |
| 8841 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); |
| 8842 | |
| 8843 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 8844 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); |
| 8845 | set_gdbarch_remote_breakpoint_from_pc (gdbarch, |
| 8846 | mips_remote_breakpoint_from_pc); |
| 8847 | set_gdbarch_adjust_breakpoint_address (gdbarch, |
| 8848 | mips_adjust_breakpoint_address); |
| 8849 | |
| 8850 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); |
| 8851 | |
| 8852 | set_gdbarch_stack_frame_destroyed_p (gdbarch, mips_stack_frame_destroyed_p); |
| 8853 | |
| 8854 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
| 8855 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); |
| 8856 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); |
| 8857 | |
| 8858 | set_gdbarch_register_type (gdbarch, mips_register_type); |
| 8859 | |
| 8860 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
| 8861 | |
| 8862 | if (mips_abi == MIPS_ABI_N32) |
| 8863 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); |
| 8864 | else if (mips_abi == MIPS_ABI_N64) |
| 8865 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); |
| 8866 | else |
| 8867 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
| 8868 | |
| 8869 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
| 8870 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint |
| 8871 | need to all be folded into the target vector. Since they are |
| 8872 | being used as guards for target_stopped_by_watchpoint, why not have |
| 8873 | target_stopped_by_watchpoint return the type of watchpoint that the code |
| 8874 | is sitting on? */ |
| 8875 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
| 8876 | |
| 8877 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
| 8878 | |
| 8879 | /* NOTE drow/2012-04-25: We overload the core solib trampoline code |
| 8880 | to support MIPS16. This is a bad thing. Make sure not to do it |
| 8881 | if we have an OS ABI that actually supports shared libraries, since |
| 8882 | shared library support is more important. If we have an OS someday |
| 8883 | that supports both shared libraries and MIPS16, we'll have to find |
| 8884 | a better place for these. |
| 8885 | macro/2012-04-25: But that applies to return trampolines only and |
| 8886 | currently no MIPS OS ABI uses shared libraries that have them. */ |
| 8887 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); |
| 8888 | |
| 8889 | set_gdbarch_single_step_through_delay (gdbarch, |
| 8890 | mips_single_step_through_delay); |
| 8891 | |
| 8892 | /* Virtual tables. */ |
| 8893 | set_gdbarch_vbit_in_delta (gdbarch, 1); |
| 8894 | |
| 8895 | mips_register_g_packet_guesses (gdbarch); |
| 8896 | |
| 8897 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
| 8898 | info.tdep_info = tdesc_data; |
| 8899 | gdbarch_init_osabi (info, gdbarch); |
| 8900 | |
| 8901 | /* The hook may have adjusted num_regs, fetch the final value and |
| 8902 | set pc_regnum and sp_regnum now that it has been fixed. */ |
| 8903 | num_regs = gdbarch_num_regs (gdbarch); |
| 8904 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
| 8905 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); |
| 8906 | |
| 8907 | /* Unwind the frame. */ |
| 8908 | dwarf2_append_unwinders (gdbarch); |
| 8909 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); |
| 8910 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); |
| 8911 | frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind); |
| 8912 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); |
| 8913 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
| 8914 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
| 8915 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
| 8916 | frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer); |
| 8917 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); |
| 8918 | |
| 8919 | if (tdesc_data) |
| 8920 | { |
| 8921 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); |
| 8922 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
| 8923 | |
| 8924 | /* Override the normal target description methods to handle our |
| 8925 | dual real and pseudo registers. */ |
| 8926 | set_gdbarch_register_name (gdbarch, mips_register_name); |
| 8927 | set_gdbarch_register_reggroup_p (gdbarch, |
| 8928 | mips_tdesc_register_reggroup_p); |
| 8929 | |
| 8930 | num_regs = gdbarch_num_regs (gdbarch); |
| 8931 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); |
| 8932 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); |
| 8933 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); |
| 8934 | } |
| 8935 | |
| 8936 | /* Add ABI-specific aliases for the registers. */ |
| 8937 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) |
| 8938 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) |
| 8939 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, |
| 8940 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); |
| 8941 | else |
| 8942 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) |
| 8943 | user_reg_add (gdbarch, mips_o32_aliases[i].name, |
| 8944 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); |
| 8945 | |
| 8946 | /* Add some other standard aliases. */ |
| 8947 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) |
| 8948 | user_reg_add (gdbarch, mips_register_aliases[i].name, |
| 8949 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); |
| 8950 | |
| 8951 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
| 8952 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, |
| 8953 | value_of_mips_user_reg, |
| 8954 | &mips_numeric_register_aliases[i].regnum); |
| 8955 | |
| 8956 | return gdbarch; |
| 8957 | } |
| 8958 | |
| 8959 | static void |
| 8960 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
| 8961 | { |
| 8962 | struct gdbarch_info info; |
| 8963 | |
| 8964 | /* Force the architecture to update, and (if it's a MIPS architecture) |
| 8965 | mips_gdbarch_init will take care of the rest. */ |
| 8966 | gdbarch_info_init (&info); |
| 8967 | gdbarch_update_p (info); |
| 8968 | } |
| 8969 | |
| 8970 | /* Print out which MIPS ABI is in use. */ |
| 8971 | |
| 8972 | static void |
| 8973 | show_mips_abi (struct ui_file *file, |
| 8974 | int from_tty, |
| 8975 | struct cmd_list_element *ignored_cmd, |
| 8976 | const char *ignored_value) |
| 8977 | { |
| 8978 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) |
| 8979 | fprintf_filtered |
| 8980 | (file, |
| 8981 | "The MIPS ABI is unknown because the current architecture " |
| 8982 | "is not MIPS.\n"); |
| 8983 | else |
| 8984 | { |
| 8985 | enum mips_abi global_abi = global_mips_abi (); |
| 8986 | enum mips_abi actual_abi = mips_abi (target_gdbarch ()); |
| 8987 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
| 8988 | |
| 8989 | if (global_abi == MIPS_ABI_UNKNOWN) |
| 8990 | fprintf_filtered |
| 8991 | (file, |
| 8992 | "The MIPS ABI is set automatically (currently \"%s\").\n", |
| 8993 | actual_abi_str); |
| 8994 | else if (global_abi == actual_abi) |
| 8995 | fprintf_filtered |
| 8996 | (file, |
| 8997 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", |
| 8998 | actual_abi_str); |
| 8999 | else |
| 9000 | { |
| 9001 | /* Probably shouldn't happen... */ |
| 9002 | fprintf_filtered (file, |
| 9003 | "The (auto detected) MIPS ABI \"%s\" is in use " |
| 9004 | "even though the user setting was \"%s\".\n", |
| 9005 | actual_abi_str, mips_abi_strings[global_abi]); |
| 9006 | } |
| 9007 | } |
| 9008 | } |
| 9009 | |
| 9010 | /* Print out which MIPS compressed ISA encoding is used. */ |
| 9011 | |
| 9012 | static void |
| 9013 | show_mips_compression (struct ui_file *file, int from_tty, |
| 9014 | struct cmd_list_element *c, const char *value) |
| 9015 | { |
| 9016 | fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"), |
| 9017 | value); |
| 9018 | } |
| 9019 | |
| 9020 | static void |
| 9021 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
| 9022 | { |
| 9023 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 9024 | if (tdep != NULL) |
| 9025 | { |
| 9026 | int ef_mips_arch; |
| 9027 | int ef_mips_32bitmode; |
| 9028 | /* Determine the ISA. */ |
| 9029 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
| 9030 | { |
| 9031 | case E_MIPS_ARCH_1: |
| 9032 | ef_mips_arch = 1; |
| 9033 | break; |
| 9034 | case E_MIPS_ARCH_2: |
| 9035 | ef_mips_arch = 2; |
| 9036 | break; |
| 9037 | case E_MIPS_ARCH_3: |
| 9038 | ef_mips_arch = 3; |
| 9039 | break; |
| 9040 | case E_MIPS_ARCH_4: |
| 9041 | ef_mips_arch = 4; |
| 9042 | break; |
| 9043 | default: |
| 9044 | ef_mips_arch = 0; |
| 9045 | break; |
| 9046 | } |
| 9047 | /* Determine the size of a pointer. */ |
| 9048 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
| 9049 | fprintf_unfiltered (file, |
| 9050 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", |
| 9051 | tdep->elf_flags); |
| 9052 | fprintf_unfiltered (file, |
| 9053 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
| 9054 | ef_mips_32bitmode); |
| 9055 | fprintf_unfiltered (file, |
| 9056 | "mips_dump_tdep: ef_mips_arch = %d\n", |
| 9057 | ef_mips_arch); |
| 9058 | fprintf_unfiltered (file, |
| 9059 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", |
| 9060 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
| 9061 | fprintf_unfiltered (file, |
| 9062 | "mips_dump_tdep: " |
| 9063 | "mips_mask_address_p() %d (default %d)\n", |
| 9064 | mips_mask_address_p (tdep), |
| 9065 | tdep->default_mask_address_p); |
| 9066 | } |
| 9067 | fprintf_unfiltered (file, |
| 9068 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", |
| 9069 | MIPS_DEFAULT_FPU_TYPE, |
| 9070 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" |
| 9071 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" |
| 9072 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" |
| 9073 | : "???")); |
| 9074 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
| 9075 | MIPS_EABI (gdbarch)); |
| 9076 | fprintf_unfiltered (file, |
| 9077 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", |
| 9078 | MIPS_FPU_TYPE (gdbarch), |
| 9079 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" |
| 9080 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" |
| 9081 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" |
| 9082 | : "???")); |
| 9083 | } |
| 9084 | |
| 9085 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
| 9086 | |
| 9087 | void |
| 9088 | _initialize_mips_tdep (void) |
| 9089 | { |
| 9090 | static struct cmd_list_element *mipsfpulist = NULL; |
| 9091 | struct cmd_list_element *c; |
| 9092 | |
| 9093 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
| 9094 | if (MIPS_ABI_LAST + 1 |
| 9095 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) |
| 9096 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
| 9097 | |
| 9098 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
| 9099 | |
| 9100 | mips_pdr_data = register_objfile_data (); |
| 9101 | |
| 9102 | /* Create feature sets with the appropriate properties. The values |
| 9103 | are not important. */ |
| 9104 | mips_tdesc_gp32 = allocate_target_description (); |
| 9105 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); |
| 9106 | |
| 9107 | mips_tdesc_gp64 = allocate_target_description (); |
| 9108 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); |
| 9109 | |
| 9110 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
| 9111 | add_prefix_cmd ("mips", no_class, set_mips_command, |
| 9112 | _("Various MIPS specific commands."), |
| 9113 | &setmipscmdlist, "set mips ", 0, &setlist); |
| 9114 | |
| 9115 | add_prefix_cmd ("mips", no_class, show_mips_command, |
| 9116 | _("Various MIPS specific commands."), |
| 9117 | &showmipscmdlist, "show mips ", 0, &showlist); |
| 9118 | |
| 9119 | /* Allow the user to override the ABI. */ |
| 9120 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
| 9121 | &mips_abi_string, _("\ |
| 9122 | Set the MIPS ABI used by this program."), _("\ |
| 9123 | Show the MIPS ABI used by this program."), _("\ |
| 9124 | This option can be set to one of:\n\ |
| 9125 | auto - the default ABI associated with the current binary\n\ |
| 9126 | o32\n\ |
| 9127 | o64\n\ |
| 9128 | n32\n\ |
| 9129 | n64\n\ |
| 9130 | eabi32\n\ |
| 9131 | eabi64"), |
| 9132 | mips_abi_update, |
| 9133 | show_mips_abi, |
| 9134 | &setmipscmdlist, &showmipscmdlist); |
| 9135 | |
| 9136 | /* Allow the user to set the ISA to assume for compressed code if ELF |
| 9137 | file flags don't tell or there is no program file selected. This |
| 9138 | setting is updated whenever unambiguous ELF file flags are interpreted, |
| 9139 | and carried over to subsequent sessions. */ |
| 9140 | add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings, |
| 9141 | &mips_compression_string, _("\ |
| 9142 | Set the compressed ISA encoding used by MIPS code."), _("\ |
| 9143 | Show the compressed ISA encoding used by MIPS code."), _("\ |
| 9144 | Select the compressed ISA encoding used in functions that have no symbol\n\ |
| 9145 | information available. The encoding can be set to either of:\n\ |
| 9146 | mips16\n\ |
| 9147 | micromips\n\ |
| 9148 | and is updated automatically from ELF file flags if available."), |
| 9149 | mips_abi_update, |
| 9150 | show_mips_compression, |
| 9151 | &setmipscmdlist, &showmipscmdlist); |
| 9152 | |
| 9153 | /* Let the user turn off floating point and set the fence post for |
| 9154 | heuristic_proc_start. */ |
| 9155 | |
| 9156 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, |
| 9157 | _("Set use of MIPS floating-point coprocessor."), |
| 9158 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
| 9159 | add_cmd ("single", class_support, set_mipsfpu_single_command, |
| 9160 | _("Select single-precision MIPS floating-point coprocessor."), |
| 9161 | &mipsfpulist); |
| 9162 | add_cmd ("double", class_support, set_mipsfpu_double_command, |
| 9163 | _("Select double-precision MIPS floating-point coprocessor."), |
| 9164 | &mipsfpulist); |
| 9165 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); |
| 9166 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); |
| 9167 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); |
| 9168 | add_cmd ("none", class_support, set_mipsfpu_none_command, |
| 9169 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
| 9170 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
| 9171 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); |
| 9172 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); |
| 9173 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, |
| 9174 | _("Select MIPS floating-point coprocessor automatically."), |
| 9175 | &mipsfpulist); |
| 9176 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, |
| 9177 | _("Show current use of MIPS floating-point coprocessor target."), |
| 9178 | &showlist); |
| 9179 | |
| 9180 | /* We really would like to have both "0" and "unlimited" work, but |
| 9181 | command.c doesn't deal with that. So make it a var_zinteger |
| 9182 | because the user can always use "999999" or some such for unlimited. */ |
| 9183 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
| 9184 | &heuristic_fence_post, _("\ |
| 9185 | Set the distance searched for the start of a function."), _("\ |
| 9186 | Show the distance searched for the start of a function."), _("\ |
| 9187 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
| 9188 | program for the start of a function. This command sets the distance of the\n\ |
| 9189 | search. The only need to set it is when debugging a stripped executable."), |
| 9190 | reinit_frame_cache_sfunc, |
| 9191 | NULL, /* FIXME: i18n: The distance searched for |
| 9192 | the start of a function is %s. */ |
| 9193 | &setlist, &showlist); |
| 9194 | |
| 9195 | /* Allow the user to control whether the upper bits of 64-bit |
| 9196 | addresses should be zeroed. */ |
| 9197 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
| 9198 | &mask_address_var, _("\ |
| 9199 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ |
| 9200 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ |
| 9201 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
| 9202 | allow GDB to determine the correct value."), |
| 9203 | NULL, show_mask_address, |
| 9204 | &setmipscmdlist, &showmipscmdlist); |
| 9205 | |
| 9206 | /* Allow the user to control the size of 32 bit registers within the |
| 9207 | raw remote packet. */ |
| 9208 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
| 9209 | &mips64_transfers_32bit_regs_p, _("\ |
| 9210 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), |
| 9211 | _("\ |
| 9212 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), |
| 9213 | _("\ |
| 9214 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
| 9215 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ |
| 9216 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
| 9217 | set_mips64_transfers_32bit_regs, |
| 9218 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
| 9219 | MIPS target that transfers 32-bit |
| 9220 | quantities is %s. */ |
| 9221 | &setlist, &showlist); |
| 9222 | |
| 9223 | /* Debug this files internals. */ |
| 9224 | add_setshow_zuinteger_cmd ("mips", class_maintenance, |
| 9225 | &mips_debug, _("\ |
| 9226 | Set mips debugging."), _("\ |
| 9227 | Show mips debugging."), _("\ |
| 9228 | When non-zero, mips specific debugging is enabled."), |
| 9229 | NULL, |
| 9230 | NULL, /* FIXME: i18n: Mips debugging is |
| 9231 | currently %s. */ |
| 9232 | &setdebuglist, &showdebuglist); |
| 9233 | } |