| 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
| 2 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995 |
| 3 | Free Software Foundation, Inc. |
| 4 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
| 5 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. |
| 6 | |
| 7 | This file is part of GDB. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 2 of the License, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program; if not, write to the Free Software |
| 21 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
| 22 | |
| 23 | #include "defs.h" |
| 24 | #include "frame.h" |
| 25 | #include "inferior.h" |
| 26 | #include "symtab.h" |
| 27 | #include "value.h" |
| 28 | #include "gdbcmd.h" |
| 29 | #include "language.h" |
| 30 | #include "gdbcore.h" |
| 31 | #include "symfile.h" |
| 32 | #include "objfiles.h" |
| 33 | #include "gdbtypes.h" |
| 34 | |
| 35 | #include "opcode/mips.h" |
| 36 | |
| 37 | #define VM_MIN_ADDRESS (unsigned)0x400000 |
| 38 | |
| 39 | /* FIXME: Put this declaration in frame.h. */ |
| 40 | extern struct obstack frame_cache_obstack; |
| 41 | \f |
| 42 | #if 0 |
| 43 | static int mips_in_lenient_prologue PARAMS ((CORE_ADDR, CORE_ADDR)); |
| 44 | #endif |
| 45 | |
| 46 | void mips_set_processor_type_command PARAMS ((char *, int)); |
| 47 | |
| 48 | int mips_set_processor_type PARAMS ((char *)); |
| 49 | |
| 50 | static void mips_show_processor_type_command PARAMS ((char *, int)); |
| 51 | |
| 52 | static void reinit_frame_cache_sfunc PARAMS ((char *, int, |
| 53 | struct cmd_list_element *)); |
| 54 | |
| 55 | /* This value is the model of MIPS in use. It is derived from the value |
| 56 | of the PrID register. */ |
| 57 | |
| 58 | char *mips_processor_type; |
| 59 | |
| 60 | char *tmp_mips_processor_type; |
| 61 | |
| 62 | /* Some MIPS boards don't support floating point, so we permit the |
| 63 | user to turn it off. */ |
| 64 | |
| 65 | int mips_fpu = 1; |
| 66 | |
| 67 | /* A set of original names, to be used when restoring back to generic |
| 68 | registers from a specific set. */ |
| 69 | |
| 70 | char *mips_generic_reg_names[] = REGISTER_NAMES; |
| 71 | |
| 72 | /* Names of IDT R3041 registers. */ |
| 73 | |
| 74 | char *mips_r3041_reg_names[] = { |
| 75 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
| 76 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", |
| 77 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
| 78 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", |
| 79 | "sr", "lo", "hi", "bad", "cause","pc", |
| 80 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 81 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 82 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 83 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 84 | "fsr", "fir", "fp", "", |
| 85 | "", "", "bus", "ccfg", "", "", "", "", |
| 86 | "", "", "port", "cmp", "", "", "epc", "prid", |
| 87 | }; |
| 88 | |
| 89 | /* Names of IDT R3051 registers. */ |
| 90 | |
| 91 | char *mips_r3051_reg_names[] = { |
| 92 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
| 93 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", |
| 94 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
| 95 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", |
| 96 | "sr", "lo", "hi", "bad", "cause","pc", |
| 97 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 98 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 99 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 100 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 101 | "fsr", "fir", "fp", "", |
| 102 | "inx", "rand", "elo", "", "ctxt", "", "", "", |
| 103 | "", "", "ehi", "", "", "", "epc", "prid", |
| 104 | }; |
| 105 | |
| 106 | /* Names of IDT R3081 registers. */ |
| 107 | |
| 108 | char *mips_r3081_reg_names[] = { |
| 109 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
| 110 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", |
| 111 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
| 112 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", |
| 113 | "sr", "lo", "hi", "bad", "cause","pc", |
| 114 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 115 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 116 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 117 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 118 | "fsr", "fir", "fp", "", |
| 119 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", |
| 120 | "", "", "ehi", "", "", "", "epc", "prid", |
| 121 | }; |
| 122 | |
| 123 | struct { |
| 124 | char *name; |
| 125 | char **regnames; |
| 126 | } mips_processor_type_table[] = { |
| 127 | { "generic", mips_generic_reg_names }, |
| 128 | { "r3041", mips_r3041_reg_names }, |
| 129 | { "r3051", mips_r3051_reg_names }, |
| 130 | { "r3071", mips_r3081_reg_names }, |
| 131 | { "r3081", mips_r3081_reg_names }, |
| 132 | { NULL, NULL } |
| 133 | }; |
| 134 | |
| 135 | /* Heuristic_proc_start may hunt through the text section for a long |
| 136 | time across a 2400 baud serial line. Allows the user to limit this |
| 137 | search. */ |
| 138 | |
| 139 | static unsigned int heuristic_fence_post = 0; |
| 140 | |
| 141 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
| 142 | #define PROC_HIGH_ADDR(proc) ((proc)->pdr.iline) /* upper address bound */ |
| 143 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
| 144 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) |
| 145 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) |
| 146 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) |
| 147 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) |
| 148 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) |
| 149 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) |
| 150 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
| 151 | #define _PROC_MAGIC_ 0x0F0F0F0F |
| 152 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) |
| 153 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) |
| 154 | |
| 155 | struct linked_proc_info |
| 156 | { |
| 157 | struct mips_extra_func_info info; |
| 158 | struct linked_proc_info *next; |
| 159 | } *linked_proc_desc_table = NULL; |
| 160 | |
| 161 | \f |
| 162 | /* Guaranteed to set fci->saved_regs to some values (it never leaves it |
| 163 | NULL). */ |
| 164 | |
| 165 | void |
| 166 | mips_find_saved_regs (fci) |
| 167 | struct frame_info *fci; |
| 168 | { |
| 169 | int ireg; |
| 170 | CORE_ADDR reg_position; |
| 171 | /* r0 bit means kernel trap */ |
| 172 | int kernel_trap; |
| 173 | /* What registers have been saved? Bitmasks. */ |
| 174 | unsigned long gen_mask, float_mask; |
| 175 | mips_extra_func_info_t proc_desc; |
| 176 | |
| 177 | fci->saved_regs = (struct frame_saved_regs *) |
| 178 | obstack_alloc (&frame_cache_obstack, sizeof(struct frame_saved_regs)); |
| 179 | memset (fci->saved_regs, 0, sizeof (struct frame_saved_regs)); |
| 180 | |
| 181 | proc_desc = fci->proc_desc; |
| 182 | if (proc_desc == NULL) |
| 183 | /* I'm not sure how/whether this can happen. Normally when we can't |
| 184 | find a proc_desc, we "synthesize" one using heuristic_proc_desc |
| 185 | and set the saved_regs right away. */ |
| 186 | return; |
| 187 | |
| 188 | kernel_trap = PROC_REG_MASK(proc_desc) & 1; |
| 189 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK(proc_desc); |
| 190 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc); |
| 191 | |
| 192 | if (/* In any frame other than the innermost, we assume that all |
| 193 | registers have been saved. This assumes that all register |
| 194 | saves in a function happen before the first function |
| 195 | call. */ |
| 196 | fci->next == NULL |
| 197 | |
| 198 | /* In a dummy frame we know exactly where things are saved. */ |
| 199 | && !PROC_DESC_IS_DUMMY (proc_desc) |
| 200 | |
| 201 | /* Not sure exactly what kernel_trap means, but if it means |
| 202 | the kernel saves the registers without a prologue doing it, |
| 203 | we better not examine the prologue to see whether registers |
| 204 | have been saved yet. */ |
| 205 | && !kernel_trap) |
| 206 | { |
| 207 | /* We need to figure out whether the registers that the proc_desc |
| 208 | claims are saved have been saved yet. */ |
| 209 | |
| 210 | CORE_ADDR addr; |
| 211 | int status; |
| 212 | char buf[4]; |
| 213 | unsigned long inst; |
| 214 | |
| 215 | /* Bitmasks; set if we have found a save for the register. */ |
| 216 | unsigned long gen_save_found = 0; |
| 217 | unsigned long float_save_found = 0; |
| 218 | |
| 219 | for (addr = PROC_LOW_ADDR (proc_desc); |
| 220 | addr < fci->pc /*&& (gen_mask != gen_save_found |
| 221 | || float_mask != float_save_found)*/; |
| 222 | addr += 4) |
| 223 | { |
| 224 | status = read_memory_nobpt (addr, buf, 4); |
| 225 | if (status) |
| 226 | memory_error (status, addr); |
| 227 | inst = extract_unsigned_integer (buf, 4); |
| 228 | if (/* sw reg,n($sp) */ |
| 229 | (inst & 0xffe00000) == 0xafa00000 |
| 230 | |
| 231 | /* sw reg,n($r30) */ |
| 232 | || (inst & 0xffe00000) == 0xafc00000 |
| 233 | |
| 234 | /* sd reg,n($sp) */ |
| 235 | || (inst & 0xffe00000) == 0xffa00000) |
| 236 | { |
| 237 | /* It might be possible to use the instruction to |
| 238 | find the offset, rather than the code below which |
| 239 | is based on things being in a certain order in the |
| 240 | frame, but figuring out what the instruction's offset |
| 241 | is relative to might be a little tricky. */ |
| 242 | int reg = (inst & 0x001f0000) >> 16; |
| 243 | gen_save_found |= (1 << reg); |
| 244 | } |
| 245 | else if (/* swc1 freg,n($sp) */ |
| 246 | (inst & 0xffe00000) == 0xe7a00000 |
| 247 | |
| 248 | /* swc1 freg,n($r30) */ |
| 249 | || (inst & 0xffe00000) == 0xe7c00000 |
| 250 | |
| 251 | /* sdc1 freg,n($sp) */ |
| 252 | || (inst & 0xffe00000) == 0xf7a00000) |
| 253 | |
| 254 | { |
| 255 | int reg = ((inst & 0x001f0000) >> 16); |
| 256 | float_save_found |= (1 << reg); |
| 257 | } |
| 258 | } |
| 259 | gen_mask = gen_save_found; |
| 260 | float_mask = float_save_found; |
| 261 | } |
| 262 | |
| 263 | /* Fill in the offsets for the registers which gen_mask says |
| 264 | were saved. */ |
| 265 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); |
| 266 | for (ireg= 31; gen_mask; --ireg, gen_mask <<= 1) |
| 267 | if (gen_mask & 0x80000000) |
| 268 | { |
| 269 | fci->saved_regs->regs[ireg] = reg_position; |
| 270 | reg_position -= MIPS_REGSIZE; |
| 271 | } |
| 272 | /* Fill in the offsets for the registers which float_mask says |
| 273 | were saved. */ |
| 274 | reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); |
| 275 | |
| 276 | /* The freg_offset points to where the first *double* register |
| 277 | is saved. So skip to the high-order word. */ |
| 278 | reg_position += 4; |
| 279 | for (ireg = 31; float_mask; --ireg, float_mask <<= 1) |
| 280 | if (float_mask & 0x80000000) |
| 281 | { |
| 282 | fci->saved_regs->regs[FP0_REGNUM+ireg] = reg_position; |
| 283 | reg_position -= MIPS_REGSIZE; |
| 284 | } |
| 285 | |
| 286 | fci->saved_regs->regs[PC_REGNUM] = fci->saved_regs->regs[RA_REGNUM]; |
| 287 | } |
| 288 | |
| 289 | static int |
| 290 | read_next_frame_reg(fi, regno) |
| 291 | struct frame_info *fi; |
| 292 | int regno; |
| 293 | { |
| 294 | /* If it is the frame for sigtramp we have a complete sigcontext |
| 295 | somewhere above the frame and we get the saved registers from there. |
| 296 | If the stack layout for sigtramp changes we might have to change these |
| 297 | constants and the companion fixup_sigtramp in mdebugread.c */ |
| 298 | #ifndef SIGFRAME_BASE |
| 299 | /* To satisfy alignment restrictions the sigcontext is located 4 bytes |
| 300 | above the sigtramp frame. */ |
| 301 | #define SIGFRAME_BASE 4 |
| 302 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * 4) |
| 303 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * 4) |
| 304 | #endif |
| 305 | #ifndef SIGFRAME_REG_SIZE |
| 306 | #define SIGFRAME_REG_SIZE 4 |
| 307 | #endif |
| 308 | for (; fi; fi = fi->next) |
| 309 | { |
| 310 | if (fi->signal_handler_caller) |
| 311 | { |
| 312 | int offset; |
| 313 | if (regno == PC_REGNUM) offset = SIGFRAME_PC_OFF; |
| 314 | else if (regno < 32) offset = (SIGFRAME_REGSAVE_OFF |
| 315 | + regno * SIGFRAME_REG_SIZE); |
| 316 | else return 0; |
| 317 | return read_memory_integer(fi->frame + offset, MIPS_REGSIZE); |
| 318 | } |
| 319 | else if (regno == SP_REGNUM) return fi->frame; |
| 320 | else |
| 321 | { |
| 322 | if (fi->saved_regs == NULL) |
| 323 | mips_find_saved_regs (fi); |
| 324 | if (fi->saved_regs->regs[regno]) |
| 325 | return read_memory_integer(fi->saved_regs->regs[regno], MIPS_REGSIZE); |
| 326 | } |
| 327 | } |
| 328 | return read_register (regno); |
| 329 | } |
| 330 | |
| 331 | int |
| 332 | mips_frame_saved_pc(frame) |
| 333 | struct frame_info *frame; |
| 334 | { |
| 335 | mips_extra_func_info_t proc_desc = frame->proc_desc; |
| 336 | /* We have to get the saved pc from the sigcontext |
| 337 | if it is a signal handler frame. */ |
| 338 | int pcreg = frame->signal_handler_caller ? PC_REGNUM |
| 339 | : (proc_desc ? PROC_PC_REG(proc_desc) : RA_REGNUM); |
| 340 | |
| 341 | if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) |
| 342 | return read_memory_integer(frame->frame - 4, 4); |
| 343 | |
| 344 | return read_next_frame_reg(frame, pcreg); |
| 345 | } |
| 346 | |
| 347 | static struct mips_extra_func_info temp_proc_desc; |
| 348 | static struct frame_saved_regs temp_saved_regs; |
| 349 | |
| 350 | /* This fencepost looks highly suspicious to me. Removing it also |
| 351 | seems suspicious as it could affect remote debugging across serial |
| 352 | lines. */ |
| 353 | |
| 354 | static CORE_ADDR |
| 355 | heuristic_proc_start(pc) |
| 356 | CORE_ADDR pc; |
| 357 | { |
| 358 | CORE_ADDR start_pc = pc; |
| 359 | CORE_ADDR fence = start_pc - heuristic_fence_post; |
| 360 | |
| 361 | if (start_pc == 0) return 0; |
| 362 | |
| 363 | if (heuristic_fence_post == UINT_MAX |
| 364 | || fence < VM_MIN_ADDRESS) |
| 365 | fence = VM_MIN_ADDRESS; |
| 366 | |
| 367 | /* search back for previous return */ |
| 368 | for (start_pc -= 4; ; start_pc -= 4) |
| 369 | if (start_pc < fence) |
| 370 | { |
| 371 | /* It's not clear to me why we reach this point when |
| 372 | stop_soon_quietly, but with this test, at least we |
| 373 | don't print out warnings for every child forked (eg, on |
| 374 | decstation). 22apr93 rich@cygnus.com. */ |
| 375 | if (!stop_soon_quietly) |
| 376 | { |
| 377 | static int blurb_printed = 0; |
| 378 | |
| 379 | if (fence == VM_MIN_ADDRESS) |
| 380 | warning("Hit beginning of text section without finding"); |
| 381 | else |
| 382 | warning("Hit heuristic-fence-post without finding"); |
| 383 | |
| 384 | warning("enclosing function for address 0x%x", pc); |
| 385 | if (!blurb_printed) |
| 386 | { |
| 387 | printf_filtered ("\ |
| 388 | This warning occurs if you are debugging a function without any symbols\n\ |
| 389 | (for example, in a stripped executable). In that case, you may wish to\n\ |
| 390 | increase the size of the search with the `set heuristic-fence-post' command.\n\ |
| 391 | \n\ |
| 392 | Otherwise, you told GDB there was a function where there isn't one, or\n\ |
| 393 | (more likely) you have encountered a bug in GDB.\n"); |
| 394 | blurb_printed = 1; |
| 395 | } |
| 396 | } |
| 397 | |
| 398 | return 0; |
| 399 | } |
| 400 | else if (ABOUT_TO_RETURN(start_pc)) |
| 401 | break; |
| 402 | |
| 403 | start_pc += 8; /* skip return, and its delay slot */ |
| 404 | #if 0 |
| 405 | /* skip nops (usually 1) 0 - is this */ |
| 406 | while (start_pc < pc && read_memory_integer (start_pc, 4) == 0) |
| 407 | start_pc += 4; |
| 408 | #endif |
| 409 | return start_pc; |
| 410 | } |
| 411 | |
| 412 | static mips_extra_func_info_t |
| 413 | heuristic_proc_desc(start_pc, limit_pc, next_frame) |
| 414 | CORE_ADDR start_pc, limit_pc; |
| 415 | struct frame_info *next_frame; |
| 416 | { |
| 417 | CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM); |
| 418 | CORE_ADDR cur_pc; |
| 419 | int frame_size; |
| 420 | int has_frame_reg = 0; |
| 421 | int reg30 = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
| 422 | unsigned long reg_mask = 0; |
| 423 | |
| 424 | if (start_pc == 0) return NULL; |
| 425 | memset (&temp_proc_desc, '\0', sizeof(temp_proc_desc)); |
| 426 | memset (&temp_saved_regs, '\0', sizeof(struct frame_saved_regs)); |
| 427 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
| 428 | |
| 429 | if (start_pc + 200 < limit_pc) |
| 430 | limit_pc = start_pc + 200; |
| 431 | restart: |
| 432 | frame_size = 0; |
| 433 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += 4) { |
| 434 | char buf[4]; |
| 435 | unsigned long word; |
| 436 | int status; |
| 437 | |
| 438 | status = read_memory_nobpt (cur_pc, buf, 4); |
| 439 | if (status) memory_error (status, cur_pc); |
| 440 | word = extract_unsigned_integer (buf, 4); |
| 441 | |
| 442 | if ((word & 0xFFFF0000) == 0x27bd0000) /* addiu $sp,$sp,-i */ |
| 443 | frame_size += (-word) & 0xFFFF; |
| 444 | else if ((word & 0xFFFF0000) == 0x23bd0000) /* addu $sp,$sp,-i */ |
| 445 | frame_size += (-word) & 0xFFFF; |
| 446 | else if ((word & 0xFFE00000) == 0xafa00000) { /* sw reg,offset($sp) */ |
| 447 | int reg = (word & 0x001F0000) >> 16; |
| 448 | reg_mask |= 1 << reg; |
| 449 | temp_saved_regs.regs[reg] = sp + (word & 0xffff); |
| 450 | } |
| 451 | else if ((word & 0xFFFF0000) == 0x27be0000) { /* addiu $30,$sp,size */ |
| 452 | if ((word & 0xffff) != frame_size) |
| 453 | reg30 = sp + (word & 0xffff); |
| 454 | else if (!has_frame_reg) { |
| 455 | int alloca_adjust; |
| 456 | has_frame_reg = 1; |
| 457 | reg30 = read_next_frame_reg(next_frame, 30); |
| 458 | alloca_adjust = reg30 - (sp + (word & 0xffff)); |
| 459 | if (alloca_adjust > 0) { |
| 460 | /* FP > SP + frame_size. This may be because |
| 461 | * of an alloca or somethings similar. |
| 462 | * Fix sp to "pre-alloca" value, and try again. |
| 463 | */ |
| 464 | sp += alloca_adjust; |
| 465 | goto restart; |
| 466 | } |
| 467 | } |
| 468 | } |
| 469 | else if ((word & 0xFFE00000) == 0xafc00000) { /* sw reg,offset($30) */ |
| 470 | int reg = (word & 0x001F0000) >> 16; |
| 471 | reg_mask |= 1 << reg; |
| 472 | temp_saved_regs.regs[reg] = reg30 + (word & 0xffff); |
| 473 | } |
| 474 | } |
| 475 | if (has_frame_reg) { |
| 476 | PROC_FRAME_REG(&temp_proc_desc) = 30; |
| 477 | PROC_FRAME_OFFSET(&temp_proc_desc) = 0; |
| 478 | } |
| 479 | else { |
| 480 | PROC_FRAME_REG(&temp_proc_desc) = SP_REGNUM; |
| 481 | PROC_FRAME_OFFSET(&temp_proc_desc) = frame_size; |
| 482 | } |
| 483 | PROC_REG_MASK(&temp_proc_desc) = reg_mask; |
| 484 | PROC_PC_REG(&temp_proc_desc) = RA_REGNUM; |
| 485 | return &temp_proc_desc; |
| 486 | } |
| 487 | |
| 488 | static mips_extra_func_info_t |
| 489 | find_proc_desc (pc, next_frame) |
| 490 | CORE_ADDR pc; |
| 491 | struct frame_info *next_frame; |
| 492 | { |
| 493 | mips_extra_func_info_t proc_desc; |
| 494 | struct block *b = block_for_pc(pc); |
| 495 | struct symbol *sym; |
| 496 | CORE_ADDR startaddr; |
| 497 | |
| 498 | find_pc_partial_function (pc, NULL, &startaddr, NULL); |
| 499 | if (b == NULL) |
| 500 | sym = NULL; |
| 501 | else |
| 502 | { |
| 503 | if (startaddr > BLOCK_START (b)) |
| 504 | /* This is the "pathological" case referred to in a comment in |
| 505 | print_frame_info. It might be better to move this check into |
| 506 | symbol reading. */ |
| 507 | sym = NULL; |
| 508 | else |
| 509 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, |
| 510 | 0, NULL); |
| 511 | } |
| 512 | |
| 513 | if (sym) |
| 514 | { |
| 515 | /* IF this is the topmost frame AND |
| 516 | * (this proc does not have debugging information OR |
| 517 | * the PC is in the procedure prologue) |
| 518 | * THEN create a "heuristic" proc_desc (by analyzing |
| 519 | * the actual code) to replace the "official" proc_desc. |
| 520 | */ |
| 521 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); |
| 522 | if (next_frame == NULL) { |
| 523 | struct symtab_and_line val; |
| 524 | struct symbol *proc_symbol = |
| 525 | PROC_DESC_IS_DUMMY(proc_desc) ? 0 : PROC_SYMBOL(proc_desc); |
| 526 | |
| 527 | if (proc_symbol) { |
| 528 | val = find_pc_line (BLOCK_START |
| 529 | (SYMBOL_BLOCK_VALUE(proc_symbol)), |
| 530 | 0); |
| 531 | val.pc = val.end ? val.end : pc; |
| 532 | } |
| 533 | if (!proc_symbol || pc < val.pc) { |
| 534 | mips_extra_func_info_t found_heuristic = |
| 535 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
| 536 | pc, next_frame); |
| 537 | if (found_heuristic) |
| 538 | proc_desc = found_heuristic; |
| 539 | } |
| 540 | } |
| 541 | } |
| 542 | else |
| 543 | { |
| 544 | /* Is linked_proc_desc_table really necessary? It only seems to be used |
| 545 | by procedure call dummys. However, the procedures being called ought |
| 546 | to have their own proc_descs, and even if they don't, |
| 547 | heuristic_proc_desc knows how to create them! */ |
| 548 | |
| 549 | register struct linked_proc_info *link; |
| 550 | |
| 551 | for (link = linked_proc_desc_table; link; link = link->next) |
| 552 | if (PROC_LOW_ADDR(&link->info) <= pc |
| 553 | && PROC_HIGH_ADDR(&link->info) > pc) |
| 554 | return &link->info; |
| 555 | |
| 556 | if (startaddr == 0) |
| 557 | startaddr = heuristic_proc_start (pc); |
| 558 | |
| 559 | proc_desc = |
| 560 | heuristic_proc_desc (startaddr, pc, next_frame); |
| 561 | } |
| 562 | return proc_desc; |
| 563 | } |
| 564 | |
| 565 | mips_extra_func_info_t cached_proc_desc; |
| 566 | |
| 567 | CORE_ADDR |
| 568 | mips_frame_chain(frame) |
| 569 | struct frame_info *frame; |
| 570 | { |
| 571 | mips_extra_func_info_t proc_desc; |
| 572 | CORE_ADDR saved_pc = FRAME_SAVED_PC(frame); |
| 573 | |
| 574 | if (saved_pc == 0 || inside_entry_file (saved_pc)) |
| 575 | return 0; |
| 576 | |
| 577 | proc_desc = find_proc_desc(saved_pc, frame); |
| 578 | if (!proc_desc) |
| 579 | return 0; |
| 580 | |
| 581 | cached_proc_desc = proc_desc; |
| 582 | |
| 583 | /* If no frame pointer and frame size is zero, we must be at end |
| 584 | of stack (or otherwise hosed). If we don't check frame size, |
| 585 | we loop forever if we see a zero size frame. */ |
| 586 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
| 587 | && PROC_FRAME_OFFSET (proc_desc) == 0 |
| 588 | /* The previous frame from a sigtramp frame might be frameless |
| 589 | and have frame size zero. */ |
| 590 | && !frame->signal_handler_caller) |
| 591 | return 0; |
| 592 | else |
| 593 | return read_next_frame_reg(frame, PROC_FRAME_REG(proc_desc)) |
| 594 | + PROC_FRAME_OFFSET(proc_desc); |
| 595 | } |
| 596 | |
| 597 | void |
| 598 | init_extra_frame_info(fci) |
| 599 | struct frame_info *fci; |
| 600 | { |
| 601 | /* Use proc_desc calculated in frame_chain */ |
| 602 | mips_extra_func_info_t proc_desc = |
| 603 | fci->next ? cached_proc_desc : find_proc_desc(fci->pc, fci->next); |
| 604 | |
| 605 | fci->saved_regs = NULL; |
| 606 | fci->proc_desc = |
| 607 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
| 608 | if (proc_desc) |
| 609 | { |
| 610 | /* Fixup frame-pointer - only needed for top frame */ |
| 611 | /* This may not be quite right, if proc has a real frame register. |
| 612 | Get the value of the frame relative sp, procedure might have been |
| 613 | interrupted by a signal at it's very start. */ |
| 614 | if (fci->pc == PROC_LOW_ADDR (proc_desc) |
| 615 | && !PROC_DESC_IS_DUMMY (proc_desc)) |
| 616 | fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); |
| 617 | else |
| 618 | fci->frame = |
| 619 | read_next_frame_reg (fci->next, PROC_FRAME_REG (proc_desc)) |
| 620 | + PROC_FRAME_OFFSET (proc_desc); |
| 621 | |
| 622 | if (proc_desc == &temp_proc_desc) |
| 623 | { |
| 624 | fci->saved_regs = (struct frame_saved_regs*) |
| 625 | obstack_alloc (&frame_cache_obstack, |
| 626 | sizeof (struct frame_saved_regs)); |
| 627 | *fci->saved_regs = temp_saved_regs; |
| 628 | fci->saved_regs->regs[PC_REGNUM] = fci->saved_regs->regs[RA_REGNUM]; |
| 629 | } |
| 630 | |
| 631 | /* hack: if argument regs are saved, guess these contain args */ |
| 632 | if ((PROC_REG_MASK(proc_desc) & 0xF0) == 0) fci->num_args = -1; |
| 633 | else if ((PROC_REG_MASK(proc_desc) & 0x80) == 0) fci->num_args = 4; |
| 634 | else if ((PROC_REG_MASK(proc_desc) & 0x40) == 0) fci->num_args = 3; |
| 635 | else if ((PROC_REG_MASK(proc_desc) & 0x20) == 0) fci->num_args = 2; |
| 636 | else if ((PROC_REG_MASK(proc_desc) & 0x10) == 0) fci->num_args = 1; |
| 637 | } |
| 638 | } |
| 639 | |
| 640 | /* MIPS stack frames are almost impenetrable. When execution stops, |
| 641 | we basically have to look at symbol information for the function |
| 642 | that we stopped in, which tells us *which* register (if any) is |
| 643 | the base of the frame pointer, and what offset from that register |
| 644 | the frame itself is at. |
| 645 | |
| 646 | This presents a problem when trying to examine a stack in memory |
| 647 | (that isn't executing at the moment), using the "frame" command. We |
| 648 | don't have a PC, nor do we have any registers except SP. |
| 649 | |
| 650 | This routine takes two arguments, SP and PC, and tries to make the |
| 651 | cached frames look as if these two arguments defined a frame on the |
| 652 | cache. This allows the rest of info frame to extract the important |
| 653 | arguments without difficulty. */ |
| 654 | |
| 655 | struct frame_info * |
| 656 | setup_arbitrary_frame (argc, argv) |
| 657 | int argc; |
| 658 | CORE_ADDR *argv; |
| 659 | { |
| 660 | if (argc != 2) |
| 661 | error ("MIPS frame specifications require two arguments: sp and pc"); |
| 662 | |
| 663 | return create_new_frame (argv[0], argv[1]); |
| 664 | } |
| 665 | |
| 666 | |
| 667 | CORE_ADDR |
| 668 | mips_push_arguments(nargs, args, sp, struct_return, struct_addr) |
| 669 | int nargs; |
| 670 | value_ptr *args; |
| 671 | CORE_ADDR sp; |
| 672 | int struct_return; |
| 673 | CORE_ADDR struct_addr; |
| 674 | { |
| 675 | register i; |
| 676 | int accumulate_size = struct_return ? MIPS_REGSIZE : 0; |
| 677 | struct mips_arg { char *contents; int len; int offset; }; |
| 678 | struct mips_arg *mips_args = |
| 679 | (struct mips_arg*)alloca((nargs + 4) * sizeof(struct mips_arg)); |
| 680 | register struct mips_arg *m_arg; |
| 681 | int fake_args = 0; |
| 682 | |
| 683 | for (i = 0, m_arg = mips_args; i < nargs; i++, m_arg++) { |
| 684 | value_ptr arg = value_arg_coerce (args[i]); |
| 685 | m_arg->len = TYPE_LENGTH (VALUE_TYPE (arg)); |
| 686 | /* This entire mips-specific routine is because doubles must be aligned |
| 687 | * on 8-byte boundaries. It still isn't quite right, because MIPS decided |
| 688 | * to align 'struct {int a, b}' on 4-byte boundaries (even though this |
| 689 | * breaks their varargs implementation...). A correct solution |
| 690 | * requires an simulation of gcc's 'alignof' (and use of 'alignof' |
| 691 | * in stdarg.h/varargs.h). |
| 692 | * On the 64 bit r4000 we always pass the first four arguments |
| 693 | * using eight bytes each, so that we can load them up correctly |
| 694 | * in CALL_DUMMY. |
| 695 | */ |
| 696 | if (m_arg->len > 4) |
| 697 | accumulate_size = (accumulate_size + 7) & -8; |
| 698 | m_arg->offset = accumulate_size; |
| 699 | m_arg->contents = VALUE_CONTENTS(arg); |
| 700 | if (! GDB_TARGET_IS_MIPS64) |
| 701 | accumulate_size = (accumulate_size + m_arg->len + 3) & -4; |
| 702 | else |
| 703 | { |
| 704 | if (accumulate_size >= 4 * MIPS_REGSIZE) |
| 705 | accumulate_size = (accumulate_size + m_arg->len + 3) &~ 4; |
| 706 | else |
| 707 | { |
| 708 | static char zeroes[8] = { 0 }; |
| 709 | int len = m_arg->len; |
| 710 | |
| 711 | if (len < 8) |
| 712 | { |
| 713 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
| 714 | m_arg->offset += 8 - len; |
| 715 | ++m_arg; |
| 716 | m_arg->len = 8 - len; |
| 717 | m_arg->contents = zeroes; |
| 718 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
| 719 | m_arg->offset = accumulate_size; |
| 720 | else |
| 721 | m_arg->offset = accumulate_size + len; |
| 722 | ++fake_args; |
| 723 | } |
| 724 | accumulate_size = (accumulate_size + len + 7) & ~8; |
| 725 | } |
| 726 | } |
| 727 | } |
| 728 | accumulate_size = (accumulate_size + 7) & (-8); |
| 729 | if (accumulate_size < 4 * MIPS_REGSIZE) |
| 730 | accumulate_size = 4 * MIPS_REGSIZE; |
| 731 | sp -= accumulate_size; |
| 732 | for (i = nargs + fake_args; m_arg--, --i >= 0; ) |
| 733 | write_memory(sp + m_arg->offset, m_arg->contents, m_arg->len); |
| 734 | if (struct_return) |
| 735 | { |
| 736 | char buf[TARGET_PTR_BIT / HOST_CHAR_BIT]; |
| 737 | |
| 738 | store_address (buf, sizeof buf, struct_addr); |
| 739 | write_memory (sp, buf, sizeof buf); |
| 740 | } |
| 741 | return sp; |
| 742 | } |
| 743 | |
| 744 | /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<31. */ |
| 745 | #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) |
| 746 | |
| 747 | void |
| 748 | mips_push_dummy_frame() |
| 749 | { |
| 750 | char buffer[MAX_REGISTER_RAW_SIZE]; |
| 751 | int ireg; |
| 752 | struct linked_proc_info *link = (struct linked_proc_info*) |
| 753 | xmalloc(sizeof(struct linked_proc_info)); |
| 754 | mips_extra_func_info_t proc_desc = &link->info; |
| 755 | CORE_ADDR sp = read_register (SP_REGNUM); |
| 756 | CORE_ADDR save_address; |
| 757 | link->next = linked_proc_desc_table; |
| 758 | linked_proc_desc_table = link; |
| 759 | #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ |
| 760 | #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<31) |
| 761 | #define GEN_REG_SAVE_COUNT 22 |
| 762 | #define FLOAT_REG_SAVE_MASK MASK(0,19) |
| 763 | #define FLOAT_REG_SAVE_COUNT 20 |
| 764 | #define SPECIAL_REG_SAVE_COUNT 4 |
| 765 | /* |
| 766 | * The registers we must save are all those not preserved across |
| 767 | * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. |
| 768 | * In addition, we must save the PC, and PUSH_FP_REGNUM. |
| 769 | * (Ideally, we should also save MDLO/-HI and FP Control/Status reg.) |
| 770 | * |
| 771 | * Dummy frame layout: |
| 772 | * (high memory) |
| 773 | * Saved PC |
| 774 | * Saved MMHI, MMLO, FPC_CSR |
| 775 | * Saved R31 |
| 776 | * Saved R28 |
| 777 | * ... |
| 778 | * Saved R1 |
| 779 | * Saved D18 (i.e. F19, F18) |
| 780 | * ... |
| 781 | * Saved D0 (i.e. F1, F0) |
| 782 | * CALL_DUMMY (subroutine stub; see tm-mips.h) |
| 783 | * Parameter build area (not yet implemented) |
| 784 | * (low memory) |
| 785 | */ |
| 786 | PROC_REG_MASK(proc_desc) = GEN_REG_SAVE_MASK; |
| 787 | PROC_FREG_MASK(proc_desc) = mips_fpu ? FLOAT_REG_SAVE_MASK : 0; |
| 788 | PROC_REG_OFFSET(proc_desc) = /* offset of (Saved R31) from FP */ |
| 789 | -sizeof(long) - 4 * SPECIAL_REG_SAVE_COUNT; |
| 790 | PROC_FREG_OFFSET(proc_desc) = /* offset of (Saved D18) from FP */ |
| 791 | -sizeof(double) - 4 * (SPECIAL_REG_SAVE_COUNT + GEN_REG_SAVE_COUNT); |
| 792 | /* save general registers */ |
| 793 | save_address = sp + PROC_REG_OFFSET(proc_desc); |
| 794 | for (ireg = 32; --ireg >= 0; ) |
| 795 | if (PROC_REG_MASK(proc_desc) & (1 << ireg)) |
| 796 | { |
| 797 | read_register_gen (ireg, buffer); |
| 798 | |
| 799 | /* Need to fix the save_address decrement below, and also make sure |
| 800 | that we don't run into problems with the size of the dummy frame |
| 801 | or any of the offsets within it. */ |
| 802 | if (REGISTER_RAW_SIZE (ireg) > 4) |
| 803 | error ("Cannot call functions on mips64"); |
| 804 | |
| 805 | write_memory (save_address, buffer, REGISTER_RAW_SIZE (ireg)); |
| 806 | save_address -= 4; |
| 807 | } |
| 808 | /* save floating-points registers starting with high order word */ |
| 809 | save_address = sp + PROC_FREG_OFFSET(proc_desc) + 4; |
| 810 | for (ireg = 32; --ireg >= 0; ) |
| 811 | if (PROC_FREG_MASK(proc_desc) & (1 << ireg)) |
| 812 | { |
| 813 | read_register_gen (ireg + FP0_REGNUM, buffer); |
| 814 | |
| 815 | if (REGISTER_RAW_SIZE (ireg + FP0_REGNUM) > 4) |
| 816 | error ("Cannot call functions on mips64"); |
| 817 | |
| 818 | write_memory (save_address, buffer, |
| 819 | REGISTER_RAW_SIZE (ireg + FP0_REGNUM)); |
| 820 | save_address -= 4; |
| 821 | } |
| 822 | write_register (PUSH_FP_REGNUM, sp); |
| 823 | PROC_FRAME_REG(proc_desc) = PUSH_FP_REGNUM; |
| 824 | PROC_FRAME_OFFSET(proc_desc) = 0; |
| 825 | read_register_gen (PC_REGNUM, buffer); |
| 826 | write_memory (sp - 4, buffer, REGISTER_RAW_SIZE (PC_REGNUM)); |
| 827 | read_register_gen (HI_REGNUM, buffer); |
| 828 | write_memory (sp - 8, buffer, REGISTER_RAW_SIZE (HI_REGNUM)); |
| 829 | read_register_gen (LO_REGNUM, buffer); |
| 830 | write_memory (sp - 12, buffer, REGISTER_RAW_SIZE (LO_REGNUM)); |
| 831 | if (mips_fpu) |
| 832 | read_register_gen (FCRCS_REGNUM, buffer); |
| 833 | else |
| 834 | memset (buffer, 0, REGISTER_RAW_SIZE (FCRCS_REGNUM)); |
| 835 | write_memory (sp - 16, buffer, REGISTER_RAW_SIZE (FCRCS_REGNUM)); |
| 836 | sp -= 4 * (GEN_REG_SAVE_COUNT |
| 837 | + (mips_fpu ? FLOAT_REG_SAVE_COUNT : 0) |
| 838 | + SPECIAL_REG_SAVE_COUNT); |
| 839 | write_register (SP_REGNUM, sp); |
| 840 | PROC_LOW_ADDR(proc_desc) = sp - CALL_DUMMY_SIZE + CALL_DUMMY_START_OFFSET; |
| 841 | PROC_HIGH_ADDR(proc_desc) = sp; |
| 842 | SET_PROC_DESC_IS_DUMMY(proc_desc); |
| 843 | PROC_PC_REG(proc_desc) = RA_REGNUM; |
| 844 | } |
| 845 | |
| 846 | void |
| 847 | mips_pop_frame() |
| 848 | { |
| 849 | register int regnum; |
| 850 | struct frame_info *frame = get_current_frame (); |
| 851 | CORE_ADDR new_sp = FRAME_FP (frame); |
| 852 | |
| 853 | mips_extra_func_info_t proc_desc = frame->proc_desc; |
| 854 | |
| 855 | write_register (PC_REGNUM, FRAME_SAVED_PC(frame)); |
| 856 | if (frame->saved_regs == NULL) |
| 857 | mips_find_saved_regs (frame); |
| 858 | if (proc_desc) |
| 859 | { |
| 860 | for (regnum = 32; --regnum >= 0; ) |
| 861 | if (PROC_REG_MASK(proc_desc) & (1 << regnum)) |
| 862 | write_register (regnum, |
| 863 | read_memory_integer (frame->saved_regs->regs[regnum], |
| 864 | 4)); |
| 865 | for (regnum = 32; --regnum >= 0; ) |
| 866 | if (PROC_FREG_MASK(proc_desc) & (1 << regnum)) |
| 867 | write_register (regnum + FP0_REGNUM, |
| 868 | read_memory_integer (frame->saved_regs->regs[regnum + FP0_REGNUM], 4)); |
| 869 | } |
| 870 | write_register (SP_REGNUM, new_sp); |
| 871 | flush_cached_frames (); |
| 872 | |
| 873 | if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) |
| 874 | { |
| 875 | struct linked_proc_info *pi_ptr, *prev_ptr; |
| 876 | |
| 877 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; |
| 878 | pi_ptr != NULL; |
| 879 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) |
| 880 | { |
| 881 | if (&pi_ptr->info == proc_desc) |
| 882 | break; |
| 883 | } |
| 884 | |
| 885 | if (pi_ptr == NULL) |
| 886 | error ("Can't locate dummy extra frame info\n"); |
| 887 | |
| 888 | if (prev_ptr != NULL) |
| 889 | prev_ptr->next = pi_ptr->next; |
| 890 | else |
| 891 | linked_proc_desc_table = pi_ptr->next; |
| 892 | |
| 893 | free (pi_ptr); |
| 894 | |
| 895 | write_register (HI_REGNUM, read_memory_integer(new_sp - 8, 4)); |
| 896 | write_register (LO_REGNUM, read_memory_integer(new_sp - 12, 4)); |
| 897 | if (mips_fpu) |
| 898 | write_register (FCRCS_REGNUM, read_memory_integer(new_sp - 16, 4)); |
| 899 | } |
| 900 | } |
| 901 | |
| 902 | static void |
| 903 | mips_print_register (regnum, all) |
| 904 | int regnum, all; |
| 905 | { |
| 906 | unsigned char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
| 907 | struct type *our_type = |
| 908 | init_type (TYPE_CODE_INT, |
| 909 | /* We will fill in the length for each register. */ |
| 910 | 0, |
| 911 | TYPE_FLAG_UNSIGNED, |
| 912 | NULL, |
| 913 | NULL); |
| 914 | |
| 915 | /* Get the data in raw format. */ |
| 916 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) |
| 917 | { |
| 918 | printf_filtered ("%s: [Invalid]", reg_names[regnum]); |
| 919 | return; |
| 920 | } |
| 921 | |
| 922 | /* If an even floating pointer register, also print as double. */ |
| 923 | if (regnum >= FP0_REGNUM && regnum < FP0_REGNUM+32 |
| 924 | && !((regnum-FP0_REGNUM) & 1)) { |
| 925 | char dbuffer[MAX_REGISTER_RAW_SIZE]; |
| 926 | |
| 927 | read_relative_register_raw_bytes (regnum, dbuffer); |
| 928 | read_relative_register_raw_bytes (regnum+1, dbuffer+4); |
| 929 | #ifdef REGISTER_CONVERT_TO_TYPE |
| 930 | REGISTER_CONVERT_TO_TYPE(regnum, builtin_type_double, dbuffer); |
| 931 | #endif |
| 932 | printf_filtered ("(d%d: ", regnum-FP0_REGNUM); |
| 933 | val_print (builtin_type_double, dbuffer, 0, |
| 934 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
| 935 | printf_filtered ("); "); |
| 936 | } |
| 937 | fputs_filtered (reg_names[regnum], gdb_stdout); |
| 938 | |
| 939 | /* The problem with printing numeric register names (r26, etc.) is that |
| 940 | the user can't use them on input. Probably the best solution is to |
| 941 | fix it so that either the numeric or the funky (a2, etc.) names |
| 942 | are accepted on input. */ |
| 943 | if (regnum < 32) |
| 944 | printf_filtered ("(r%d): ", regnum); |
| 945 | else |
| 946 | printf_filtered (": "); |
| 947 | |
| 948 | /* If virtual format is floating, print it that way. */ |
| 949 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
| 950 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, |
| 951 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
| 952 | /* Else print as integer in hex. */ |
| 953 | else |
| 954 | print_scalar_formatted (raw_buffer, REGISTER_VIRTUAL_TYPE (regnum), |
| 955 | 'x', 0, gdb_stdout); |
| 956 | } |
| 957 | |
| 958 | /* Replacement for generic do_registers_info. */ |
| 959 | |
| 960 | void |
| 961 | mips_do_registers_info (regnum, fpregs) |
| 962 | int regnum; |
| 963 | int fpregs; |
| 964 | { |
| 965 | if (regnum != -1) |
| 966 | { |
| 967 | if (*(reg_names[regnum]) == '\0') |
| 968 | error ("Not a valid register for the current processor type"); |
| 969 | |
| 970 | mips_print_register (regnum, 0); |
| 971 | printf_filtered ("\n"); |
| 972 | } |
| 973 | else |
| 974 | { |
| 975 | int did_newline; |
| 976 | |
| 977 | for (regnum = 0; regnum < NUM_REGS; ) |
| 978 | { |
| 979 | if (((!fpregs) && regnum >= FP0_REGNUM && regnum <= FCRIR_REGNUM) |
| 980 | || *(reg_names[regnum]) == '\0') |
| 981 | { |
| 982 | regnum++; |
| 983 | continue; |
| 984 | } |
| 985 | mips_print_register (regnum, 1); |
| 986 | regnum++; |
| 987 | printf_filtered ("; "); |
| 988 | did_newline = 0; |
| 989 | if ((regnum & 3) == 0) |
| 990 | { |
| 991 | printf_filtered ("\n"); |
| 992 | did_newline = 1; |
| 993 | } |
| 994 | } |
| 995 | if (!did_newline) |
| 996 | printf_filtered ("\n"); |
| 997 | } |
| 998 | } |
| 999 | |
| 1000 | /* Return number of args passed to a frame. described by FIP. |
| 1001 | Can return -1, meaning no way to tell. */ |
| 1002 | |
| 1003 | int |
| 1004 | mips_frame_num_args (frame) |
| 1005 | struct frame_info *frame; |
| 1006 | { |
| 1007 | #if 0 /* FIXME Use or lose this! */ |
| 1008 | struct chain_info_t *p; |
| 1009 | |
| 1010 | p = mips_find_cached_frame (FRAME_FP (frame)); |
| 1011 | if (p->valid) |
| 1012 | return p->the_info.numargs; |
| 1013 | #endif |
| 1014 | return -1; |
| 1015 | } |
| 1016 | \f |
| 1017 | /* Is this a branch with a delay slot? */ |
| 1018 | |
| 1019 | static int is_delayed PARAMS ((unsigned long)); |
| 1020 | |
| 1021 | static int |
| 1022 | is_delayed (insn) |
| 1023 | unsigned long insn; |
| 1024 | { |
| 1025 | int i; |
| 1026 | for (i = 0; i < NUMOPCODES; ++i) |
| 1027 | if (mips_opcodes[i].pinfo != INSN_MACRO |
| 1028 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) |
| 1029 | break; |
| 1030 | return (i < NUMOPCODES |
| 1031 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY |
| 1032 | | INSN_COND_BRANCH_DELAY |
| 1033 | | INSN_COND_BRANCH_LIKELY))); |
| 1034 | } |
| 1035 | |
| 1036 | int |
| 1037 | mips_step_skips_delay (pc) |
| 1038 | CORE_ADDR pc; |
| 1039 | { |
| 1040 | char buf[4]; |
| 1041 | |
| 1042 | if (target_read_memory (pc, buf, 4) != 0) |
| 1043 | /* If error reading memory, guess that it is not a delayed branch. */ |
| 1044 | return 0; |
| 1045 | return is_delayed (extract_unsigned_integer (buf, 4)); |
| 1046 | } |
| 1047 | |
| 1048 | /* To skip prologues, I use this predicate. Returns either PC itself |
| 1049 | if the code at PC does not look like a function prologue; otherwise |
| 1050 | returns an address that (if we're lucky) follows the prologue. If |
| 1051 | LENIENT, then we must skip everything which is involved in setting |
| 1052 | up the frame (it's OK to skip more, just so long as we don't skip |
| 1053 | anything which might clobber the registers which are being saved. |
| 1054 | We must skip more in the case where part of the prologue is in the |
| 1055 | delay slot of a non-prologue instruction). */ |
| 1056 | |
| 1057 | CORE_ADDR |
| 1058 | mips_skip_prologue (pc, lenient) |
| 1059 | CORE_ADDR pc; |
| 1060 | int lenient; |
| 1061 | { |
| 1062 | unsigned long inst; |
| 1063 | int offset; |
| 1064 | int seen_sp_adjust = 0; |
| 1065 | int load_immediate_bytes = 0; |
| 1066 | |
| 1067 | /* Skip the typical prologue instructions. These are the stack adjustment |
| 1068 | instruction and the instructions that save registers on the stack |
| 1069 | or in the gcc frame. */ |
| 1070 | for (offset = 0; offset < 100; offset += 4) |
| 1071 | { |
| 1072 | char buf[4]; |
| 1073 | int status; |
| 1074 | |
| 1075 | status = read_memory_nobpt (pc + offset, buf, 4); |
| 1076 | if (status) |
| 1077 | memory_error (status, pc + offset); |
| 1078 | inst = extract_unsigned_integer (buf, 4); |
| 1079 | |
| 1080 | #if 0 |
| 1081 | if (lenient && is_delayed (inst)) |
| 1082 | continue; |
| 1083 | #endif |
| 1084 | |
| 1085 | if ((inst & 0xffff0000) == 0x27bd0000) /* addiu $sp,$sp,offset */ |
| 1086 | seen_sp_adjust = 1; |
| 1087 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ |
| 1088 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ |
| 1089 | seen_sp_adjust = 1; |
| 1090 | else if ((inst & 0xFFE00000) == 0xAFA00000 && (inst & 0x001F0000)) |
| 1091 | continue; /* sw reg,n($sp) */ |
| 1092 | /* reg != $zero */ |
| 1093 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ |
| 1094 | continue; |
| 1095 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) |
| 1096 | /* sx reg,n($s8) */ |
| 1097 | continue; /* reg != $zero */ |
| 1098 | |
| 1099 | /* move $s8,$sp. With different versions of gas this will be either |
| 1100 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero'. Accept either. */ |
| 1101 | else if (inst == 0x03A0F021 || inst == 0x03a0f025) |
| 1102 | continue; |
| 1103 | |
| 1104 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ |
| 1105 | continue; |
| 1106 | else if ((inst & 0xffff0000) == 0x3c1c0000) /* lui $gp,n */ |
| 1107 | continue; |
| 1108 | else if ((inst & 0xffff0000) == 0x279c0000) /* addiu $gp,$gp,n */ |
| 1109 | continue; |
| 1110 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ |
| 1111 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ |
| 1112 | continue; |
| 1113 | /* The following instructions load $at or $t0 with an immediate |
| 1114 | value in preparation for a stack adjustment via |
| 1115 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize |
| 1116 | a local variable, so we accept them only before a stack adjustment |
| 1117 | instruction was seen. */ |
| 1118 | else if (!seen_sp_adjust) |
| 1119 | { |
| 1120 | if ((inst & 0xffff0000) == 0x3c010000 || /* lui $at,n */ |
| 1121 | (inst & 0xffff0000) == 0x3c080000) /* lui $t0,n */ |
| 1122 | { |
| 1123 | load_immediate_bytes += 4; |
| 1124 | continue; |
| 1125 | } |
| 1126 | else if ((inst & 0xffff0000) == 0x34210000 || /* ori $at,$at,n */ |
| 1127 | (inst & 0xffff0000) == 0x35080000 || /* ori $t0,$t0,n */ |
| 1128 | (inst & 0xffff0000) == 0x34010000 || /* ori $at,$zero,n */ |
| 1129 | (inst & 0xffff0000) == 0x34080000) /* ori $t0,$zero,n */ |
| 1130 | { |
| 1131 | load_immediate_bytes += 4; |
| 1132 | continue; |
| 1133 | } |
| 1134 | else |
| 1135 | break; |
| 1136 | } |
| 1137 | else |
| 1138 | break; |
| 1139 | } |
| 1140 | |
| 1141 | /* In a frameless function, we might have incorrectly |
| 1142 | skipped some load immediate instructions. Undo the skipping |
| 1143 | if the load immediate was not followed by a stack adjustment. */ |
| 1144 | if (load_immediate_bytes && !seen_sp_adjust) |
| 1145 | offset -= load_immediate_bytes; |
| 1146 | return pc + offset; |
| 1147 | } |
| 1148 | |
| 1149 | #if 0 |
| 1150 | /* The lenient prologue stuff should be superceded by the code in |
| 1151 | init_extra_frame_info which looks to see whether the stores mentioned |
| 1152 | in the proc_desc have actually taken place. */ |
| 1153 | |
| 1154 | /* Is address PC in the prologue (loosely defined) for function at |
| 1155 | STARTADDR? */ |
| 1156 | |
| 1157 | static int |
| 1158 | mips_in_lenient_prologue (startaddr, pc) |
| 1159 | CORE_ADDR startaddr; |
| 1160 | CORE_ADDR pc; |
| 1161 | { |
| 1162 | CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1); |
| 1163 | return pc >= startaddr && pc < end_prologue; |
| 1164 | } |
| 1165 | #endif |
| 1166 | |
| 1167 | /* Given a return value in `regbuf' with a type `valtype', |
| 1168 | extract and copy its value into `valbuf'. */ |
| 1169 | void |
| 1170 | mips_extract_return_value (valtype, regbuf, valbuf) |
| 1171 | struct type *valtype; |
| 1172 | char regbuf[REGISTER_BYTES]; |
| 1173 | char *valbuf; |
| 1174 | { |
| 1175 | int regnum; |
| 1176 | |
| 1177 | regnum = TYPE_CODE (valtype) == TYPE_CODE_FLT && mips_fpu ? FP0_REGNUM : 2; |
| 1178 | |
| 1179 | memcpy (valbuf, regbuf + REGISTER_BYTE (regnum), TYPE_LENGTH (valtype)); |
| 1180 | #ifdef REGISTER_CONVERT_TO_TYPE |
| 1181 | REGISTER_CONVERT_TO_TYPE(regnum, valtype, valbuf); |
| 1182 | #endif |
| 1183 | } |
| 1184 | |
| 1185 | /* Given a return value in `regbuf' with a type `valtype', |
| 1186 | write it's value into the appropriate register. */ |
| 1187 | void |
| 1188 | mips_store_return_value (valtype, valbuf) |
| 1189 | struct type *valtype; |
| 1190 | char *valbuf; |
| 1191 | { |
| 1192 | int regnum; |
| 1193 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
| 1194 | |
| 1195 | regnum = TYPE_CODE (valtype) == TYPE_CODE_FLT && mips_fpu ? FP0_REGNUM : 2; |
| 1196 | memcpy(raw_buffer, valbuf, TYPE_LENGTH (valtype)); |
| 1197 | |
| 1198 | #ifdef REGISTER_CONVERT_FROM_TYPE |
| 1199 | REGISTER_CONVERT_FROM_TYPE(regnum, valtype, raw_buffer); |
| 1200 | #endif |
| 1201 | |
| 1202 | write_register_bytes(REGISTER_BYTE (regnum), raw_buffer, TYPE_LENGTH (valtype)); |
| 1203 | } |
| 1204 | |
| 1205 | /* These exist in mdebugread.c. */ |
| 1206 | extern CORE_ADDR sigtramp_address, sigtramp_end; |
| 1207 | extern void fixup_sigtramp PARAMS ((void)); |
| 1208 | |
| 1209 | /* Exported procedure: Is PC in the signal trampoline code */ |
| 1210 | |
| 1211 | int |
| 1212 | in_sigtramp (pc, ignore) |
| 1213 | CORE_ADDR pc; |
| 1214 | char *ignore; /* function name */ |
| 1215 | { |
| 1216 | if (sigtramp_address == 0) |
| 1217 | fixup_sigtramp (); |
| 1218 | return (pc >= sigtramp_address && pc < sigtramp_end); |
| 1219 | } |
| 1220 | |
| 1221 | /* Command to set the processor type. */ |
| 1222 | |
| 1223 | void |
| 1224 | mips_set_processor_type_command (args, from_tty) |
| 1225 | char *args; |
| 1226 | int from_tty; |
| 1227 | { |
| 1228 | int i; |
| 1229 | |
| 1230 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') |
| 1231 | { |
| 1232 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); |
| 1233 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) |
| 1234 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); |
| 1235 | |
| 1236 | /* Restore the value. */ |
| 1237 | tmp_mips_processor_type = strsave (mips_processor_type); |
| 1238 | |
| 1239 | return; |
| 1240 | } |
| 1241 | |
| 1242 | if (!mips_set_processor_type (tmp_mips_processor_type)) |
| 1243 | { |
| 1244 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); |
| 1245 | /* Restore its value. */ |
| 1246 | tmp_mips_processor_type = strsave (mips_processor_type); |
| 1247 | } |
| 1248 | } |
| 1249 | |
| 1250 | static void |
| 1251 | mips_show_processor_type_command (args, from_tty) |
| 1252 | char *args; |
| 1253 | int from_tty; |
| 1254 | { |
| 1255 | } |
| 1256 | |
| 1257 | /* Modify the actual processor type. */ |
| 1258 | |
| 1259 | int |
| 1260 | mips_set_processor_type (str) |
| 1261 | char *str; |
| 1262 | { |
| 1263 | int i, j; |
| 1264 | |
| 1265 | if (str == NULL) |
| 1266 | return 0; |
| 1267 | |
| 1268 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) |
| 1269 | { |
| 1270 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) |
| 1271 | { |
| 1272 | mips_processor_type = str; |
| 1273 | |
| 1274 | for (j = 0; j < NUM_REGS; ++j) |
| 1275 | reg_names[j] = mips_processor_type_table[i].regnames[j]; |
| 1276 | |
| 1277 | return 1; |
| 1278 | |
| 1279 | /* FIXME tweak fpu flag too */ |
| 1280 | } |
| 1281 | } |
| 1282 | |
| 1283 | return 0; |
| 1284 | } |
| 1285 | |
| 1286 | /* Attempt to identify the particular processor model by reading the |
| 1287 | processor id. */ |
| 1288 | |
| 1289 | char * |
| 1290 | mips_read_processor_type () |
| 1291 | { |
| 1292 | int prid; |
| 1293 | |
| 1294 | prid = read_register (PRID_REGNUM); |
| 1295 | |
| 1296 | if (prid & ~0xf == 0x700) |
| 1297 | return savestring ("r3041", strlen("r3041")); |
| 1298 | |
| 1299 | return NULL; |
| 1300 | } |
| 1301 | |
| 1302 | /* Just like reinit_frame_cache, but with the right arguments to be |
| 1303 | callable as an sfunc. */ |
| 1304 | |
| 1305 | static void |
| 1306 | reinit_frame_cache_sfunc (args, from_tty, c) |
| 1307 | char *args; |
| 1308 | int from_tty; |
| 1309 | struct cmd_list_element *c; |
| 1310 | { |
| 1311 | reinit_frame_cache (); |
| 1312 | } |
| 1313 | |
| 1314 | int |
| 1315 | gdb_print_insn_mips (memaddr, info) |
| 1316 | bfd_vma memaddr; |
| 1317 | disassemble_info *info; |
| 1318 | { |
| 1319 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
| 1320 | return print_insn_big_mips (memaddr, info); |
| 1321 | else |
| 1322 | return print_insn_little_mips (memaddr, info); |
| 1323 | } |
| 1324 | |
| 1325 | void |
| 1326 | _initialize_mips_tdep () |
| 1327 | { |
| 1328 | struct cmd_list_element *c; |
| 1329 | |
| 1330 | tm_print_insn = gdb_print_insn_mips; |
| 1331 | |
| 1332 | /* Let the user turn off floating point and set the fence post for |
| 1333 | heuristic_proc_start. */ |
| 1334 | |
| 1335 | add_show_from_set |
| 1336 | (add_set_cmd ("mipsfpu", class_support, var_boolean, |
| 1337 | (char *) &mips_fpu, |
| 1338 | "Set use of floating point coprocessor.\n\ |
| 1339 | Turn off to avoid using floating point instructions when calling functions\n\ |
| 1340 | or dealing with return values.", &setlist), |
| 1341 | &showlist); |
| 1342 | |
| 1343 | c = add_set_cmd ("processor", class_support, var_string_noescape, |
| 1344 | (char *) &tmp_mips_processor_type, |
| 1345 | "Set the type of MIPS processor in use.\n\ |
| 1346 | Set this to be able to access processor-type-specific registers.\n\ |
| 1347 | ", |
| 1348 | &setlist); |
| 1349 | c->function.cfunc = mips_set_processor_type_command; |
| 1350 | c = add_show_from_set (c, &showlist); |
| 1351 | c->function.cfunc = mips_show_processor_type_command; |
| 1352 | |
| 1353 | tmp_mips_processor_type = strsave (DEFAULT_MIPS_TYPE); |
| 1354 | mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE), 0); |
| 1355 | |
| 1356 | /* We really would like to have both "0" and "unlimited" work, but |
| 1357 | command.c doesn't deal with that. So make it a var_zinteger |
| 1358 | because the user can always use "999999" or some such for unlimited. */ |
| 1359 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, |
| 1360 | (char *) &heuristic_fence_post, |
| 1361 | "\ |
| 1362 | Set the distance searched for the start of a function.\n\ |
| 1363 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
| 1364 | program for the start of a function. This command sets the distance of the\n\ |
| 1365 | search. The only need to set it is when debugging a stripped executable.", |
| 1366 | &setlist); |
| 1367 | /* We need to throw away the frame cache when we set this, since it |
| 1368 | might change our ability to get backtraces. */ |
| 1369 | c->function.sfunc = reinit_frame_cache_sfunc; |
| 1370 | add_show_from_set (c, &showlist); |
| 1371 | } |