| 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
| 2 | |
| 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
| 4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
| 5 | 2010, 2011 Free Software Foundation, Inc. |
| 6 | |
| 7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
| 8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. |
| 9 | |
| 10 | This file is part of GDB. |
| 11 | |
| 12 | This program is free software; you can redistribute it and/or modify |
| 13 | it under the terms of the GNU General Public License as published by |
| 14 | the Free Software Foundation; either version 3 of the License, or |
| 15 | (at your option) any later version. |
| 16 | |
| 17 | This program is distributed in the hope that it will be useful, |
| 18 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | GNU General Public License for more details. |
| 21 | |
| 22 | You should have received a copy of the GNU General Public License |
| 23 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 24 | |
| 25 | #include "defs.h" |
| 26 | #include "gdb_string.h" |
| 27 | #include "gdb_assert.h" |
| 28 | #include "frame.h" |
| 29 | #include "inferior.h" |
| 30 | #include "symtab.h" |
| 31 | #include "value.h" |
| 32 | #include "gdbcmd.h" |
| 33 | #include "language.h" |
| 34 | #include "gdbcore.h" |
| 35 | #include "symfile.h" |
| 36 | #include "objfiles.h" |
| 37 | #include "gdbtypes.h" |
| 38 | #include "target.h" |
| 39 | #include "arch-utils.h" |
| 40 | #include "regcache.h" |
| 41 | #include "osabi.h" |
| 42 | #include "mips-tdep.h" |
| 43 | #include "block.h" |
| 44 | #include "reggroups.h" |
| 45 | #include "opcode/mips.h" |
| 46 | #include "elf/mips.h" |
| 47 | #include "elf-bfd.h" |
| 48 | #include "symcat.h" |
| 49 | #include "sim-regno.h" |
| 50 | #include "dis-asm.h" |
| 51 | #include "frame-unwind.h" |
| 52 | #include "frame-base.h" |
| 53 | #include "trad-frame.h" |
| 54 | #include "infcall.h" |
| 55 | #include "floatformat.h" |
| 56 | #include "remote.h" |
| 57 | #include "target-descriptions.h" |
| 58 | #include "dwarf2-frame.h" |
| 59 | #include "user-regs.h" |
| 60 | #include "valprint.h" |
| 61 | #include "ax.h" |
| 62 | |
| 63 | static const struct objfile_data *mips_pdr_data; |
| 64 | |
| 65 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
| 66 | |
| 67 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
| 68 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
| 69 | #define ST0_FR (1 << 26) |
| 70 | |
| 71 | /* The sizes of floating point registers. */ |
| 72 | |
| 73 | enum |
| 74 | { |
| 75 | MIPS_FPU_SINGLE_REGSIZE = 4, |
| 76 | MIPS_FPU_DOUBLE_REGSIZE = 8 |
| 77 | }; |
| 78 | |
| 79 | enum |
| 80 | { |
| 81 | MIPS32_REGSIZE = 4, |
| 82 | MIPS64_REGSIZE = 8 |
| 83 | }; |
| 84 | |
| 85 | static const char *mips_abi_string; |
| 86 | |
| 87 | static const char *mips_abi_strings[] = { |
| 88 | "auto", |
| 89 | "n32", |
| 90 | "o32", |
| 91 | "n64", |
| 92 | "o64", |
| 93 | "eabi32", |
| 94 | "eabi64", |
| 95 | NULL |
| 96 | }; |
| 97 | |
| 98 | /* The standard register names, and all the valid aliases for them. */ |
| 99 | struct register_alias |
| 100 | { |
| 101 | const char *name; |
| 102 | int regnum; |
| 103 | }; |
| 104 | |
| 105 | /* Aliases for o32 and most other ABIs. */ |
| 106 | const struct register_alias mips_o32_aliases[] = { |
| 107 | { "ta0", 12 }, |
| 108 | { "ta1", 13 }, |
| 109 | { "ta2", 14 }, |
| 110 | { "ta3", 15 } |
| 111 | }; |
| 112 | |
| 113 | /* Aliases for n32 and n64. */ |
| 114 | const struct register_alias mips_n32_n64_aliases[] = { |
| 115 | { "ta0", 8 }, |
| 116 | { "ta1", 9 }, |
| 117 | { "ta2", 10 }, |
| 118 | { "ta3", 11 } |
| 119 | }; |
| 120 | |
| 121 | /* Aliases for ABI-independent registers. */ |
| 122 | const struct register_alias mips_register_aliases[] = { |
| 123 | /* The architecture manuals specify these ABI-independent names for |
| 124 | the GPRs. */ |
| 125 | #define R(n) { "r" #n, n } |
| 126 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), |
| 127 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), |
| 128 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), |
| 129 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), |
| 130 | #undef R |
| 131 | |
| 132 | /* k0 and k1 are sometimes called these instead (for "kernel |
| 133 | temp"). */ |
| 134 | { "kt0", 26 }, |
| 135 | { "kt1", 27 }, |
| 136 | |
| 137 | /* This is the traditional GDB name for the CP0 status register. */ |
| 138 | { "sr", MIPS_PS_REGNUM }, |
| 139 | |
| 140 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ |
| 141 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, |
| 142 | |
| 143 | /* This is the traditional GDB name for the FCSR. */ |
| 144 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } |
| 145 | }; |
| 146 | |
| 147 | const struct register_alias mips_numeric_register_aliases[] = { |
| 148 | #define R(n) { #n, n } |
| 149 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), |
| 150 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), |
| 151 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), |
| 152 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), |
| 153 | #undef R |
| 154 | }; |
| 155 | |
| 156 | #ifndef MIPS_DEFAULT_FPU_TYPE |
| 157 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE |
| 158 | #endif |
| 159 | static int mips_fpu_type_auto = 1; |
| 160 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; |
| 161 | |
| 162 | static int mips_debug = 0; |
| 163 | |
| 164 | /* Properties (for struct target_desc) describing the g/G packet |
| 165 | layout. */ |
| 166 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" |
| 167 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" |
| 168 | |
| 169 | struct target_desc *mips_tdesc_gp32; |
| 170 | struct target_desc *mips_tdesc_gp64; |
| 171 | |
| 172 | const struct mips_regnum * |
| 173 | mips_regnum (struct gdbarch *gdbarch) |
| 174 | { |
| 175 | return gdbarch_tdep (gdbarch)->regnum; |
| 176 | } |
| 177 | |
| 178 | static int |
| 179 | mips_fpa0_regnum (struct gdbarch *gdbarch) |
| 180 | { |
| 181 | return mips_regnum (gdbarch)->fp0 + 12; |
| 182 | } |
| 183 | |
| 184 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
| 185 | == MIPS_ABI_EABI32 \ |
| 186 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) |
| 187 | |
| 188 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ |
| 189 | (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) |
| 190 | |
| 191 | #define MIPS_LAST_ARG_REGNUM(gdbarch) \ |
| 192 | (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) |
| 193 | |
| 194 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
| 195 | |
| 196 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
| 197 | functions to test, set, or clear bit 0 of addresses. */ |
| 198 | |
| 199 | static CORE_ADDR |
| 200 | is_mips16_addr (CORE_ADDR addr) |
| 201 | { |
| 202 | return ((addr) & 1); |
| 203 | } |
| 204 | |
| 205 | static CORE_ADDR |
| 206 | unmake_mips16_addr (CORE_ADDR addr) |
| 207 | { |
| 208 | return ((addr) & ~(CORE_ADDR) 1); |
| 209 | } |
| 210 | |
| 211 | static CORE_ADDR |
| 212 | make_mips16_addr (CORE_ADDR addr) |
| 213 | { |
| 214 | return ((addr) | (CORE_ADDR) 1); |
| 215 | } |
| 216 | |
| 217 | /* Return the MIPS ABI associated with GDBARCH. */ |
| 218 | enum mips_abi |
| 219 | mips_abi (struct gdbarch *gdbarch) |
| 220 | { |
| 221 | return gdbarch_tdep (gdbarch)->mips_abi; |
| 222 | } |
| 223 | |
| 224 | int |
| 225 | mips_isa_regsize (struct gdbarch *gdbarch) |
| 226 | { |
| 227 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 228 | |
| 229 | /* If we know how big the registers are, use that size. */ |
| 230 | if (tdep->register_size_valid_p) |
| 231 | return tdep->register_size; |
| 232 | |
| 233 | /* Fall back to the previous behavior. */ |
| 234 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
| 235 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); |
| 236 | } |
| 237 | |
| 238 | /* Return the currently configured (or set) saved register size. */ |
| 239 | |
| 240 | unsigned int |
| 241 | mips_abi_regsize (struct gdbarch *gdbarch) |
| 242 | { |
| 243 | switch (mips_abi (gdbarch)) |
| 244 | { |
| 245 | case MIPS_ABI_EABI32: |
| 246 | case MIPS_ABI_O32: |
| 247 | return 4; |
| 248 | case MIPS_ABI_N32: |
| 249 | case MIPS_ABI_N64: |
| 250 | case MIPS_ABI_O64: |
| 251 | case MIPS_ABI_EABI64: |
| 252 | return 8; |
| 253 | case MIPS_ABI_UNKNOWN: |
| 254 | case MIPS_ABI_LAST: |
| 255 | default: |
| 256 | internal_error (__FILE__, __LINE__, _("bad switch")); |
| 257 | } |
| 258 | } |
| 259 | |
| 260 | /* Functions for setting and testing a bit in a minimal symbol that |
| 261 | marks it as 16-bit function. The MSB of the minimal symbol's |
| 262 | "info" field is used for this purpose. |
| 263 | |
| 264 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
| 265 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
| 266 | minimal symbol to mark it as a 16-bit function |
| 267 | |
| 268 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
| 269 | |
| 270 | static void |
| 271 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
| 272 | { |
| 273 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) |
| 274 | { |
| 275 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
| 276 | } |
| 277 | } |
| 278 | |
| 279 | static int |
| 280 | msymbol_is_special (struct minimal_symbol *msym) |
| 281 | { |
| 282 | return MSYMBOL_TARGET_FLAG_1 (msym); |
| 283 | } |
| 284 | |
| 285 | /* XFER a value from the big/little/left end of the register. |
| 286 | Depending on the size of the value it might occupy the entire |
| 287 | register or just part of it. Make an allowance for this, aligning |
| 288 | things accordingly. */ |
| 289 | |
| 290 | static void |
| 291 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
| 292 | int reg_num, int length, |
| 293 | enum bfd_endian endian, gdb_byte *in, |
| 294 | const gdb_byte *out, int buf_offset) |
| 295 | { |
| 296 | int reg_offset = 0; |
| 297 | |
| 298 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); |
| 299 | /* Need to transfer the left or right part of the register, based on |
| 300 | the targets byte order. */ |
| 301 | switch (endian) |
| 302 | { |
| 303 | case BFD_ENDIAN_BIG: |
| 304 | reg_offset = register_size (gdbarch, reg_num) - length; |
| 305 | break; |
| 306 | case BFD_ENDIAN_LITTLE: |
| 307 | reg_offset = 0; |
| 308 | break; |
| 309 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
| 310 | reg_offset = 0; |
| 311 | break; |
| 312 | default: |
| 313 | internal_error (__FILE__, __LINE__, _("bad switch")); |
| 314 | } |
| 315 | if (mips_debug) |
| 316 | fprintf_unfiltered (gdb_stderr, |
| 317 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", |
| 318 | reg_num, reg_offset, buf_offset, length); |
| 319 | if (mips_debug && out != NULL) |
| 320 | { |
| 321 | int i; |
| 322 | fprintf_unfiltered (gdb_stdlog, "out "); |
| 323 | for (i = 0; i < length; i++) |
| 324 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
| 325 | } |
| 326 | if (in != NULL) |
| 327 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
| 328 | in + buf_offset); |
| 329 | if (out != NULL) |
| 330 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
| 331 | out + buf_offset); |
| 332 | if (mips_debug && in != NULL) |
| 333 | { |
| 334 | int i; |
| 335 | fprintf_unfiltered (gdb_stdlog, "in "); |
| 336 | for (i = 0; i < length; i++) |
| 337 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
| 338 | } |
| 339 | if (mips_debug) |
| 340 | fprintf_unfiltered (gdb_stdlog, "\n"); |
| 341 | } |
| 342 | |
| 343 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
| 344 | compatiblity mode. A return value of 1 means that we have |
| 345 | physical 64-bit registers, but should treat them as 32-bit registers. */ |
| 346 | |
| 347 | static int |
| 348 | mips2_fp_compat (struct frame_info *frame) |
| 349 | { |
| 350 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 351 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
| 352 | meaningful. */ |
| 353 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
| 354 | return 0; |
| 355 | |
| 356 | #if 0 |
| 357 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, |
| 358 | in all the places we deal with FP registers. PR gdb/413. */ |
| 359 | /* Otherwise check the FR bit in the status register - it controls |
| 360 | the FP compatiblity mode. If it is clear we are in compatibility |
| 361 | mode. */ |
| 362 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
| 363 | return 1; |
| 364 | #endif |
| 365 | |
| 366 | return 0; |
| 367 | } |
| 368 | |
| 369 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
| 370 | |
| 371 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
| 372 | |
| 373 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
| 374 | |
| 375 | /* The list of available "set mips " and "show mips " commands. */ |
| 376 | |
| 377 | static struct cmd_list_element *setmipscmdlist = NULL; |
| 378 | static struct cmd_list_element *showmipscmdlist = NULL; |
| 379 | |
| 380 | /* Integer registers 0 thru 31 are handled explicitly by |
| 381 | mips_register_name(). Processor specific registers 32 and above |
| 382 | are listed in the following tables. */ |
| 383 | |
| 384 | enum |
| 385 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; |
| 386 | |
| 387 | /* Generic MIPS. */ |
| 388 | |
| 389 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
| 390 | "sr", "lo", "hi", "bad", "cause", "pc", |
| 391 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 392 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 393 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 394 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 395 | "fsr", "fir", "" /*"fp" */ , "", |
| 396 | "", "", "", "", "", "", "", "", |
| 397 | "", "", "", "", "", "", "", "", |
| 398 | }; |
| 399 | |
| 400 | /* Names of IDT R3041 registers. */ |
| 401 | |
| 402 | static const char *mips_r3041_reg_names[] = { |
| 403 | "sr", "lo", "hi", "bad", "cause", "pc", |
| 404 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 405 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 406 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 407 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 408 | "fsr", "fir", "", /*"fp" */ "", |
| 409 | "", "", "bus", "ccfg", "", "", "", "", |
| 410 | "", "", "port", "cmp", "", "", "epc", "prid", |
| 411 | }; |
| 412 | |
| 413 | /* Names of tx39 registers. */ |
| 414 | |
| 415 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
| 416 | "sr", "lo", "hi", "bad", "cause", "pc", |
| 417 | "", "", "", "", "", "", "", "", |
| 418 | "", "", "", "", "", "", "", "", |
| 419 | "", "", "", "", "", "", "", "", |
| 420 | "", "", "", "", "", "", "", "", |
| 421 | "", "", "", "", |
| 422 | "", "", "", "", "", "", "", "", |
| 423 | "", "", "config", "cache", "debug", "depc", "epc", "" |
| 424 | }; |
| 425 | |
| 426 | /* Names of IRIX registers. */ |
| 427 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
| 428 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 429 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 430 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 431 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 432 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" |
| 433 | }; |
| 434 | |
| 435 | |
| 436 | /* Return the name of the register corresponding to REGNO. */ |
| 437 | static const char * |
| 438 | mips_register_name (struct gdbarch *gdbarch, int regno) |
| 439 | { |
| 440 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 441 | /* GPR names for all ABIs other than n32/n64. */ |
| 442 | static char *mips_gpr_names[] = { |
| 443 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
| 444 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", |
| 445 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
| 446 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", |
| 447 | }; |
| 448 | |
| 449 | /* GPR names for n32 and n64 ABIs. */ |
| 450 | static char *mips_n32_n64_gpr_names[] = { |
| 451 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
| 452 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", |
| 453 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
| 454 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" |
| 455 | }; |
| 456 | |
| 457 | enum mips_abi abi = mips_abi (gdbarch); |
| 458 | |
| 459 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
| 460 | but then don't make the raw register names visible. This (upper) |
| 461 | range of user visible register numbers are the pseudo-registers. |
| 462 | |
| 463 | This approach was adopted accommodate the following scenario: |
| 464 | It is possible to debug a 64-bit device using a 32-bit |
| 465 | programming model. In such instances, the raw registers are |
| 466 | configured to be 64-bits wide, while the pseudo registers are |
| 467 | configured to be 32-bits wide. The registers that the user |
| 468 | sees - the pseudo registers - match the users expectations |
| 469 | given the programming model being used. */ |
| 470 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
| 471 | if (regno < gdbarch_num_regs (gdbarch)) |
| 472 | return ""; |
| 473 | |
| 474 | /* The MIPS integer registers are always mapped from 0 to 31. The |
| 475 | names of the registers (which reflects the conventions regarding |
| 476 | register use) vary depending on the ABI. */ |
| 477 | if (0 <= rawnum && rawnum < 32) |
| 478 | { |
| 479 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) |
| 480 | return mips_n32_n64_gpr_names[rawnum]; |
| 481 | else |
| 482 | return mips_gpr_names[rawnum]; |
| 483 | } |
| 484 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
| 485 | return tdesc_register_name (gdbarch, rawnum); |
| 486 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) |
| 487 | { |
| 488 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); |
| 489 | return tdep->mips_processor_reg_names[rawnum - 32]; |
| 490 | } |
| 491 | else |
| 492 | internal_error (__FILE__, __LINE__, |
| 493 | _("mips_register_name: bad register number %d"), rawnum); |
| 494 | } |
| 495 | |
| 496 | /* Return the groups that a MIPS register can be categorised into. */ |
| 497 | |
| 498 | static int |
| 499 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
| 500 | struct reggroup *reggroup) |
| 501 | { |
| 502 | int vector_p; |
| 503 | int float_p; |
| 504 | int raw_p; |
| 505 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
| 506 | int pseudo = regnum / gdbarch_num_regs (gdbarch); |
| 507 | if (reggroup == all_reggroup) |
| 508 | return pseudo; |
| 509 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); |
| 510 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; |
| 511 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs |
| 512 | (gdbarch), as not all architectures are multi-arch. */ |
| 513 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
| 514 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
| 515 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') |
| 516 | return 0; |
| 517 | if (reggroup == float_reggroup) |
| 518 | return float_p && pseudo; |
| 519 | if (reggroup == vector_reggroup) |
| 520 | return vector_p && pseudo; |
| 521 | if (reggroup == general_reggroup) |
| 522 | return (!vector_p && !float_p) && pseudo; |
| 523 | /* Save the pseudo registers. Need to make certain that any code |
| 524 | extracting register values from a saved register cache also uses |
| 525 | pseudo registers. */ |
| 526 | if (reggroup == save_reggroup) |
| 527 | return raw_p && pseudo; |
| 528 | /* Restore the same pseudo register. */ |
| 529 | if (reggroup == restore_reggroup) |
| 530 | return raw_p && pseudo; |
| 531 | return 0; |
| 532 | } |
| 533 | |
| 534 | /* Return the groups that a MIPS register can be categorised into. |
| 535 | This version is only used if we have a target description which |
| 536 | describes real registers (and their groups). */ |
| 537 | |
| 538 | static int |
| 539 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
| 540 | struct reggroup *reggroup) |
| 541 | { |
| 542 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
| 543 | int pseudo = regnum / gdbarch_num_regs (gdbarch); |
| 544 | int ret; |
| 545 | |
| 546 | /* Only save, restore, and display the pseudo registers. Need to |
| 547 | make certain that any code extracting register values from a |
| 548 | saved register cache also uses pseudo registers. |
| 549 | |
| 550 | Note: saving and restoring the pseudo registers is slightly |
| 551 | strange; if we have 64 bits, we should save and restore all |
| 552 | 64 bits. But this is hard and has little benefit. */ |
| 553 | if (!pseudo) |
| 554 | return 0; |
| 555 | |
| 556 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); |
| 557 | if (ret != -1) |
| 558 | return ret; |
| 559 | |
| 560 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); |
| 561 | } |
| 562 | |
| 563 | /* Map the symbol table registers which live in the range [1 * |
| 564 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
| 565 | registers. Take care of alignment and size problems. */ |
| 566 | |
| 567 | static void |
| 568 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
| 569 | int cookednum, gdb_byte *buf) |
| 570 | { |
| 571 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
| 572 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) |
| 573 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); |
| 574 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
| 575 | regcache_raw_read (regcache, rawnum, buf); |
| 576 | else if (register_size (gdbarch, rawnum) > |
| 577 | register_size (gdbarch, cookednum)) |
| 578 | { |
| 579 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
| 580 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
| 581 | else |
| 582 | { |
| 583 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 584 | LONGEST regval; |
| 585 | regcache_raw_read_signed (regcache, rawnum, ®val); |
| 586 | store_signed_integer (buf, 4, byte_order, regval); |
| 587 | } |
| 588 | } |
| 589 | else |
| 590 | internal_error (__FILE__, __LINE__, _("bad register size")); |
| 591 | } |
| 592 | |
| 593 | static void |
| 594 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
| 595 | struct regcache *regcache, int cookednum, |
| 596 | const gdb_byte *buf) |
| 597 | { |
| 598 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
| 599 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) |
| 600 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); |
| 601 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
| 602 | regcache_raw_write (regcache, rawnum, buf); |
| 603 | else if (register_size (gdbarch, rawnum) > |
| 604 | register_size (gdbarch, cookednum)) |
| 605 | { |
| 606 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
| 607 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
| 608 | else |
| 609 | { |
| 610 | /* Sign extend the shortened version of the register prior |
| 611 | to placing it in the raw register. This is required for |
| 612 | some mips64 parts in order to avoid unpredictable behavior. */ |
| 613 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 614 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); |
| 615 | regcache_raw_write_signed (regcache, rawnum, regval); |
| 616 | } |
| 617 | } |
| 618 | else |
| 619 | internal_error (__FILE__, __LINE__, _("bad register size")); |
| 620 | } |
| 621 | |
| 622 | static int |
| 623 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, |
| 624 | struct agent_expr *ax, int reg) |
| 625 | { |
| 626 | int rawnum = reg % gdbarch_num_regs (gdbarch); |
| 627 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) |
| 628 | && reg < 2 * gdbarch_num_regs (gdbarch)); |
| 629 | |
| 630 | ax_reg_mask (ax, rawnum); |
| 631 | |
| 632 | return 0; |
| 633 | } |
| 634 | |
| 635 | static int |
| 636 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, |
| 637 | struct agent_expr *ax, int reg) |
| 638 | { |
| 639 | int rawnum = reg % gdbarch_num_regs (gdbarch); |
| 640 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) |
| 641 | && reg < 2 * gdbarch_num_regs (gdbarch)); |
| 642 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) |
| 643 | { |
| 644 | ax_reg (ax, rawnum); |
| 645 | |
| 646 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) |
| 647 | { |
| 648 | if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p |
| 649 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) |
| 650 | { |
| 651 | ax_const_l (ax, 32); |
| 652 | ax_simple (ax, aop_lsh); |
| 653 | } |
| 654 | ax_const_l (ax, 32); |
| 655 | ax_simple (ax, aop_rsh_signed); |
| 656 | } |
| 657 | } |
| 658 | else |
| 659 | internal_error (__FILE__, __LINE__, _("bad register size")); |
| 660 | |
| 661 | return 0; |
| 662 | } |
| 663 | |
| 664 | /* Table to translate MIPS16 register field to actual register number. */ |
| 665 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
| 666 | |
| 667 | /* Heuristic_proc_start may hunt through the text section for a long |
| 668 | time across a 2400 baud serial line. Allows the user to limit this |
| 669 | search. */ |
| 670 | |
| 671 | static unsigned int heuristic_fence_post = 0; |
| 672 | |
| 673 | /* Number of bytes of storage in the actual machine representation for |
| 674 | register N. NOTE: This defines the pseudo register type so need to |
| 675 | rebuild the architecture vector. */ |
| 676 | |
| 677 | static int mips64_transfers_32bit_regs_p = 0; |
| 678 | |
| 679 | static void |
| 680 | set_mips64_transfers_32bit_regs (char *args, int from_tty, |
| 681 | struct cmd_list_element *c) |
| 682 | { |
| 683 | struct gdbarch_info info; |
| 684 | gdbarch_info_init (&info); |
| 685 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
| 686 | instead of relying on globals. Doing that would let generic code |
| 687 | handle the search for this specific architecture. */ |
| 688 | if (!gdbarch_update_p (info)) |
| 689 | { |
| 690 | mips64_transfers_32bit_regs_p = 0; |
| 691 | error (_("32-bit compatibility mode not supported")); |
| 692 | } |
| 693 | } |
| 694 | |
| 695 | /* Convert to/from a register and the corresponding memory value. */ |
| 696 | |
| 697 | /* This predicate tests for the case of an 8 byte floating point |
| 698 | value that is being transferred to or from a pair of floating point |
| 699 | registers each of which are (or are considered to be) only 4 bytes |
| 700 | wide. */ |
| 701 | static int |
| 702 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
| 703 | struct type *type) |
| 704 | { |
| 705 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
| 706 | && register_size (gdbarch, regnum) == 4 |
| 707 | && (regnum % gdbarch_num_regs (gdbarch)) |
| 708 | >= mips_regnum (gdbarch)->fp0 |
| 709 | && (regnum % gdbarch_num_regs (gdbarch)) |
| 710 | < mips_regnum (gdbarch)->fp0 + 32 |
| 711 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
| 712 | } |
| 713 | |
| 714 | /* This predicate tests for the case of a value of less than 8 |
| 715 | bytes in width that is being transfered to or from an 8 byte |
| 716 | general purpose register. */ |
| 717 | static int |
| 718 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, |
| 719 | struct type *type) |
| 720 | { |
| 721 | int num_regs = gdbarch_num_regs (gdbarch); |
| 722 | |
| 723 | return (register_size (gdbarch, regnum) == 8 |
| 724 | && regnum % num_regs > 0 && regnum % num_regs < 32 |
| 725 | && TYPE_LENGTH (type) < 8); |
| 726 | } |
| 727 | |
| 728 | static int |
| 729 | mips_convert_register_p (struct gdbarch *gdbarch, |
| 730 | int regnum, struct type *type) |
| 731 | { |
| 732 | return mips_convert_register_float_case_p (gdbarch, regnum, type) |
| 733 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type); |
| 734 | } |
| 735 | |
| 736 | static void |
| 737 | mips_register_to_value (struct frame_info *frame, int regnum, |
| 738 | struct type *type, gdb_byte *to) |
| 739 | { |
| 740 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 741 | |
| 742 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) |
| 743 | { |
| 744 | get_frame_register (frame, regnum + 0, to + 4); |
| 745 | get_frame_register (frame, regnum + 1, to + 0); |
| 746 | } |
| 747 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) |
| 748 | { |
| 749 | int len = TYPE_LENGTH (type); |
| 750 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 751 | get_frame_register_bytes (frame, regnum, 8 - len, len, to); |
| 752 | else |
| 753 | get_frame_register_bytes (frame, regnum, 0, len, to); |
| 754 | } |
| 755 | else |
| 756 | { |
| 757 | internal_error (__FILE__, __LINE__, |
| 758 | _("mips_register_to_value: unrecognized case")); |
| 759 | } |
| 760 | } |
| 761 | |
| 762 | static void |
| 763 | mips_value_to_register (struct frame_info *frame, int regnum, |
| 764 | struct type *type, const gdb_byte *from) |
| 765 | { |
| 766 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 767 | |
| 768 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) |
| 769 | { |
| 770 | put_frame_register (frame, regnum + 0, from + 4); |
| 771 | put_frame_register (frame, regnum + 1, from + 0); |
| 772 | } |
| 773 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) |
| 774 | { |
| 775 | gdb_byte fill[8]; |
| 776 | int len = TYPE_LENGTH (type); |
| 777 | |
| 778 | /* Sign extend values, irrespective of type, that are stored to |
| 779 | a 64-bit general purpose register. (32-bit unsigned values |
| 780 | are stored as signed quantities within a 64-bit register. |
| 781 | When performing an operation, in compiled code, that combines |
| 782 | a 32-bit unsigned value with a signed 64-bit value, a type |
| 783 | conversion is first performed that zeroes out the high 32 bits.) */ |
| 784 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 785 | { |
| 786 | if (from[0] & 0x80) |
| 787 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); |
| 788 | else |
| 789 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); |
| 790 | put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); |
| 791 | put_frame_register_bytes (frame, regnum, 8 - len, len, from); |
| 792 | } |
| 793 | else |
| 794 | { |
| 795 | if (from[len-1] & 0x80) |
| 796 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); |
| 797 | else |
| 798 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); |
| 799 | put_frame_register_bytes (frame, regnum, 0, len, from); |
| 800 | put_frame_register_bytes (frame, regnum, len, 8 - len, fill); |
| 801 | } |
| 802 | } |
| 803 | else |
| 804 | { |
| 805 | internal_error (__FILE__, __LINE__, |
| 806 | _("mips_value_to_register: unrecognized case")); |
| 807 | } |
| 808 | } |
| 809 | |
| 810 | /* Return the GDB type object for the "standard" data type of data in |
| 811 | register REG. */ |
| 812 | |
| 813 | static struct type * |
| 814 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
| 815 | { |
| 816 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
| 817 | if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0 |
| 818 | && (regnum % gdbarch_num_regs (gdbarch)) |
| 819 | < mips_regnum (gdbarch)->fp0 + 32) |
| 820 | { |
| 821 | /* The floating-point registers raw, or cooked, always match |
| 822 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
| 823 | if (mips_isa_regsize (gdbarch) == 4) |
| 824 | return builtin_type (gdbarch)->builtin_float; |
| 825 | else |
| 826 | return builtin_type (gdbarch)->builtin_double; |
| 827 | } |
| 828 | else if (regnum < gdbarch_num_regs (gdbarch)) |
| 829 | { |
| 830 | /* The raw or ISA registers. These are all sized according to |
| 831 | the ISA regsize. */ |
| 832 | if (mips_isa_regsize (gdbarch) == 4) |
| 833 | return builtin_type (gdbarch)->builtin_int32; |
| 834 | else |
| 835 | return builtin_type (gdbarch)->builtin_int64; |
| 836 | } |
| 837 | else |
| 838 | { |
| 839 | /* The cooked or ABI registers. These are sized according to |
| 840 | the ABI (with a few complications). */ |
| 841 | if (regnum >= (gdbarch_num_regs (gdbarch) |
| 842 | + mips_regnum (gdbarch)->fp_control_status) |
| 843 | && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM) |
| 844 | /* The pseudo/cooked view of the embedded registers is always |
| 845 | 32-bit. The raw view is handled below. */ |
| 846 | return builtin_type (gdbarch)->builtin_int32; |
| 847 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
| 848 | /* The target, while possibly using a 64-bit register buffer, |
| 849 | is only transfering 32-bits of each integer register. |
| 850 | Reflect this in the cooked/pseudo (ABI) register value. */ |
| 851 | return builtin_type (gdbarch)->builtin_int32; |
| 852 | else if (mips_abi_regsize (gdbarch) == 4) |
| 853 | /* The ABI is restricted to 32-bit registers (the ISA could be |
| 854 | 32- or 64-bit). */ |
| 855 | return builtin_type (gdbarch)->builtin_int32; |
| 856 | else |
| 857 | /* 64-bit ABI. */ |
| 858 | return builtin_type (gdbarch)->builtin_int64; |
| 859 | } |
| 860 | } |
| 861 | |
| 862 | /* Return the GDB type for the pseudo register REGNUM, which is the |
| 863 | ABI-level view. This function is only called if there is a target |
| 864 | description which includes registers, so we know precisely the |
| 865 | types of hardware registers. */ |
| 866 | |
| 867 | static struct type * |
| 868 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
| 869 | { |
| 870 | const int num_regs = gdbarch_num_regs (gdbarch); |
| 871 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 872 | int rawnum = regnum % num_regs; |
| 873 | struct type *rawtype; |
| 874 | |
| 875 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); |
| 876 | |
| 877 | /* Absent registers are still absent. */ |
| 878 | rawtype = gdbarch_register_type (gdbarch, rawnum); |
| 879 | if (TYPE_LENGTH (rawtype) == 0) |
| 880 | return rawtype; |
| 881 | |
| 882 | if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) |
| 883 | /* Present the floating point registers however the hardware did; |
| 884 | do not try to convert between FPU layouts. */ |
| 885 | return rawtype; |
| 886 | |
| 887 | if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) |
| 888 | { |
| 889 | /* The pseudo/cooked view of embedded registers is always |
| 890 | 32-bit, even if the target transfers 64-bit values for them. |
| 891 | New targets relying on XML descriptions should only transfer |
| 892 | the necessary 32 bits, but older versions of GDB expected 64, |
| 893 | so allow the target to provide 64 bits without interfering |
| 894 | with the displayed type. */ |
| 895 | return builtin_type (gdbarch)->builtin_int32; |
| 896 | } |
| 897 | |
| 898 | /* Use pointer types for registers if we can. For n32 we can not, |
| 899 | since we do not have a 64-bit pointer type. */ |
| 900 | if (mips_abi_regsize (gdbarch) |
| 901 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) |
| 902 | { |
| 903 | if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) |
| 904 | return builtin_type (gdbarch)->builtin_data_ptr; |
| 905 | else if (rawnum == MIPS_EMBED_PC_REGNUM) |
| 906 | return builtin_type (gdbarch)->builtin_func_ptr; |
| 907 | } |
| 908 | |
| 909 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 |
| 910 | && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) |
| 911 | return builtin_type (gdbarch)->builtin_int32; |
| 912 | |
| 913 | /* For all other registers, pass through the hardware type. */ |
| 914 | return rawtype; |
| 915 | } |
| 916 | |
| 917 | /* Should the upper word of 64-bit addresses be zeroed? */ |
| 918 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
| 919 | |
| 920 | static int |
| 921 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
| 922 | { |
| 923 | switch (mask_address_var) |
| 924 | { |
| 925 | case AUTO_BOOLEAN_TRUE: |
| 926 | return 1; |
| 927 | case AUTO_BOOLEAN_FALSE: |
| 928 | return 0; |
| 929 | break; |
| 930 | case AUTO_BOOLEAN_AUTO: |
| 931 | return tdep->default_mask_address_p; |
| 932 | default: |
| 933 | internal_error (__FILE__, __LINE__, |
| 934 | _("mips_mask_address_p: bad switch")); |
| 935 | return -1; |
| 936 | } |
| 937 | } |
| 938 | |
| 939 | static void |
| 940 | show_mask_address (struct ui_file *file, int from_tty, |
| 941 | struct cmd_list_element *c, const char *value) |
| 942 | { |
| 943 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
| 944 | |
| 945 | deprecated_show_value_hack (file, from_tty, c, value); |
| 946 | switch (mask_address_var) |
| 947 | { |
| 948 | case AUTO_BOOLEAN_TRUE: |
| 949 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
| 950 | break; |
| 951 | case AUTO_BOOLEAN_FALSE: |
| 952 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
| 953 | break; |
| 954 | case AUTO_BOOLEAN_AUTO: |
| 955 | printf_filtered |
| 956 | ("The 32 bit address mask is set automatically. Currently %s\n", |
| 957 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); |
| 958 | break; |
| 959 | default: |
| 960 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
| 961 | break; |
| 962 | } |
| 963 | } |
| 964 | |
| 965 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
| 966 | |
| 967 | int |
| 968 | mips_pc_is_mips16 (CORE_ADDR memaddr) |
| 969 | { |
| 970 | struct minimal_symbol *sym; |
| 971 | |
| 972 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ |
| 973 | if (is_mips16_addr (memaddr)) |
| 974 | return 1; |
| 975 | |
| 976 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in |
| 977 | the high bit of the info field. Use this to decide if the function is |
| 978 | MIPS16 or normal MIPS. */ |
| 979 | sym = lookup_minimal_symbol_by_pc (memaddr); |
| 980 | if (sym) |
| 981 | return msymbol_is_special (sym); |
| 982 | else |
| 983 | return 0; |
| 984 | } |
| 985 | |
| 986 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
| 987 | all registers should be sign extended for simplicity? */ |
| 988 | |
| 989 | static CORE_ADDR |
| 990 | mips_read_pc (struct regcache *regcache) |
| 991 | { |
| 992 | ULONGEST pc; |
| 993 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
| 994 | regcache_cooked_read_signed (regcache, regnum, &pc); |
| 995 | if (is_mips16_addr (pc)) |
| 996 | pc = unmake_mips16_addr (pc); |
| 997 | return pc; |
| 998 | } |
| 999 | |
| 1000 | static CORE_ADDR |
| 1001 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1002 | { |
| 1003 | ULONGEST pc; |
| 1004 | |
| 1005 | pc = frame_unwind_register_signed |
| 1006 | (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc); |
| 1007 | if (is_mips16_addr (pc)) |
| 1008 | pc = unmake_mips16_addr (pc); |
| 1009 | return pc; |
| 1010 | } |
| 1011 | |
| 1012 | static CORE_ADDR |
| 1013 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1014 | { |
| 1015 | return frame_unwind_register_signed |
| 1016 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); |
| 1017 | } |
| 1018 | |
| 1019 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
| 1020 | dummy frame. The frame ID's base needs to match the TOS value |
| 1021 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's |
| 1022 | breakpoint. */ |
| 1023 | |
| 1024 | static struct frame_id |
| 1025 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1026 | { |
| 1027 | return frame_id_build |
| 1028 | (get_frame_register_signed (this_frame, |
| 1029 | gdbarch_num_regs (gdbarch) |
| 1030 | + MIPS_SP_REGNUM), |
| 1031 | get_frame_pc (this_frame)); |
| 1032 | } |
| 1033 | |
| 1034 | static void |
| 1035 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
| 1036 | { |
| 1037 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
| 1038 | if (mips_pc_is_mips16 (pc)) |
| 1039 | regcache_cooked_write_unsigned (regcache, regnum, make_mips16_addr (pc)); |
| 1040 | else |
| 1041 | regcache_cooked_write_unsigned (regcache, regnum, pc); |
| 1042 | } |
| 1043 | |
| 1044 | /* Fetch and return instruction from the specified location. If the PC |
| 1045 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ |
| 1046 | |
| 1047 | static ULONGEST |
| 1048 | mips_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 1049 | { |
| 1050 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1051 | gdb_byte buf[MIPS_INSN32_SIZE]; |
| 1052 | int instlen; |
| 1053 | int status; |
| 1054 | |
| 1055 | if (mips_pc_is_mips16 (addr)) |
| 1056 | { |
| 1057 | instlen = MIPS_INSN16_SIZE; |
| 1058 | addr = unmake_mips16_addr (addr); |
| 1059 | } |
| 1060 | else |
| 1061 | instlen = MIPS_INSN32_SIZE; |
| 1062 | status = target_read_memory (addr, buf, instlen); |
| 1063 | if (status) |
| 1064 | memory_error (status, addr); |
| 1065 | return extract_unsigned_integer (buf, instlen, byte_order); |
| 1066 | } |
| 1067 | |
| 1068 | /* These are the fields of 32 bit mips instructions. */ |
| 1069 | #define mips32_op(x) (x >> 26) |
| 1070 | #define itype_op(x) (x >> 26) |
| 1071 | #define itype_rs(x) ((x >> 21) & 0x1f) |
| 1072 | #define itype_rt(x) ((x >> 16) & 0x1f) |
| 1073 | #define itype_immediate(x) (x & 0xffff) |
| 1074 | |
| 1075 | #define jtype_op(x) (x >> 26) |
| 1076 | #define jtype_target(x) (x & 0x03ffffff) |
| 1077 | |
| 1078 | #define rtype_op(x) (x >> 26) |
| 1079 | #define rtype_rs(x) ((x >> 21) & 0x1f) |
| 1080 | #define rtype_rt(x) ((x >> 16) & 0x1f) |
| 1081 | #define rtype_rd(x) ((x >> 11) & 0x1f) |
| 1082 | #define rtype_shamt(x) ((x >> 6) & 0x1f) |
| 1083 | #define rtype_funct(x) (x & 0x3f) |
| 1084 | |
| 1085 | static LONGEST |
| 1086 | mips32_relative_offset (ULONGEST inst) |
| 1087 | { |
| 1088 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
| 1089 | } |
| 1090 | |
| 1091 | /* Determine where to set a single step breakpoint while considering |
| 1092 | branch prediction. */ |
| 1093 | static CORE_ADDR |
| 1094 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
| 1095 | { |
| 1096 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 1097 | unsigned long inst; |
| 1098 | int op; |
| 1099 | inst = mips_fetch_instruction (gdbarch, pc); |
| 1100 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
| 1101 | instruction. */ |
| 1102 | { |
| 1103 | if (itype_op (inst) >> 2 == 5) |
| 1104 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
| 1105 | { |
| 1106 | op = (itype_op (inst) & 0x03); |
| 1107 | switch (op) |
| 1108 | { |
| 1109 | case 0: /* BEQL */ |
| 1110 | goto equal_branch; |
| 1111 | case 1: /* BNEL */ |
| 1112 | goto neq_branch; |
| 1113 | case 2: /* BLEZL */ |
| 1114 | goto less_branch; |
| 1115 | case 3: /* BGTZL */ |
| 1116 | goto greater_branch; |
| 1117 | default: |
| 1118 | pc += 4; |
| 1119 | } |
| 1120 | } |
| 1121 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
| 1122 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
| 1123 | { |
| 1124 | int tf = itype_rt (inst) & 0x01; |
| 1125 | int cnum = itype_rt (inst) >> 2; |
| 1126 | int fcrcs = |
| 1127 | get_frame_register_signed (frame, |
| 1128 | mips_regnum (get_frame_arch (frame))-> |
| 1129 | fp_control_status); |
| 1130 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
| 1131 | |
| 1132 | if (((cond >> cnum) & 0x01) == tf) |
| 1133 | pc += mips32_relative_offset (inst) + 4; |
| 1134 | else |
| 1135 | pc += 8; |
| 1136 | } |
| 1137 | else |
| 1138 | pc += 4; /* Not a branch, next instruction is easy. */ |
| 1139 | } |
| 1140 | else |
| 1141 | { /* This gets way messy. */ |
| 1142 | |
| 1143 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
| 1144 | switch (op = itype_op (inst) & 0x07) /* Extract bits 28,27,26. */ |
| 1145 | { |
| 1146 | case 0: /* SPECIAL */ |
| 1147 | op = rtype_funct (inst); |
| 1148 | switch (op) |
| 1149 | { |
| 1150 | case 8: /* JR */ |
| 1151 | case 9: /* JALR */ |
| 1152 | /* Set PC to that address. */ |
| 1153 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
| 1154 | break; |
| 1155 | case 12: /* SYSCALL */ |
| 1156 | { |
| 1157 | struct gdbarch_tdep *tdep; |
| 1158 | |
| 1159 | tdep = gdbarch_tdep (get_frame_arch (frame)); |
| 1160 | if (tdep->syscall_next_pc != NULL) |
| 1161 | pc = tdep->syscall_next_pc (frame); |
| 1162 | else |
| 1163 | pc += 4; |
| 1164 | } |
| 1165 | break; |
| 1166 | default: |
| 1167 | pc += 4; |
| 1168 | } |
| 1169 | |
| 1170 | break; /* end SPECIAL */ |
| 1171 | case 1: /* REGIMM */ |
| 1172 | { |
| 1173 | op = itype_rt (inst); /* branch condition */ |
| 1174 | switch (op) |
| 1175 | { |
| 1176 | case 0: /* BLTZ */ |
| 1177 | case 2: /* BLTZL */ |
| 1178 | case 16: /* BLTZAL */ |
| 1179 | case 18: /* BLTZALL */ |
| 1180 | less_branch: |
| 1181 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
| 1182 | pc += mips32_relative_offset (inst) + 4; |
| 1183 | else |
| 1184 | pc += 8; /* after the delay slot */ |
| 1185 | break; |
| 1186 | case 1: /* BGEZ */ |
| 1187 | case 3: /* BGEZL */ |
| 1188 | case 17: /* BGEZAL */ |
| 1189 | case 19: /* BGEZALL */ |
| 1190 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
| 1191 | pc += mips32_relative_offset (inst) + 4; |
| 1192 | else |
| 1193 | pc += 8; /* after the delay slot */ |
| 1194 | break; |
| 1195 | /* All of the other instructions in the REGIMM category */ |
| 1196 | default: |
| 1197 | pc += 4; |
| 1198 | } |
| 1199 | } |
| 1200 | break; /* end REGIMM */ |
| 1201 | case 2: /* J */ |
| 1202 | case 3: /* JAL */ |
| 1203 | { |
| 1204 | unsigned long reg; |
| 1205 | reg = jtype_target (inst) << 2; |
| 1206 | /* Upper four bits get never changed... */ |
| 1207 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
| 1208 | } |
| 1209 | break; |
| 1210 | /* FIXME case JALX : */ |
| 1211 | { |
| 1212 | unsigned long reg; |
| 1213 | reg = jtype_target (inst) << 2; |
| 1214 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
| 1215 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
| 1216 | } |
| 1217 | break; /* The new PC will be alternate mode */ |
| 1218 | case 4: /* BEQ, BEQL */ |
| 1219 | equal_branch: |
| 1220 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
| 1221 | get_frame_register_signed (frame, itype_rt (inst))) |
| 1222 | pc += mips32_relative_offset (inst) + 4; |
| 1223 | else |
| 1224 | pc += 8; |
| 1225 | break; |
| 1226 | case 5: /* BNE, BNEL */ |
| 1227 | neq_branch: |
| 1228 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
| 1229 | get_frame_register_signed (frame, itype_rt (inst))) |
| 1230 | pc += mips32_relative_offset (inst) + 4; |
| 1231 | else |
| 1232 | pc += 8; |
| 1233 | break; |
| 1234 | case 6: /* BLEZ, BLEZL */ |
| 1235 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
| 1236 | pc += mips32_relative_offset (inst) + 4; |
| 1237 | else |
| 1238 | pc += 8; |
| 1239 | break; |
| 1240 | case 7: |
| 1241 | default: |
| 1242 | greater_branch: /* BGTZ, BGTZL */ |
| 1243 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
| 1244 | pc += mips32_relative_offset (inst) + 4; |
| 1245 | else |
| 1246 | pc += 8; |
| 1247 | break; |
| 1248 | } /* switch */ |
| 1249 | } /* else */ |
| 1250 | return pc; |
| 1251 | } /* mips32_next_pc */ |
| 1252 | |
| 1253 | /* Decoding the next place to set a breakpoint is irregular for the |
| 1254 | mips 16 variant, but fortunately, there fewer instructions. We have |
| 1255 | to cope ith extensions for 16 bit instructions and a pair of actual |
| 1256 | 32 bit instructions. We dont want to set a single step instruction |
| 1257 | on the extend instruction either. */ |
| 1258 | |
| 1259 | /* Lots of mips16 instruction formats */ |
| 1260 | /* Predicting jumps requires itype,ritype,i8type |
| 1261 | and their extensions extItype,extritype,extI8type. */ |
| 1262 | enum mips16_inst_fmts |
| 1263 | { |
| 1264 | itype, /* 0 immediate 5,10 */ |
| 1265 | ritype, /* 1 5,3,8 */ |
| 1266 | rrtype, /* 2 5,3,3,5 */ |
| 1267 | rritype, /* 3 5,3,3,5 */ |
| 1268 | rrrtype, /* 4 5,3,3,3,2 */ |
| 1269 | rriatype, /* 5 5,3,3,1,4 */ |
| 1270 | shifttype, /* 6 5,3,3,3,2 */ |
| 1271 | i8type, /* 7 5,3,8 */ |
| 1272 | i8movtype, /* 8 5,3,3,5 */ |
| 1273 | i8mov32rtype, /* 9 5,3,5,3 */ |
| 1274 | i64type, /* 10 5,3,8 */ |
| 1275 | ri64type, /* 11 5,3,3,5 */ |
| 1276 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ |
| 1277 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ |
| 1278 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ |
| 1279 | extRRItype, /* 15 5,5,5,5,3,3,5 */ |
| 1280 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ |
| 1281 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ |
| 1282 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ |
| 1283 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ |
| 1284 | extRi64type, /* 20 5,6,5,5,3,3,5 */ |
| 1285 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ |
| 1286 | }; |
| 1287 | /* I am heaping all the fields of the formats into one structure and |
| 1288 | then, only the fields which are involved in instruction extension. */ |
| 1289 | struct upk_mips16 |
| 1290 | { |
| 1291 | CORE_ADDR offset; |
| 1292 | unsigned int regx; /* Function in i8 type. */ |
| 1293 | unsigned int regy; |
| 1294 | }; |
| 1295 | |
| 1296 | |
| 1297 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
| 1298 | for the bits which make up the immediate extension. */ |
| 1299 | |
| 1300 | static CORE_ADDR |
| 1301 | extended_offset (unsigned int extension) |
| 1302 | { |
| 1303 | CORE_ADDR value; |
| 1304 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
| 1305 | value = value << 6; |
| 1306 | value |= (extension >> 16) & 0x1f; /* extract 10:5 */ |
| 1307 | value = value << 5; |
| 1308 | value |= extension & 0x01f; /* extract 4:0 */ |
| 1309 | return value; |
| 1310 | } |
| 1311 | |
| 1312 | /* Only call this function if you know that this is an extendable |
| 1313 | instruction. It won't malfunction, but why make excess remote memory |
| 1314 | references? If the immediate operands get sign extended or something, |
| 1315 | do it after the extension is performed. */ |
| 1316 | /* FIXME: Every one of these cases needs to worry about sign extension |
| 1317 | when the offset is to be used in relative addressing. */ |
| 1318 | |
| 1319 | static unsigned int |
| 1320 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 1321 | { |
| 1322 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1323 | gdb_byte buf[8]; |
| 1324 | pc &= 0xfffffffe; /* Clear the low order bit. */ |
| 1325 | target_read_memory (pc, buf, 2); |
| 1326 | return extract_unsigned_integer (buf, 2, byte_order); |
| 1327 | } |
| 1328 | |
| 1329 | static void |
| 1330 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
| 1331 | unsigned int extension, |
| 1332 | unsigned int inst, |
| 1333 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
| 1334 | { |
| 1335 | CORE_ADDR offset; |
| 1336 | int regx; |
| 1337 | int regy; |
| 1338 | switch (insn_format) |
| 1339 | { |
| 1340 | case itype: |
| 1341 | { |
| 1342 | CORE_ADDR value; |
| 1343 | if (extension) |
| 1344 | { |
| 1345 | value = extended_offset (extension); |
| 1346 | value = value << 11; /* rom for the original value */ |
| 1347 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
| 1348 | } |
| 1349 | else |
| 1350 | { |
| 1351 | value = inst & 0x7ff; |
| 1352 | /* FIXME : Consider sign extension. */ |
| 1353 | } |
| 1354 | offset = value; |
| 1355 | regx = -1; |
| 1356 | regy = -1; |
| 1357 | } |
| 1358 | break; |
| 1359 | case ritype: |
| 1360 | case i8type: |
| 1361 | { /* A register identifier and an offset. */ |
| 1362 | /* Most of the fields are the same as I type but the |
| 1363 | immediate value is of a different length. */ |
| 1364 | CORE_ADDR value; |
| 1365 | if (extension) |
| 1366 | { |
| 1367 | value = extended_offset (extension); |
| 1368 | value = value << 8; /* from the original instruction */ |
| 1369 | value |= inst & 0xff; /* eleven bits from instruction */ |
| 1370 | regx = (extension >> 8) & 0x07; /* or i8 funct */ |
| 1371 | if (value & 0x4000) /* Test the sign bit, bit 26. */ |
| 1372 | { |
| 1373 | value &= ~0x3fff; /* Remove the sign bit. */ |
| 1374 | value = -value; |
| 1375 | } |
| 1376 | } |
| 1377 | else |
| 1378 | { |
| 1379 | value = inst & 0xff; /* 8 bits */ |
| 1380 | regx = (inst >> 8) & 0x07; /* or i8 funct */ |
| 1381 | /* FIXME: Do sign extension, this format needs it. */ |
| 1382 | if (value & 0x80) /* THIS CONFUSES ME. */ |
| 1383 | { |
| 1384 | value &= 0xef; /* Remove the sign bit. */ |
| 1385 | value = -value; |
| 1386 | } |
| 1387 | } |
| 1388 | offset = value; |
| 1389 | regy = -1; |
| 1390 | break; |
| 1391 | } |
| 1392 | case jalxtype: |
| 1393 | { |
| 1394 | unsigned long value; |
| 1395 | unsigned int nexthalf; |
| 1396 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); |
| 1397 | value = value << 16; |
| 1398 | nexthalf = mips_fetch_instruction (gdbarch, pc + 2); /* low bit |
| 1399 | still set. */ |
| 1400 | value |= nexthalf; |
| 1401 | offset = value; |
| 1402 | regx = -1; |
| 1403 | regy = -1; |
| 1404 | break; |
| 1405 | } |
| 1406 | default: |
| 1407 | internal_error (__FILE__, __LINE__, _("bad switch")); |
| 1408 | } |
| 1409 | upk->offset = offset; |
| 1410 | upk->regx = regx; |
| 1411 | upk->regy = regy; |
| 1412 | } |
| 1413 | |
| 1414 | |
| 1415 | static CORE_ADDR |
| 1416 | add_offset_16 (CORE_ADDR pc, int offset) |
| 1417 | { |
| 1418 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
| 1419 | } |
| 1420 | |
| 1421 | static CORE_ADDR |
| 1422 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
| 1423 | unsigned int extension, unsigned int insn) |
| 1424 | { |
| 1425 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 1426 | int op = (insn >> 11); |
| 1427 | switch (op) |
| 1428 | { |
| 1429 | case 2: /* Branch */ |
| 1430 | { |
| 1431 | CORE_ADDR offset; |
| 1432 | struct upk_mips16 upk; |
| 1433 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
| 1434 | offset = upk.offset; |
| 1435 | if (offset & 0x800) |
| 1436 | { |
| 1437 | offset &= 0xeff; |
| 1438 | offset = -offset; |
| 1439 | } |
| 1440 | pc += (offset << 1) + 2; |
| 1441 | break; |
| 1442 | } |
| 1443 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
| 1444 | instructions. */ |
| 1445 | { |
| 1446 | struct upk_mips16 upk; |
| 1447 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
| 1448 | pc = add_offset_16 (pc, upk.offset); |
| 1449 | if ((insn >> 10) & 0x01) /* Exchange mode */ |
| 1450 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
| 1451 | else |
| 1452 | pc |= 0x01; |
| 1453 | break; |
| 1454 | } |
| 1455 | case 4: /* beqz */ |
| 1456 | { |
| 1457 | struct upk_mips16 upk; |
| 1458 | int reg; |
| 1459 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
| 1460 | reg = get_frame_register_signed (frame, upk.regx); |
| 1461 | if (reg == 0) |
| 1462 | pc += (upk.offset << 1) + 2; |
| 1463 | else |
| 1464 | pc += 2; |
| 1465 | break; |
| 1466 | } |
| 1467 | case 5: /* bnez */ |
| 1468 | { |
| 1469 | struct upk_mips16 upk; |
| 1470 | int reg; |
| 1471 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
| 1472 | reg = get_frame_register_signed (frame, upk.regx); |
| 1473 | if (reg != 0) |
| 1474 | pc += (upk.offset << 1) + 2; |
| 1475 | else |
| 1476 | pc += 2; |
| 1477 | break; |
| 1478 | } |
| 1479 | case 12: /* I8 Formats btez btnez */ |
| 1480 | { |
| 1481 | struct upk_mips16 upk; |
| 1482 | int reg; |
| 1483 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
| 1484 | /* upk.regx contains the opcode */ |
| 1485 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
| 1486 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
| 1487 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ |
| 1488 | /* pc = add_offset_16(pc,upk.offset) ; */ |
| 1489 | pc += (upk.offset << 1) + 2; |
| 1490 | else |
| 1491 | pc += 2; |
| 1492 | break; |
| 1493 | } |
| 1494 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
| 1495 | { |
| 1496 | struct upk_mips16 upk; |
| 1497 | /* upk.fmt = rrtype; */ |
| 1498 | op = insn & 0x1f; |
| 1499 | if (op == 0) |
| 1500 | { |
| 1501 | int reg; |
| 1502 | upk.regx = (insn >> 8) & 0x07; |
| 1503 | upk.regy = (insn >> 5) & 0x07; |
| 1504 | switch (upk.regy) |
| 1505 | { |
| 1506 | case 0: |
| 1507 | reg = upk.regx; |
| 1508 | break; |
| 1509 | case 1: |
| 1510 | reg = 31; |
| 1511 | break; /* Function return instruction. */ |
| 1512 | case 2: |
| 1513 | reg = upk.regx; |
| 1514 | break; |
| 1515 | default: |
| 1516 | reg = 31; |
| 1517 | break; /* BOGUS Guess */ |
| 1518 | } |
| 1519 | pc = get_frame_register_signed (frame, reg); |
| 1520 | } |
| 1521 | else |
| 1522 | pc += 2; |
| 1523 | break; |
| 1524 | } |
| 1525 | case 30: |
| 1526 | /* This is an instruction extension. Fetch the real instruction |
| 1527 | (which follows the extension) and decode things based on |
| 1528 | that. */ |
| 1529 | { |
| 1530 | pc += 2; |
| 1531 | pc = extended_mips16_next_pc (frame, pc, insn, |
| 1532 | fetch_mips_16 (gdbarch, pc)); |
| 1533 | break; |
| 1534 | } |
| 1535 | default: |
| 1536 | { |
| 1537 | pc += 2; |
| 1538 | break; |
| 1539 | } |
| 1540 | } |
| 1541 | return pc; |
| 1542 | } |
| 1543 | |
| 1544 | static CORE_ADDR |
| 1545 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
| 1546 | { |
| 1547 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 1548 | unsigned int insn = fetch_mips_16 (gdbarch, pc); |
| 1549 | return extended_mips16_next_pc (frame, pc, 0, insn); |
| 1550 | } |
| 1551 | |
| 1552 | /* The mips_next_pc function supports single_step when the remote |
| 1553 | target monitor or stub is not developed enough to do a single_step. |
| 1554 | It works by decoding the current instruction and predicting where a |
| 1555 | branch will go. This isnt hard because all the data is available. |
| 1556 | The MIPS32 and MIPS16 variants are quite different. */ |
| 1557 | static CORE_ADDR |
| 1558 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
| 1559 | { |
| 1560 | if (is_mips16_addr (pc)) |
| 1561 | return mips16_next_pc (frame, pc); |
| 1562 | else |
| 1563 | return mips32_next_pc (frame, pc); |
| 1564 | } |
| 1565 | |
| 1566 | struct mips_frame_cache |
| 1567 | { |
| 1568 | CORE_ADDR base; |
| 1569 | struct trad_frame_saved_reg *saved_regs; |
| 1570 | }; |
| 1571 | |
| 1572 | /* Set a register's saved stack address in temp_saved_regs. If an |
| 1573 | address has already been set for this register, do nothing; this |
| 1574 | way we will only recognize the first save of a given register in a |
| 1575 | function prologue. |
| 1576 | |
| 1577 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
| 1578 | [gdbarch_num_regs .. 2*gdbarch_num_regs). |
| 1579 | Strictly speaking, only the second range is used as it is only second |
| 1580 | range (the ABI instead of ISA registers) that comes into play when finding |
| 1581 | saved registers in a frame. */ |
| 1582 | |
| 1583 | static void |
| 1584 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
| 1585 | int regnum, CORE_ADDR offset) |
| 1586 | { |
| 1587 | if (this_cache != NULL |
| 1588 | && this_cache->saved_regs[regnum].addr == -1) |
| 1589 | { |
| 1590 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
| 1591 | = offset; |
| 1592 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr |
| 1593 | = offset; |
| 1594 | } |
| 1595 | } |
| 1596 | |
| 1597 | |
| 1598 | /* Fetch the immediate value from a MIPS16 instruction. |
| 1599 | If the previous instruction was an EXTEND, use it to extend |
| 1600 | the upper bits of the immediate value. This is a helper function |
| 1601 | for mips16_scan_prologue. */ |
| 1602 | |
| 1603 | static int |
| 1604 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
| 1605 | unsigned short inst, /* current instruction */ |
| 1606 | int nbits, /* number of bits in imm field */ |
| 1607 | int scale, /* scale factor to be applied to imm */ |
| 1608 | int is_signed) /* is the imm field signed? */ |
| 1609 | { |
| 1610 | int offset; |
| 1611 | |
| 1612 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
| 1613 | { |
| 1614 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); |
| 1615 | if (offset & 0x8000) /* check for negative extend */ |
| 1616 | offset = 0 - (0x10000 - (offset & 0xffff)); |
| 1617 | return offset | (inst & 0x1f); |
| 1618 | } |
| 1619 | else |
| 1620 | { |
| 1621 | int max_imm = 1 << nbits; |
| 1622 | int mask = max_imm - 1; |
| 1623 | int sign_bit = max_imm >> 1; |
| 1624 | |
| 1625 | offset = inst & mask; |
| 1626 | if (is_signed && (offset & sign_bit)) |
| 1627 | offset = 0 - (max_imm - offset); |
| 1628 | return offset * scale; |
| 1629 | } |
| 1630 | } |
| 1631 | |
| 1632 | |
| 1633 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
| 1634 | the associated FRAME_CACHE if not null. |
| 1635 | Return the address of the first instruction past the prologue. */ |
| 1636 | |
| 1637 | static CORE_ADDR |
| 1638 | mips16_scan_prologue (struct gdbarch *gdbarch, |
| 1639 | CORE_ADDR start_pc, CORE_ADDR limit_pc, |
| 1640 | struct frame_info *this_frame, |
| 1641 | struct mips_frame_cache *this_cache) |
| 1642 | { |
| 1643 | CORE_ADDR cur_pc; |
| 1644 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
| 1645 | CORE_ADDR sp; |
| 1646 | long frame_offset = 0; /* Size of stack frame. */ |
| 1647 | long frame_adjust = 0; /* Offset of FP from SP. */ |
| 1648 | int frame_reg = MIPS_SP_REGNUM; |
| 1649 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
| 1650 | unsigned inst = 0; /* current instruction */ |
| 1651 | unsigned entry_inst = 0; /* the entry instruction */ |
| 1652 | unsigned save_inst = 0; /* the save instruction */ |
| 1653 | int reg, offset; |
| 1654 | |
| 1655 | int extend_bytes = 0; |
| 1656 | int prev_extend_bytes; |
| 1657 | CORE_ADDR end_prologue_addr = 0; |
| 1658 | |
| 1659 | /* Can be called when there's no process, and hence when there's no |
| 1660 | THIS_FRAME. */ |
| 1661 | if (this_frame != NULL) |
| 1662 | sp = get_frame_register_signed (this_frame, |
| 1663 | gdbarch_num_regs (gdbarch) |
| 1664 | + MIPS_SP_REGNUM); |
| 1665 | else |
| 1666 | sp = 0; |
| 1667 | |
| 1668 | if (limit_pc > start_pc + 200) |
| 1669 | limit_pc = start_pc + 200; |
| 1670 | |
| 1671 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
| 1672 | { |
| 1673 | /* Save the previous instruction. If it's an EXTEND, we'll extract |
| 1674 | the immediate offset extension from it in mips16_get_imm. */ |
| 1675 | prev_inst = inst; |
| 1676 | |
| 1677 | /* Fetch and decode the instruction. */ |
| 1678 | inst = (unsigned short) mips_fetch_instruction (gdbarch, cur_pc); |
| 1679 | |
| 1680 | /* Normally we ignore extend instructions. However, if it is |
| 1681 | not followed by a valid prologue instruction, then this |
| 1682 | instruction is not part of the prologue either. We must |
| 1683 | remember in this case to adjust the end_prologue_addr back |
| 1684 | over the extend. */ |
| 1685 | if ((inst & 0xf800) == 0xf000) /* extend */ |
| 1686 | { |
| 1687 | extend_bytes = MIPS_INSN16_SIZE; |
| 1688 | continue; |
| 1689 | } |
| 1690 | |
| 1691 | prev_extend_bytes = extend_bytes; |
| 1692 | extend_bytes = 0; |
| 1693 | |
| 1694 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
| 1695 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
| 1696 | { |
| 1697 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); |
| 1698 | if (offset < 0) /* Negative stack adjustment? */ |
| 1699 | frame_offset -= offset; |
| 1700 | else |
| 1701 | /* Exit loop if a positive stack adjustment is found, which |
| 1702 | usually means that the stack cleanup code in the function |
| 1703 | epilogue is reached. */ |
| 1704 | break; |
| 1705 | } |
| 1706 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
| 1707 | { |
| 1708 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); |
| 1709 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; |
| 1710 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
| 1711 | } |
| 1712 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
| 1713 | { |
| 1714 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); |
| 1715 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; |
| 1716 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
| 1717 | } |
| 1718 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ |
| 1719 | { |
| 1720 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); |
| 1721 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
| 1722 | } |
| 1723 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
| 1724 | { |
| 1725 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); |
| 1726 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
| 1727 | } |
| 1728 | else if (inst == 0x673d) /* move $s1, $sp */ |
| 1729 | { |
| 1730 | frame_addr = sp; |
| 1731 | frame_reg = 17; |
| 1732 | } |
| 1733 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ |
| 1734 | { |
| 1735 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); |
| 1736 | frame_addr = sp + offset; |
| 1737 | frame_reg = 17; |
| 1738 | frame_adjust = offset; |
| 1739 | } |
| 1740 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ |
| 1741 | { |
| 1742 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); |
| 1743 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; |
| 1744 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
| 1745 | } |
| 1746 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ |
| 1747 | { |
| 1748 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); |
| 1749 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; |
| 1750 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
| 1751 | } |
| 1752 | else if ((inst & 0xf81f) == 0xe809 |
| 1753 | && (inst & 0x700) != 0x700) /* entry */ |
| 1754 | entry_inst = inst; /* Save for later processing. */ |
| 1755 | else if ((inst & 0xff80) == 0x6480) /* save */ |
| 1756 | { |
| 1757 | save_inst = inst; /* Save for later processing. */ |
| 1758 | if (prev_extend_bytes) /* extend */ |
| 1759 | save_inst |= prev_inst << 16; |
| 1760 | } |
| 1761 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
| 1762 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
| 1763 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
| 1764 | { |
| 1765 | /* This instruction is part of the prologue, but we don't |
| 1766 | need to do anything special to handle it. */ |
| 1767 | } |
| 1768 | else |
| 1769 | { |
| 1770 | /* This instruction is not an instruction typically found |
| 1771 | in a prologue, so we must have reached the end of the |
| 1772 | prologue. */ |
| 1773 | if (end_prologue_addr == 0) |
| 1774 | end_prologue_addr = cur_pc - prev_extend_bytes; |
| 1775 | } |
| 1776 | } |
| 1777 | |
| 1778 | /* The entry instruction is typically the first instruction in a function, |
| 1779 | and it stores registers at offsets relative to the value of the old SP |
| 1780 | (before the prologue). But the value of the sp parameter to this |
| 1781 | function is the new SP (after the prologue has been executed). So we |
| 1782 | can't calculate those offsets until we've seen the entire prologue, |
| 1783 | and can calculate what the old SP must have been. */ |
| 1784 | if (entry_inst != 0) |
| 1785 | { |
| 1786 | int areg_count = (entry_inst >> 8) & 7; |
| 1787 | int sreg_count = (entry_inst >> 6) & 3; |
| 1788 | |
| 1789 | /* The entry instruction always subtracts 32 from the SP. */ |
| 1790 | frame_offset += 32; |
| 1791 | |
| 1792 | /* Now we can calculate what the SP must have been at the |
| 1793 | start of the function prologue. */ |
| 1794 | sp += frame_offset; |
| 1795 | |
| 1796 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
| 1797 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) |
| 1798 | { |
| 1799 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
| 1800 | offset += mips_abi_regsize (gdbarch); |
| 1801 | } |
| 1802 | |
| 1803 | /* Check if the ra register was pushed on the stack. */ |
| 1804 | offset = -4; |
| 1805 | if (entry_inst & 0x20) |
| 1806 | { |
| 1807 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
| 1808 | offset -= mips_abi_regsize (gdbarch); |
| 1809 | } |
| 1810 | |
| 1811 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
| 1812 | for (reg = 16; reg < sreg_count + 16; reg++) |
| 1813 | { |
| 1814 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
| 1815 | offset -= mips_abi_regsize (gdbarch); |
| 1816 | } |
| 1817 | } |
| 1818 | |
| 1819 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
| 1820 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the |
| 1821 | size of the frame is specified as an immediate field of instruction |
| 1822 | and an extended variation exists which lets additional registers and |
| 1823 | frame space to be specified. The instruction always treats registers |
| 1824 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ |
| 1825 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) |
| 1826 | { |
| 1827 | static int args_table[16] = { |
| 1828 | 0, 0, 0, 0, 1, 1, 1, 1, |
| 1829 | 2, 2, 2, 0, 3, 3, 4, -1, |
| 1830 | }; |
| 1831 | static int astatic_table[16] = { |
| 1832 | 0, 1, 2, 3, 0, 1, 2, 3, |
| 1833 | 0, 1, 2, 4, 0, 1, 0, -1, |
| 1834 | }; |
| 1835 | int aregs = (save_inst >> 16) & 0xf; |
| 1836 | int xsregs = (save_inst >> 24) & 0x7; |
| 1837 | int args = args_table[aregs]; |
| 1838 | int astatic = astatic_table[aregs]; |
| 1839 | long frame_size; |
| 1840 | |
| 1841 | if (args < 0) |
| 1842 | { |
| 1843 | warning (_("Invalid number of argument registers encoded in SAVE.")); |
| 1844 | args = 0; |
| 1845 | } |
| 1846 | if (astatic < 0) |
| 1847 | { |
| 1848 | warning (_("Invalid number of static registers encoded in SAVE.")); |
| 1849 | astatic = 0; |
| 1850 | } |
| 1851 | |
| 1852 | /* For standard SAVE the frame size of 0 means 128. */ |
| 1853 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); |
| 1854 | if (frame_size == 0 && (save_inst >> 16) == 0) |
| 1855 | frame_size = 16; |
| 1856 | frame_size *= 8; |
| 1857 | frame_offset += frame_size; |
| 1858 | |
| 1859 | /* Now we can calculate what the SP must have been at the |
| 1860 | start of the function prologue. */ |
| 1861 | sp += frame_offset; |
| 1862 | |
| 1863 | /* Check if A0-A3 were saved in the caller's argument save area. */ |
| 1864 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) |
| 1865 | { |
| 1866 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
| 1867 | offset += mips_abi_regsize (gdbarch); |
| 1868 | } |
| 1869 | |
| 1870 | offset = -4; |
| 1871 | |
| 1872 | /* Check if the RA register was pushed on the stack. */ |
| 1873 | if (save_inst & 0x40) |
| 1874 | { |
| 1875 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
| 1876 | offset -= mips_abi_regsize (gdbarch); |
| 1877 | } |
| 1878 | |
| 1879 | /* Check if the S8 register was pushed on the stack. */ |
| 1880 | if (xsregs > 6) |
| 1881 | { |
| 1882 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
| 1883 | offset -= mips_abi_regsize (gdbarch); |
| 1884 | xsregs--; |
| 1885 | } |
| 1886 | /* Check if S2-S7 were pushed on the stack. */ |
| 1887 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) |
| 1888 | { |
| 1889 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
| 1890 | offset -= mips_abi_regsize (gdbarch); |
| 1891 | } |
| 1892 | |
| 1893 | /* Check if the S1 register was pushed on the stack. */ |
| 1894 | if (save_inst & 0x10) |
| 1895 | { |
| 1896 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
| 1897 | offset -= mips_abi_regsize (gdbarch); |
| 1898 | } |
| 1899 | /* Check if the S0 register was pushed on the stack. */ |
| 1900 | if (save_inst & 0x20) |
| 1901 | { |
| 1902 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
| 1903 | offset -= mips_abi_regsize (gdbarch); |
| 1904 | } |
| 1905 | |
| 1906 | /* Check if A0-A3 were pushed on the stack. */ |
| 1907 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) |
| 1908 | { |
| 1909 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
| 1910 | offset -= mips_abi_regsize (gdbarch); |
| 1911 | } |
| 1912 | } |
| 1913 | |
| 1914 | if (this_cache != NULL) |
| 1915 | { |
| 1916 | this_cache->base = |
| 1917 | (get_frame_register_signed (this_frame, |
| 1918 | gdbarch_num_regs (gdbarch) + frame_reg) |
| 1919 | + frame_offset - frame_adjust); |
| 1920 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should |
| 1921 | be able to get rid of the assignment below, evetually. But it's |
| 1922 | still needed for now. */ |
| 1923 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
| 1924 | + mips_regnum (gdbarch)->pc] |
| 1925 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; |
| 1926 | } |
| 1927 | |
| 1928 | /* If we didn't reach the end of the prologue when scanning the function |
| 1929 | instructions, then set end_prologue_addr to the address of the |
| 1930 | instruction immediately after the last one we scanned. */ |
| 1931 | if (end_prologue_addr == 0) |
| 1932 | end_prologue_addr = cur_pc; |
| 1933 | |
| 1934 | return end_prologue_addr; |
| 1935 | } |
| 1936 | |
| 1937 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
| 1938 | Procedures that use the 32-bit instruction set are handled by the |
| 1939 | mips_insn32 unwinder. */ |
| 1940 | |
| 1941 | static struct mips_frame_cache * |
| 1942 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 1943 | { |
| 1944 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1945 | struct mips_frame_cache *cache; |
| 1946 | |
| 1947 | if ((*this_cache) != NULL) |
| 1948 | return (*this_cache); |
| 1949 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
| 1950 | (*this_cache) = cache; |
| 1951 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 1952 | |
| 1953 | /* Analyze the function prologue. */ |
| 1954 | { |
| 1955 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
| 1956 | CORE_ADDR start_addr; |
| 1957 | |
| 1958 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
| 1959 | if (start_addr == 0) |
| 1960 | start_addr = heuristic_proc_start (gdbarch, pc); |
| 1961 | /* We can't analyze the prologue if we couldn't find the begining |
| 1962 | of the function. */ |
| 1963 | if (start_addr == 0) |
| 1964 | return cache; |
| 1965 | |
| 1966 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
| 1967 | } |
| 1968 | |
| 1969 | /* gdbarch_sp_regnum contains the value and not the address. */ |
| 1970 | trad_frame_set_value (cache->saved_regs, |
| 1971 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
| 1972 | cache->base); |
| 1973 | |
| 1974 | return (*this_cache); |
| 1975 | } |
| 1976 | |
| 1977 | static void |
| 1978 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 1979 | struct frame_id *this_id) |
| 1980 | { |
| 1981 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
| 1982 | this_cache); |
| 1983 | /* This marks the outermost frame. */ |
| 1984 | if (info->base == 0) |
| 1985 | return; |
| 1986 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
| 1987 | } |
| 1988 | |
| 1989 | static struct value * |
| 1990 | mips_insn16_frame_prev_register (struct frame_info *this_frame, |
| 1991 | void **this_cache, int regnum) |
| 1992 | { |
| 1993 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
| 1994 | this_cache); |
| 1995 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
| 1996 | } |
| 1997 | |
| 1998 | static int |
| 1999 | mips_insn16_frame_sniffer (const struct frame_unwind *self, |
| 2000 | struct frame_info *this_frame, void **this_cache) |
| 2001 | { |
| 2002 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 2003 | if (mips_pc_is_mips16 (pc)) |
| 2004 | return 1; |
| 2005 | return 0; |
| 2006 | } |
| 2007 | |
| 2008 | static const struct frame_unwind mips_insn16_frame_unwind = |
| 2009 | { |
| 2010 | NORMAL_FRAME, |
| 2011 | mips_insn16_frame_this_id, |
| 2012 | mips_insn16_frame_prev_register, |
| 2013 | NULL, |
| 2014 | mips_insn16_frame_sniffer |
| 2015 | }; |
| 2016 | |
| 2017 | static CORE_ADDR |
| 2018 | mips_insn16_frame_base_address (struct frame_info *this_frame, |
| 2019 | void **this_cache) |
| 2020 | { |
| 2021 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
| 2022 | this_cache); |
| 2023 | return info->base; |
| 2024 | } |
| 2025 | |
| 2026 | static const struct frame_base mips_insn16_frame_base = |
| 2027 | { |
| 2028 | &mips_insn16_frame_unwind, |
| 2029 | mips_insn16_frame_base_address, |
| 2030 | mips_insn16_frame_base_address, |
| 2031 | mips_insn16_frame_base_address |
| 2032 | }; |
| 2033 | |
| 2034 | static const struct frame_base * |
| 2035 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) |
| 2036 | { |
| 2037 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 2038 | if (mips_pc_is_mips16 (pc)) |
| 2039 | return &mips_insn16_frame_base; |
| 2040 | else |
| 2041 | return NULL; |
| 2042 | } |
| 2043 | |
| 2044 | /* Mark all the registers as unset in the saved_regs array |
| 2045 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ |
| 2046 | |
| 2047 | static void |
| 2048 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) |
| 2049 | { |
| 2050 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
| 2051 | return; |
| 2052 | |
| 2053 | { |
| 2054 | const int num_regs = gdbarch_num_regs (gdbarch); |
| 2055 | int i; |
| 2056 | |
| 2057 | for (i = 0; i < num_regs; i++) |
| 2058 | { |
| 2059 | this_cache->saved_regs[i].addr = -1; |
| 2060 | } |
| 2061 | } |
| 2062 | } |
| 2063 | |
| 2064 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
| 2065 | the associated FRAME_CACHE if not null. |
| 2066 | Return the address of the first instruction past the prologue. */ |
| 2067 | |
| 2068 | static CORE_ADDR |
| 2069 | mips32_scan_prologue (struct gdbarch *gdbarch, |
| 2070 | CORE_ADDR start_pc, CORE_ADDR limit_pc, |
| 2071 | struct frame_info *this_frame, |
| 2072 | struct mips_frame_cache *this_cache) |
| 2073 | { |
| 2074 | CORE_ADDR cur_pc; |
| 2075 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
| 2076 | frame-pointer. */ |
| 2077 | CORE_ADDR sp; |
| 2078 | long frame_offset; |
| 2079 | int frame_reg = MIPS_SP_REGNUM; |
| 2080 | |
| 2081 | CORE_ADDR end_prologue_addr = 0; |
| 2082 | int seen_sp_adjust = 0; |
| 2083 | int load_immediate_bytes = 0; |
| 2084 | int in_delay_slot = 0; |
| 2085 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
| 2086 | |
| 2087 | /* Can be called when there's no process, and hence when there's no |
| 2088 | THIS_FRAME. */ |
| 2089 | if (this_frame != NULL) |
| 2090 | sp = get_frame_register_signed (this_frame, |
| 2091 | gdbarch_num_regs (gdbarch) |
| 2092 | + MIPS_SP_REGNUM); |
| 2093 | else |
| 2094 | sp = 0; |
| 2095 | |
| 2096 | if (limit_pc > start_pc + 200) |
| 2097 | limit_pc = start_pc + 200; |
| 2098 | |
| 2099 | restart: |
| 2100 | |
| 2101 | frame_offset = 0; |
| 2102 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
| 2103 | { |
| 2104 | unsigned long inst, high_word, low_word; |
| 2105 | int reg; |
| 2106 | |
| 2107 | /* Fetch the instruction. */ |
| 2108 | inst = (unsigned long) mips_fetch_instruction (gdbarch, cur_pc); |
| 2109 | |
| 2110 | /* Save some code by pre-extracting some useful fields. */ |
| 2111 | high_word = (inst >> 16) & 0xffff; |
| 2112 | low_word = inst & 0xffff; |
| 2113 | reg = high_word & 0x1f; |
| 2114 | |
| 2115 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
| 2116 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
| 2117 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ |
| 2118 | { |
| 2119 | if (low_word & 0x8000) /* Negative stack adjustment? */ |
| 2120 | frame_offset += 0x10000 - low_word; |
| 2121 | else |
| 2122 | /* Exit loop if a positive stack adjustment is found, which |
| 2123 | usually means that the stack cleanup code in the function |
| 2124 | epilogue is reached. */ |
| 2125 | break; |
| 2126 | seen_sp_adjust = 1; |
| 2127 | } |
| 2128 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
| 2129 | && !regsize_is_64_bits) |
| 2130 | { |
| 2131 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
| 2132 | } |
| 2133 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
| 2134 | && regsize_is_64_bits) |
| 2135 | { |
| 2136 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ |
| 2137 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
| 2138 | } |
| 2139 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
| 2140 | { |
| 2141 | /* Old gcc frame, r30 is virtual frame pointer. */ |
| 2142 | if ((long) low_word != frame_offset) |
| 2143 | frame_addr = sp + low_word; |
| 2144 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
| 2145 | { |
| 2146 | unsigned alloca_adjust; |
| 2147 | |
| 2148 | frame_reg = 30; |
| 2149 | frame_addr = get_frame_register_signed |
| 2150 | (this_frame, gdbarch_num_regs (gdbarch) + 30); |
| 2151 | |
| 2152 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
| 2153 | if (alloca_adjust > 0) |
| 2154 | { |
| 2155 | /* FP > SP + frame_size. This may be because of |
| 2156 | an alloca or somethings similar. Fix sp to |
| 2157 | "pre-alloca" value, and try again. */ |
| 2158 | sp += alloca_adjust; |
| 2159 | /* Need to reset the status of all registers. Otherwise, |
| 2160 | we will hit a guard that prevents the new address |
| 2161 | for each register to be recomputed during the second |
| 2162 | pass. */ |
| 2163 | reset_saved_regs (gdbarch, this_cache); |
| 2164 | goto restart; |
| 2165 | } |
| 2166 | } |
| 2167 | } |
| 2168 | /* move $30,$sp. With different versions of gas this will be either |
| 2169 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. |
| 2170 | Accept any one of these. */ |
| 2171 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
| 2172 | { |
| 2173 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ |
| 2174 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
| 2175 | { |
| 2176 | unsigned alloca_adjust; |
| 2177 | |
| 2178 | frame_reg = 30; |
| 2179 | frame_addr = get_frame_register_signed |
| 2180 | (this_frame, gdbarch_num_regs (gdbarch) + 30); |
| 2181 | |
| 2182 | alloca_adjust = (unsigned) (frame_addr - sp); |
| 2183 | if (alloca_adjust > 0) |
| 2184 | { |
| 2185 | /* FP > SP + frame_size. This may be because of |
| 2186 | an alloca or somethings similar. Fix sp to |
| 2187 | "pre-alloca" value, and try again. */ |
| 2188 | sp = frame_addr; |
| 2189 | /* Need to reset the status of all registers. Otherwise, |
| 2190 | we will hit a guard that prevents the new address |
| 2191 | for each register to be recomputed during the second |
| 2192 | pass. */ |
| 2193 | reset_saved_regs (gdbarch, this_cache); |
| 2194 | goto restart; |
| 2195 | } |
| 2196 | } |
| 2197 | } |
| 2198 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
| 2199 | && !regsize_is_64_bits) |
| 2200 | { |
| 2201 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
| 2202 | } |
| 2203 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ |
| 2204 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ |
| 2205 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ |
| 2206 | || high_word == 0x3c1c /* lui $gp,n */ |
| 2207 | || high_word == 0x279c /* addiu $gp,$gp,n */ |
| 2208 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ |
| 2209 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ |
| 2210 | ) |
| 2211 | { |
| 2212 | /* These instructions are part of the prologue, but we don't |
| 2213 | need to do anything special to handle them. */ |
| 2214 | } |
| 2215 | /* The instructions below load $at or $t0 with an immediate |
| 2216 | value in preparation for a stack adjustment via |
| 2217 | subu $sp,$sp,[$at,$t0]. These instructions could also |
| 2218 | initialize a local variable, so we accept them only before |
| 2219 | a stack adjustment instruction was seen. */ |
| 2220 | else if (!seen_sp_adjust |
| 2221 | && (high_word == 0x3c01 /* lui $at,n */ |
| 2222 | || high_word == 0x3c08 /* lui $t0,n */ |
| 2223 | || high_word == 0x3421 /* ori $at,$at,n */ |
| 2224 | || high_word == 0x3508 /* ori $t0,$t0,n */ |
| 2225 | || high_word == 0x3401 /* ori $at,$zero,n */ |
| 2226 | || high_word == 0x3408 /* ori $t0,$zero,n */ |
| 2227 | )) |
| 2228 | { |
| 2229 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
| 2230 | } |
| 2231 | else |
| 2232 | { |
| 2233 | /* This instruction is not an instruction typically found |
| 2234 | in a prologue, so we must have reached the end of the |
| 2235 | prologue. */ |
| 2236 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this |
| 2237 | loop now? Why would we need to continue scanning the function |
| 2238 | instructions? */ |
| 2239 | if (end_prologue_addr == 0) |
| 2240 | end_prologue_addr = cur_pc; |
| 2241 | |
| 2242 | /* Check for branches and jumps. For now, only jump to |
| 2243 | register are caught (i.e. returns). */ |
| 2244 | if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) |
| 2245 | in_delay_slot = 1; |
| 2246 | } |
| 2247 | |
| 2248 | /* If the previous instruction was a jump, we must have reached |
| 2249 | the end of the prologue by now. Stop scanning so that we do |
| 2250 | not go past the function return. */ |
| 2251 | if (in_delay_slot) |
| 2252 | break; |
| 2253 | } |
| 2254 | |
| 2255 | if (this_cache != NULL) |
| 2256 | { |
| 2257 | this_cache->base = |
| 2258 | (get_frame_register_signed (this_frame, |
| 2259 | gdbarch_num_regs (gdbarch) + frame_reg) |
| 2260 | + frame_offset); |
| 2261 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of |
| 2262 | this assignment below, eventually. But it's still needed |
| 2263 | for now. */ |
| 2264 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
| 2265 | + mips_regnum (gdbarch)->pc] |
| 2266 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
| 2267 | + MIPS_RA_REGNUM]; |
| 2268 | } |
| 2269 | |
| 2270 | /* If we didn't reach the end of the prologue when scanning the function |
| 2271 | instructions, then set end_prologue_addr to the address of the |
| 2272 | instruction immediately after the last one we scanned. */ |
| 2273 | /* brobecker/2004-10-10: I don't think this would ever happen, but |
| 2274 | we may as well be careful and do our best if we have a null |
| 2275 | end_prologue_addr. */ |
| 2276 | if (end_prologue_addr == 0) |
| 2277 | end_prologue_addr = cur_pc; |
| 2278 | |
| 2279 | /* In a frameless function, we might have incorrectly |
| 2280 | skipped some load immediate instructions. Undo the skipping |
| 2281 | if the load immediate was not followed by a stack adjustment. */ |
| 2282 | if (load_immediate_bytes && !seen_sp_adjust) |
| 2283 | end_prologue_addr -= load_immediate_bytes; |
| 2284 | |
| 2285 | return end_prologue_addr; |
| 2286 | } |
| 2287 | |
| 2288 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
| 2289 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit |
| 2290 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 |
| 2291 | unwinder. */ |
| 2292 | |
| 2293 | static struct mips_frame_cache * |
| 2294 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 2295 | { |
| 2296 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 2297 | struct mips_frame_cache *cache; |
| 2298 | |
| 2299 | if ((*this_cache) != NULL) |
| 2300 | return (*this_cache); |
| 2301 | |
| 2302 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
| 2303 | (*this_cache) = cache; |
| 2304 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 2305 | |
| 2306 | /* Analyze the function prologue. */ |
| 2307 | { |
| 2308 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
| 2309 | CORE_ADDR start_addr; |
| 2310 | |
| 2311 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
| 2312 | if (start_addr == 0) |
| 2313 | start_addr = heuristic_proc_start (gdbarch, pc); |
| 2314 | /* We can't analyze the prologue if we couldn't find the begining |
| 2315 | of the function. */ |
| 2316 | if (start_addr == 0) |
| 2317 | return cache; |
| 2318 | |
| 2319 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
| 2320 | } |
| 2321 | |
| 2322 | /* gdbarch_sp_regnum contains the value and not the address. */ |
| 2323 | trad_frame_set_value (cache->saved_regs, |
| 2324 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
| 2325 | cache->base); |
| 2326 | |
| 2327 | return (*this_cache); |
| 2328 | } |
| 2329 | |
| 2330 | static void |
| 2331 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 2332 | struct frame_id *this_id) |
| 2333 | { |
| 2334 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
| 2335 | this_cache); |
| 2336 | /* This marks the outermost frame. */ |
| 2337 | if (info->base == 0) |
| 2338 | return; |
| 2339 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
| 2340 | } |
| 2341 | |
| 2342 | static struct value * |
| 2343 | mips_insn32_frame_prev_register (struct frame_info *this_frame, |
| 2344 | void **this_cache, int regnum) |
| 2345 | { |
| 2346 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
| 2347 | this_cache); |
| 2348 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
| 2349 | } |
| 2350 | |
| 2351 | static int |
| 2352 | mips_insn32_frame_sniffer (const struct frame_unwind *self, |
| 2353 | struct frame_info *this_frame, void **this_cache) |
| 2354 | { |
| 2355 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 2356 | if (! mips_pc_is_mips16 (pc)) |
| 2357 | return 1; |
| 2358 | return 0; |
| 2359 | } |
| 2360 | |
| 2361 | static const struct frame_unwind mips_insn32_frame_unwind = |
| 2362 | { |
| 2363 | NORMAL_FRAME, |
| 2364 | mips_insn32_frame_this_id, |
| 2365 | mips_insn32_frame_prev_register, |
| 2366 | NULL, |
| 2367 | mips_insn32_frame_sniffer |
| 2368 | }; |
| 2369 | |
| 2370 | static CORE_ADDR |
| 2371 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
| 2372 | void **this_cache) |
| 2373 | { |
| 2374 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
| 2375 | this_cache); |
| 2376 | return info->base; |
| 2377 | } |
| 2378 | |
| 2379 | static const struct frame_base mips_insn32_frame_base = |
| 2380 | { |
| 2381 | &mips_insn32_frame_unwind, |
| 2382 | mips_insn32_frame_base_address, |
| 2383 | mips_insn32_frame_base_address, |
| 2384 | mips_insn32_frame_base_address |
| 2385 | }; |
| 2386 | |
| 2387 | static const struct frame_base * |
| 2388 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
| 2389 | { |
| 2390 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 2391 | if (! mips_pc_is_mips16 (pc)) |
| 2392 | return &mips_insn32_frame_base; |
| 2393 | else |
| 2394 | return NULL; |
| 2395 | } |
| 2396 | |
| 2397 | static struct trad_frame_cache * |
| 2398 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 2399 | { |
| 2400 | CORE_ADDR pc; |
| 2401 | CORE_ADDR start_addr; |
| 2402 | CORE_ADDR stack_addr; |
| 2403 | struct trad_frame_cache *this_trad_cache; |
| 2404 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 2405 | int num_regs = gdbarch_num_regs (gdbarch); |
| 2406 | |
| 2407 | if ((*this_cache) != NULL) |
| 2408 | return (*this_cache); |
| 2409 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
| 2410 | (*this_cache) = this_trad_cache; |
| 2411 | |
| 2412 | /* The return address is in the link register. */ |
| 2413 | trad_frame_set_reg_realreg (this_trad_cache, |
| 2414 | gdbarch_pc_regnum (gdbarch), |
| 2415 | num_regs + MIPS_RA_REGNUM); |
| 2416 | |
| 2417 | /* Frame ID, since it's a frameless / stackless function, no stack |
| 2418 | space is allocated and SP on entry is the current SP. */ |
| 2419 | pc = get_frame_pc (this_frame); |
| 2420 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
| 2421 | stack_addr = get_frame_register_signed (this_frame, |
| 2422 | num_regs + MIPS_SP_REGNUM); |
| 2423 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
| 2424 | |
| 2425 | /* Assume that the frame's base is the same as the |
| 2426 | stack-pointer. */ |
| 2427 | trad_frame_set_this_base (this_trad_cache, stack_addr); |
| 2428 | |
| 2429 | return this_trad_cache; |
| 2430 | } |
| 2431 | |
| 2432 | static void |
| 2433 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 2434 | struct frame_id *this_id) |
| 2435 | { |
| 2436 | struct trad_frame_cache *this_trad_cache |
| 2437 | = mips_stub_frame_cache (this_frame, this_cache); |
| 2438 | trad_frame_get_id (this_trad_cache, this_id); |
| 2439 | } |
| 2440 | |
| 2441 | static struct value * |
| 2442 | mips_stub_frame_prev_register (struct frame_info *this_frame, |
| 2443 | void **this_cache, int regnum) |
| 2444 | { |
| 2445 | struct trad_frame_cache *this_trad_cache |
| 2446 | = mips_stub_frame_cache (this_frame, this_cache); |
| 2447 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); |
| 2448 | } |
| 2449 | |
| 2450 | static int |
| 2451 | mips_stub_frame_sniffer (const struct frame_unwind *self, |
| 2452 | struct frame_info *this_frame, void **this_cache) |
| 2453 | { |
| 2454 | gdb_byte dummy[4]; |
| 2455 | struct obj_section *s; |
| 2456 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
| 2457 | struct minimal_symbol *msym; |
| 2458 | |
| 2459 | /* Use the stub unwinder for unreadable code. */ |
| 2460 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
| 2461 | return 1; |
| 2462 | |
| 2463 | if (in_plt_section (pc, NULL)) |
| 2464 | return 1; |
| 2465 | |
| 2466 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ |
| 2467 | s = find_pc_section (pc); |
| 2468 | |
| 2469 | if (s != NULL |
| 2470 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), |
| 2471 | ".MIPS.stubs") == 0) |
| 2472 | return 1; |
| 2473 | |
| 2474 | /* Calling a PIC function from a non-PIC function passes through a |
| 2475 | stub. The stub for foo is named ".pic.foo". */ |
| 2476 | msym = lookup_minimal_symbol_by_pc (pc); |
| 2477 | if (msym != NULL |
| 2478 | && SYMBOL_LINKAGE_NAME (msym) != NULL |
| 2479 | && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0) |
| 2480 | return 1; |
| 2481 | |
| 2482 | return 0; |
| 2483 | } |
| 2484 | |
| 2485 | static const struct frame_unwind mips_stub_frame_unwind = |
| 2486 | { |
| 2487 | NORMAL_FRAME, |
| 2488 | mips_stub_frame_this_id, |
| 2489 | mips_stub_frame_prev_register, |
| 2490 | NULL, |
| 2491 | mips_stub_frame_sniffer |
| 2492 | }; |
| 2493 | |
| 2494 | static CORE_ADDR |
| 2495 | mips_stub_frame_base_address (struct frame_info *this_frame, |
| 2496 | void **this_cache) |
| 2497 | { |
| 2498 | struct trad_frame_cache *this_trad_cache |
| 2499 | = mips_stub_frame_cache (this_frame, this_cache); |
| 2500 | return trad_frame_get_this_base (this_trad_cache); |
| 2501 | } |
| 2502 | |
| 2503 | static const struct frame_base mips_stub_frame_base = |
| 2504 | { |
| 2505 | &mips_stub_frame_unwind, |
| 2506 | mips_stub_frame_base_address, |
| 2507 | mips_stub_frame_base_address, |
| 2508 | mips_stub_frame_base_address |
| 2509 | }; |
| 2510 | |
| 2511 | static const struct frame_base * |
| 2512 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
| 2513 | { |
| 2514 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
| 2515 | return &mips_stub_frame_base; |
| 2516 | else |
| 2517 | return NULL; |
| 2518 | } |
| 2519 | |
| 2520 | /* mips_addr_bits_remove - remove useless address bits */ |
| 2521 | |
| 2522 | static CORE_ADDR |
| 2523 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 2524 | { |
| 2525 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2526 | |
| 2527 | if (is_mips16_addr (addr)) |
| 2528 | addr = unmake_mips16_addr (addr); |
| 2529 | |
| 2530 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
| 2531 | /* This hack is a work-around for existing boards using PMON, the |
| 2532 | simulator, and any other 64-bit targets that doesn't have true |
| 2533 | 64-bit addressing. On these targets, the upper 32 bits of |
| 2534 | addresses are ignored by the hardware. Thus, the PC or SP are |
| 2535 | likely to have been sign extended to all 1s by instruction |
| 2536 | sequences that load 32-bit addresses. For example, a typical |
| 2537 | piece of code that loads an address is this: |
| 2538 | |
| 2539 | lui $r2, <upper 16 bits> |
| 2540 | ori $r2, <lower 16 bits> |
| 2541 | |
| 2542 | But the lui sign-extends the value such that the upper 32 bits |
| 2543 | may be all 1s. The workaround is simply to mask off these |
| 2544 | bits. In the future, gcc may be changed to support true 64-bit |
| 2545 | addressing, and this masking will have to be disabled. */ |
| 2546 | return addr &= 0xffffffffUL; |
| 2547 | else |
| 2548 | return addr; |
| 2549 | } |
| 2550 | |
| 2551 | /* Instructions used during single-stepping of atomic sequences. */ |
| 2552 | #define LL_OPCODE 0x30 |
| 2553 | #define LLD_OPCODE 0x34 |
| 2554 | #define SC_OPCODE 0x38 |
| 2555 | #define SCD_OPCODE 0x3c |
| 2556 | |
| 2557 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD |
| 2558 | instruction and ending with a SC/SCD instruction. If such a sequence |
| 2559 | is found, attempt to step through it. A breakpoint is placed at the end of |
| 2560 | the sequence. */ |
| 2561 | |
| 2562 | static int |
| 2563 | deal_with_atomic_sequence (struct gdbarch *gdbarch, |
| 2564 | struct address_space *aspace, CORE_ADDR pc) |
| 2565 | { |
| 2566 | CORE_ADDR breaks[2] = {-1, -1}; |
| 2567 | CORE_ADDR loc = pc; |
| 2568 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ |
| 2569 | unsigned long insn; |
| 2570 | int insn_count; |
| 2571 | int index; |
| 2572 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ |
| 2573 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ |
| 2574 | |
| 2575 | if (pc & 0x01) |
| 2576 | return 0; |
| 2577 | |
| 2578 | insn = mips_fetch_instruction (gdbarch, loc); |
| 2579 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
| 2580 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) |
| 2581 | return 0; |
| 2582 | |
| 2583 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" |
| 2584 | instructions. */ |
| 2585 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) |
| 2586 | { |
| 2587 | int is_branch = 0; |
| 2588 | loc += MIPS_INSN32_SIZE; |
| 2589 | insn = mips_fetch_instruction (gdbarch, loc); |
| 2590 | |
| 2591 | /* Assume that there is at most one branch in the atomic |
| 2592 | sequence. If a branch is found, put a breakpoint in its |
| 2593 | destination address. */ |
| 2594 | switch (itype_op (insn)) |
| 2595 | { |
| 2596 | case 0: /* SPECIAL */ |
| 2597 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ |
| 2598 | return 0; /* fallback to the standard single-step code. */ |
| 2599 | break; |
| 2600 | case 1: /* REGIMM */ |
| 2601 | is_branch = ((itype_rt (insn) & 0xc0) == 0); /* B{LT,GE}Z* */ |
| 2602 | break; |
| 2603 | case 2: /* J */ |
| 2604 | case 3: /* JAL */ |
| 2605 | return 0; /* fallback to the standard single-step code. */ |
| 2606 | case 4: /* BEQ */ |
| 2607 | case 5: /* BNE */ |
| 2608 | case 6: /* BLEZ */ |
| 2609 | case 7: /* BGTZ */ |
| 2610 | case 20: /* BEQL */ |
| 2611 | case 21: /* BNEL */ |
| 2612 | case 22: /* BLEZL */ |
| 2613 | case 23: /* BGTTL */ |
| 2614 | is_branch = 1; |
| 2615 | break; |
| 2616 | case 17: /* COP1 */ |
| 2617 | case 18: /* COP2 */ |
| 2618 | case 19: /* COP3 */ |
| 2619 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ |
| 2620 | break; |
| 2621 | } |
| 2622 | if (is_branch) |
| 2623 | { |
| 2624 | branch_bp = loc + mips32_relative_offset (insn) + 4; |
| 2625 | if (last_breakpoint >= 1) |
| 2626 | return 0; /* More than one branch found, fallback to the |
| 2627 | standard single-step code. */ |
| 2628 | breaks[1] = branch_bp; |
| 2629 | last_breakpoint++; |
| 2630 | } |
| 2631 | |
| 2632 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) |
| 2633 | break; |
| 2634 | } |
| 2635 | |
| 2636 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ |
| 2637 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) |
| 2638 | return 0; |
| 2639 | |
| 2640 | loc += MIPS_INSN32_SIZE; |
| 2641 | |
| 2642 | /* Insert a breakpoint right after the end of the atomic sequence. */ |
| 2643 | breaks[0] = loc; |
| 2644 | |
| 2645 | /* Check for duplicated breakpoints. Check also for a breakpoint |
| 2646 | placed (branch instruction's destination) in the atomic sequence. */ |
| 2647 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
| 2648 | last_breakpoint = 0; |
| 2649 | |
| 2650 | /* Effectively inserts the breakpoints. */ |
| 2651 | for (index = 0; index <= last_breakpoint; index++) |
| 2652 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
| 2653 | |
| 2654 | return 1; |
| 2655 | } |
| 2656 | |
| 2657 | /* mips_software_single_step() is called just before we want to resume |
| 2658 | the inferior, if we want to single-step it but there is no hardware |
| 2659 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
| 2660 | the target of the coming instruction and breakpoint it. */ |
| 2661 | |
| 2662 | int |
| 2663 | mips_software_single_step (struct frame_info *frame) |
| 2664 | { |
| 2665 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2666 | struct address_space *aspace = get_frame_address_space (frame); |
| 2667 | CORE_ADDR pc, next_pc; |
| 2668 | |
| 2669 | pc = get_frame_pc (frame); |
| 2670 | if (deal_with_atomic_sequence (gdbarch, aspace, pc)) |
| 2671 | return 1; |
| 2672 | |
| 2673 | next_pc = mips_next_pc (frame, pc); |
| 2674 | |
| 2675 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
| 2676 | return 1; |
| 2677 | } |
| 2678 | |
| 2679 | /* Test whether the PC points to the return instruction at the |
| 2680 | end of a function. */ |
| 2681 | |
| 2682 | static int |
| 2683 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 2684 | { |
| 2685 | if (mips_pc_is_mips16 (pc)) |
| 2686 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
| 2687 | generates a "jr $ra"; other times it generates code to load |
| 2688 | the return address from the stack to an accessible register (such |
| 2689 | as $a3), then a "jr" using that register. This second case |
| 2690 | is almost impossible to distinguish from an indirect jump |
| 2691 | used for switch statements, so we don't even try. */ |
| 2692 | return mips_fetch_instruction (gdbarch, pc) == 0xe820; /* jr $ra */ |
| 2693 | else |
| 2694 | return mips_fetch_instruction (gdbarch, pc) == 0x3e00008; /* jr $ra */ |
| 2695 | } |
| 2696 | |
| 2697 | |
| 2698 | /* This fencepost looks highly suspicious to me. Removing it also |
| 2699 | seems suspicious as it could affect remote debugging across serial |
| 2700 | lines. */ |
| 2701 | |
| 2702 | static CORE_ADDR |
| 2703 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 2704 | { |
| 2705 | CORE_ADDR start_pc; |
| 2706 | CORE_ADDR fence; |
| 2707 | int instlen; |
| 2708 | int seen_adjsp = 0; |
| 2709 | struct inferior *inf; |
| 2710 | |
| 2711 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
| 2712 | start_pc = pc; |
| 2713 | fence = start_pc - heuristic_fence_post; |
| 2714 | if (start_pc == 0) |
| 2715 | return 0; |
| 2716 | |
| 2717 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
| 2718 | fence = VM_MIN_ADDRESS; |
| 2719 | |
| 2720 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
| 2721 | |
| 2722 | inf = current_inferior (); |
| 2723 | |
| 2724 | /* Search back for previous return. */ |
| 2725 | for (start_pc -= instlen;; start_pc -= instlen) |
| 2726 | if (start_pc < fence) |
| 2727 | { |
| 2728 | /* It's not clear to me why we reach this point when |
| 2729 | stop_soon, but with this test, at least we |
| 2730 | don't print out warnings for every child forked (eg, on |
| 2731 | decstation). 22apr93 rich@cygnus.com. */ |
| 2732 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
| 2733 | { |
| 2734 | static int blurb_printed = 0; |
| 2735 | |
| 2736 | warning (_("GDB can't find the start of the function at %s."), |
| 2737 | paddress (gdbarch, pc)); |
| 2738 | |
| 2739 | if (!blurb_printed) |
| 2740 | { |
| 2741 | /* This actually happens frequently in embedded |
| 2742 | development, when you first connect to a board |
| 2743 | and your stack pointer and pc are nowhere in |
| 2744 | particular. This message needs to give people |
| 2745 | in that situation enough information to |
| 2746 | determine that it's no big deal. */ |
| 2747 | printf_filtered ("\n\ |
| 2748 | GDB is unable to find the start of the function at %s\n\ |
| 2749 | and thus can't determine the size of that function's stack frame.\n\ |
| 2750 | This means that GDB may be unable to access that stack frame, or\n\ |
| 2751 | the frames below it.\n\ |
| 2752 | This problem is most likely caused by an invalid program counter or\n\ |
| 2753 | stack pointer.\n\ |
| 2754 | However, if you think GDB should simply search farther back\n\ |
| 2755 | from %s for code which looks like the beginning of a\n\ |
| 2756 | function, you can increase the range of the search using the `set\n\ |
| 2757 | heuristic-fence-post' command.\n", |
| 2758 | paddress (gdbarch, pc), paddress (gdbarch, pc)); |
| 2759 | blurb_printed = 1; |
| 2760 | } |
| 2761 | } |
| 2762 | |
| 2763 | return 0; |
| 2764 | } |
| 2765 | else if (mips_pc_is_mips16 (start_pc)) |
| 2766 | { |
| 2767 | unsigned short inst; |
| 2768 | |
| 2769 | /* On MIPS16, any one of the following is likely to be the |
| 2770 | start of a function: |
| 2771 | extend save |
| 2772 | save |
| 2773 | entry |
| 2774 | addiu sp,-n |
| 2775 | daddiu sp,-n |
| 2776 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
| 2777 | inst = mips_fetch_instruction (gdbarch, start_pc); |
| 2778 | if ((inst & 0xff80) == 0x6480) /* save */ |
| 2779 | { |
| 2780 | if (start_pc - instlen >= fence) |
| 2781 | { |
| 2782 | inst = mips_fetch_instruction (gdbarch, start_pc - instlen); |
| 2783 | if ((inst & 0xf800) == 0xf000) /* extend */ |
| 2784 | start_pc -= instlen; |
| 2785 | } |
| 2786 | break; |
| 2787 | } |
| 2788 | else if (((inst & 0xf81f) == 0xe809 |
| 2789 | && (inst & 0x700) != 0x700) /* entry */ |
| 2790 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ |
| 2791 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ |
| 2792 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ |
| 2793 | break; |
| 2794 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
| 2795 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
| 2796 | seen_adjsp = 1; |
| 2797 | else |
| 2798 | seen_adjsp = 0; |
| 2799 | } |
| 2800 | else if (mips_about_to_return (gdbarch, start_pc)) |
| 2801 | { |
| 2802 | /* Skip return and its delay slot. */ |
| 2803 | start_pc += 2 * MIPS_INSN32_SIZE; |
| 2804 | break; |
| 2805 | } |
| 2806 | |
| 2807 | return start_pc; |
| 2808 | } |
| 2809 | |
| 2810 | struct mips_objfile_private |
| 2811 | { |
| 2812 | bfd_size_type size; |
| 2813 | char *contents; |
| 2814 | }; |
| 2815 | |
| 2816 | /* According to the current ABI, should the type be passed in a |
| 2817 | floating-point register (assuming that there is space)? When there |
| 2818 | is no FPU, FP are not even considered as possible candidates for |
| 2819 | FP registers and, consequently this returns false - forces FP |
| 2820 | arguments into integer registers. */ |
| 2821 | |
| 2822 | static int |
| 2823 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
| 2824 | struct type *arg_type) |
| 2825 | { |
| 2826 | return ((typecode == TYPE_CODE_FLT |
| 2827 | || (MIPS_EABI (gdbarch) |
| 2828 | && (typecode == TYPE_CODE_STRUCT |
| 2829 | || typecode == TYPE_CODE_UNION) |
| 2830 | && TYPE_NFIELDS (arg_type) == 1 |
| 2831 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
| 2832 | == TYPE_CODE_FLT)) |
| 2833 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
| 2834 | } |
| 2835 | |
| 2836 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
| 2837 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
| 2838 | |
| 2839 | static int |
| 2840 | mips_type_needs_double_align (struct type *type) |
| 2841 | { |
| 2842 | enum type_code typecode = TYPE_CODE (type); |
| 2843 | |
| 2844 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
| 2845 | return 1; |
| 2846 | else if (typecode == TYPE_CODE_STRUCT) |
| 2847 | { |
| 2848 | if (TYPE_NFIELDS (type) < 1) |
| 2849 | return 0; |
| 2850 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); |
| 2851 | } |
| 2852 | else if (typecode == TYPE_CODE_UNION) |
| 2853 | { |
| 2854 | int i, n; |
| 2855 | |
| 2856 | n = TYPE_NFIELDS (type); |
| 2857 | for (i = 0; i < n; i++) |
| 2858 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) |
| 2859 | return 1; |
| 2860 | return 0; |
| 2861 | } |
| 2862 | return 0; |
| 2863 | } |
| 2864 | |
| 2865 | /* Adjust the address downward (direction of stack growth) so that it |
| 2866 | is correctly aligned for a new stack frame. */ |
| 2867 | static CORE_ADDR |
| 2868 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 2869 | { |
| 2870 | return align_down (addr, 16); |
| 2871 | } |
| 2872 | |
| 2873 | static CORE_ADDR |
| 2874 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 2875 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 2876 | int nargs, struct value **args, CORE_ADDR sp, |
| 2877 | int struct_return, CORE_ADDR struct_addr) |
| 2878 | { |
| 2879 | int argreg; |
| 2880 | int float_argreg; |
| 2881 | int argnum; |
| 2882 | int len = 0; |
| 2883 | int stack_offset = 0; |
| 2884 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2885 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2886 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
| 2887 | int regsize = mips_abi_regsize (gdbarch); |
| 2888 | |
| 2889 | /* For shared libraries, "t9" needs to point at the function |
| 2890 | address. */ |
| 2891 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
| 2892 | |
| 2893 | /* Set the return address register to point to the entry point of |
| 2894 | the program, where a breakpoint lies in wait. */ |
| 2895 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
| 2896 | |
| 2897 | /* First ensure that the stack and structure return address (if any) |
| 2898 | are properly aligned. The stack has to be at least 64-bit |
| 2899 | aligned even on 32-bit machines, because doubles must be 64-bit |
| 2900 | aligned. For n32 and n64, stack frames need to be 128-bit |
| 2901 | aligned, so we round to this widest known alignment. */ |
| 2902 | |
| 2903 | sp = align_down (sp, 16); |
| 2904 | struct_addr = align_down (struct_addr, 16); |
| 2905 | |
| 2906 | /* Now make space on the stack for the args. We allocate more |
| 2907 | than necessary for EABI, because the first few arguments are |
| 2908 | passed in registers, but that's OK. */ |
| 2909 | for (argnum = 0; argnum < nargs; argnum++) |
| 2910 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
| 2911 | sp -= align_up (len, 16); |
| 2912 | |
| 2913 | if (mips_debug) |
| 2914 | fprintf_unfiltered (gdb_stdlog, |
| 2915 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
| 2916 | paddress (gdbarch, sp), (long) align_up (len, 16)); |
| 2917 | |
| 2918 | /* Initialize the integer and float register pointers. */ |
| 2919 | argreg = MIPS_A0_REGNUM; |
| 2920 | float_argreg = mips_fpa0_regnum (gdbarch); |
| 2921 | |
| 2922 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
| 2923 | if (struct_return) |
| 2924 | { |
| 2925 | if (mips_debug) |
| 2926 | fprintf_unfiltered (gdb_stdlog, |
| 2927 | "mips_eabi_push_dummy_call: " |
| 2928 | "struct_return reg=%d %s\n", |
| 2929 | argreg, paddress (gdbarch, struct_addr)); |
| 2930 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
| 2931 | } |
| 2932 | |
| 2933 | /* Now load as many as possible of the first arguments into |
| 2934 | registers, and push the rest onto the stack. Loop thru args |
| 2935 | from first to last. */ |
| 2936 | for (argnum = 0; argnum < nargs; argnum++) |
| 2937 | { |
| 2938 | const gdb_byte *val; |
| 2939 | gdb_byte valbuf[MAX_REGISTER_SIZE]; |
| 2940 | struct value *arg = args[argnum]; |
| 2941 | struct type *arg_type = check_typedef (value_type (arg)); |
| 2942 | int len = TYPE_LENGTH (arg_type); |
| 2943 | enum type_code typecode = TYPE_CODE (arg_type); |
| 2944 | |
| 2945 | if (mips_debug) |
| 2946 | fprintf_unfiltered (gdb_stdlog, |
| 2947 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
| 2948 | argnum + 1, len, (int) typecode); |
| 2949 | |
| 2950 | /* Function pointer arguments to mips16 code need to be made into |
| 2951 | mips16 pointers. */ |
| 2952 | if (typecode == TYPE_CODE_PTR |
| 2953 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) |
| 2954 | { |
| 2955 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), |
| 2956 | len, byte_order); |
| 2957 | if (mips_pc_is_mips16 (addr)) |
| 2958 | { |
| 2959 | store_signed_integer (valbuf, len, byte_order, |
| 2960 | make_mips16_addr (addr)); |
| 2961 | val = valbuf; |
| 2962 | } |
| 2963 | else |
| 2964 | val = value_contents (arg); |
| 2965 | } |
| 2966 | /* The EABI passes structures that do not fit in a register by |
| 2967 | reference. */ |
| 2968 | else if (len > regsize |
| 2969 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
| 2970 | { |
| 2971 | store_unsigned_integer (valbuf, regsize, byte_order, |
| 2972 | value_address (arg)); |
| 2973 | typecode = TYPE_CODE_PTR; |
| 2974 | len = regsize; |
| 2975 | val = valbuf; |
| 2976 | if (mips_debug) |
| 2977 | fprintf_unfiltered (gdb_stdlog, " push"); |
| 2978 | } |
| 2979 | else |
| 2980 | val = value_contents (arg); |
| 2981 | |
| 2982 | /* 32-bit ABIs always start floating point arguments in an |
| 2983 | even-numbered floating point register. Round the FP register |
| 2984 | up before the check to see if there are any FP registers |
| 2985 | left. Non MIPS_EABI targets also pass the FP in the integer |
| 2986 | registers so also round up normal registers. */ |
| 2987 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
| 2988 | { |
| 2989 | if ((float_argreg & 1)) |
| 2990 | float_argreg++; |
| 2991 | } |
| 2992 | |
| 2993 | /* Floating point arguments passed in registers have to be |
| 2994 | treated specially. On 32-bit architectures, doubles |
| 2995 | are passed in register pairs; the even register gets |
| 2996 | the low word, and the odd register gets the high word. |
| 2997 | On non-EABI processors, the first two floating point arguments are |
| 2998 | also copied to general registers, because MIPS16 functions |
| 2999 | don't use float registers for arguments. This duplication of |
| 3000 | arguments in general registers can't hurt non-MIPS16 functions |
| 3001 | because those registers are normally skipped. */ |
| 3002 | /* MIPS_EABI squeezes a struct that contains a single floating |
| 3003 | point value into an FP register instead of pushing it onto the |
| 3004 | stack. */ |
| 3005 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
| 3006 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) |
| 3007 | { |
| 3008 | /* EABI32 will pass doubles in consecutive registers, even on |
| 3009 | 64-bit cores. At one time, we used to check the size of |
| 3010 | `float_argreg' to determine whether or not to pass doubles |
| 3011 | in consecutive registers, but this is not sufficient for |
| 3012 | making the ABI determination. */ |
| 3013 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) |
| 3014 | { |
| 3015 | int low_offset = gdbarch_byte_order (gdbarch) |
| 3016 | == BFD_ENDIAN_BIG ? 4 : 0; |
| 3017 | long regval; |
| 3018 | |
| 3019 | /* Write the low word of the double to the even register(s). */ |
| 3020 | regval = extract_signed_integer (val + low_offset, |
| 3021 | 4, byte_order); |
| 3022 | if (mips_debug) |
| 3023 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
| 3024 | float_argreg, phex (regval, 4)); |
| 3025 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
| 3026 | |
| 3027 | /* Write the high word of the double to the odd register(s). */ |
| 3028 | regval = extract_signed_integer (val + 4 - low_offset, |
| 3029 | 4, byte_order); |
| 3030 | if (mips_debug) |
| 3031 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
| 3032 | float_argreg, phex (regval, 4)); |
| 3033 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
| 3034 | } |
| 3035 | else |
| 3036 | { |
| 3037 | /* This is a floating point value that fits entirely |
| 3038 | in a single register. */ |
| 3039 | /* On 32 bit ABI's the float_argreg is further adjusted |
| 3040 | above to ensure that it is even register aligned. */ |
| 3041 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
| 3042 | if (mips_debug) |
| 3043 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
| 3044 | float_argreg, phex (regval, len)); |
| 3045 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
| 3046 | } |
| 3047 | } |
| 3048 | else |
| 3049 | { |
| 3050 | /* Copy the argument to general registers or the stack in |
| 3051 | register-sized pieces. Large arguments are split between |
| 3052 | registers and stack. */ |
| 3053 | /* Note: structs whose size is not a multiple of regsize |
| 3054 | are treated specially: Irix cc passes |
| 3055 | them in registers where gcc sometimes puts them on the |
| 3056 | stack. For maximum compatibility, we will put them in |
| 3057 | both places. */ |
| 3058 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
| 3059 | |
| 3060 | /* Note: Floating-point values that didn't fit into an FP |
| 3061 | register are only written to memory. */ |
| 3062 | while (len > 0) |
| 3063 | { |
| 3064 | /* Remember if the argument was written to the stack. */ |
| 3065 | int stack_used_p = 0; |
| 3066 | int partial_len = (len < regsize ? len : regsize); |
| 3067 | |
| 3068 | if (mips_debug) |
| 3069 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", |
| 3070 | partial_len); |
| 3071 | |
| 3072 | /* Write this portion of the argument to the stack. */ |
| 3073 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
| 3074 | || odd_sized_struct |
| 3075 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
| 3076 | { |
| 3077 | /* Should shorter than int integer values be |
| 3078 | promoted to int before being stored? */ |
| 3079 | int longword_offset = 0; |
| 3080 | CORE_ADDR addr; |
| 3081 | stack_used_p = 1; |
| 3082 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 3083 | { |
| 3084 | if (regsize == 8 |
| 3085 | && (typecode == TYPE_CODE_INT |
| 3086 | || typecode == TYPE_CODE_PTR |
| 3087 | || typecode == TYPE_CODE_FLT) && len <= 4) |
| 3088 | longword_offset = regsize - len; |
| 3089 | else if ((typecode == TYPE_CODE_STRUCT |
| 3090 | || typecode == TYPE_CODE_UNION) |
| 3091 | && TYPE_LENGTH (arg_type) < regsize) |
| 3092 | longword_offset = regsize - len; |
| 3093 | } |
| 3094 | |
| 3095 | if (mips_debug) |
| 3096 | { |
| 3097 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
| 3098 | paddress (gdbarch, stack_offset)); |
| 3099 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", |
| 3100 | paddress (gdbarch, longword_offset)); |
| 3101 | } |
| 3102 | |
| 3103 | addr = sp + stack_offset + longword_offset; |
| 3104 | |
| 3105 | if (mips_debug) |
| 3106 | { |
| 3107 | int i; |
| 3108 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
| 3109 | paddress (gdbarch, addr)); |
| 3110 | for (i = 0; i < partial_len; i++) |
| 3111 | { |
| 3112 | fprintf_unfiltered (gdb_stdlog, "%02x", |
| 3113 | val[i] & 0xff); |
| 3114 | } |
| 3115 | } |
| 3116 | write_memory (addr, val, partial_len); |
| 3117 | } |
| 3118 | |
| 3119 | /* Note!!! This is NOT an else clause. Odd sized |
| 3120 | structs may go thru BOTH paths. Floating point |
| 3121 | arguments will not. */ |
| 3122 | /* Write this portion of the argument to a general |
| 3123 | purpose register. */ |
| 3124 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
| 3125 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) |
| 3126 | { |
| 3127 | LONGEST regval = |
| 3128 | extract_signed_integer (val, partial_len, byte_order); |
| 3129 | |
| 3130 | if (mips_debug) |
| 3131 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
| 3132 | argreg, |
| 3133 | phex (regval, regsize)); |
| 3134 | regcache_cooked_write_signed (regcache, argreg, regval); |
| 3135 | argreg++; |
| 3136 | } |
| 3137 | |
| 3138 | len -= partial_len; |
| 3139 | val += partial_len; |
| 3140 | |
| 3141 | /* Compute the offset into the stack at which we will |
| 3142 | copy the next parameter. |
| 3143 | |
| 3144 | In the new EABI (and the NABI32), the stack_offset |
| 3145 | only needs to be adjusted when it has been used. */ |
| 3146 | |
| 3147 | if (stack_used_p) |
| 3148 | stack_offset += align_up (partial_len, regsize); |
| 3149 | } |
| 3150 | } |
| 3151 | if (mips_debug) |
| 3152 | fprintf_unfiltered (gdb_stdlog, "\n"); |
| 3153 | } |
| 3154 | |
| 3155 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
| 3156 | |
| 3157 | /* Return adjusted stack pointer. */ |
| 3158 | return sp; |
| 3159 | } |
| 3160 | |
| 3161 | /* Determine the return value convention being used. */ |
| 3162 | |
| 3163 | static enum return_value_convention |
| 3164 | mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type, |
| 3165 | struct type *type, struct regcache *regcache, |
| 3166 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 3167 | { |
| 3168 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3169 | int fp_return_type = 0; |
| 3170 | int offset, regnum, xfer; |
| 3171 | |
| 3172 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
| 3173 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 3174 | |
| 3175 | /* Floating point type? */ |
| 3176 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) |
| 3177 | { |
| 3178 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
| 3179 | fp_return_type = 1; |
| 3180 | /* Structs with a single field of float type |
| 3181 | are returned in a floating point register. */ |
| 3182 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 3183 | || TYPE_CODE (type) == TYPE_CODE_UNION) |
| 3184 | && TYPE_NFIELDS (type) == 1) |
| 3185 | { |
| 3186 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); |
| 3187 | |
| 3188 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) |
| 3189 | fp_return_type = 1; |
| 3190 | } |
| 3191 | } |
| 3192 | |
| 3193 | if (fp_return_type) |
| 3194 | { |
| 3195 | /* A floating-point value belongs in the least significant part |
| 3196 | of FP0/FP1. */ |
| 3197 | if (mips_debug) |
| 3198 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); |
| 3199 | regnum = mips_regnum (gdbarch)->fp0; |
| 3200 | } |
| 3201 | else |
| 3202 | { |
| 3203 | /* An integer value goes in V0/V1. */ |
| 3204 | if (mips_debug) |
| 3205 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); |
| 3206 | regnum = MIPS_V0_REGNUM; |
| 3207 | } |
| 3208 | for (offset = 0; |
| 3209 | offset < TYPE_LENGTH (type); |
| 3210 | offset += mips_abi_regsize (gdbarch), regnum++) |
| 3211 | { |
| 3212 | xfer = mips_abi_regsize (gdbarch); |
| 3213 | if (offset + xfer > TYPE_LENGTH (type)) |
| 3214 | xfer = TYPE_LENGTH (type) - offset; |
| 3215 | mips_xfer_register (gdbarch, regcache, |
| 3216 | gdbarch_num_regs (gdbarch) + regnum, xfer, |
| 3217 | gdbarch_byte_order (gdbarch), readbuf, writebuf, |
| 3218 | offset); |
| 3219 | } |
| 3220 | |
| 3221 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 3222 | } |
| 3223 | |
| 3224 | |
| 3225 | /* N32/N64 ABI stuff. */ |
| 3226 | |
| 3227 | /* Search for a naturally aligned double at OFFSET inside a struct |
| 3228 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point |
| 3229 | registers. */ |
| 3230 | |
| 3231 | static int |
| 3232 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
| 3233 | int offset) |
| 3234 | { |
| 3235 | int i; |
| 3236 | |
| 3237 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) |
| 3238 | return 0; |
| 3239 | |
| 3240 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
| 3241 | return 0; |
| 3242 | |
| 3243 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) |
| 3244 | return 0; |
| 3245 | |
| 3246 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) |
| 3247 | { |
| 3248 | int pos; |
| 3249 | struct type *field_type; |
| 3250 | |
| 3251 | /* We're only looking at normal fields. */ |
| 3252 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
| 3253 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
| 3254 | continue; |
| 3255 | |
| 3256 | /* If we have gone past the offset, there is no double to pass. */ |
| 3257 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; |
| 3258 | if (pos > offset) |
| 3259 | return 0; |
| 3260 | |
| 3261 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); |
| 3262 | |
| 3263 | /* If this field is entirely before the requested offset, go |
| 3264 | on to the next one. */ |
| 3265 | if (pos + TYPE_LENGTH (field_type) <= offset) |
| 3266 | continue; |
| 3267 | |
| 3268 | /* If this is our special aligned double, we can stop. */ |
| 3269 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT |
| 3270 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) |
| 3271 | return 1; |
| 3272 | |
| 3273 | /* This field starts at or before the requested offset, and |
| 3274 | overlaps it. If it is a structure, recurse inwards. */ |
| 3275 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
| 3276 | } |
| 3277 | |
| 3278 | return 0; |
| 3279 | } |
| 3280 | |
| 3281 | static CORE_ADDR |
| 3282 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 3283 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 3284 | int nargs, struct value **args, CORE_ADDR sp, |
| 3285 | int struct_return, CORE_ADDR struct_addr) |
| 3286 | { |
| 3287 | int argreg; |
| 3288 | int float_argreg; |
| 3289 | int argnum; |
| 3290 | int len = 0; |
| 3291 | int stack_offset = 0; |
| 3292 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3293 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 3294 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
| 3295 | |
| 3296 | /* For shared libraries, "t9" needs to point at the function |
| 3297 | address. */ |
| 3298 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
| 3299 | |
| 3300 | /* Set the return address register to point to the entry point of |
| 3301 | the program, where a breakpoint lies in wait. */ |
| 3302 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
| 3303 | |
| 3304 | /* First ensure that the stack and structure return address (if any) |
| 3305 | are properly aligned. The stack has to be at least 64-bit |
| 3306 | aligned even on 32-bit machines, because doubles must be 64-bit |
| 3307 | aligned. For n32 and n64, stack frames need to be 128-bit |
| 3308 | aligned, so we round to this widest known alignment. */ |
| 3309 | |
| 3310 | sp = align_down (sp, 16); |
| 3311 | struct_addr = align_down (struct_addr, 16); |
| 3312 | |
| 3313 | /* Now make space on the stack for the args. */ |
| 3314 | for (argnum = 0; argnum < nargs; argnum++) |
| 3315 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
| 3316 | sp -= align_up (len, 16); |
| 3317 | |
| 3318 | if (mips_debug) |
| 3319 | fprintf_unfiltered (gdb_stdlog, |
| 3320 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
| 3321 | paddress (gdbarch, sp), (long) align_up (len, 16)); |
| 3322 | |
| 3323 | /* Initialize the integer and float register pointers. */ |
| 3324 | argreg = MIPS_A0_REGNUM; |
| 3325 | float_argreg = mips_fpa0_regnum (gdbarch); |
| 3326 | |
| 3327 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
| 3328 | if (struct_return) |
| 3329 | { |
| 3330 | if (mips_debug) |
| 3331 | fprintf_unfiltered (gdb_stdlog, |
| 3332 | "mips_n32n64_push_dummy_call: " |
| 3333 | "struct_return reg=%d %s\n", |
| 3334 | argreg, paddress (gdbarch, struct_addr)); |
| 3335 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
| 3336 | } |
| 3337 | |
| 3338 | /* Now load as many as possible of the first arguments into |
| 3339 | registers, and push the rest onto the stack. Loop thru args |
| 3340 | from first to last. */ |
| 3341 | for (argnum = 0; argnum < nargs; argnum++) |
| 3342 | { |
| 3343 | const gdb_byte *val; |
| 3344 | struct value *arg = args[argnum]; |
| 3345 | struct type *arg_type = check_typedef (value_type (arg)); |
| 3346 | int len = TYPE_LENGTH (arg_type); |
| 3347 | enum type_code typecode = TYPE_CODE (arg_type); |
| 3348 | |
| 3349 | if (mips_debug) |
| 3350 | fprintf_unfiltered (gdb_stdlog, |
| 3351 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
| 3352 | argnum + 1, len, (int) typecode); |
| 3353 | |
| 3354 | val = value_contents (arg); |
| 3355 | |
| 3356 | /* A 128-bit long double value requires an even-odd pair of |
| 3357 | floating-point registers. */ |
| 3358 | if (len == 16 |
| 3359 | && fp_register_arg_p (gdbarch, typecode, arg_type) |
| 3360 | && (float_argreg & 1)) |
| 3361 | { |
| 3362 | float_argreg++; |
| 3363 | argreg++; |
| 3364 | } |
| 3365 | |
| 3366 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
| 3367 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
| 3368 | { |
| 3369 | /* This is a floating point value that fits entirely |
| 3370 | in a single register or a pair of registers. */ |
| 3371 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
| 3372 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
| 3373 | if (mips_debug) |
| 3374 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
| 3375 | float_argreg, phex (regval, reglen)); |
| 3376 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
| 3377 | |
| 3378 | if (mips_debug) |
| 3379 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
| 3380 | argreg, phex (regval, reglen)); |
| 3381 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 3382 | float_argreg++; |
| 3383 | argreg++; |
| 3384 | if (len == 16) |
| 3385 | { |
| 3386 | regval = extract_unsigned_integer (val + reglen, |
| 3387 | reglen, byte_order); |
| 3388 | if (mips_debug) |
| 3389 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
| 3390 | float_argreg, phex (regval, reglen)); |
| 3391 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
| 3392 | |
| 3393 | if (mips_debug) |
| 3394 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
| 3395 | argreg, phex (regval, reglen)); |
| 3396 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 3397 | float_argreg++; |
| 3398 | argreg++; |
| 3399 | } |
| 3400 | } |
| 3401 | else |
| 3402 | { |
| 3403 | /* Copy the argument to general registers or the stack in |
| 3404 | register-sized pieces. Large arguments are split between |
| 3405 | registers and stack. */ |
| 3406 | /* For N32/N64, structs, unions, or other composite types are |
| 3407 | treated as a sequence of doublewords, and are passed in integer |
| 3408 | or floating point registers as though they were simple scalar |
| 3409 | parameters to the extent that they fit, with any excess on the |
| 3410 | stack packed according to the normal memory layout of the |
| 3411 | object. |
| 3412 | The caller does not reserve space for the register arguments; |
| 3413 | the callee is responsible for reserving it if required. */ |
| 3414 | /* Note: Floating-point values that didn't fit into an FP |
| 3415 | register are only written to memory. */ |
| 3416 | while (len > 0) |
| 3417 | { |
| 3418 | /* Remember if the argument was written to the stack. */ |
| 3419 | int stack_used_p = 0; |
| 3420 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
| 3421 | |
| 3422 | if (mips_debug) |
| 3423 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", |
| 3424 | partial_len); |
| 3425 | |
| 3426 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
| 3427 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); |
| 3428 | |
| 3429 | /* Write this portion of the argument to the stack. */ |
| 3430 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
| 3431 | { |
| 3432 | /* Should shorter than int integer values be |
| 3433 | promoted to int before being stored? */ |
| 3434 | int longword_offset = 0; |
| 3435 | CORE_ADDR addr; |
| 3436 | stack_used_p = 1; |
| 3437 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 3438 | { |
| 3439 | if ((typecode == TYPE_CODE_INT |
| 3440 | || typecode == TYPE_CODE_PTR) |
| 3441 | && len <= 4) |
| 3442 | longword_offset = MIPS64_REGSIZE - len; |
| 3443 | } |
| 3444 | |
| 3445 | if (mips_debug) |
| 3446 | { |
| 3447 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
| 3448 | paddress (gdbarch, stack_offset)); |
| 3449 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", |
| 3450 | paddress (gdbarch, longword_offset)); |
| 3451 | } |
| 3452 | |
| 3453 | addr = sp + stack_offset + longword_offset; |
| 3454 | |
| 3455 | if (mips_debug) |
| 3456 | { |
| 3457 | int i; |
| 3458 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
| 3459 | paddress (gdbarch, addr)); |
| 3460 | for (i = 0; i < partial_len; i++) |
| 3461 | { |
| 3462 | fprintf_unfiltered (gdb_stdlog, "%02x", |
| 3463 | val[i] & 0xff); |
| 3464 | } |
| 3465 | } |
| 3466 | write_memory (addr, val, partial_len); |
| 3467 | } |
| 3468 | |
| 3469 | /* Note!!! This is NOT an else clause. Odd sized |
| 3470 | structs may go thru BOTH paths. */ |
| 3471 | /* Write this portion of the argument to a general |
| 3472 | purpose register. */ |
| 3473 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
| 3474 | { |
| 3475 | LONGEST regval; |
| 3476 | |
| 3477 | /* Sign extend pointers, 32-bit integers and signed |
| 3478 | 16-bit and 8-bit integers; everything else is taken |
| 3479 | as is. */ |
| 3480 | |
| 3481 | if ((partial_len == 4 |
| 3482 | && (typecode == TYPE_CODE_PTR |
| 3483 | || typecode == TYPE_CODE_INT)) |
| 3484 | || (partial_len < 4 |
| 3485 | && typecode == TYPE_CODE_INT |
| 3486 | && !TYPE_UNSIGNED (arg_type))) |
| 3487 | regval = extract_signed_integer (val, partial_len, |
| 3488 | byte_order); |
| 3489 | else |
| 3490 | regval = extract_unsigned_integer (val, partial_len, |
| 3491 | byte_order); |
| 3492 | |
| 3493 | /* A non-floating-point argument being passed in a |
| 3494 | general register. If a struct or union, and if |
| 3495 | the remaining length is smaller than the register |
| 3496 | size, we have to adjust the register value on |
| 3497 | big endian targets. |
| 3498 | |
| 3499 | It does not seem to be necessary to do the |
| 3500 | same for integral types. */ |
| 3501 | |
| 3502 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
| 3503 | && partial_len < MIPS64_REGSIZE |
| 3504 | && (typecode == TYPE_CODE_STRUCT |
| 3505 | || typecode == TYPE_CODE_UNION)) |
| 3506 | regval <<= ((MIPS64_REGSIZE - partial_len) |
| 3507 | * TARGET_CHAR_BIT); |
| 3508 | |
| 3509 | if (mips_debug) |
| 3510 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
| 3511 | argreg, |
| 3512 | phex (regval, MIPS64_REGSIZE)); |
| 3513 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 3514 | |
| 3515 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
| 3516 | TYPE_LENGTH (arg_type) - len)) |
| 3517 | { |
| 3518 | if (mips_debug) |
| 3519 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", |
| 3520 | float_argreg, |
| 3521 | phex (regval, MIPS64_REGSIZE)); |
| 3522 | regcache_cooked_write_unsigned (regcache, float_argreg, |
| 3523 | regval); |
| 3524 | } |
| 3525 | |
| 3526 | float_argreg++; |
| 3527 | argreg++; |
| 3528 | } |
| 3529 | |
| 3530 | len -= partial_len; |
| 3531 | val += partial_len; |
| 3532 | |
| 3533 | /* Compute the offset into the stack at which we will |
| 3534 | copy the next parameter. |
| 3535 | |
| 3536 | In N32 (N64?), the stack_offset only needs to be |
| 3537 | adjusted when it has been used. */ |
| 3538 | |
| 3539 | if (stack_used_p) |
| 3540 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
| 3541 | } |
| 3542 | } |
| 3543 | if (mips_debug) |
| 3544 | fprintf_unfiltered (gdb_stdlog, "\n"); |
| 3545 | } |
| 3546 | |
| 3547 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
| 3548 | |
| 3549 | /* Return adjusted stack pointer. */ |
| 3550 | return sp; |
| 3551 | } |
| 3552 | |
| 3553 | static enum return_value_convention |
| 3554 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
| 3555 | struct type *type, struct regcache *regcache, |
| 3556 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 3557 | { |
| 3558 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3559 | |
| 3560 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 |
| 3561 | |
| 3562 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 |
| 3563 | if needed), as appropriate for the type. Composite results (struct, |
| 3564 | union, or array) are returned in $2/$f0 and $3/$f2 according to the |
| 3565 | following rules: |
| 3566 | |
| 3567 | * A struct with only one or two floating point fields is returned in $f0 |
| 3568 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX |
| 3569 | case. |
| 3570 | |
| 3571 | * Any other composite results of at most 128 bits are returned in |
| 3572 | $2 (first 64 bits) and $3 (remainder, if necessary). |
| 3573 | |
| 3574 | * Larger composite results are handled by converting the function to a |
| 3575 | procedure with an implicit first parameter, which is a pointer to an area |
| 3576 | reserved by the caller to receive the result. [The o32-bit ABI requires |
| 3577 | that all composite results be handled by conversion to implicit first |
| 3578 | parameters. The MIPS/SGI Fortran implementation has always made a |
| 3579 | specific exception to return COMPLEX results in the floating point |
| 3580 | registers.] */ |
| 3581 | |
| 3582 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
| 3583 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 3584 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
| 3585 | && TYPE_LENGTH (type) == 16 |
| 3586 | && tdep->mips_fpu_type != MIPS_FPU_NONE) |
| 3587 | { |
| 3588 | /* A 128-bit floating-point value fills both $f0 and $f2. The |
| 3589 | two registers are used in the same as memory order, so the |
| 3590 | eight bytes with the lower memory address are in $f0. */ |
| 3591 | if (mips_debug) |
| 3592 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); |
| 3593 | mips_xfer_register (gdbarch, regcache, |
| 3594 | gdbarch_num_regs (gdbarch) |
| 3595 | + mips_regnum (gdbarch)->fp0, |
| 3596 | 8, gdbarch_byte_order (gdbarch), |
| 3597 | readbuf, writebuf, 0); |
| 3598 | mips_xfer_register (gdbarch, regcache, |
| 3599 | gdbarch_num_regs (gdbarch) |
| 3600 | + mips_regnum (gdbarch)->fp0 + 2, |
| 3601 | 8, gdbarch_byte_order (gdbarch), |
| 3602 | readbuf ? readbuf + 8 : readbuf, |
| 3603 | writebuf ? writebuf + 8 : writebuf, 0); |
| 3604 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 3605 | } |
| 3606 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
| 3607 | && tdep->mips_fpu_type != MIPS_FPU_NONE) |
| 3608 | { |
| 3609 | /* A single or double floating-point value that fits in FP0. */ |
| 3610 | if (mips_debug) |
| 3611 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); |
| 3612 | mips_xfer_register (gdbarch, regcache, |
| 3613 | gdbarch_num_regs (gdbarch) |
| 3614 | + mips_regnum (gdbarch)->fp0, |
| 3615 | TYPE_LENGTH (type), |
| 3616 | gdbarch_byte_order (gdbarch), |
| 3617 | readbuf, writebuf, 0); |
| 3618 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 3619 | } |
| 3620 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 3621 | && TYPE_NFIELDS (type) <= 2 |
| 3622 | && TYPE_NFIELDS (type) >= 1 |
| 3623 | && ((TYPE_NFIELDS (type) == 1 |
| 3624 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
| 3625 | == TYPE_CODE_FLT)) |
| 3626 | || (TYPE_NFIELDS (type) == 2 |
| 3627 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
| 3628 | == TYPE_CODE_FLT) |
| 3629 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
| 3630 | == TYPE_CODE_FLT)))) |
| 3631 | { |
| 3632 | /* A struct that contains one or two floats. Each value is part |
| 3633 | in the least significant part of their floating point |
| 3634 | register (or GPR, for soft float). */ |
| 3635 | int regnum; |
| 3636 | int field; |
| 3637 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
| 3638 | ? mips_regnum (gdbarch)->fp0 |
| 3639 | : MIPS_V0_REGNUM); |
| 3640 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
| 3641 | { |
| 3642 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) |
| 3643 | / TARGET_CHAR_BIT); |
| 3644 | if (mips_debug) |
| 3645 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", |
| 3646 | offset); |
| 3647 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
| 3648 | { |
| 3649 | /* A 16-byte long double field goes in two consecutive |
| 3650 | registers. */ |
| 3651 | mips_xfer_register (gdbarch, regcache, |
| 3652 | gdbarch_num_regs (gdbarch) + regnum, |
| 3653 | 8, |
| 3654 | gdbarch_byte_order (gdbarch), |
| 3655 | readbuf, writebuf, offset); |
| 3656 | mips_xfer_register (gdbarch, regcache, |
| 3657 | gdbarch_num_regs (gdbarch) + regnum + 1, |
| 3658 | 8, |
| 3659 | gdbarch_byte_order (gdbarch), |
| 3660 | readbuf, writebuf, offset + 8); |
| 3661 | } |
| 3662 | else |
| 3663 | mips_xfer_register (gdbarch, regcache, |
| 3664 | gdbarch_num_regs (gdbarch) + regnum, |
| 3665 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
| 3666 | gdbarch_byte_order (gdbarch), |
| 3667 | readbuf, writebuf, offset); |
| 3668 | } |
| 3669 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 3670 | } |
| 3671 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 3672 | || TYPE_CODE (type) == TYPE_CODE_UNION |
| 3673 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) |
| 3674 | { |
| 3675 | /* A composite type. Extract the left justified value, |
| 3676 | regardless of the byte order. I.e. DO NOT USE |
| 3677 | mips_xfer_lower. */ |
| 3678 | int offset; |
| 3679 | int regnum; |
| 3680 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
| 3681 | offset < TYPE_LENGTH (type); |
| 3682 | offset += register_size (gdbarch, regnum), regnum++) |
| 3683 | { |
| 3684 | int xfer = register_size (gdbarch, regnum); |
| 3685 | if (offset + xfer > TYPE_LENGTH (type)) |
| 3686 | xfer = TYPE_LENGTH (type) - offset; |
| 3687 | if (mips_debug) |
| 3688 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", |
| 3689 | offset, xfer, regnum); |
| 3690 | mips_xfer_register (gdbarch, regcache, |
| 3691 | gdbarch_num_regs (gdbarch) + regnum, |
| 3692 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
| 3693 | offset); |
| 3694 | } |
| 3695 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 3696 | } |
| 3697 | else |
| 3698 | { |
| 3699 | /* A scalar extract each part but least-significant-byte |
| 3700 | justified. */ |
| 3701 | int offset; |
| 3702 | int regnum; |
| 3703 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
| 3704 | offset < TYPE_LENGTH (type); |
| 3705 | offset += register_size (gdbarch, regnum), regnum++) |
| 3706 | { |
| 3707 | int xfer = register_size (gdbarch, regnum); |
| 3708 | if (offset + xfer > TYPE_LENGTH (type)) |
| 3709 | xfer = TYPE_LENGTH (type) - offset; |
| 3710 | if (mips_debug) |
| 3711 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", |
| 3712 | offset, xfer, regnum); |
| 3713 | mips_xfer_register (gdbarch, regcache, |
| 3714 | gdbarch_num_regs (gdbarch) + regnum, |
| 3715 | xfer, gdbarch_byte_order (gdbarch), |
| 3716 | readbuf, writebuf, offset); |
| 3717 | } |
| 3718 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 3719 | } |
| 3720 | } |
| 3721 | |
| 3722 | /* O32 ABI stuff. */ |
| 3723 | |
| 3724 | static CORE_ADDR |
| 3725 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 3726 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 3727 | int nargs, struct value **args, CORE_ADDR sp, |
| 3728 | int struct_return, CORE_ADDR struct_addr) |
| 3729 | { |
| 3730 | int argreg; |
| 3731 | int float_argreg; |
| 3732 | int argnum; |
| 3733 | int len = 0; |
| 3734 | int stack_offset = 0; |
| 3735 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3736 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 3737 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
| 3738 | |
| 3739 | /* For shared libraries, "t9" needs to point at the function |
| 3740 | address. */ |
| 3741 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
| 3742 | |
| 3743 | /* Set the return address register to point to the entry point of |
| 3744 | the program, where a breakpoint lies in wait. */ |
| 3745 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
| 3746 | |
| 3747 | /* First ensure that the stack and structure return address (if any) |
| 3748 | are properly aligned. The stack has to be at least 64-bit |
| 3749 | aligned even on 32-bit machines, because doubles must be 64-bit |
| 3750 | aligned. For n32 and n64, stack frames need to be 128-bit |
| 3751 | aligned, so we round to this widest known alignment. */ |
| 3752 | |
| 3753 | sp = align_down (sp, 16); |
| 3754 | struct_addr = align_down (struct_addr, 16); |
| 3755 | |
| 3756 | /* Now make space on the stack for the args. */ |
| 3757 | for (argnum = 0; argnum < nargs; argnum++) |
| 3758 | { |
| 3759 | struct type *arg_type = check_typedef (value_type (args[argnum])); |
| 3760 | int arglen = TYPE_LENGTH (arg_type); |
| 3761 | |
| 3762 | /* Align to double-word if necessary. */ |
| 3763 | if (mips_type_needs_double_align (arg_type)) |
| 3764 | len = align_up (len, MIPS32_REGSIZE * 2); |
| 3765 | /* Allocate space on the stack. */ |
| 3766 | len += align_up (arglen, MIPS32_REGSIZE); |
| 3767 | } |
| 3768 | sp -= align_up (len, 16); |
| 3769 | |
| 3770 | if (mips_debug) |
| 3771 | fprintf_unfiltered (gdb_stdlog, |
| 3772 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
| 3773 | paddress (gdbarch, sp), (long) align_up (len, 16)); |
| 3774 | |
| 3775 | /* Initialize the integer and float register pointers. */ |
| 3776 | argreg = MIPS_A0_REGNUM; |
| 3777 | float_argreg = mips_fpa0_regnum (gdbarch); |
| 3778 | |
| 3779 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
| 3780 | if (struct_return) |
| 3781 | { |
| 3782 | if (mips_debug) |
| 3783 | fprintf_unfiltered (gdb_stdlog, |
| 3784 | "mips_o32_push_dummy_call: " |
| 3785 | "struct_return reg=%d %s\n", |
| 3786 | argreg, paddress (gdbarch, struct_addr)); |
| 3787 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
| 3788 | stack_offset += MIPS32_REGSIZE; |
| 3789 | } |
| 3790 | |
| 3791 | /* Now load as many as possible of the first arguments into |
| 3792 | registers, and push the rest onto the stack. Loop thru args |
| 3793 | from first to last. */ |
| 3794 | for (argnum = 0; argnum < nargs; argnum++) |
| 3795 | { |
| 3796 | const gdb_byte *val; |
| 3797 | struct value *arg = args[argnum]; |
| 3798 | struct type *arg_type = check_typedef (value_type (arg)); |
| 3799 | int len = TYPE_LENGTH (arg_type); |
| 3800 | enum type_code typecode = TYPE_CODE (arg_type); |
| 3801 | |
| 3802 | if (mips_debug) |
| 3803 | fprintf_unfiltered (gdb_stdlog, |
| 3804 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
| 3805 | argnum + 1, len, (int) typecode); |
| 3806 | |
| 3807 | val = value_contents (arg); |
| 3808 | |
| 3809 | /* 32-bit ABIs always start floating point arguments in an |
| 3810 | even-numbered floating point register. Round the FP register |
| 3811 | up before the check to see if there are any FP registers |
| 3812 | left. O32/O64 targets also pass the FP in the integer |
| 3813 | registers so also round up normal registers. */ |
| 3814 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
| 3815 | { |
| 3816 | if ((float_argreg & 1)) |
| 3817 | float_argreg++; |
| 3818 | } |
| 3819 | |
| 3820 | /* Floating point arguments passed in registers have to be |
| 3821 | treated specially. On 32-bit architectures, doubles |
| 3822 | are passed in register pairs; the even register gets |
| 3823 | the low word, and the odd register gets the high word. |
| 3824 | On O32/O64, the first two floating point arguments are |
| 3825 | also copied to general registers, because MIPS16 functions |
| 3826 | don't use float registers for arguments. This duplication of |
| 3827 | arguments in general registers can't hurt non-MIPS16 functions |
| 3828 | because those registers are normally skipped. */ |
| 3829 | |
| 3830 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
| 3831 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) |
| 3832 | { |
| 3833 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
| 3834 | { |
| 3835 | int low_offset = gdbarch_byte_order (gdbarch) |
| 3836 | == BFD_ENDIAN_BIG ? 4 : 0; |
| 3837 | unsigned long regval; |
| 3838 | |
| 3839 | /* Write the low word of the double to the even register(s). */ |
| 3840 | regval = extract_unsigned_integer (val + low_offset, |
| 3841 | 4, byte_order); |
| 3842 | if (mips_debug) |
| 3843 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
| 3844 | float_argreg, phex (regval, 4)); |
| 3845 | regcache_cooked_write_unsigned (regcache, |
| 3846 | float_argreg++, regval); |
| 3847 | if (mips_debug) |
| 3848 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
| 3849 | argreg, phex (regval, 4)); |
| 3850 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
| 3851 | |
| 3852 | /* Write the high word of the double to the odd register(s). */ |
| 3853 | regval = extract_unsigned_integer (val + 4 - low_offset, |
| 3854 | 4, byte_order); |
| 3855 | if (mips_debug) |
| 3856 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
| 3857 | float_argreg, phex (regval, 4)); |
| 3858 | regcache_cooked_write_unsigned (regcache, |
| 3859 | float_argreg++, regval); |
| 3860 | |
| 3861 | if (mips_debug) |
| 3862 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
| 3863 | argreg, phex (regval, 4)); |
| 3864 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
| 3865 | } |
| 3866 | else |
| 3867 | { |
| 3868 | /* This is a floating point value that fits entirely |
| 3869 | in a single register. */ |
| 3870 | /* On 32 bit ABI's the float_argreg is further adjusted |
| 3871 | above to ensure that it is even register aligned. */ |
| 3872 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
| 3873 | if (mips_debug) |
| 3874 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
| 3875 | float_argreg, phex (regval, len)); |
| 3876 | regcache_cooked_write_unsigned (regcache, |
| 3877 | float_argreg++, regval); |
| 3878 | /* Although two FP registers are reserved for each |
| 3879 | argument, only one corresponding integer register is |
| 3880 | reserved. */ |
| 3881 | if (mips_debug) |
| 3882 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
| 3883 | argreg, phex (regval, len)); |
| 3884 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
| 3885 | } |
| 3886 | /* Reserve space for the FP register. */ |
| 3887 | stack_offset += align_up (len, MIPS32_REGSIZE); |
| 3888 | } |
| 3889 | else |
| 3890 | { |
| 3891 | /* Copy the argument to general registers or the stack in |
| 3892 | register-sized pieces. Large arguments are split between |
| 3893 | registers and stack. */ |
| 3894 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
| 3895 | are treated specially: Irix cc passes |
| 3896 | them in registers where gcc sometimes puts them on the |
| 3897 | stack. For maximum compatibility, we will put them in |
| 3898 | both places. */ |
| 3899 | int odd_sized_struct = (len > MIPS32_REGSIZE |
| 3900 | && len % MIPS32_REGSIZE != 0); |
| 3901 | /* Structures should be aligned to eight bytes (even arg registers) |
| 3902 | on MIPS_ABI_O32, if their first member has double precision. */ |
| 3903 | if (mips_type_needs_double_align (arg_type)) |
| 3904 | { |
| 3905 | if ((argreg & 1)) |
| 3906 | { |
| 3907 | argreg++; |
| 3908 | stack_offset += MIPS32_REGSIZE; |
| 3909 | } |
| 3910 | } |
| 3911 | while (len > 0) |
| 3912 | { |
| 3913 | /* Remember if the argument was written to the stack. */ |
| 3914 | int stack_used_p = 0; |
| 3915 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
| 3916 | |
| 3917 | if (mips_debug) |
| 3918 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", |
| 3919 | partial_len); |
| 3920 | |
| 3921 | /* Write this portion of the argument to the stack. */ |
| 3922 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
| 3923 | || odd_sized_struct) |
| 3924 | { |
| 3925 | /* Should shorter than int integer values be |
| 3926 | promoted to int before being stored? */ |
| 3927 | int longword_offset = 0; |
| 3928 | CORE_ADDR addr; |
| 3929 | stack_used_p = 1; |
| 3930 | |
| 3931 | if (mips_debug) |
| 3932 | { |
| 3933 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
| 3934 | paddress (gdbarch, stack_offset)); |
| 3935 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", |
| 3936 | paddress (gdbarch, longword_offset)); |
| 3937 | } |
| 3938 | |
| 3939 | addr = sp + stack_offset + longword_offset; |
| 3940 | |
| 3941 | if (mips_debug) |
| 3942 | { |
| 3943 | int i; |
| 3944 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
| 3945 | paddress (gdbarch, addr)); |
| 3946 | for (i = 0; i < partial_len; i++) |
| 3947 | { |
| 3948 | fprintf_unfiltered (gdb_stdlog, "%02x", |
| 3949 | val[i] & 0xff); |
| 3950 | } |
| 3951 | } |
| 3952 | write_memory (addr, val, partial_len); |
| 3953 | } |
| 3954 | |
| 3955 | /* Note!!! This is NOT an else clause. Odd sized |
| 3956 | structs may go thru BOTH paths. */ |
| 3957 | /* Write this portion of the argument to a general |
| 3958 | purpose register. */ |
| 3959 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
| 3960 | { |
| 3961 | LONGEST regval = extract_signed_integer (val, partial_len, |
| 3962 | byte_order); |
| 3963 | /* Value may need to be sign extended, because |
| 3964 | mips_isa_regsize() != mips_abi_regsize(). */ |
| 3965 | |
| 3966 | /* A non-floating-point argument being passed in a |
| 3967 | general register. If a struct or union, and if |
| 3968 | the remaining length is smaller than the register |
| 3969 | size, we have to adjust the register value on |
| 3970 | big endian targets. |
| 3971 | |
| 3972 | It does not seem to be necessary to do the |
| 3973 | same for integral types. |
| 3974 | |
| 3975 | Also don't do this adjustment on O64 binaries. |
| 3976 | |
| 3977 | cagney/2001-07-23: gdb/179: Also, GCC, when |
| 3978 | outputting LE O32 with sizeof (struct) < |
| 3979 | mips_abi_regsize(), generates a left shift |
| 3980 | as part of storing the argument in a register |
| 3981 | (the left shift isn't generated when |
| 3982 | sizeof (struct) >= mips_abi_regsize()). Since |
| 3983 | it is quite possible that this is GCC |
| 3984 | contradicting the LE/O32 ABI, GDB has not been |
| 3985 | adjusted to accommodate this. Either someone |
| 3986 | needs to demonstrate that the LE/O32 ABI |
| 3987 | specifies such a left shift OR this new ABI gets |
| 3988 | identified as such and GDB gets tweaked |
| 3989 | accordingly. */ |
| 3990 | |
| 3991 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
| 3992 | && partial_len < MIPS32_REGSIZE |
| 3993 | && (typecode == TYPE_CODE_STRUCT |
| 3994 | || typecode == TYPE_CODE_UNION)) |
| 3995 | regval <<= ((MIPS32_REGSIZE - partial_len) |
| 3996 | * TARGET_CHAR_BIT); |
| 3997 | |
| 3998 | if (mips_debug) |
| 3999 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
| 4000 | argreg, |
| 4001 | phex (regval, MIPS32_REGSIZE)); |
| 4002 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 4003 | argreg++; |
| 4004 | |
| 4005 | /* Prevent subsequent floating point arguments from |
| 4006 | being passed in floating point registers. */ |
| 4007 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
| 4008 | } |
| 4009 | |
| 4010 | len -= partial_len; |
| 4011 | val += partial_len; |
| 4012 | |
| 4013 | /* Compute the offset into the stack at which we will |
| 4014 | copy the next parameter. |
| 4015 | |
| 4016 | In older ABIs, the caller reserved space for |
| 4017 | registers that contained arguments. This was loosely |
| 4018 | refered to as their "home". Consequently, space is |
| 4019 | always allocated. */ |
| 4020 | |
| 4021 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
| 4022 | } |
| 4023 | } |
| 4024 | if (mips_debug) |
| 4025 | fprintf_unfiltered (gdb_stdlog, "\n"); |
| 4026 | } |
| 4027 | |
| 4028 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
| 4029 | |
| 4030 | /* Return adjusted stack pointer. */ |
| 4031 | return sp; |
| 4032 | } |
| 4033 | |
| 4034 | static enum return_value_convention |
| 4035 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type, |
| 4036 | struct type *type, struct regcache *regcache, |
| 4037 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 4038 | { |
| 4039 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 4040 | |
| 4041 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 4042 | || TYPE_CODE (type) == TYPE_CODE_UNION |
| 4043 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) |
| 4044 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 4045 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
| 4046 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) |
| 4047 | { |
| 4048 | /* A single-precision floating-point value. It fits in the |
| 4049 | least significant part of FP0. */ |
| 4050 | if (mips_debug) |
| 4051 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); |
| 4052 | mips_xfer_register (gdbarch, regcache, |
| 4053 | gdbarch_num_regs (gdbarch) |
| 4054 | + mips_regnum (gdbarch)->fp0, |
| 4055 | TYPE_LENGTH (type), |
| 4056 | gdbarch_byte_order (gdbarch), |
| 4057 | readbuf, writebuf, 0); |
| 4058 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 4059 | } |
| 4060 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
| 4061 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) |
| 4062 | { |
| 4063 | /* A double-precision floating-point value. The most |
| 4064 | significant part goes in FP1, and the least significant in |
| 4065 | FP0. */ |
| 4066 | if (mips_debug) |
| 4067 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); |
| 4068 | switch (gdbarch_byte_order (gdbarch)) |
| 4069 | { |
| 4070 | case BFD_ENDIAN_LITTLE: |
| 4071 | mips_xfer_register (gdbarch, regcache, |
| 4072 | gdbarch_num_regs (gdbarch) |
| 4073 | + mips_regnum (gdbarch)->fp0 + |
| 4074 | 0, 4, gdbarch_byte_order (gdbarch), |
| 4075 | readbuf, writebuf, 0); |
| 4076 | mips_xfer_register (gdbarch, regcache, |
| 4077 | gdbarch_num_regs (gdbarch) |
| 4078 | + mips_regnum (gdbarch)->fp0 + 1, |
| 4079 | 4, gdbarch_byte_order (gdbarch), |
| 4080 | readbuf, writebuf, 4); |
| 4081 | break; |
| 4082 | case BFD_ENDIAN_BIG: |
| 4083 | mips_xfer_register (gdbarch, regcache, |
| 4084 | gdbarch_num_regs (gdbarch) |
| 4085 | + mips_regnum (gdbarch)->fp0 + 1, |
| 4086 | 4, gdbarch_byte_order (gdbarch), |
| 4087 | readbuf, writebuf, 0); |
| 4088 | mips_xfer_register (gdbarch, regcache, |
| 4089 | gdbarch_num_regs (gdbarch) |
| 4090 | + mips_regnum (gdbarch)->fp0 + 0, |
| 4091 | 4, gdbarch_byte_order (gdbarch), |
| 4092 | readbuf, writebuf, 4); |
| 4093 | break; |
| 4094 | default: |
| 4095 | internal_error (__FILE__, __LINE__, _("bad switch")); |
| 4096 | } |
| 4097 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 4098 | } |
| 4099 | #if 0 |
| 4100 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 4101 | && TYPE_NFIELDS (type) <= 2 |
| 4102 | && TYPE_NFIELDS (type) >= 1 |
| 4103 | && ((TYPE_NFIELDS (type) == 1 |
| 4104 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) |
| 4105 | == TYPE_CODE_FLT)) |
| 4106 | || (TYPE_NFIELDS (type) == 2 |
| 4107 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) |
| 4108 | == TYPE_CODE_FLT) |
| 4109 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) |
| 4110 | == TYPE_CODE_FLT))) |
| 4111 | && tdep->mips_fpu_type != MIPS_FPU_NONE) |
| 4112 | { |
| 4113 | /* A struct that contains one or two floats. Each value is part |
| 4114 | in the least significant part of their floating point |
| 4115 | register.. */ |
| 4116 | gdb_byte reg[MAX_REGISTER_SIZE]; |
| 4117 | int regnum; |
| 4118 | int field; |
| 4119 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
| 4120 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
| 4121 | { |
| 4122 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) |
| 4123 | / TARGET_CHAR_BIT); |
| 4124 | if (mips_debug) |
| 4125 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", |
| 4126 | offset); |
| 4127 | mips_xfer_register (gdbarch, regcache, |
| 4128 | gdbarch_num_regs (gdbarch) + regnum, |
| 4129 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
| 4130 | gdbarch_byte_order (gdbarch), |
| 4131 | readbuf, writebuf, offset); |
| 4132 | } |
| 4133 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 4134 | } |
| 4135 | #endif |
| 4136 | #if 0 |
| 4137 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 4138 | || TYPE_CODE (type) == TYPE_CODE_UNION) |
| 4139 | { |
| 4140 | /* A structure or union. Extract the left justified value, |
| 4141 | regardless of the byte order. I.e. DO NOT USE |
| 4142 | mips_xfer_lower. */ |
| 4143 | int offset; |
| 4144 | int regnum; |
| 4145 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
| 4146 | offset < TYPE_LENGTH (type); |
| 4147 | offset += register_size (gdbarch, regnum), regnum++) |
| 4148 | { |
| 4149 | int xfer = register_size (gdbarch, regnum); |
| 4150 | if (offset + xfer > TYPE_LENGTH (type)) |
| 4151 | xfer = TYPE_LENGTH (type) - offset; |
| 4152 | if (mips_debug) |
| 4153 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", |
| 4154 | offset, xfer, regnum); |
| 4155 | mips_xfer_register (gdbarch, regcache, |
| 4156 | gdbarch_num_regs (gdbarch) + regnum, xfer, |
| 4157 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
| 4158 | } |
| 4159 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 4160 | } |
| 4161 | #endif |
| 4162 | else |
| 4163 | { |
| 4164 | /* A scalar extract each part but least-significant-byte |
| 4165 | justified. o32 thinks registers are 4 byte, regardless of |
| 4166 | the ISA. */ |
| 4167 | int offset; |
| 4168 | int regnum; |
| 4169 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
| 4170 | offset < TYPE_LENGTH (type); |
| 4171 | offset += MIPS32_REGSIZE, regnum++) |
| 4172 | { |
| 4173 | int xfer = MIPS32_REGSIZE; |
| 4174 | if (offset + xfer > TYPE_LENGTH (type)) |
| 4175 | xfer = TYPE_LENGTH (type) - offset; |
| 4176 | if (mips_debug) |
| 4177 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", |
| 4178 | offset, xfer, regnum); |
| 4179 | mips_xfer_register (gdbarch, regcache, |
| 4180 | gdbarch_num_regs (gdbarch) + regnum, xfer, |
| 4181 | gdbarch_byte_order (gdbarch), |
| 4182 | readbuf, writebuf, offset); |
| 4183 | } |
| 4184 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 4185 | } |
| 4186 | } |
| 4187 | |
| 4188 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 |
| 4189 | ABI. */ |
| 4190 | |
| 4191 | static CORE_ADDR |
| 4192 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 4193 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 4194 | int nargs, |
| 4195 | struct value **args, CORE_ADDR sp, |
| 4196 | int struct_return, CORE_ADDR struct_addr) |
| 4197 | { |
| 4198 | int argreg; |
| 4199 | int float_argreg; |
| 4200 | int argnum; |
| 4201 | int len = 0; |
| 4202 | int stack_offset = 0; |
| 4203 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 4204 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 4205 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
| 4206 | |
| 4207 | /* For shared libraries, "t9" needs to point at the function |
| 4208 | address. */ |
| 4209 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
| 4210 | |
| 4211 | /* Set the return address register to point to the entry point of |
| 4212 | the program, where a breakpoint lies in wait. */ |
| 4213 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
| 4214 | |
| 4215 | /* First ensure that the stack and structure return address (if any) |
| 4216 | are properly aligned. The stack has to be at least 64-bit |
| 4217 | aligned even on 32-bit machines, because doubles must be 64-bit |
| 4218 | aligned. For n32 and n64, stack frames need to be 128-bit |
| 4219 | aligned, so we round to this widest known alignment. */ |
| 4220 | |
| 4221 | sp = align_down (sp, 16); |
| 4222 | struct_addr = align_down (struct_addr, 16); |
| 4223 | |
| 4224 | /* Now make space on the stack for the args. */ |
| 4225 | for (argnum = 0; argnum < nargs; argnum++) |
| 4226 | { |
| 4227 | struct type *arg_type = check_typedef (value_type (args[argnum])); |
| 4228 | int arglen = TYPE_LENGTH (arg_type); |
| 4229 | |
| 4230 | /* Allocate space on the stack. */ |
| 4231 | len += align_up (arglen, MIPS64_REGSIZE); |
| 4232 | } |
| 4233 | sp -= align_up (len, 16); |
| 4234 | |
| 4235 | if (mips_debug) |
| 4236 | fprintf_unfiltered (gdb_stdlog, |
| 4237 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
| 4238 | paddress (gdbarch, sp), (long) align_up (len, 16)); |
| 4239 | |
| 4240 | /* Initialize the integer and float register pointers. */ |
| 4241 | argreg = MIPS_A0_REGNUM; |
| 4242 | float_argreg = mips_fpa0_regnum (gdbarch); |
| 4243 | |
| 4244 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
| 4245 | if (struct_return) |
| 4246 | { |
| 4247 | if (mips_debug) |
| 4248 | fprintf_unfiltered (gdb_stdlog, |
| 4249 | "mips_o64_push_dummy_call: " |
| 4250 | "struct_return reg=%d %s\n", |
| 4251 | argreg, paddress (gdbarch, struct_addr)); |
| 4252 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
| 4253 | stack_offset += MIPS64_REGSIZE; |
| 4254 | } |
| 4255 | |
| 4256 | /* Now load as many as possible of the first arguments into |
| 4257 | registers, and push the rest onto the stack. Loop thru args |
| 4258 | from first to last. */ |
| 4259 | for (argnum = 0; argnum < nargs; argnum++) |
| 4260 | { |
| 4261 | const gdb_byte *val; |
| 4262 | gdb_byte valbuf[MAX_REGISTER_SIZE]; |
| 4263 | struct value *arg = args[argnum]; |
| 4264 | struct type *arg_type = check_typedef (value_type (arg)); |
| 4265 | int len = TYPE_LENGTH (arg_type); |
| 4266 | enum type_code typecode = TYPE_CODE (arg_type); |
| 4267 | |
| 4268 | if (mips_debug) |
| 4269 | fprintf_unfiltered (gdb_stdlog, |
| 4270 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
| 4271 | argnum + 1, len, (int) typecode); |
| 4272 | |
| 4273 | val = value_contents (arg); |
| 4274 | |
| 4275 | /* Function pointer arguments to mips16 code need to be made into |
| 4276 | mips16 pointers. */ |
| 4277 | if (typecode == TYPE_CODE_PTR |
| 4278 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) |
| 4279 | { |
| 4280 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), |
| 4281 | len, byte_order); |
| 4282 | if (mips_pc_is_mips16 (addr)) |
| 4283 | { |
| 4284 | store_signed_integer (valbuf, len, byte_order, |
| 4285 | make_mips16_addr (addr)); |
| 4286 | val = valbuf; |
| 4287 | } |
| 4288 | } |
| 4289 | |
| 4290 | /* Floating point arguments passed in registers have to be |
| 4291 | treated specially. On 32-bit architectures, doubles |
| 4292 | are passed in register pairs; the even register gets |
| 4293 | the low word, and the odd register gets the high word. |
| 4294 | On O32/O64, the first two floating point arguments are |
| 4295 | also copied to general registers, because MIPS16 functions |
| 4296 | don't use float registers for arguments. This duplication of |
| 4297 | arguments in general registers can't hurt non-MIPS16 functions |
| 4298 | because those registers are normally skipped. */ |
| 4299 | |
| 4300 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
| 4301 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) |
| 4302 | { |
| 4303 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
| 4304 | if (mips_debug) |
| 4305 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
| 4306 | float_argreg, phex (regval, len)); |
| 4307 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
| 4308 | if (mips_debug) |
| 4309 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
| 4310 | argreg, phex (regval, len)); |
| 4311 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 4312 | argreg++; |
| 4313 | /* Reserve space for the FP register. */ |
| 4314 | stack_offset += align_up (len, MIPS64_REGSIZE); |
| 4315 | } |
| 4316 | else |
| 4317 | { |
| 4318 | /* Copy the argument to general registers or the stack in |
| 4319 | register-sized pieces. Large arguments are split between |
| 4320 | registers and stack. */ |
| 4321 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
| 4322 | are treated specially: Irix cc passes them in registers |
| 4323 | where gcc sometimes puts them on the stack. For maximum |
| 4324 | compatibility, we will put them in both places. */ |
| 4325 | int odd_sized_struct = (len > MIPS64_REGSIZE |
| 4326 | && len % MIPS64_REGSIZE != 0); |
| 4327 | while (len > 0) |
| 4328 | { |
| 4329 | /* Remember if the argument was written to the stack. */ |
| 4330 | int stack_used_p = 0; |
| 4331 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
| 4332 | |
| 4333 | if (mips_debug) |
| 4334 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", |
| 4335 | partial_len); |
| 4336 | |
| 4337 | /* Write this portion of the argument to the stack. */ |
| 4338 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
| 4339 | || odd_sized_struct) |
| 4340 | { |
| 4341 | /* Should shorter than int integer values be |
| 4342 | promoted to int before being stored? */ |
| 4343 | int longword_offset = 0; |
| 4344 | CORE_ADDR addr; |
| 4345 | stack_used_p = 1; |
| 4346 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 4347 | { |
| 4348 | if ((typecode == TYPE_CODE_INT |
| 4349 | || typecode == TYPE_CODE_PTR |
| 4350 | || typecode == TYPE_CODE_FLT) |
| 4351 | && len <= 4) |
| 4352 | longword_offset = MIPS64_REGSIZE - len; |
| 4353 | } |
| 4354 | |
| 4355 | if (mips_debug) |
| 4356 | { |
| 4357 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
| 4358 | paddress (gdbarch, stack_offset)); |
| 4359 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", |
| 4360 | paddress (gdbarch, longword_offset)); |
| 4361 | } |
| 4362 | |
| 4363 | addr = sp + stack_offset + longword_offset; |
| 4364 | |
| 4365 | if (mips_debug) |
| 4366 | { |
| 4367 | int i; |
| 4368 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
| 4369 | paddress (gdbarch, addr)); |
| 4370 | for (i = 0; i < partial_len; i++) |
| 4371 | { |
| 4372 | fprintf_unfiltered (gdb_stdlog, "%02x", |
| 4373 | val[i] & 0xff); |
| 4374 | } |
| 4375 | } |
| 4376 | write_memory (addr, val, partial_len); |
| 4377 | } |
| 4378 | |
| 4379 | /* Note!!! This is NOT an else clause. Odd sized |
| 4380 | structs may go thru BOTH paths. */ |
| 4381 | /* Write this portion of the argument to a general |
| 4382 | purpose register. */ |
| 4383 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
| 4384 | { |
| 4385 | LONGEST regval = extract_signed_integer (val, partial_len, |
| 4386 | byte_order); |
| 4387 | /* Value may need to be sign extended, because |
| 4388 | mips_isa_regsize() != mips_abi_regsize(). */ |
| 4389 | |
| 4390 | /* A non-floating-point argument being passed in a |
| 4391 | general register. If a struct or union, and if |
| 4392 | the remaining length is smaller than the register |
| 4393 | size, we have to adjust the register value on |
| 4394 | big endian targets. |
| 4395 | |
| 4396 | It does not seem to be necessary to do the |
| 4397 | same for integral types. */ |
| 4398 | |
| 4399 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
| 4400 | && partial_len < MIPS64_REGSIZE |
| 4401 | && (typecode == TYPE_CODE_STRUCT |
| 4402 | || typecode == TYPE_CODE_UNION)) |
| 4403 | regval <<= ((MIPS64_REGSIZE - partial_len) |
| 4404 | * TARGET_CHAR_BIT); |
| 4405 | |
| 4406 | if (mips_debug) |
| 4407 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
| 4408 | argreg, |
| 4409 | phex (regval, MIPS64_REGSIZE)); |
| 4410 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 4411 | argreg++; |
| 4412 | |
| 4413 | /* Prevent subsequent floating point arguments from |
| 4414 | being passed in floating point registers. */ |
| 4415 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
| 4416 | } |
| 4417 | |
| 4418 | len -= partial_len; |
| 4419 | val += partial_len; |
| 4420 | |
| 4421 | /* Compute the offset into the stack at which we will |
| 4422 | copy the next parameter. |
| 4423 | |
| 4424 | In older ABIs, the caller reserved space for |
| 4425 | registers that contained arguments. This was loosely |
| 4426 | refered to as their "home". Consequently, space is |
| 4427 | always allocated. */ |
| 4428 | |
| 4429 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
| 4430 | } |
| 4431 | } |
| 4432 | if (mips_debug) |
| 4433 | fprintf_unfiltered (gdb_stdlog, "\n"); |
| 4434 | } |
| 4435 | |
| 4436 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
| 4437 | |
| 4438 | /* Return adjusted stack pointer. */ |
| 4439 | return sp; |
| 4440 | } |
| 4441 | |
| 4442 | static enum return_value_convention |
| 4443 | mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
| 4444 | struct type *type, struct regcache *regcache, |
| 4445 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 4446 | { |
| 4447 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 4448 | |
| 4449 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 4450 | || TYPE_CODE (type) == TYPE_CODE_UNION |
| 4451 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) |
| 4452 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 4453 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
| 4454 | { |
| 4455 | /* A floating-point value. It fits in the least significant |
| 4456 | part of FP0. */ |
| 4457 | if (mips_debug) |
| 4458 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); |
| 4459 | mips_xfer_register (gdbarch, regcache, |
| 4460 | gdbarch_num_regs (gdbarch) |
| 4461 | + mips_regnum (gdbarch)->fp0, |
| 4462 | TYPE_LENGTH (type), |
| 4463 | gdbarch_byte_order (gdbarch), |
| 4464 | readbuf, writebuf, 0); |
| 4465 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 4466 | } |
| 4467 | else |
| 4468 | { |
| 4469 | /* A scalar extract each part but least-significant-byte |
| 4470 | justified. */ |
| 4471 | int offset; |
| 4472 | int regnum; |
| 4473 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
| 4474 | offset < TYPE_LENGTH (type); |
| 4475 | offset += MIPS64_REGSIZE, regnum++) |
| 4476 | { |
| 4477 | int xfer = MIPS64_REGSIZE; |
| 4478 | if (offset + xfer > TYPE_LENGTH (type)) |
| 4479 | xfer = TYPE_LENGTH (type) - offset; |
| 4480 | if (mips_debug) |
| 4481 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", |
| 4482 | offset, xfer, regnum); |
| 4483 | mips_xfer_register (gdbarch, regcache, |
| 4484 | gdbarch_num_regs (gdbarch) + regnum, |
| 4485 | xfer, gdbarch_byte_order (gdbarch), |
| 4486 | readbuf, writebuf, offset); |
| 4487 | } |
| 4488 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 4489 | } |
| 4490 | } |
| 4491 | |
| 4492 | /* Floating point register management. |
| 4493 | |
| 4494 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support |
| 4495 | 64bit operations, these early MIPS cpus treat fp register pairs |
| 4496 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp |
| 4497 | registers and offer a compatibility mode that emulates the MIPS2 fp |
| 4498 | model. When operating in MIPS2 fp compat mode, later cpu's split |
| 4499 | double precision floats into two 32-bit chunks and store them in |
| 4500 | consecutive fp regs. To display 64-bit floats stored in this |
| 4501 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. |
| 4502 | Throw in user-configurable endianness and you have a real mess. |
| 4503 | |
| 4504 | The way this works is: |
| 4505 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit |
| 4506 | double-precision value will be split across two logical registers. |
| 4507 | The lower-numbered logical register will hold the low-order bits, |
| 4508 | regardless of the processor's endianness. |
| 4509 | - If we are on a 64-bit processor, and we are looking for a |
| 4510 | single-precision value, it will be in the low ordered bits |
| 4511 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register |
| 4512 | save slot in memory. |
| 4513 | - If we are in 64-bit mode, everything is straightforward. |
| 4514 | |
| 4515 | Note that this code only deals with "live" registers at the top of the |
| 4516 | stack. We will attempt to deal with saved registers later, when |
| 4517 | the raw/cooked register interface is in place. (We need a general |
| 4518 | interface that can deal with dynamic saved register sizes -- fp |
| 4519 | regs could be 32 bits wide in one frame and 64 on the frame above |
| 4520 | and below). */ |
| 4521 | |
| 4522 | /* Copy a 32-bit single-precision value from the current frame |
| 4523 | into rare_buffer. */ |
| 4524 | |
| 4525 | static void |
| 4526 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
| 4527 | gdb_byte *rare_buffer) |
| 4528 | { |
| 4529 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 4530 | int raw_size = register_size (gdbarch, regno); |
| 4531 | gdb_byte *raw_buffer = alloca (raw_size); |
| 4532 | |
| 4533 | if (!frame_register_read (frame, regno, raw_buffer)) |
| 4534 | error (_("can't read register %d (%s)"), |
| 4535 | regno, gdbarch_register_name (gdbarch, regno)); |
| 4536 | if (raw_size == 8) |
| 4537 | { |
| 4538 | /* We have a 64-bit value for this register. Find the low-order |
| 4539 | 32 bits. */ |
| 4540 | int offset; |
| 4541 | |
| 4542 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 4543 | offset = 4; |
| 4544 | else |
| 4545 | offset = 0; |
| 4546 | |
| 4547 | memcpy (rare_buffer, raw_buffer + offset, 4); |
| 4548 | } |
| 4549 | else |
| 4550 | { |
| 4551 | memcpy (rare_buffer, raw_buffer, 4); |
| 4552 | } |
| 4553 | } |
| 4554 | |
| 4555 | /* Copy a 64-bit double-precision value from the current frame into |
| 4556 | rare_buffer. This may include getting half of it from the next |
| 4557 | register. */ |
| 4558 | |
| 4559 | static void |
| 4560 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
| 4561 | gdb_byte *rare_buffer) |
| 4562 | { |
| 4563 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 4564 | int raw_size = register_size (gdbarch, regno); |
| 4565 | |
| 4566 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
| 4567 | { |
| 4568 | /* We have a 64-bit value for this register, and we should use |
| 4569 | all 64 bits. */ |
| 4570 | if (!frame_register_read (frame, regno, rare_buffer)) |
| 4571 | error (_("can't read register %d (%s)"), |
| 4572 | regno, gdbarch_register_name (gdbarch, regno)); |
| 4573 | } |
| 4574 | else |
| 4575 | { |
| 4576 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
| 4577 | |
| 4578 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
| 4579 | internal_error (__FILE__, __LINE__, |
| 4580 | _("mips_read_fp_register_double: bad access to " |
| 4581 | "odd-numbered FP register")); |
| 4582 | |
| 4583 | /* mips_read_fp_register_single will find the correct 32 bits from |
| 4584 | each register. */ |
| 4585 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 4586 | { |
| 4587 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
| 4588 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); |
| 4589 | } |
| 4590 | else |
| 4591 | { |
| 4592 | mips_read_fp_register_single (frame, regno, rare_buffer); |
| 4593 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); |
| 4594 | } |
| 4595 | } |
| 4596 | } |
| 4597 | |
| 4598 | static void |
| 4599 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
| 4600 | int regnum) |
| 4601 | { /* Do values for FP (float) regs. */ |
| 4602 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 4603 | gdb_byte *raw_buffer; |
| 4604 | double doub, flt1; /* Doubles extracted from raw hex data. */ |
| 4605 | int inv1, inv2; |
| 4606 | |
| 4607 | raw_buffer = alloca (2 * register_size (gdbarch, |
| 4608 | mips_regnum (gdbarch)->fp0)); |
| 4609 | |
| 4610 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
| 4611 | fprintf_filtered (file, "%*s", |
| 4612 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
| 4613 | ""); |
| 4614 | |
| 4615 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
| 4616 | { |
| 4617 | struct value_print_options opts; |
| 4618 | |
| 4619 | /* 4-byte registers: Print hex and floating. Also print even |
| 4620 | numbered registers as doubles. */ |
| 4621 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
| 4622 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
| 4623 | raw_buffer, &inv1); |
| 4624 | |
| 4625 | get_formatted_print_options (&opts, 'x'); |
| 4626 | print_scalar_formatted (raw_buffer, |
| 4627 | builtin_type (gdbarch)->builtin_uint32, |
| 4628 | &opts, 'w', file); |
| 4629 | |
| 4630 | fprintf_filtered (file, " flt: "); |
| 4631 | if (inv1) |
| 4632 | fprintf_filtered (file, " <invalid float> "); |
| 4633 | else |
| 4634 | fprintf_filtered (file, "%-17.9g", flt1); |
| 4635 | |
| 4636 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
| 4637 | { |
| 4638 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
| 4639 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
| 4640 | raw_buffer, &inv2); |
| 4641 | |
| 4642 | fprintf_filtered (file, " dbl: "); |
| 4643 | if (inv2) |
| 4644 | fprintf_filtered (file, "<invalid double>"); |
| 4645 | else |
| 4646 | fprintf_filtered (file, "%-24.17g", doub); |
| 4647 | } |
| 4648 | } |
| 4649 | else |
| 4650 | { |
| 4651 | struct value_print_options opts; |
| 4652 | |
| 4653 | /* Eight byte registers: print each one as hex, float and double. */ |
| 4654 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
| 4655 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
| 4656 | raw_buffer, &inv1); |
| 4657 | |
| 4658 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
| 4659 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
| 4660 | raw_buffer, &inv2); |
| 4661 | |
| 4662 | get_formatted_print_options (&opts, 'x'); |
| 4663 | print_scalar_formatted (raw_buffer, |
| 4664 | builtin_type (gdbarch)->builtin_uint64, |
| 4665 | &opts, 'g', file); |
| 4666 | |
| 4667 | fprintf_filtered (file, " flt: "); |
| 4668 | if (inv1) |
| 4669 | fprintf_filtered (file, "<invalid float>"); |
| 4670 | else |
| 4671 | fprintf_filtered (file, "%-17.9g", flt1); |
| 4672 | |
| 4673 | fprintf_filtered (file, " dbl: "); |
| 4674 | if (inv2) |
| 4675 | fprintf_filtered (file, "<invalid double>"); |
| 4676 | else |
| 4677 | fprintf_filtered (file, "%-24.17g", doub); |
| 4678 | } |
| 4679 | } |
| 4680 | |
| 4681 | static void |
| 4682 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
| 4683 | int regnum) |
| 4684 | { |
| 4685 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 4686 | int offset; |
| 4687 | struct value_print_options opts; |
| 4688 | struct value *val; |
| 4689 | |
| 4690 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
| 4691 | { |
| 4692 | mips_print_fp_register (file, frame, regnum); |
| 4693 | return; |
| 4694 | } |
| 4695 | |
| 4696 | val = get_frame_register_value (frame, regnum); |
| 4697 | if (value_optimized_out (val)) |
| 4698 | { |
| 4699 | fprintf_filtered (file, "%s: [Invalid]", |
| 4700 | gdbarch_register_name (gdbarch, regnum)); |
| 4701 | return; |
| 4702 | } |
| 4703 | |
| 4704 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
| 4705 | |
| 4706 | /* The problem with printing numeric register names (r26, etc.) is that |
| 4707 | the user can't use them on input. Probably the best solution is to |
| 4708 | fix it so that either the numeric or the funky (a2, etc.) names |
| 4709 | are accepted on input. */ |
| 4710 | if (regnum < MIPS_NUMREGS) |
| 4711 | fprintf_filtered (file, "(r%d): ", regnum); |
| 4712 | else |
| 4713 | fprintf_filtered (file, ": "); |
| 4714 | |
| 4715 | get_formatted_print_options (&opts, 'x'); |
| 4716 | val_print_scalar_formatted (value_type (val), |
| 4717 | value_contents_for_printing (val), |
| 4718 | value_embedded_offset (val), |
| 4719 | val, |
| 4720 | &opts, 0, file); |
| 4721 | } |
| 4722 | |
| 4723 | /* Replacement for generic do_registers_info. |
| 4724 | Print regs in pretty columns. */ |
| 4725 | |
| 4726 | static int |
| 4727 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
| 4728 | int regnum) |
| 4729 | { |
| 4730 | fprintf_filtered (file, " "); |
| 4731 | mips_print_fp_register (file, frame, regnum); |
| 4732 | fprintf_filtered (file, "\n"); |
| 4733 | return regnum + 1; |
| 4734 | } |
| 4735 | |
| 4736 | |
| 4737 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
| 4738 | |
| 4739 | static int |
| 4740 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
| 4741 | int start_regnum) |
| 4742 | { |
| 4743 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 4744 | /* Do values for GP (int) regs. */ |
| 4745 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
| 4746 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
| 4747 | per row. */ |
| 4748 | int col, byte; |
| 4749 | int regnum; |
| 4750 | |
| 4751 | /* For GP registers, we print a separate row of names above the vals. */ |
| 4752 | for (col = 0, regnum = start_regnum; |
| 4753 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
| 4754 | + gdbarch_num_pseudo_regs (gdbarch); |
| 4755 | regnum++) |
| 4756 | { |
| 4757 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
| 4758 | continue; /* unused register */ |
| 4759 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
| 4760 | TYPE_CODE_FLT) |
| 4761 | break; /* End the row: reached FP register. */ |
| 4762 | /* Large registers are handled separately. */ |
| 4763 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
| 4764 | { |
| 4765 | if (col > 0) |
| 4766 | break; /* End the row before this register. */ |
| 4767 | |
| 4768 | /* Print this register on a row by itself. */ |
| 4769 | mips_print_register (file, frame, regnum); |
| 4770 | fprintf_filtered (file, "\n"); |
| 4771 | return regnum + 1; |
| 4772 | } |
| 4773 | if (col == 0) |
| 4774 | fprintf_filtered (file, " "); |
| 4775 | fprintf_filtered (file, |
| 4776 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
| 4777 | gdbarch_register_name (gdbarch, regnum)); |
| 4778 | col++; |
| 4779 | } |
| 4780 | |
| 4781 | if (col == 0) |
| 4782 | return regnum; |
| 4783 | |
| 4784 | /* Print the R0 to R31 names. */ |
| 4785 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
| 4786 | fprintf_filtered (file, "\n R%-4d", |
| 4787 | start_regnum % gdbarch_num_regs (gdbarch)); |
| 4788 | else |
| 4789 | fprintf_filtered (file, "\n "); |
| 4790 | |
| 4791 | /* Now print the values in hex, 4 or 8 to the row. */ |
| 4792 | for (col = 0, regnum = start_regnum; |
| 4793 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
| 4794 | + gdbarch_num_pseudo_regs (gdbarch); |
| 4795 | regnum++) |
| 4796 | { |
| 4797 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
| 4798 | continue; /* unused register */ |
| 4799 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
| 4800 | TYPE_CODE_FLT) |
| 4801 | break; /* End row: reached FP register. */ |
| 4802 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
| 4803 | break; /* End row: large register. */ |
| 4804 | |
| 4805 | /* OK: get the data in raw format. */ |
| 4806 | if (!frame_register_read (frame, regnum, raw_buffer)) |
| 4807 | error (_("can't read register %d (%s)"), |
| 4808 | regnum, gdbarch_register_name (gdbarch, regnum)); |
| 4809 | /* pad small registers */ |
| 4810 | for (byte = 0; |
| 4811 | byte < (mips_abi_regsize (gdbarch) |
| 4812 | - register_size (gdbarch, regnum)); byte++) |
| 4813 | printf_filtered (" "); |
| 4814 | /* Now print the register value in hex, endian order. */ |
| 4815 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 4816 | for (byte = |
| 4817 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
| 4818 | byte < register_size (gdbarch, regnum); byte++) |
| 4819 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
| 4820 | else |
| 4821 | for (byte = register_size (gdbarch, regnum) - 1; |
| 4822 | byte >= 0; byte--) |
| 4823 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
| 4824 | fprintf_filtered (file, " "); |
| 4825 | col++; |
| 4826 | } |
| 4827 | if (col > 0) /* ie. if we actually printed anything... */ |
| 4828 | fprintf_filtered (file, "\n"); |
| 4829 | |
| 4830 | return regnum; |
| 4831 | } |
| 4832 | |
| 4833 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
| 4834 | |
| 4835 | static void |
| 4836 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
| 4837 | struct frame_info *frame, int regnum, int all) |
| 4838 | { |
| 4839 | if (regnum != -1) /* Do one specified register. */ |
| 4840 | { |
| 4841 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
| 4842 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') |
| 4843 | error (_("Not a valid register for the current processor type")); |
| 4844 | |
| 4845 | mips_print_register (file, frame, regnum); |
| 4846 | fprintf_filtered (file, "\n"); |
| 4847 | } |
| 4848 | else |
| 4849 | /* Do all (or most) registers. */ |
| 4850 | { |
| 4851 | regnum = gdbarch_num_regs (gdbarch); |
| 4852 | while (regnum < gdbarch_num_regs (gdbarch) |
| 4853 | + gdbarch_num_pseudo_regs (gdbarch)) |
| 4854 | { |
| 4855 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
| 4856 | TYPE_CODE_FLT) |
| 4857 | { |
| 4858 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
| 4859 | regnum = print_fp_register_row (file, frame, regnum); |
| 4860 | else |
| 4861 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
| 4862 | } |
| 4863 | else |
| 4864 | regnum = print_gp_register_row (file, frame, regnum); |
| 4865 | } |
| 4866 | } |
| 4867 | } |
| 4868 | |
| 4869 | /* Is this a branch with a delay slot? */ |
| 4870 | |
| 4871 | static int |
| 4872 | is_delayed (unsigned long insn) |
| 4873 | { |
| 4874 | int i; |
| 4875 | for (i = 0; i < NUMOPCODES; ++i) |
| 4876 | if (mips_opcodes[i].pinfo != INSN_MACRO |
| 4877 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) |
| 4878 | break; |
| 4879 | return (i < NUMOPCODES |
| 4880 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY |
| 4881 | | INSN_COND_BRANCH_DELAY |
| 4882 | | INSN_COND_BRANCH_LIKELY))); |
| 4883 | } |
| 4884 | |
| 4885 | static int |
| 4886 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
| 4887 | struct frame_info *frame) |
| 4888 | { |
| 4889 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 4890 | CORE_ADDR pc = get_frame_pc (frame); |
| 4891 | gdb_byte buf[MIPS_INSN32_SIZE]; |
| 4892 | |
| 4893 | /* There is no branch delay slot on MIPS16. */ |
| 4894 | if (mips_pc_is_mips16 (pc)) |
| 4895 | return 0; |
| 4896 | |
| 4897 | if (!breakpoint_here_p (get_frame_address_space (frame), pc + 4)) |
| 4898 | return 0; |
| 4899 | |
| 4900 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
| 4901 | /* If error reading memory, guess that it is not a delayed |
| 4902 | branch. */ |
| 4903 | return 0; |
| 4904 | return is_delayed (extract_unsigned_integer (buf, sizeof buf, byte_order)); |
| 4905 | } |
| 4906 | |
| 4907 | /* To skip prologues, I use this predicate. Returns either PC itself |
| 4908 | if the code at PC does not look like a function prologue; otherwise |
| 4909 | returns an address that (if we're lucky) follows the prologue. If |
| 4910 | LENIENT, then we must skip everything which is involved in setting |
| 4911 | up the frame (it's OK to skip more, just so long as we don't skip |
| 4912 | anything which might clobber the registers which are being saved. |
| 4913 | We must skip more in the case where part of the prologue is in the |
| 4914 | delay slot of a non-prologue instruction). */ |
| 4915 | |
| 4916 | static CORE_ADDR |
| 4917 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 4918 | { |
| 4919 | CORE_ADDR limit_pc; |
| 4920 | CORE_ADDR func_addr; |
| 4921 | |
| 4922 | /* See if we can determine the end of the prologue via the symbol table. |
| 4923 | If so, then return either PC, or the PC after the prologue, whichever |
| 4924 | is greater. */ |
| 4925 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
| 4926 | { |
| 4927 | CORE_ADDR post_prologue_pc |
| 4928 | = skip_prologue_using_sal (gdbarch, func_addr); |
| 4929 | if (post_prologue_pc != 0) |
| 4930 | return max (pc, post_prologue_pc); |
| 4931 | } |
| 4932 | |
| 4933 | /* Can't determine prologue from the symbol table, need to examine |
| 4934 | instructions. */ |
| 4935 | |
| 4936 | /* Find an upper limit on the function prologue using the debug |
| 4937 | information. If the debug information could not be used to provide |
| 4938 | that bound, then use an arbitrary large number as the upper bound. */ |
| 4939 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
| 4940 | if (limit_pc == 0) |
| 4941 | limit_pc = pc + 100; /* Magic. */ |
| 4942 | |
| 4943 | if (mips_pc_is_mips16 (pc)) |
| 4944 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
| 4945 | else |
| 4946 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
| 4947 | } |
| 4948 | |
| 4949 | /* Check whether the PC is in a function epilogue (32-bit version). |
| 4950 | This is a helper function for mips_in_function_epilogue_p. */ |
| 4951 | static int |
| 4952 | mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 4953 | { |
| 4954 | CORE_ADDR func_addr = 0, func_end = 0; |
| 4955 | |
| 4956 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
| 4957 | { |
| 4958 | /* The MIPS epilogue is max. 12 bytes long. */ |
| 4959 | CORE_ADDR addr = func_end - 12; |
| 4960 | |
| 4961 | if (addr < func_addr + 4) |
| 4962 | addr = func_addr + 4; |
| 4963 | if (pc < addr) |
| 4964 | return 0; |
| 4965 | |
| 4966 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) |
| 4967 | { |
| 4968 | unsigned long high_word; |
| 4969 | unsigned long inst; |
| 4970 | |
| 4971 | inst = mips_fetch_instruction (gdbarch, pc); |
| 4972 | high_word = (inst >> 16) & 0xffff; |
| 4973 | |
| 4974 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ |
| 4975 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ |
| 4976 | && inst != 0x03e00008 /* jr $ra */ |
| 4977 | && inst != 0x00000000) /* nop */ |
| 4978 | return 0; |
| 4979 | } |
| 4980 | |
| 4981 | return 1; |
| 4982 | } |
| 4983 | |
| 4984 | return 0; |
| 4985 | } |
| 4986 | |
| 4987 | /* Check whether the PC is in a function epilogue (16-bit version). |
| 4988 | This is a helper function for mips_in_function_epilogue_p. */ |
| 4989 | static int |
| 4990 | mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 4991 | { |
| 4992 | CORE_ADDR func_addr = 0, func_end = 0; |
| 4993 | |
| 4994 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
| 4995 | { |
| 4996 | /* The MIPS epilogue is max. 12 bytes long. */ |
| 4997 | CORE_ADDR addr = func_end - 12; |
| 4998 | |
| 4999 | if (addr < func_addr + 4) |
| 5000 | addr = func_addr + 4; |
| 5001 | if (pc < addr) |
| 5002 | return 0; |
| 5003 | |
| 5004 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) |
| 5005 | { |
| 5006 | unsigned short inst; |
| 5007 | |
| 5008 | inst = mips_fetch_instruction (gdbarch, pc); |
| 5009 | |
| 5010 | if ((inst & 0xf800) == 0xf000) /* extend */ |
| 5011 | continue; |
| 5012 | |
| 5013 | if (inst != 0x6300 /* addiu $sp,offset */ |
| 5014 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ |
| 5015 | && inst != 0xe820 /* jr $ra */ |
| 5016 | && inst != 0xe8a0 /* jrc $ra */ |
| 5017 | && inst != 0x6500) /* nop */ |
| 5018 | return 0; |
| 5019 | } |
| 5020 | |
| 5021 | return 1; |
| 5022 | } |
| 5023 | |
| 5024 | return 0; |
| 5025 | } |
| 5026 | |
| 5027 | /* The epilogue is defined here as the area at the end of a function, |
| 5028 | after an instruction which destroys the function's stack frame. */ |
| 5029 | static int |
| 5030 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 5031 | { |
| 5032 | if (mips_pc_is_mips16 (pc)) |
| 5033 | return mips16_in_function_epilogue_p (gdbarch, pc); |
| 5034 | else |
| 5035 | return mips32_in_function_epilogue_p (gdbarch, pc); |
| 5036 | } |
| 5037 | |
| 5038 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
| 5039 | used for all MIPS-specific commands. */ |
| 5040 | |
| 5041 | static void |
| 5042 | show_mips_command (char *args, int from_tty) |
| 5043 | { |
| 5044 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); |
| 5045 | } |
| 5046 | |
| 5047 | static void |
| 5048 | set_mips_command (char *args, int from_tty) |
| 5049 | { |
| 5050 | printf_unfiltered |
| 5051 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); |
| 5052 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
| 5053 | } |
| 5054 | |
| 5055 | /* Commands to show/set the MIPS FPU type. */ |
| 5056 | |
| 5057 | static void |
| 5058 | show_mipsfpu_command (char *args, int from_tty) |
| 5059 | { |
| 5060 | char *fpu; |
| 5061 | |
| 5062 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
| 5063 | { |
| 5064 | printf_unfiltered |
| 5065 | ("The MIPS floating-point coprocessor is unknown " |
| 5066 | "because the current architecture is not MIPS.\n"); |
| 5067 | return; |
| 5068 | } |
| 5069 | |
| 5070 | switch (MIPS_FPU_TYPE (target_gdbarch)) |
| 5071 | { |
| 5072 | case MIPS_FPU_SINGLE: |
| 5073 | fpu = "single-precision"; |
| 5074 | break; |
| 5075 | case MIPS_FPU_DOUBLE: |
| 5076 | fpu = "double-precision"; |
| 5077 | break; |
| 5078 | case MIPS_FPU_NONE: |
| 5079 | fpu = "absent (none)"; |
| 5080 | break; |
| 5081 | default: |
| 5082 | internal_error (__FILE__, __LINE__, _("bad switch")); |
| 5083 | } |
| 5084 | if (mips_fpu_type_auto) |
| 5085 | printf_unfiltered ("The MIPS floating-point coprocessor " |
| 5086 | "is set automatically (currently %s)\n", |
| 5087 | fpu); |
| 5088 | else |
| 5089 | printf_unfiltered |
| 5090 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); |
| 5091 | } |
| 5092 | |
| 5093 | |
| 5094 | static void |
| 5095 | set_mipsfpu_command (char *args, int from_tty) |
| 5096 | { |
| 5097 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", " |
| 5098 | "\"single\",\"none\" or \"auto\".\n"); |
| 5099 | show_mipsfpu_command (args, from_tty); |
| 5100 | } |
| 5101 | |
| 5102 | static void |
| 5103 | set_mipsfpu_single_command (char *args, int from_tty) |
| 5104 | { |
| 5105 | struct gdbarch_info info; |
| 5106 | gdbarch_info_init (&info); |
| 5107 | mips_fpu_type = MIPS_FPU_SINGLE; |
| 5108 | mips_fpu_type_auto = 0; |
| 5109 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
| 5110 | instead of relying on globals. Doing that would let generic code |
| 5111 | handle the search for this specific architecture. */ |
| 5112 | if (!gdbarch_update_p (info)) |
| 5113 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
| 5114 | } |
| 5115 | |
| 5116 | static void |
| 5117 | set_mipsfpu_double_command (char *args, int from_tty) |
| 5118 | { |
| 5119 | struct gdbarch_info info; |
| 5120 | gdbarch_info_init (&info); |
| 5121 | mips_fpu_type = MIPS_FPU_DOUBLE; |
| 5122 | mips_fpu_type_auto = 0; |
| 5123 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
| 5124 | instead of relying on globals. Doing that would let generic code |
| 5125 | handle the search for this specific architecture. */ |
| 5126 | if (!gdbarch_update_p (info)) |
| 5127 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
| 5128 | } |
| 5129 | |
| 5130 | static void |
| 5131 | set_mipsfpu_none_command (char *args, int from_tty) |
| 5132 | { |
| 5133 | struct gdbarch_info info; |
| 5134 | gdbarch_info_init (&info); |
| 5135 | mips_fpu_type = MIPS_FPU_NONE; |
| 5136 | mips_fpu_type_auto = 0; |
| 5137 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
| 5138 | instead of relying on globals. Doing that would let generic code |
| 5139 | handle the search for this specific architecture. */ |
| 5140 | if (!gdbarch_update_p (info)) |
| 5141 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
| 5142 | } |
| 5143 | |
| 5144 | static void |
| 5145 | set_mipsfpu_auto_command (char *args, int from_tty) |
| 5146 | { |
| 5147 | mips_fpu_type_auto = 1; |
| 5148 | } |
| 5149 | |
| 5150 | /* Attempt to identify the particular processor model by reading the |
| 5151 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
| 5152 | the relevant processor still exists (it dates back to '94) and |
| 5153 | secondly this is not the way to do this. The processor type should |
| 5154 | be set by forcing an architecture change. */ |
| 5155 | |
| 5156 | void |
| 5157 | deprecated_mips_set_processor_regs_hack (void) |
| 5158 | { |
| 5159 | struct regcache *regcache = get_current_regcache (); |
| 5160 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 5161 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 5162 | ULONGEST prid; |
| 5163 | |
| 5164 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
| 5165 | if ((prid & ~0xf) == 0x700) |
| 5166 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
| 5167 | } |
| 5168 | |
| 5169 | /* Just like reinit_frame_cache, but with the right arguments to be |
| 5170 | callable as an sfunc. */ |
| 5171 | |
| 5172 | static void |
| 5173 | reinit_frame_cache_sfunc (char *args, int from_tty, |
| 5174 | struct cmd_list_element *c) |
| 5175 | { |
| 5176 | reinit_frame_cache (); |
| 5177 | } |
| 5178 | |
| 5179 | static int |
| 5180 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) |
| 5181 | { |
| 5182 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
| 5183 | disassembler needs to be able to locally determine the ISA, and |
| 5184 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not |
| 5185 | work. */ |
| 5186 | if (mips_pc_is_mips16 (memaddr)) |
| 5187 | info->mach = bfd_mach_mips16; |
| 5188 | |
| 5189 | /* Round down the instruction address to the appropriate boundary. */ |
| 5190 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
| 5191 | |
| 5192 | /* Set the disassembler options. */ |
| 5193 | if (!info->disassembler_options) |
| 5194 | /* This string is not recognized explicitly by the disassembler, |
| 5195 | but it tells the disassembler to not try to guess the ABI from |
| 5196 | the bfd elf headers, such that, if the user overrides the ABI |
| 5197 | of a program linked as NewABI, the disassembly will follow the |
| 5198 | register naming conventions specified by the user. */ |
| 5199 | info->disassembler_options = "gpr-names=32"; |
| 5200 | |
| 5201 | /* Call the appropriate disassembler based on the target endian-ness. */ |
| 5202 | if (info->endian == BFD_ENDIAN_BIG) |
| 5203 | return print_insn_big_mips (memaddr, info); |
| 5204 | else |
| 5205 | return print_insn_little_mips (memaddr, info); |
| 5206 | } |
| 5207 | |
| 5208 | static int |
| 5209 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) |
| 5210 | { |
| 5211 | /* Set up the disassembler info, so that we get the right |
| 5212 | register names from libopcodes. */ |
| 5213 | info->disassembler_options = "gpr-names=n32"; |
| 5214 | info->flavour = bfd_target_elf_flavour; |
| 5215 | |
| 5216 | return gdb_print_insn_mips (memaddr, info); |
| 5217 | } |
| 5218 | |
| 5219 | static int |
| 5220 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) |
| 5221 | { |
| 5222 | /* Set up the disassembler info, so that we get the right |
| 5223 | register names from libopcodes. */ |
| 5224 | info->disassembler_options = "gpr-names=64"; |
| 5225 | info->flavour = bfd_target_elf_flavour; |
| 5226 | |
| 5227 | return gdb_print_insn_mips (memaddr, info); |
| 5228 | } |
| 5229 | |
| 5230 | /* This function implements gdbarch_breakpoint_from_pc. It uses the |
| 5231 | program counter value to determine whether a 16- or 32-bit breakpoint |
| 5232 | should be used. It returns a pointer to a string of bytes that encode a |
| 5233 | breakpoint instruction, stores the length of the string to *lenptr, and |
| 5234 | adjusts pc (if necessary) to point to the actual memory location where |
| 5235 | the breakpoint should be inserted. */ |
| 5236 | |
| 5237 | static const gdb_byte * |
| 5238 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, |
| 5239 | CORE_ADDR *pcptr, int *lenptr) |
| 5240 | { |
| 5241 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 5242 | { |
| 5243 | if (mips_pc_is_mips16 (*pcptr)) |
| 5244 | { |
| 5245 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
| 5246 | *pcptr = unmake_mips16_addr (*pcptr); |
| 5247 | *lenptr = sizeof (mips16_big_breakpoint); |
| 5248 | return mips16_big_breakpoint; |
| 5249 | } |
| 5250 | else |
| 5251 | { |
| 5252 | /* The IDT board uses an unusual breakpoint value, and |
| 5253 | sometimes gets confused when it sees the usual MIPS |
| 5254 | breakpoint instruction. */ |
| 5255 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
| 5256 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; |
| 5257 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; |
| 5258 | /* Likewise, IRIX appears to expect a different breakpoint, |
| 5259 | although this is not apparent until you try to use pthreads. */ |
| 5260 | static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; |
| 5261 | |
| 5262 | *lenptr = sizeof (big_breakpoint); |
| 5263 | |
| 5264 | if (strcmp (target_shortname, "mips") == 0) |
| 5265 | return idt_big_breakpoint; |
| 5266 | else if (strcmp (target_shortname, "ddb") == 0 |
| 5267 | || strcmp (target_shortname, "pmon") == 0 |
| 5268 | || strcmp (target_shortname, "lsi") == 0) |
| 5269 | return pmon_big_breakpoint; |
| 5270 | else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) |
| 5271 | return irix_big_breakpoint; |
| 5272 | else |
| 5273 | return big_breakpoint; |
| 5274 | } |
| 5275 | } |
| 5276 | else |
| 5277 | { |
| 5278 | if (mips_pc_is_mips16 (*pcptr)) |
| 5279 | { |
| 5280 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
| 5281 | *pcptr = unmake_mips16_addr (*pcptr); |
| 5282 | *lenptr = sizeof (mips16_little_breakpoint); |
| 5283 | return mips16_little_breakpoint; |
| 5284 | } |
| 5285 | else |
| 5286 | { |
| 5287 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
| 5288 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; |
| 5289 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; |
| 5290 | |
| 5291 | *lenptr = sizeof (little_breakpoint); |
| 5292 | |
| 5293 | if (strcmp (target_shortname, "mips") == 0) |
| 5294 | return idt_little_breakpoint; |
| 5295 | else if (strcmp (target_shortname, "ddb") == 0 |
| 5296 | || strcmp (target_shortname, "pmon") == 0 |
| 5297 | || strcmp (target_shortname, "lsi") == 0) |
| 5298 | return pmon_little_breakpoint; |
| 5299 | else |
| 5300 | return little_breakpoint; |
| 5301 | } |
| 5302 | } |
| 5303 | } |
| 5304 | |
| 5305 | /* If PC is in a mips16 call or return stub, return the address of the target |
| 5306 | PC, which is either the callee or the caller. There are several |
| 5307 | cases which must be handled: |
| 5308 | |
| 5309 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the |
| 5310 | target PC is in $31 ($ra). |
| 5311 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
| 5312 | and the target PC is in $2. |
| 5313 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
| 5314 | before the jal instruction, this is effectively a call stub |
| 5315 | and the target PC is in $2. Otherwise this is effectively |
| 5316 | a return stub and the target PC is in $18. |
| 5317 | |
| 5318 | See the source code for the stubs in gcc/config/mips/mips16.S for |
| 5319 | gory details. */ |
| 5320 | |
| 5321 | static CORE_ADDR |
| 5322 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
| 5323 | { |
| 5324 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 5325 | char *name; |
| 5326 | CORE_ADDR start_addr; |
| 5327 | |
| 5328 | /* Find the starting address and name of the function containing the PC. */ |
| 5329 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) |
| 5330 | return 0; |
| 5331 | |
| 5332 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the |
| 5333 | target PC is in $31 ($ra). */ |
| 5334 | if (strcmp (name, "__mips16_ret_sf") == 0 |
| 5335 | || strcmp (name, "__mips16_ret_df") == 0) |
| 5336 | return get_frame_register_signed (frame, MIPS_RA_REGNUM); |
| 5337 | |
| 5338 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) |
| 5339 | { |
| 5340 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
| 5341 | and the target PC is in $2. */ |
| 5342 | if (name[19] >= '0' && name[19] <= '9') |
| 5343 | return get_frame_register_signed (frame, 2); |
| 5344 | |
| 5345 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
| 5346 | before the jal instruction, this is effectively a call stub |
| 5347 | and the target PC is in $2. Otherwise this is effectively |
| 5348 | a return stub and the target PC is in $18. */ |
| 5349 | else if (name[19] == 's' || name[19] == 'd') |
| 5350 | { |
| 5351 | if (pc == start_addr) |
| 5352 | { |
| 5353 | /* Check if the target of the stub is a compiler-generated |
| 5354 | stub. Such a stub for a function bar might have a name |
| 5355 | like __fn_stub_bar, and might look like this: |
| 5356 | mfc1 $4,$f13 |
| 5357 | mfc1 $5,$f12 |
| 5358 | mfc1 $6,$f15 |
| 5359 | mfc1 $7,$f14 |
| 5360 | la $1,bar (becomes a lui/addiu pair) |
| 5361 | jr $1 |
| 5362 | So scan down to the lui/addi and extract the target |
| 5363 | address from those two instructions. */ |
| 5364 | |
| 5365 | CORE_ADDR target_pc = get_frame_register_signed (frame, 2); |
| 5366 | ULONGEST inst; |
| 5367 | int i; |
| 5368 | |
| 5369 | /* See if the name of the target function is __fn_stub_*. */ |
| 5370 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
| 5371 | 0) |
| 5372 | return target_pc; |
| 5373 | if (strncmp (name, "__fn_stub_", 10) != 0 |
| 5374 | && strcmp (name, "etext") != 0 |
| 5375 | && strcmp (name, "_etext") != 0) |
| 5376 | return target_pc; |
| 5377 | |
| 5378 | /* Scan through this _fn_stub_ code for the lui/addiu pair. |
| 5379 | The limit on the search is arbitrarily set to 20 |
| 5380 | instructions. FIXME. */ |
| 5381 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
| 5382 | { |
| 5383 | inst = mips_fetch_instruction (gdbarch, target_pc); |
| 5384 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ |
| 5385 | pc = (inst << 16) & 0xffff0000; /* high word */ |
| 5386 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ |
| 5387 | return pc | (inst & 0xffff); /* low word */ |
| 5388 | } |
| 5389 | |
| 5390 | /* Couldn't find the lui/addui pair, so return stub address. */ |
| 5391 | return target_pc; |
| 5392 | } |
| 5393 | else |
| 5394 | /* This is the 'return' part of a call stub. The return |
| 5395 | address is in $r18. */ |
| 5396 | return get_frame_register_signed (frame, 18); |
| 5397 | } |
| 5398 | } |
| 5399 | return 0; /* not a stub */ |
| 5400 | } |
| 5401 | |
| 5402 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
| 5403 | PC of the stub target. The stub just loads $t9 and jumps to it, |
| 5404 | so that $t9 has the correct value at function entry. */ |
| 5405 | |
| 5406 | static CORE_ADDR |
| 5407 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
| 5408 | { |
| 5409 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 5410 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 5411 | struct minimal_symbol *msym; |
| 5412 | int i; |
| 5413 | gdb_byte stub_code[16]; |
| 5414 | int32_t stub_words[4]; |
| 5415 | |
| 5416 | /* The stub for foo is named ".pic.foo", and is either two |
| 5417 | instructions inserted before foo or a three instruction sequence |
| 5418 | which jumps to foo. */ |
| 5419 | msym = lookup_minimal_symbol_by_pc (pc); |
| 5420 | if (msym == NULL |
| 5421 | || SYMBOL_VALUE_ADDRESS (msym) != pc |
| 5422 | || SYMBOL_LINKAGE_NAME (msym) == NULL |
| 5423 | || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0) |
| 5424 | return 0; |
| 5425 | |
| 5426 | /* A two-instruction header. */ |
| 5427 | if (MSYMBOL_SIZE (msym) == 8) |
| 5428 | return pc + 8; |
| 5429 | |
| 5430 | /* A three-instruction (plus delay slot) trampoline. */ |
| 5431 | if (MSYMBOL_SIZE (msym) == 16) |
| 5432 | { |
| 5433 | if (target_read_memory (pc, stub_code, 16) != 0) |
| 5434 | return 0; |
| 5435 | for (i = 0; i < 4; i++) |
| 5436 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
| 5437 | 4, byte_order); |
| 5438 | |
| 5439 | /* A stub contains these instructions: |
| 5440 | lui t9, %hi(target) |
| 5441 | j target |
| 5442 | addiu t9, t9, %lo(target) |
| 5443 | nop |
| 5444 | |
| 5445 | This works even for N64, since stubs are only generated with |
| 5446 | -msym32. */ |
| 5447 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 |
| 5448 | && (stub_words[1] & 0xfc000000U) == 0x08000000 |
| 5449 | && (stub_words[2] & 0xffff0000U) == 0x27390000 |
| 5450 | && stub_words[3] == 0x00000000) |
| 5451 | return (((stub_words[0] & 0x0000ffff) << 16) |
| 5452 | + (stub_words[2] & 0x0000ffff)); |
| 5453 | } |
| 5454 | |
| 5455 | /* Not a recognized stub. */ |
| 5456 | return 0; |
| 5457 | } |
| 5458 | |
| 5459 | static CORE_ADDR |
| 5460 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
| 5461 | { |
| 5462 | CORE_ADDR target_pc; |
| 5463 | |
| 5464 | target_pc = mips_skip_mips16_trampoline_code (frame, pc); |
| 5465 | if (target_pc) |
| 5466 | return target_pc; |
| 5467 | |
| 5468 | target_pc = find_solib_trampoline_target (frame, pc); |
| 5469 | if (target_pc) |
| 5470 | return target_pc; |
| 5471 | |
| 5472 | target_pc = mips_skip_pic_trampoline_code (frame, pc); |
| 5473 | if (target_pc) |
| 5474 | return target_pc; |
| 5475 | |
| 5476 | return 0; |
| 5477 | } |
| 5478 | |
| 5479 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
| 5480 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
| 5481 | |
| 5482 | static int |
| 5483 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
| 5484 | { |
| 5485 | int regnum; |
| 5486 | if (num >= 0 && num < 32) |
| 5487 | regnum = num; |
| 5488 | else if (num >= 38 && num < 70) |
| 5489 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
| 5490 | else if (num == 70) |
| 5491 | regnum = mips_regnum (gdbarch)->hi; |
| 5492 | else if (num == 71) |
| 5493 | regnum = mips_regnum (gdbarch)->lo; |
| 5494 | else |
| 5495 | /* This will hopefully (eventually) provoke a warning. Should |
| 5496 | we be calling complaint() here? */ |
| 5497 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
| 5498 | return gdbarch_num_regs (gdbarch) + regnum; |
| 5499 | } |
| 5500 | |
| 5501 | |
| 5502 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
| 5503 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
| 5504 | |
| 5505 | static int |
| 5506 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
| 5507 | { |
| 5508 | int regnum; |
| 5509 | if (num >= 0 && num < 32) |
| 5510 | regnum = num; |
| 5511 | else if (num >= 32 && num < 64) |
| 5512 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
| 5513 | else if (num == 64) |
| 5514 | regnum = mips_regnum (gdbarch)->hi; |
| 5515 | else if (num == 65) |
| 5516 | regnum = mips_regnum (gdbarch)->lo; |
| 5517 | else |
| 5518 | /* This will hopefully (eventually) provoke a warning. Should we |
| 5519 | be calling complaint() here? */ |
| 5520 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
| 5521 | return gdbarch_num_regs (gdbarch) + regnum; |
| 5522 | } |
| 5523 | |
| 5524 | static int |
| 5525 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
| 5526 | { |
| 5527 | /* Only makes sense to supply raw registers. */ |
| 5528 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
| 5529 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
| 5530 | decide if it is valid. Should instead define a standard sim/gdb |
| 5531 | register numbering scheme. */ |
| 5532 | if (gdbarch_register_name (gdbarch, |
| 5533 | gdbarch_num_regs (gdbarch) + regnum) != NULL |
| 5534 | && gdbarch_register_name (gdbarch, |
| 5535 | gdbarch_num_regs (gdbarch) |
| 5536 | + regnum)[0] != '\0') |
| 5537 | return regnum; |
| 5538 | else |
| 5539 | return LEGACY_SIM_REGNO_IGNORE; |
| 5540 | } |
| 5541 | |
| 5542 | |
| 5543 | /* Convert an integer into an address. Extracting the value signed |
| 5544 | guarantees a correctly sign extended address. */ |
| 5545 | |
| 5546 | static CORE_ADDR |
| 5547 | mips_integer_to_address (struct gdbarch *gdbarch, |
| 5548 | struct type *type, const gdb_byte *buf) |
| 5549 | { |
| 5550 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 5551 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); |
| 5552 | } |
| 5553 | |
| 5554 | /* Dummy virtual frame pointer method. This is no more or less accurate |
| 5555 | than most other architectures; we just need to be explicit about it, |
| 5556 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to |
| 5557 | an assertion failure. */ |
| 5558 | |
| 5559 | static void |
| 5560 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
| 5561 | CORE_ADDR pc, int *reg, LONGEST *offset) |
| 5562 | { |
| 5563 | *reg = MIPS_SP_REGNUM; |
| 5564 | *offset = 0; |
| 5565 | } |
| 5566 | |
| 5567 | static void |
| 5568 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) |
| 5569 | { |
| 5570 | enum mips_abi *abip = (enum mips_abi *) obj; |
| 5571 | const char *name = bfd_get_section_name (abfd, sect); |
| 5572 | |
| 5573 | if (*abip != MIPS_ABI_UNKNOWN) |
| 5574 | return; |
| 5575 | |
| 5576 | if (strncmp (name, ".mdebug.", 8) != 0) |
| 5577 | return; |
| 5578 | |
| 5579 | if (strcmp (name, ".mdebug.abi32") == 0) |
| 5580 | *abip = MIPS_ABI_O32; |
| 5581 | else if (strcmp (name, ".mdebug.abiN32") == 0) |
| 5582 | *abip = MIPS_ABI_N32; |
| 5583 | else if (strcmp (name, ".mdebug.abi64") == 0) |
| 5584 | *abip = MIPS_ABI_N64; |
| 5585 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
| 5586 | *abip = MIPS_ABI_O64; |
| 5587 | else if (strcmp (name, ".mdebug.eabi32") == 0) |
| 5588 | *abip = MIPS_ABI_EABI32; |
| 5589 | else if (strcmp (name, ".mdebug.eabi64") == 0) |
| 5590 | *abip = MIPS_ABI_EABI64; |
| 5591 | else |
| 5592 | warning (_("unsupported ABI %s."), name + 8); |
| 5593 | } |
| 5594 | |
| 5595 | static void |
| 5596 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) |
| 5597 | { |
| 5598 | int *lbp = (int *) obj; |
| 5599 | const char *name = bfd_get_section_name (abfd, sect); |
| 5600 | |
| 5601 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) |
| 5602 | *lbp = 32; |
| 5603 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) |
| 5604 | *lbp = 64; |
| 5605 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) |
| 5606 | warning (_("unrecognized .gcc_compiled_longXX")); |
| 5607 | } |
| 5608 | |
| 5609 | static enum mips_abi |
| 5610 | global_mips_abi (void) |
| 5611 | { |
| 5612 | int i; |
| 5613 | |
| 5614 | for (i = 0; mips_abi_strings[i] != NULL; i++) |
| 5615 | if (mips_abi_strings[i] == mips_abi_string) |
| 5616 | return (enum mips_abi) i; |
| 5617 | |
| 5618 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
| 5619 | } |
| 5620 | |
| 5621 | static void |
| 5622 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) |
| 5623 | { |
| 5624 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
| 5625 | assume that's what we've got. */ |
| 5626 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
| 5627 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); |
| 5628 | |
| 5629 | /* If the size matches the full set of registers GDB traditionally |
| 5630 | knows about, including floating point, for either 32-bit or |
| 5631 | 64-bit, assume that's what we've got. */ |
| 5632 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
| 5633 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); |
| 5634 | |
| 5635 | /* Otherwise we don't have a useful guess. */ |
| 5636 | } |
| 5637 | |
| 5638 | static struct value * |
| 5639 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) |
| 5640 | { |
| 5641 | const int *reg_p = baton; |
| 5642 | return value_of_register (*reg_p, frame); |
| 5643 | } |
| 5644 | |
| 5645 | static struct gdbarch * |
| 5646 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 5647 | { |
| 5648 | struct gdbarch *gdbarch; |
| 5649 | struct gdbarch_tdep *tdep; |
| 5650 | int elf_flags; |
| 5651 | enum mips_abi mips_abi, found_abi, wanted_abi; |
| 5652 | int i, num_regs; |
| 5653 | enum mips_fpu_type fpu_type; |
| 5654 | struct tdesc_arch_data *tdesc_data = NULL; |
| 5655 | int elf_fpu_type = 0; |
| 5656 | |
| 5657 | /* Check any target description for validity. */ |
| 5658 | if (tdesc_has_registers (info.target_desc)) |
| 5659 | { |
| 5660 | static const char *const mips_gprs[] = { |
| 5661 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 5662 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 5663 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
| 5664 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" |
| 5665 | }; |
| 5666 | static const char *const mips_fprs[] = { |
| 5667 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 5668 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 5669 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 5670 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 5671 | }; |
| 5672 | |
| 5673 | const struct tdesc_feature *feature; |
| 5674 | int valid_p; |
| 5675 | |
| 5676 | feature = tdesc_find_feature (info.target_desc, |
| 5677 | "org.gnu.gdb.mips.cpu"); |
| 5678 | if (feature == NULL) |
| 5679 | return NULL; |
| 5680 | |
| 5681 | tdesc_data = tdesc_data_alloc (); |
| 5682 | |
| 5683 | valid_p = 1; |
| 5684 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) |
| 5685 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, |
| 5686 | mips_gprs[i]); |
| 5687 | |
| 5688 | |
| 5689 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 5690 | MIPS_EMBED_LO_REGNUM, "lo"); |
| 5691 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 5692 | MIPS_EMBED_HI_REGNUM, "hi"); |
| 5693 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 5694 | MIPS_EMBED_PC_REGNUM, "pc"); |
| 5695 | |
| 5696 | if (!valid_p) |
| 5697 | { |
| 5698 | tdesc_data_cleanup (tdesc_data); |
| 5699 | return NULL; |
| 5700 | } |
| 5701 | |
| 5702 | feature = tdesc_find_feature (info.target_desc, |
| 5703 | "org.gnu.gdb.mips.cp0"); |
| 5704 | if (feature == NULL) |
| 5705 | { |
| 5706 | tdesc_data_cleanup (tdesc_data); |
| 5707 | return NULL; |
| 5708 | } |
| 5709 | |
| 5710 | valid_p = 1; |
| 5711 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 5712 | MIPS_EMBED_BADVADDR_REGNUM, |
| 5713 | "badvaddr"); |
| 5714 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 5715 | MIPS_PS_REGNUM, "status"); |
| 5716 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 5717 | MIPS_EMBED_CAUSE_REGNUM, "cause"); |
| 5718 | |
| 5719 | if (!valid_p) |
| 5720 | { |
| 5721 | tdesc_data_cleanup (tdesc_data); |
| 5722 | return NULL; |
| 5723 | } |
| 5724 | |
| 5725 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS |
| 5726 | backend is not prepared for that, though. */ |
| 5727 | feature = tdesc_find_feature (info.target_desc, |
| 5728 | "org.gnu.gdb.mips.fpu"); |
| 5729 | if (feature == NULL) |
| 5730 | { |
| 5731 | tdesc_data_cleanup (tdesc_data); |
| 5732 | return NULL; |
| 5733 | } |
| 5734 | |
| 5735 | valid_p = 1; |
| 5736 | for (i = 0; i < 32; i++) |
| 5737 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 5738 | i + MIPS_EMBED_FP0_REGNUM, |
| 5739 | mips_fprs[i]); |
| 5740 | |
| 5741 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 5742 | MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); |
| 5743 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 5744 | MIPS_EMBED_FP0_REGNUM + 33, "fir"); |
| 5745 | |
| 5746 | if (!valid_p) |
| 5747 | { |
| 5748 | tdesc_data_cleanup (tdesc_data); |
| 5749 | return NULL; |
| 5750 | } |
| 5751 | |
| 5752 | /* It would be nice to detect an attempt to use a 64-bit ABI |
| 5753 | when only 32-bit registers are provided. */ |
| 5754 | } |
| 5755 | |
| 5756 | /* First of all, extract the elf_flags, if available. */ |
| 5757 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) |
| 5758 | elf_flags = elf_elfheader (info.abfd)->e_flags; |
| 5759 | else if (arches != NULL) |
| 5760 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; |
| 5761 | else |
| 5762 | elf_flags = 0; |
| 5763 | if (gdbarch_debug) |
| 5764 | fprintf_unfiltered (gdb_stdlog, |
| 5765 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
| 5766 | |
| 5767 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
| 5768 | switch ((elf_flags & EF_MIPS_ABI)) |
| 5769 | { |
| 5770 | case E_MIPS_ABI_O32: |
| 5771 | found_abi = MIPS_ABI_O32; |
| 5772 | break; |
| 5773 | case E_MIPS_ABI_O64: |
| 5774 | found_abi = MIPS_ABI_O64; |
| 5775 | break; |
| 5776 | case E_MIPS_ABI_EABI32: |
| 5777 | found_abi = MIPS_ABI_EABI32; |
| 5778 | break; |
| 5779 | case E_MIPS_ABI_EABI64: |
| 5780 | found_abi = MIPS_ABI_EABI64; |
| 5781 | break; |
| 5782 | default: |
| 5783 | if ((elf_flags & EF_MIPS_ABI2)) |
| 5784 | found_abi = MIPS_ABI_N32; |
| 5785 | else |
| 5786 | found_abi = MIPS_ABI_UNKNOWN; |
| 5787 | break; |
| 5788 | } |
| 5789 | |
| 5790 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
| 5791 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
| 5792 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); |
| 5793 | |
| 5794 | /* If we have no useful BFD information, use the ABI from the last |
| 5795 | MIPS architecture (if there is one). */ |
| 5796 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) |
| 5797 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; |
| 5798 | |
| 5799 | /* Try the architecture for any hint of the correct ABI. */ |
| 5800 | if (found_abi == MIPS_ABI_UNKNOWN |
| 5801 | && info.bfd_arch_info != NULL |
| 5802 | && info.bfd_arch_info->arch == bfd_arch_mips) |
| 5803 | { |
| 5804 | switch (info.bfd_arch_info->mach) |
| 5805 | { |
| 5806 | case bfd_mach_mips3900: |
| 5807 | found_abi = MIPS_ABI_EABI32; |
| 5808 | break; |
| 5809 | case bfd_mach_mips4100: |
| 5810 | case bfd_mach_mips5000: |
| 5811 | found_abi = MIPS_ABI_EABI64; |
| 5812 | break; |
| 5813 | case bfd_mach_mips8000: |
| 5814 | case bfd_mach_mips10000: |
| 5815 | /* On Irix, ELF64 executables use the N64 ABI. The |
| 5816 | pseudo-sections which describe the ABI aren't present |
| 5817 | on IRIX. (Even for executables created by gcc.) */ |
| 5818 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
| 5819 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) |
| 5820 | found_abi = MIPS_ABI_N64; |
| 5821 | else |
| 5822 | found_abi = MIPS_ABI_N32; |
| 5823 | break; |
| 5824 | } |
| 5825 | } |
| 5826 | |
| 5827 | /* Default 64-bit objects to N64 instead of O32. */ |
| 5828 | if (found_abi == MIPS_ABI_UNKNOWN |
| 5829 | && info.abfd != NULL |
| 5830 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
| 5831 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) |
| 5832 | found_abi = MIPS_ABI_N64; |
| 5833 | |
| 5834 | if (gdbarch_debug) |
| 5835 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", |
| 5836 | found_abi); |
| 5837 | |
| 5838 | /* What has the user specified from the command line? */ |
| 5839 | wanted_abi = global_mips_abi (); |
| 5840 | if (gdbarch_debug) |
| 5841 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", |
| 5842 | wanted_abi); |
| 5843 | |
| 5844 | /* Now that we have found what the ABI for this binary would be, |
| 5845 | check whether the user is overriding it. */ |
| 5846 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
| 5847 | mips_abi = wanted_abi; |
| 5848 | else if (found_abi != MIPS_ABI_UNKNOWN) |
| 5849 | mips_abi = found_abi; |
| 5850 | else |
| 5851 | mips_abi = MIPS_ABI_O32; |
| 5852 | if (gdbarch_debug) |
| 5853 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", |
| 5854 | mips_abi); |
| 5855 | |
| 5856 | /* Also used when doing an architecture lookup. */ |
| 5857 | if (gdbarch_debug) |
| 5858 | fprintf_unfiltered (gdb_stdlog, |
| 5859 | "mips_gdbarch_init: " |
| 5860 | "mips64_transfers_32bit_regs_p = %d\n", |
| 5861 | mips64_transfers_32bit_regs_p); |
| 5862 | |
| 5863 | /* Determine the MIPS FPU type. */ |
| 5864 | #ifdef HAVE_ELF |
| 5865 | if (info.abfd |
| 5866 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) |
| 5867 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, |
| 5868 | Tag_GNU_MIPS_ABI_FP); |
| 5869 | #endif /* HAVE_ELF */ |
| 5870 | |
| 5871 | if (!mips_fpu_type_auto) |
| 5872 | fpu_type = mips_fpu_type; |
| 5873 | else if (elf_fpu_type != 0) |
| 5874 | { |
| 5875 | switch (elf_fpu_type) |
| 5876 | { |
| 5877 | case 1: |
| 5878 | fpu_type = MIPS_FPU_DOUBLE; |
| 5879 | break; |
| 5880 | case 2: |
| 5881 | fpu_type = MIPS_FPU_SINGLE; |
| 5882 | break; |
| 5883 | case 3: |
| 5884 | default: |
| 5885 | /* Soft float or unknown. */ |
| 5886 | fpu_type = MIPS_FPU_NONE; |
| 5887 | break; |
| 5888 | } |
| 5889 | } |
| 5890 | else if (info.bfd_arch_info != NULL |
| 5891 | && info.bfd_arch_info->arch == bfd_arch_mips) |
| 5892 | switch (info.bfd_arch_info->mach) |
| 5893 | { |
| 5894 | case bfd_mach_mips3900: |
| 5895 | case bfd_mach_mips4100: |
| 5896 | case bfd_mach_mips4111: |
| 5897 | case bfd_mach_mips4120: |
| 5898 | fpu_type = MIPS_FPU_NONE; |
| 5899 | break; |
| 5900 | case bfd_mach_mips4650: |
| 5901 | fpu_type = MIPS_FPU_SINGLE; |
| 5902 | break; |
| 5903 | default: |
| 5904 | fpu_type = MIPS_FPU_DOUBLE; |
| 5905 | break; |
| 5906 | } |
| 5907 | else if (arches != NULL) |
| 5908 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; |
| 5909 | else |
| 5910 | fpu_type = MIPS_FPU_DOUBLE; |
| 5911 | if (gdbarch_debug) |
| 5912 | fprintf_unfiltered (gdb_stdlog, |
| 5913 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
| 5914 | |
| 5915 | /* Check for blatant incompatibilities. */ |
| 5916 | |
| 5917 | /* If we have only 32-bit registers, then we can't debug a 64-bit |
| 5918 | ABI. */ |
| 5919 | if (info.target_desc |
| 5920 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL |
| 5921 | && mips_abi != MIPS_ABI_EABI32 |
| 5922 | && mips_abi != MIPS_ABI_O32) |
| 5923 | { |
| 5924 | if (tdesc_data != NULL) |
| 5925 | tdesc_data_cleanup (tdesc_data); |
| 5926 | return NULL; |
| 5927 | } |
| 5928 | |
| 5929 | /* Try to find a pre-existing architecture. */ |
| 5930 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
| 5931 | arches != NULL; |
| 5932 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) |
| 5933 | { |
| 5934 | /* MIPS needs to be pedantic about which ABI the object is |
| 5935 | using. */ |
| 5936 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
| 5937 | continue; |
| 5938 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
| 5939 | continue; |
| 5940 | /* Need to be pedantic about which register virtual size is |
| 5941 | used. */ |
| 5942 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p |
| 5943 | != mips64_transfers_32bit_regs_p) |
| 5944 | continue; |
| 5945 | /* Be pedantic about which FPU is selected. */ |
| 5946 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) |
| 5947 | continue; |
| 5948 | |
| 5949 | if (tdesc_data != NULL) |
| 5950 | tdesc_data_cleanup (tdesc_data); |
| 5951 | return arches->gdbarch; |
| 5952 | } |
| 5953 | |
| 5954 | /* Need a new architecture. Fill in a target specific vector. */ |
| 5955 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
| 5956 | gdbarch = gdbarch_alloc (&info, tdep); |
| 5957 | tdep->elf_flags = elf_flags; |
| 5958 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
| 5959 | tdep->found_abi = found_abi; |
| 5960 | tdep->mips_abi = mips_abi; |
| 5961 | tdep->mips_fpu_type = fpu_type; |
| 5962 | tdep->register_size_valid_p = 0; |
| 5963 | tdep->register_size = 0; |
| 5964 | tdep->gregset = NULL; |
| 5965 | tdep->gregset64 = NULL; |
| 5966 | tdep->fpregset = NULL; |
| 5967 | tdep->fpregset64 = NULL; |
| 5968 | |
| 5969 | if (info.target_desc) |
| 5970 | { |
| 5971 | /* Some useful properties can be inferred from the target. */ |
| 5972 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) |
| 5973 | { |
| 5974 | tdep->register_size_valid_p = 1; |
| 5975 | tdep->register_size = 4; |
| 5976 | } |
| 5977 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) |
| 5978 | { |
| 5979 | tdep->register_size_valid_p = 1; |
| 5980 | tdep->register_size = 8; |
| 5981 | } |
| 5982 | } |
| 5983 | |
| 5984 | /* Initially set everything according to the default ABI/ISA. */ |
| 5985 | set_gdbarch_short_bit (gdbarch, 16); |
| 5986 | set_gdbarch_int_bit (gdbarch, 32); |
| 5987 | set_gdbarch_float_bit (gdbarch, 32); |
| 5988 | set_gdbarch_double_bit (gdbarch, 64); |
| 5989 | set_gdbarch_long_double_bit (gdbarch, 64); |
| 5990 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
| 5991 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); |
| 5992 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); |
| 5993 | |
| 5994 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
| 5995 | mips_ax_pseudo_register_collect); |
| 5996 | set_gdbarch_ax_pseudo_register_push_stack |
| 5997 | (gdbarch, mips_ax_pseudo_register_push_stack); |
| 5998 | |
| 5999 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
| 6000 | mips_elf_make_msymbol_special); |
| 6001 | |
| 6002 | /* Fill in the OS dependant register numbers and names. */ |
| 6003 | { |
| 6004 | const char **reg_names; |
| 6005 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
| 6006 | struct mips_regnum); |
| 6007 | if (tdesc_has_registers (info.target_desc)) |
| 6008 | { |
| 6009 | regnum->lo = MIPS_EMBED_LO_REGNUM; |
| 6010 | regnum->hi = MIPS_EMBED_HI_REGNUM; |
| 6011 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; |
| 6012 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; |
| 6013 | regnum->pc = MIPS_EMBED_PC_REGNUM; |
| 6014 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; |
| 6015 | regnum->fp_control_status = 70; |
| 6016 | regnum->fp_implementation_revision = 71; |
| 6017 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; |
| 6018 | reg_names = NULL; |
| 6019 | } |
| 6020 | else if (info.osabi == GDB_OSABI_IRIX) |
| 6021 | { |
| 6022 | regnum->fp0 = 32; |
| 6023 | regnum->pc = 64; |
| 6024 | regnum->cause = 65; |
| 6025 | regnum->badvaddr = 66; |
| 6026 | regnum->hi = 67; |
| 6027 | regnum->lo = 68; |
| 6028 | regnum->fp_control_status = 69; |
| 6029 | regnum->fp_implementation_revision = 70; |
| 6030 | num_regs = 71; |
| 6031 | reg_names = mips_irix_reg_names; |
| 6032 | } |
| 6033 | else |
| 6034 | { |
| 6035 | regnum->lo = MIPS_EMBED_LO_REGNUM; |
| 6036 | regnum->hi = MIPS_EMBED_HI_REGNUM; |
| 6037 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; |
| 6038 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; |
| 6039 | regnum->pc = MIPS_EMBED_PC_REGNUM; |
| 6040 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; |
| 6041 | regnum->fp_control_status = 70; |
| 6042 | regnum->fp_implementation_revision = 71; |
| 6043 | num_regs = 90; |
| 6044 | if (info.bfd_arch_info != NULL |
| 6045 | && info.bfd_arch_info->mach == bfd_mach_mips3900) |
| 6046 | reg_names = mips_tx39_reg_names; |
| 6047 | else |
| 6048 | reg_names = mips_generic_reg_names; |
| 6049 | } |
| 6050 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been |
| 6051 | replaced by gdbarch_read_pc? */ |
| 6052 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
| 6053 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); |
| 6054 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
| 6055 | set_gdbarch_num_regs (gdbarch, num_regs); |
| 6056 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); |
| 6057 | set_gdbarch_register_name (gdbarch, mips_register_name); |
| 6058 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); |
| 6059 | tdep->mips_processor_reg_names = reg_names; |
| 6060 | tdep->regnum = regnum; |
| 6061 | } |
| 6062 | |
| 6063 | switch (mips_abi) |
| 6064 | { |
| 6065 | case MIPS_ABI_O32: |
| 6066 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
| 6067 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
| 6068 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
| 6069 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
| 6070 | tdep->default_mask_address_p = 0; |
| 6071 | set_gdbarch_long_bit (gdbarch, 32); |
| 6072 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 6073 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 6074 | break; |
| 6075 | case MIPS_ABI_O64: |
| 6076 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
| 6077 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
| 6078 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
| 6079 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
| 6080 | tdep->default_mask_address_p = 0; |
| 6081 | set_gdbarch_long_bit (gdbarch, 32); |
| 6082 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 6083 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 6084 | break; |
| 6085 | case MIPS_ABI_EABI32: |
| 6086 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
| 6087 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
| 6088 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
| 6089 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
| 6090 | tdep->default_mask_address_p = 0; |
| 6091 | set_gdbarch_long_bit (gdbarch, 32); |
| 6092 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 6093 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 6094 | break; |
| 6095 | case MIPS_ABI_EABI64: |
| 6096 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
| 6097 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
| 6098 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
| 6099 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
| 6100 | tdep->default_mask_address_p = 0; |
| 6101 | set_gdbarch_long_bit (gdbarch, 64); |
| 6102 | set_gdbarch_ptr_bit (gdbarch, 64); |
| 6103 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 6104 | break; |
| 6105 | case MIPS_ABI_N32: |
| 6106 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
| 6107 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
| 6108 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
| 6109 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
| 6110 | tdep->default_mask_address_p = 0; |
| 6111 | set_gdbarch_long_bit (gdbarch, 32); |
| 6112 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 6113 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 6114 | set_gdbarch_long_double_bit (gdbarch, 128); |
| 6115 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
| 6116 | break; |
| 6117 | case MIPS_ABI_N64: |
| 6118 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
| 6119 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
| 6120 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
| 6121 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
| 6122 | tdep->default_mask_address_p = 0; |
| 6123 | set_gdbarch_long_bit (gdbarch, 64); |
| 6124 | set_gdbarch_ptr_bit (gdbarch, 64); |
| 6125 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 6126 | set_gdbarch_long_double_bit (gdbarch, 128); |
| 6127 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
| 6128 | break; |
| 6129 | default: |
| 6130 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
| 6131 | } |
| 6132 | |
| 6133 | /* GCC creates a pseudo-section whose name specifies the size of |
| 6134 | longs, since -mlong32 or -mlong64 may be used independent of |
| 6135 | other options. How those options affect pointer sizes is ABI and |
| 6136 | architecture dependent, so use them to override the default sizes |
| 6137 | set by the ABI. This table shows the relationship between ABI, |
| 6138 | -mlongXX, and size of pointers: |
| 6139 | |
| 6140 | ABI -mlongXX ptr bits |
| 6141 | --- -------- -------- |
| 6142 | o32 32 32 |
| 6143 | o32 64 32 |
| 6144 | n32 32 32 |
| 6145 | n32 64 64 |
| 6146 | o64 32 32 |
| 6147 | o64 64 64 |
| 6148 | n64 32 32 |
| 6149 | n64 64 64 |
| 6150 | eabi32 32 32 |
| 6151 | eabi32 64 32 |
| 6152 | eabi64 32 32 |
| 6153 | eabi64 64 64 |
| 6154 | |
| 6155 | Note that for o32 and eabi32, pointers are always 32 bits |
| 6156 | regardless of any -mlongXX option. For all others, pointers and |
| 6157 | longs are the same, as set by -mlongXX or set by defaults. */ |
| 6158 | |
| 6159 | if (info.abfd != NULL) |
| 6160 | { |
| 6161 | int long_bit = 0; |
| 6162 | |
| 6163 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); |
| 6164 | if (long_bit) |
| 6165 | { |
| 6166 | set_gdbarch_long_bit (gdbarch, long_bit); |
| 6167 | switch (mips_abi) |
| 6168 | { |
| 6169 | case MIPS_ABI_O32: |
| 6170 | case MIPS_ABI_EABI32: |
| 6171 | break; |
| 6172 | case MIPS_ABI_N32: |
| 6173 | case MIPS_ABI_O64: |
| 6174 | case MIPS_ABI_N64: |
| 6175 | case MIPS_ABI_EABI64: |
| 6176 | set_gdbarch_ptr_bit (gdbarch, long_bit); |
| 6177 | break; |
| 6178 | default: |
| 6179 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
| 6180 | } |
| 6181 | } |
| 6182 | } |
| 6183 | |
| 6184 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
| 6185 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the |
| 6186 | comment: |
| 6187 | |
| 6188 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE |
| 6189 | flag in object files because to do so would make it impossible to |
| 6190 | link with libraries compiled without "-gp32". This is |
| 6191 | unnecessarily restrictive. |
| 6192 | |
| 6193 | We could solve this problem by adding "-gp32" multilibs to gcc, |
| 6194 | but to set this flag before gcc is built with such multilibs will |
| 6195 | break too many systems.'' |
| 6196 | |
| 6197 | But even more unhelpfully, the default linker output target for |
| 6198 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even |
| 6199 | for 64-bit programs - you need to change the ABI to change this, |
| 6200 | and not all gcc targets support that currently. Therefore using |
| 6201 | this flag to detect 32-bit mode would do the wrong thing given |
| 6202 | the current gcc - it would make GDB treat these 64-bit programs |
| 6203 | as 32-bit programs by default. */ |
| 6204 | |
| 6205 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
| 6206 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
| 6207 | |
| 6208 | /* Add/remove bits from an address. The MIPS needs be careful to |
| 6209 | ensure that all 32 bit addresses are sign extended to 64 bits. */ |
| 6210 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
| 6211 | |
| 6212 | /* Unwind the frame. */ |
| 6213 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); |
| 6214 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
| 6215 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
| 6216 | |
| 6217 | /* Map debug register numbers onto internal register numbers. */ |
| 6218 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
| 6219 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
| 6220 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); |
| 6221 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
| 6222 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); |
| 6223 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
| 6224 | |
| 6225 | /* MIPS version of CALL_DUMMY. */ |
| 6226 | |
| 6227 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
| 6228 | replaced by a command, and all targets will default to on stack |
| 6229 | (regardless of the stack's execute status). */ |
| 6230 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); |
| 6231 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
| 6232 | |
| 6233 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
| 6234 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); |
| 6235 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); |
| 6236 | |
| 6237 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 6238 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); |
| 6239 | |
| 6240 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); |
| 6241 | |
| 6242 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
| 6243 | |
| 6244 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
| 6245 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); |
| 6246 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); |
| 6247 | |
| 6248 | set_gdbarch_register_type (gdbarch, mips_register_type); |
| 6249 | |
| 6250 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
| 6251 | |
| 6252 | if (mips_abi == MIPS_ABI_N32) |
| 6253 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); |
| 6254 | else if (mips_abi == MIPS_ABI_N64) |
| 6255 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); |
| 6256 | else |
| 6257 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
| 6258 | |
| 6259 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
| 6260 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint |
| 6261 | need to all be folded into the target vector. Since they are |
| 6262 | being used as guards for target_stopped_by_watchpoint, why not have |
| 6263 | target_stopped_by_watchpoint return the type of watchpoint that the code |
| 6264 | is sitting on? */ |
| 6265 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
| 6266 | |
| 6267 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
| 6268 | |
| 6269 | set_gdbarch_single_step_through_delay (gdbarch, |
| 6270 | mips_single_step_through_delay); |
| 6271 | |
| 6272 | /* Virtual tables. */ |
| 6273 | set_gdbarch_vbit_in_delta (gdbarch, 1); |
| 6274 | |
| 6275 | mips_register_g_packet_guesses (gdbarch); |
| 6276 | |
| 6277 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
| 6278 | info.tdep_info = (void *) tdesc_data; |
| 6279 | gdbarch_init_osabi (info, gdbarch); |
| 6280 | |
| 6281 | /* Unwind the frame. */ |
| 6282 | dwarf2_append_unwinders (gdbarch); |
| 6283 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); |
| 6284 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); |
| 6285 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); |
| 6286 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
| 6287 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
| 6288 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
| 6289 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); |
| 6290 | |
| 6291 | if (tdesc_data) |
| 6292 | { |
| 6293 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); |
| 6294 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
| 6295 | |
| 6296 | /* Override the normal target description methods to handle our |
| 6297 | dual real and pseudo registers. */ |
| 6298 | set_gdbarch_register_name (gdbarch, mips_register_name); |
| 6299 | set_gdbarch_register_reggroup_p (gdbarch, |
| 6300 | mips_tdesc_register_reggroup_p); |
| 6301 | |
| 6302 | num_regs = gdbarch_num_regs (gdbarch); |
| 6303 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); |
| 6304 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); |
| 6305 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); |
| 6306 | } |
| 6307 | |
| 6308 | /* Add ABI-specific aliases for the registers. */ |
| 6309 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) |
| 6310 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) |
| 6311 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, |
| 6312 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); |
| 6313 | else |
| 6314 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) |
| 6315 | user_reg_add (gdbarch, mips_o32_aliases[i].name, |
| 6316 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); |
| 6317 | |
| 6318 | /* Add some other standard aliases. */ |
| 6319 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) |
| 6320 | user_reg_add (gdbarch, mips_register_aliases[i].name, |
| 6321 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); |
| 6322 | |
| 6323 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
| 6324 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, |
| 6325 | value_of_mips_user_reg, |
| 6326 | &mips_numeric_register_aliases[i].regnum); |
| 6327 | |
| 6328 | return gdbarch; |
| 6329 | } |
| 6330 | |
| 6331 | static void |
| 6332 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
| 6333 | { |
| 6334 | struct gdbarch_info info; |
| 6335 | |
| 6336 | /* Force the architecture to update, and (if it's a MIPS architecture) |
| 6337 | mips_gdbarch_init will take care of the rest. */ |
| 6338 | gdbarch_info_init (&info); |
| 6339 | gdbarch_update_p (info); |
| 6340 | } |
| 6341 | |
| 6342 | /* Print out which MIPS ABI is in use. */ |
| 6343 | |
| 6344 | static void |
| 6345 | show_mips_abi (struct ui_file *file, |
| 6346 | int from_tty, |
| 6347 | struct cmd_list_element *ignored_cmd, |
| 6348 | const char *ignored_value) |
| 6349 | { |
| 6350 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
| 6351 | fprintf_filtered |
| 6352 | (file, |
| 6353 | "The MIPS ABI is unknown because the current architecture " |
| 6354 | "is not MIPS.\n"); |
| 6355 | else |
| 6356 | { |
| 6357 | enum mips_abi global_abi = global_mips_abi (); |
| 6358 | enum mips_abi actual_abi = mips_abi (target_gdbarch); |
| 6359 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
| 6360 | |
| 6361 | if (global_abi == MIPS_ABI_UNKNOWN) |
| 6362 | fprintf_filtered |
| 6363 | (file, |
| 6364 | "The MIPS ABI is set automatically (currently \"%s\").\n", |
| 6365 | actual_abi_str); |
| 6366 | else if (global_abi == actual_abi) |
| 6367 | fprintf_filtered |
| 6368 | (file, |
| 6369 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", |
| 6370 | actual_abi_str); |
| 6371 | else |
| 6372 | { |
| 6373 | /* Probably shouldn't happen... */ |
| 6374 | fprintf_filtered (file, |
| 6375 | "The (auto detected) MIPS ABI \"%s\" is in use " |
| 6376 | "even though the user setting was \"%s\".\n", |
| 6377 | actual_abi_str, mips_abi_strings[global_abi]); |
| 6378 | } |
| 6379 | } |
| 6380 | } |
| 6381 | |
| 6382 | static void |
| 6383 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
| 6384 | { |
| 6385 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 6386 | if (tdep != NULL) |
| 6387 | { |
| 6388 | int ef_mips_arch; |
| 6389 | int ef_mips_32bitmode; |
| 6390 | /* Determine the ISA. */ |
| 6391 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
| 6392 | { |
| 6393 | case E_MIPS_ARCH_1: |
| 6394 | ef_mips_arch = 1; |
| 6395 | break; |
| 6396 | case E_MIPS_ARCH_2: |
| 6397 | ef_mips_arch = 2; |
| 6398 | break; |
| 6399 | case E_MIPS_ARCH_3: |
| 6400 | ef_mips_arch = 3; |
| 6401 | break; |
| 6402 | case E_MIPS_ARCH_4: |
| 6403 | ef_mips_arch = 4; |
| 6404 | break; |
| 6405 | default: |
| 6406 | ef_mips_arch = 0; |
| 6407 | break; |
| 6408 | } |
| 6409 | /* Determine the size of a pointer. */ |
| 6410 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
| 6411 | fprintf_unfiltered (file, |
| 6412 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", |
| 6413 | tdep->elf_flags); |
| 6414 | fprintf_unfiltered (file, |
| 6415 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
| 6416 | ef_mips_32bitmode); |
| 6417 | fprintf_unfiltered (file, |
| 6418 | "mips_dump_tdep: ef_mips_arch = %d\n", |
| 6419 | ef_mips_arch); |
| 6420 | fprintf_unfiltered (file, |
| 6421 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", |
| 6422 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
| 6423 | fprintf_unfiltered (file, |
| 6424 | "mips_dump_tdep: " |
| 6425 | "mips_mask_address_p() %d (default %d)\n", |
| 6426 | mips_mask_address_p (tdep), |
| 6427 | tdep->default_mask_address_p); |
| 6428 | } |
| 6429 | fprintf_unfiltered (file, |
| 6430 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", |
| 6431 | MIPS_DEFAULT_FPU_TYPE, |
| 6432 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" |
| 6433 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" |
| 6434 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" |
| 6435 | : "???")); |
| 6436 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
| 6437 | MIPS_EABI (gdbarch)); |
| 6438 | fprintf_unfiltered (file, |
| 6439 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", |
| 6440 | MIPS_FPU_TYPE (gdbarch), |
| 6441 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" |
| 6442 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" |
| 6443 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" |
| 6444 | : "???")); |
| 6445 | } |
| 6446 | |
| 6447 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
| 6448 | |
| 6449 | void |
| 6450 | _initialize_mips_tdep (void) |
| 6451 | { |
| 6452 | static struct cmd_list_element *mipsfpulist = NULL; |
| 6453 | struct cmd_list_element *c; |
| 6454 | |
| 6455 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
| 6456 | if (MIPS_ABI_LAST + 1 |
| 6457 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) |
| 6458 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
| 6459 | |
| 6460 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
| 6461 | |
| 6462 | mips_pdr_data = register_objfile_data (); |
| 6463 | |
| 6464 | /* Create feature sets with the appropriate properties. The values |
| 6465 | are not important. */ |
| 6466 | mips_tdesc_gp32 = allocate_target_description (); |
| 6467 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); |
| 6468 | |
| 6469 | mips_tdesc_gp64 = allocate_target_description (); |
| 6470 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); |
| 6471 | |
| 6472 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
| 6473 | add_prefix_cmd ("mips", no_class, set_mips_command, |
| 6474 | _("Various MIPS specific commands."), |
| 6475 | &setmipscmdlist, "set mips ", 0, &setlist); |
| 6476 | |
| 6477 | add_prefix_cmd ("mips", no_class, show_mips_command, |
| 6478 | _("Various MIPS specific commands."), |
| 6479 | &showmipscmdlist, "show mips ", 0, &showlist); |
| 6480 | |
| 6481 | /* Allow the user to override the ABI. */ |
| 6482 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
| 6483 | &mips_abi_string, _("\ |
| 6484 | Set the MIPS ABI used by this program."), _("\ |
| 6485 | Show the MIPS ABI used by this program."), _("\ |
| 6486 | This option can be set to one of:\n\ |
| 6487 | auto - the default ABI associated with the current binary\n\ |
| 6488 | o32\n\ |
| 6489 | o64\n\ |
| 6490 | n32\n\ |
| 6491 | n64\n\ |
| 6492 | eabi32\n\ |
| 6493 | eabi64"), |
| 6494 | mips_abi_update, |
| 6495 | show_mips_abi, |
| 6496 | &setmipscmdlist, &showmipscmdlist); |
| 6497 | |
| 6498 | /* Let the user turn off floating point and set the fence post for |
| 6499 | heuristic_proc_start. */ |
| 6500 | |
| 6501 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, |
| 6502 | _("Set use of MIPS floating-point coprocessor."), |
| 6503 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
| 6504 | add_cmd ("single", class_support, set_mipsfpu_single_command, |
| 6505 | _("Select single-precision MIPS floating-point coprocessor."), |
| 6506 | &mipsfpulist); |
| 6507 | add_cmd ("double", class_support, set_mipsfpu_double_command, |
| 6508 | _("Select double-precision MIPS floating-point coprocessor."), |
| 6509 | &mipsfpulist); |
| 6510 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); |
| 6511 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); |
| 6512 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); |
| 6513 | add_cmd ("none", class_support, set_mipsfpu_none_command, |
| 6514 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
| 6515 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
| 6516 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); |
| 6517 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); |
| 6518 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, |
| 6519 | _("Select MIPS floating-point coprocessor automatically."), |
| 6520 | &mipsfpulist); |
| 6521 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, |
| 6522 | _("Show current use of MIPS floating-point coprocessor target."), |
| 6523 | &showlist); |
| 6524 | |
| 6525 | /* We really would like to have both "0" and "unlimited" work, but |
| 6526 | command.c doesn't deal with that. So make it a var_zinteger |
| 6527 | because the user can always use "999999" or some such for unlimited. */ |
| 6528 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
| 6529 | &heuristic_fence_post, _("\ |
| 6530 | Set the distance searched for the start of a function."), _("\ |
| 6531 | Show the distance searched for the start of a function."), _("\ |
| 6532 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
| 6533 | program for the start of a function. This command sets the distance of the\n\ |
| 6534 | search. The only need to set it is when debugging a stripped executable."), |
| 6535 | reinit_frame_cache_sfunc, |
| 6536 | NULL, /* FIXME: i18n: The distance searched for |
| 6537 | the start of a function is %s. */ |
| 6538 | &setlist, &showlist); |
| 6539 | |
| 6540 | /* Allow the user to control whether the upper bits of 64-bit |
| 6541 | addresses should be zeroed. */ |
| 6542 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
| 6543 | &mask_address_var, _("\ |
| 6544 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ |
| 6545 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ |
| 6546 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
| 6547 | allow GDB to determine the correct value."), |
| 6548 | NULL, show_mask_address, |
| 6549 | &setmipscmdlist, &showmipscmdlist); |
| 6550 | |
| 6551 | /* Allow the user to control the size of 32 bit registers within the |
| 6552 | raw remote packet. */ |
| 6553 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
| 6554 | &mips64_transfers_32bit_regs_p, _("\ |
| 6555 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), |
| 6556 | _("\ |
| 6557 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), |
| 6558 | _("\ |
| 6559 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
| 6560 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ |
| 6561 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
| 6562 | set_mips64_transfers_32bit_regs, |
| 6563 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
| 6564 | MIPS target that transfers 32-bit |
| 6565 | quantities is %s. */ |
| 6566 | &setlist, &showlist); |
| 6567 | |
| 6568 | /* Debug this files internals. */ |
| 6569 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
| 6570 | &mips_debug, _("\ |
| 6571 | Set mips debugging."), _("\ |
| 6572 | Show mips debugging."), _("\ |
| 6573 | When non-zero, mips specific debugging is enabled."), |
| 6574 | NULL, |
| 6575 | NULL, /* FIXME: i18n: Mips debugging is |
| 6576 | currently %s. */ |
| 6577 | &setdebuglist, &showdebuglist); |
| 6578 | } |