[deliverable/binutils-gdb.git] / gdb / mips-tdep.h

/* Target-dependent header for the MIPS architecture, for GDB, the GNU Debugger.

   Copyright (C) 2002-2003, 2007-2012 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef MIPS_TDEP_H
#define MIPS_TDEP_H

struct gdbarch;

/* All the possible MIPS ABIs.  */
enum mips_abi
  {
    MIPS_ABI_UNKNOWN = 0,
    MIPS_ABI_N32,
    MIPS_ABI_O32,
    MIPS_ABI_N64,
    MIPS_ABI_O64,
    MIPS_ABI_EABI32,
    MIPS_ABI_EABI64,
    MIPS_ABI_LAST
  };

/* Return the MIPS ABI associated with GDBARCH.  */
enum mips_abi mips_abi (struct gdbarch *gdbarch);

/* Base and compressed MIPS ISA variations.  */
enum mips_isa
  {
    ISA_MIPS = -1,		/* mips_compression_string depends on it.  */
    ISA_MIPS16,
    ISA_MICROMIPS
  };

/* Return the MIPS ISA's register size.  Just a short cut to the BFD
   architecture's word size.  */
extern int mips_isa_regsize (struct gdbarch *gdbarch);

/* Return the current index for various MIPS registers.  */
struct mips_regnum
{
  int pc;
  int fp0;
  int fp_implementation_revision;
  int fp_control_status;
  int badvaddr;		/* Bad vaddr for addressing exception.  */
  int cause;		/* Describes last exception.  */
  int hi;		/* Multiply/divide temp.  */
  int lo;		/* ...  */
  int dspacc;		/* SmartMIPS/DSP accumulators.  */
  int dspctl;		/* DSP control.  */
};
extern const struct mips_regnum *mips_regnum (struct gdbarch *gdbarch);

/* Some MIPS boards don't support floating point while others only
   support single-precision floating-point operations.  */

enum mips_fpu_type
{
  MIPS_FPU_DOUBLE,		/* Full double precision floating point.  */
  MIPS_FPU_SINGLE,		/* Single precision floating point (R4650).  */
  MIPS_FPU_NONE			/* No floating point.  */
};

/* MIPS specific per-architecture information.  */
struct gdbarch_tdep
{
  /* from the elf header */
  int elf_flags;

  /* mips options */
  enum mips_abi mips_abi;
  enum mips_abi found_abi;
  enum mips_isa mips_isa;
  enum mips_fpu_type mips_fpu_type;
  int mips_last_arg_regnum;
  int mips_last_fp_arg_regnum;
  int default_mask_address_p;
  /* Is the target using 64-bit raw integer registers but only
     storing a left-aligned 32-bit value in each?  */
  int mips64_transfers_32bit_regs_p;
  /* Indexes for various registers.  IRIX and embedded have
     different values.  This contains the "public" fields.  Don't
     add any that do not need to be public.  */
  const struct mips_regnum *regnum;
  /* Register names table for the current register set.  */
  const char **mips_processor_reg_names;

  /* The size of register data available from the target, if known.
     This doesn't quite obsolete the manual
     mips64_transfers_32bit_regs_p, since that is documented to force
     left alignment even for big endian (very strange).  */
  int register_size_valid_p;
  int register_size;

  /* General-purpose registers.  */
  struct regset *gregset;
  struct regset *gregset64;

  /* Floating-point registers.  */
  struct regset *fpregset;
  struct regset *fpregset64;

  /* Return the expected next PC if FRAME is stopped at a syscall
     instruction.  */
  CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
};

/* Register numbers of various important registers.  */

enum
{
  MIPS_ZERO_REGNUM = 0,		/* Read-only register, always 0.  */
  MIPS_AT_REGNUM = 1,
  MIPS_V0_REGNUM = 2,		/* Function integer return value.  */
  MIPS_A0_REGNUM = 4,		/* Loc of first arg during a subr call.  */
  MIPS_S2_REGNUM = 18,		/* Contains return address in MIPS16 thunks. */
  MIPS_T9_REGNUM = 25,		/* Contains address of callee in PIC.  */
  MIPS_GP_REGNUM = 28,
  MIPS_SP_REGNUM = 29,
  MIPS_RA_REGNUM = 31,
  MIPS_PS_REGNUM = 32,		/* Contains processor status.  */
  MIPS_EMBED_LO_REGNUM = 33,
  MIPS_EMBED_HI_REGNUM = 34,
  MIPS_EMBED_BADVADDR_REGNUM = 35,
  MIPS_EMBED_CAUSE_REGNUM = 36,
  MIPS_EMBED_PC_REGNUM = 37,
  MIPS_EMBED_FP0_REGNUM = 38,
  MIPS_UNUSED_REGNUM = 73,	/* Never used, FIXME.  */
  MIPS_FIRST_EMBED_REGNUM = 74,	/* First CP0 register for embedded use.  */
  MIPS_PRID_REGNUM = 89,	/* Processor ID.  */
  MIPS_LAST_EMBED_REGNUM = 89	/* Last one.  */
};

/* Defined in mips-tdep.c and used in remote-mips.c.  */
extern void deprecated_mips_set_processor_regs_hack (void);

/* Instruction sizes and other useful constants.  */
enum
{
  MIPS_INSN16_SIZE = 2,
  MIPS_INSN32_SIZE = 4,
  /* The number of floating-point or integer registers.  */
  MIPS_NUMREGS = 32
};

/* Single step based on where the current instruction will take us.  */
extern int mips_software_single_step (struct frame_info *frame);

/* Tell if the program counter value in MEMADDR is in a standard
   MIPS function.  */
extern int mips_pc_is_mips (bfd_vma memaddr);

/* Tell if the program counter value in MEMADDR is in a MIPS16
   function.  */
extern int mips_pc_is_mips16 (struct gdbarch *gdbarch, bfd_vma memaddr);

/* Tell if the program counter value in MEMADDR is in a microMIPS
   function.  */
extern int mips_pc_is_micromips (struct gdbarch *gdbarch, bfd_vma memaddr);

/* Return the currently configured (or set) saved register size.  */
extern unsigned int mips_abi_regsize (struct gdbarch *gdbarch);

/* Make PC the address of the next instruction to execute.  */
extern void mips_write_pc (struct regcache *regcache, CORE_ADDR pc);

/* Target descriptions which only indicate the size of general
   registers.  */
extern struct target_desc *mips_tdesc_gp32;
extern struct target_desc *mips_tdesc_gp64;

#endif /* MIPS_TDEP_H */
Commit	Line	Data
	1	/* Target-dependent header for the MIPS architecture, for GDB, the GNU Debugger.
	2
	3	Copyright (C) 2002-2003, 2007-2012 Free Software Foundation, Inc.
	4
	5	This file is part of GDB.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 3 of the License, or
	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	19
	20	#ifndef MIPS_TDEP_H
	21	#define MIPS_TDEP_H
	22
	23	struct gdbarch;
	24
	25	/* All the possible MIPS ABIs. */
	26	enum mips_abi
	27	{
	28	MIPS_ABI_UNKNOWN = 0,
	29	MIPS_ABI_N32,
	30	MIPS_ABI_O32,
	31	MIPS_ABI_N64,
	32	MIPS_ABI_O64,
	33	MIPS_ABI_EABI32,
	34	MIPS_ABI_EABI64,
	35	MIPS_ABI_LAST
	36	};
	37
	38	/* Return the MIPS ABI associated with GDBARCH. */
	39	enum mips_abi mips_abi (struct gdbarch *gdbarch);
	40
	41	/* Base and compressed MIPS ISA variations. */
	42	enum mips_isa
	43	{
	44	ISA_MIPS = -1, /* mips_compression_string depends on it. */
	45	ISA_MIPS16,
	46	ISA_MICROMIPS
	47	};
	48
	49	/* Return the MIPS ISA's register size. Just a short cut to the BFD
	50	architecture's word size. */
	51	extern int mips_isa_regsize (struct gdbarch *gdbarch);
	52
	53	/* Return the current index for various MIPS registers. */
	54	struct mips_regnum
	55	{
	56	int pc;
	57	int fp0;
	58	int fp_implementation_revision;
	59	int fp_control_status;
	60	int badvaddr; /* Bad vaddr for addressing exception. */
	61	int cause; /* Describes last exception. */
	62	int hi; /* Multiply/divide temp. */
	63	int lo; /* ... */
	64	int dspacc; /* SmartMIPS/DSP accumulators. */
	65	int dspctl; /* DSP control. */
	66	};
	67	extern const struct mips_regnum mips_regnum (struct gdbarch gdbarch);
	68
	69	/* Some MIPS boards don't support floating point while others only
	70	support single-precision floating-point operations. */
	71
	72	enum mips_fpu_type
	73	{
	74	MIPS_FPU_DOUBLE, /* Full double precision floating point. */
	75	MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
	76	MIPS_FPU_NONE /* No floating point. */
	77	};
	78
	79	/* MIPS specific per-architecture information. */
	80	struct gdbarch_tdep
	81	{
	82	/* from the elf header */
	83	int elf_flags;
	84
	85	/* mips options */
	86	enum mips_abi mips_abi;
	87	enum mips_abi found_abi;
	88	enum mips_isa mips_isa;
	89	enum mips_fpu_type mips_fpu_type;
	90	int mips_last_arg_regnum;
	91	int mips_last_fp_arg_regnum;
	92	int default_mask_address_p;
	93	/* Is the target using 64-bit raw integer registers but only
	94	storing a left-aligned 32-bit value in each? */
	95	int mips64_transfers_32bit_regs_p;
	96	/* Indexes for various registers. IRIX and embedded have
	97	different values. This contains the "public" fields. Don't
	98	add any that do not need to be public. */
	99	const struct mips_regnum *regnum;
	100	/* Register names table for the current register set. */
	101	const char **mips_processor_reg_names;
	102
	103	/* The size of register data available from the target, if known.
	104	This doesn't quite obsolete the manual
	105	mips64_transfers_32bit_regs_p, since that is documented to force
	106	left alignment even for big endian (very strange). */
	107	int register_size_valid_p;
	108	int register_size;
	109
	110	/* General-purpose registers. */
	111	struct regset *gregset;
	112	struct regset *gregset64;
	113
	114	/* Floating-point registers. */
	115	struct regset *fpregset;
	116	struct regset *fpregset64;
	117
	118	/* Return the expected next PC if FRAME is stopped at a syscall
	119	instruction. */
	120	CORE_ADDR (syscall_next_pc) (struct frame_info frame);
	121	};
	122
	123	/* Register numbers of various important registers. */
	124
	125	enum
	126	{
	127	MIPS_ZERO_REGNUM = 0, /* Read-only register, always 0. */
	128	MIPS_AT_REGNUM = 1,
	129	MIPS_V0_REGNUM = 2, /* Function integer return value. */
	130	MIPS_A0_REGNUM = 4, /* Loc of first arg during a subr call. */
	131	MIPS_S2_REGNUM = 18, /* Contains return address in MIPS16 thunks. */
	132	MIPS_T9_REGNUM = 25, /* Contains address of callee in PIC. */
	133	MIPS_GP_REGNUM = 28,
	134	MIPS_SP_REGNUM = 29,
	135	MIPS_RA_REGNUM = 31,
	136	MIPS_PS_REGNUM = 32, /* Contains processor status. */
	137	MIPS_EMBED_LO_REGNUM = 33,
	138	MIPS_EMBED_HI_REGNUM = 34,
	139	MIPS_EMBED_BADVADDR_REGNUM = 35,
	140	MIPS_EMBED_CAUSE_REGNUM = 36,
	141	MIPS_EMBED_PC_REGNUM = 37,
	142	MIPS_EMBED_FP0_REGNUM = 38,
	143	MIPS_UNUSED_REGNUM = 73, /* Never used, FIXME. */
	144	MIPS_FIRST_EMBED_REGNUM = 74, /* First CP0 register for embedded use. */
	145	MIPS_PRID_REGNUM = 89, /* Processor ID. */
	146	MIPS_LAST_EMBED_REGNUM = 89 /* Last one. */
	147	};
	148
	149	/* Defined in mips-tdep.c and used in remote-mips.c. */
	150	extern void deprecated_mips_set_processor_regs_hack (void);
	151
	152	/* Instruction sizes and other useful constants. */
	153	enum
	154	{
	155	MIPS_INSN16_SIZE = 2,
	156	MIPS_INSN32_SIZE = 4,
	157	/* The number of floating-point or integer registers. */
	158	MIPS_NUMREGS = 32
	159	};
	160
	161	/* Single step based on where the current instruction will take us. */
	162	extern int mips_software_single_step (struct frame_info *frame);
	163
	164	/* Tell if the program counter value in MEMADDR is in a standard
	165	MIPS function. */
	166	extern int mips_pc_is_mips (bfd_vma memaddr);
	167
	168	/* Tell if the program counter value in MEMADDR is in a MIPS16
	169	function. */
	170	extern int mips_pc_is_mips16 (struct gdbarch *gdbarch, bfd_vma memaddr);
	171
	172	/* Tell if the program counter value in MEMADDR is in a microMIPS
	173	function. */
	174	extern int mips_pc_is_micromips (struct gdbarch *gdbarch, bfd_vma memaddr);
	175
	176	/* Return the currently configured (or set) saved register size. */
	177	extern unsigned int mips_abi_regsize (struct gdbarch *gdbarch);
	178
	179	/* Make PC the address of the next instruction to execute. */
	180	extern void mips_write_pc (struct regcache *regcache, CORE_ADDR pc);
	181
	182	/* Target descriptions which only indicate the size of general
	183	registers. */
	184	extern struct target_desc *mips_tdesc_gp32;
	185	extern struct target_desc *mips_tdesc_gp64;
	186
	187	#endif /* MIPS_TDEP_H */