[deliverable/binutils-gdb.git] / gdb / mips-tdep.h

/* Target-dependent header for the MIPS architecture, for GDB, the GNU Debugger.

   Copyright (C) 2002, 2003, 2007, 2008, 2009, 2010, 2011
   Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef MIPS_TDEP_H
#define MIPS_TDEP_H

struct gdbarch;

/* All the possible MIPS ABIs.  */
enum mips_abi
  {
    MIPS_ABI_UNKNOWN = 0,
    MIPS_ABI_N32,
    MIPS_ABI_O32,
    MIPS_ABI_N64,
    MIPS_ABI_O64,
    MIPS_ABI_EABI32,
    MIPS_ABI_EABI64,
    MIPS_ABI_LAST
  };

/* Return the MIPS ABI associated with GDBARCH.  */
enum mips_abi mips_abi (struct gdbarch *gdbarch);

/* Return the MIPS ISA's register size.  Just a short cut to the BFD
   architecture's word size.  */
extern int mips_isa_regsize (struct gdbarch *gdbarch);

/* Return the current index for various MIPS registers.  */
struct mips_regnum
{
  int pc;
  int fp0;
  int fp_implementation_revision;
  int fp_control_status;
  int badvaddr;		/* Bad vaddr for addressing exception.  */
  int cause;		/* Describes last exception.  */
  int hi;		/* Multiply/divide temp.  */
  int lo;		/* ...  */
};
extern const struct mips_regnum *mips_regnum (struct gdbarch *gdbarch);

/* Some MIPS boards don't support floating point while others only
   support single-precision floating-point operations.  */

enum mips_fpu_type
{
  MIPS_FPU_DOUBLE,		/* Full double precision floating point.  */
  MIPS_FPU_SINGLE,		/* Single precision floating point (R4650).  */
  MIPS_FPU_NONE			/* No floating point.  */
};

/* MIPS specific per-architecture information.  */
struct gdbarch_tdep
{
  /* from the elf header */
  int elf_flags;

  /* mips options */
  enum mips_abi mips_abi;
  enum mips_abi found_abi;
  enum mips_fpu_type mips_fpu_type;
  int mips_last_arg_regnum;
  int mips_last_fp_arg_regnum;
  int default_mask_address_p;
  /* Is the target using 64-bit raw integer registers but only
     storing a left-aligned 32-bit value in each?  */
  int mips64_transfers_32bit_regs_p;
  /* Indexes for various registers.  IRIX and embedded have
     different values.  This contains the "public" fields.  Don't
     add any that do not need to be public.  */
  const struct mips_regnum *regnum;
  /* Register names table for the current register set.  */
  const char **mips_processor_reg_names;

  /* The size of register data available from the target, if known.
     This doesn't quite obsolete the manual
     mips64_transfers_32bit_regs_p, since that is documented to force
     left alignment even for big endian (very strange).  */
  int register_size_valid_p;
  int register_size;

  /* General-purpose registers.  */
  struct regset *gregset;
  struct regset *gregset64;

  /* Floating-point registers.  */
  struct regset *fpregset;
  struct regset *fpregset64;

  /* Return the expected next PC if FRAME is stopped at a syscall
     instruction.  */
  CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
};

/* Register numbers of various important registers.  */

enum
{
  MIPS_ZERO_REGNUM = 0,		/* Read-only register, always 0.  */
  MIPS_AT_REGNUM = 1,
  MIPS_V0_REGNUM = 2,		/* Function integer return value.  */
  MIPS_A0_REGNUM = 4,		/* Loc of first arg during a subr call.  */
  MIPS_T9_REGNUM = 25,		/* Contains address of callee in PIC.  */
  MIPS_SP_REGNUM = 29,
  MIPS_RA_REGNUM = 31,
  MIPS_PS_REGNUM = 32,		/* Contains processor status.  */
  MIPS_EMBED_LO_REGNUM = 33,
  MIPS_EMBED_HI_REGNUM = 34,
  MIPS_EMBED_BADVADDR_REGNUM = 35,
  MIPS_EMBED_CAUSE_REGNUM = 36,
  MIPS_EMBED_PC_REGNUM = 37,
  MIPS_EMBED_FP0_REGNUM = 38,
  MIPS_UNUSED_REGNUM = 73,	/* Never used, FIXME.  */
  MIPS_FIRST_EMBED_REGNUM = 74,	/* First CP0 register for embedded use.  */
  MIPS_PRID_REGNUM = 89,	/* Processor ID.  */
  MIPS_LAST_EMBED_REGNUM = 89	/* Last one.  */
};

/* Defined in mips-tdep.c and used in remote-mips.c.  */
extern void deprecated_mips_set_processor_regs_hack (void);

/* Instruction sizes and other useful constants.  */
enum
{
  MIPS_INSN16_SIZE = 2,
  MIPS_INSN32_SIZE = 4,
  /* The number of floating-point or integer registers.  */
  MIPS_NUMREGS = 32
};

/* Single step based on where the current instruction will take us.  */
extern int mips_software_single_step (struct frame_info *frame);

/* Tell if the program counter value in MEMADDR is in a MIPS16
   function.  */
extern int mips_pc_is_mips16 (bfd_vma memaddr);

/* Return the currently configured (or set) saved register size.  */
extern unsigned int mips_abi_regsize (struct gdbarch *gdbarch);

/* Target descriptions which only indicate the size of general
   registers.  */
extern struct target_desc *mips_tdesc_gp32;
extern struct target_desc *mips_tdesc_gp64;

#endif /* MIPS_TDEP_H */
Commit	Line	Data
	1	/* Target-dependent header for the MIPS architecture, for GDB, the GNU Debugger.
	2
	3	Copyright (C) 2002, 2003, 2007, 2008, 2009, 2010, 2011
	4	Free Software Foundation, Inc.
	5
	6	This file is part of GDB.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 3 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	20
	21	#ifndef MIPS_TDEP_H
	22	#define MIPS_TDEP_H
	23
	24	struct gdbarch;
	25
	26	/* All the possible MIPS ABIs. */
	27	enum mips_abi
	28	{
	29	MIPS_ABI_UNKNOWN = 0,
	30	MIPS_ABI_N32,
	31	MIPS_ABI_O32,
	32	MIPS_ABI_N64,
	33	MIPS_ABI_O64,
	34	MIPS_ABI_EABI32,
	35	MIPS_ABI_EABI64,
	36	MIPS_ABI_LAST
	37	};
	38
	39	/* Return the MIPS ABI associated with GDBARCH. */
	40	enum mips_abi mips_abi (struct gdbarch *gdbarch);
	41
	42	/* Return the MIPS ISA's register size. Just a short cut to the BFD
	43	architecture's word size. */
	44	extern int mips_isa_regsize (struct gdbarch *gdbarch);
	45
	46	/* Return the current index for various MIPS registers. */
	47	struct mips_regnum
	48	{
	49	int pc;
	50	int fp0;
	51	int fp_implementation_revision;
	52	int fp_control_status;
	53	int badvaddr; /* Bad vaddr for addressing exception. */
	54	int cause; /* Describes last exception. */
	55	int hi; /* Multiply/divide temp. */
	56	int lo; /* ... */
	57	};
	58	extern const struct mips_regnum mips_regnum (struct gdbarch gdbarch);
	59
	60	/* Some MIPS boards don't support floating point while others only
	61	support single-precision floating-point operations. */
	62
	63	enum mips_fpu_type
	64	{
	65	MIPS_FPU_DOUBLE, /* Full double precision floating point. */
	66	MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
	67	MIPS_FPU_NONE /* No floating point. */
	68	};
	69
	70	/* MIPS specific per-architecture information. */
	71	struct gdbarch_tdep
	72	{
	73	/* from the elf header */
	74	int elf_flags;
	75
	76	/* mips options */
	77	enum mips_abi mips_abi;
	78	enum mips_abi found_abi;
	79	enum mips_fpu_type mips_fpu_type;
	80	int mips_last_arg_regnum;
	81	int mips_last_fp_arg_regnum;
	82	int default_mask_address_p;
	83	/* Is the target using 64-bit raw integer registers but only
	84	storing a left-aligned 32-bit value in each? */
	85	int mips64_transfers_32bit_regs_p;
	86	/* Indexes for various registers. IRIX and embedded have
	87	different values. This contains the "public" fields. Don't
	88	add any that do not need to be public. */
	89	const struct mips_regnum *regnum;
	90	/* Register names table for the current register set. */
	91	const char **mips_processor_reg_names;
	92
	93	/* The size of register data available from the target, if known.
	94	This doesn't quite obsolete the manual
	95	mips64_transfers_32bit_regs_p, since that is documented to force
	96	left alignment even for big endian (very strange). */
	97	int register_size_valid_p;
	98	int register_size;
	99
	100	/* General-purpose registers. */
	101	struct regset *gregset;
	102	struct regset *gregset64;
	103
	104	/* Floating-point registers. */
	105	struct regset *fpregset;
	106	struct regset *fpregset64;
	107
	108	/* Return the expected next PC if FRAME is stopped at a syscall
	109	instruction. */
	110	CORE_ADDR (syscall_next_pc) (struct frame_info frame);
	111	};
	112
	113	/* Register numbers of various important registers. */
	114
	115	enum
	116	{
	117	MIPS_ZERO_REGNUM = 0, /* Read-only register, always 0. */
	118	MIPS_AT_REGNUM = 1,
	119	MIPS_V0_REGNUM = 2, /* Function integer return value. */
	120	MIPS_A0_REGNUM = 4, /* Loc of first arg during a subr call. */
	121	MIPS_T9_REGNUM = 25, /* Contains address of callee in PIC. */
	122	MIPS_SP_REGNUM = 29,
	123	MIPS_RA_REGNUM = 31,
	124	MIPS_PS_REGNUM = 32, /* Contains processor status. */
	125	MIPS_EMBED_LO_REGNUM = 33,
	126	MIPS_EMBED_HI_REGNUM = 34,
	127	MIPS_EMBED_BADVADDR_REGNUM = 35,
	128	MIPS_EMBED_CAUSE_REGNUM = 36,
	129	MIPS_EMBED_PC_REGNUM = 37,
	130	MIPS_EMBED_FP0_REGNUM = 38,
	131	MIPS_UNUSED_REGNUM = 73, /* Never used, FIXME. */
	132	MIPS_FIRST_EMBED_REGNUM = 74, /* First CP0 register for embedded use. */
	133	MIPS_PRID_REGNUM = 89, /* Processor ID. */
	134	MIPS_LAST_EMBED_REGNUM = 89 /* Last one. */
	135	};
	136
	137	/* Defined in mips-tdep.c and used in remote-mips.c. */
	138	extern void deprecated_mips_set_processor_regs_hack (void);
	139
	140	/* Instruction sizes and other useful constants. */
	141	enum
	142	{
	143	MIPS_INSN16_SIZE = 2,
	144	MIPS_INSN32_SIZE = 4,
	145	/* The number of floating-point or integer registers. */
	146	MIPS_NUMREGS = 32
	147	};
	148
	149	/* Single step based on where the current instruction will take us. */
	150	extern int mips_software_single_step (struct frame_info *frame);
	151
	152	/* Tell if the program counter value in MEMADDR is in a MIPS16
	153	function. */
	154	extern int mips_pc_is_mips16 (bfd_vma memaddr);
	155
	156	/* Return the currently configured (or set) saved register size. */
	157	extern unsigned int mips_abi_regsize (struct gdbarch *gdbarch);
	158
	159	/* Target descriptions which only indicate the size of general
	160	registers. */
	161	extern struct target_desc *mips_tdesc_gp32;
	162	extern struct target_desc *mips_tdesc_gp64;
	163
	164	#endif /* MIPS_TDEP_H */