| 1 | /* Target-dependent header for the MIPS architecture, for GDB, the GNU Debugger. |
| 2 | |
| 3 | Copyright (C) 2002, 2003, 2007, 2008, 2009 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #ifndef MIPS_TDEP_H |
| 21 | #define MIPS_TDEP_H |
| 22 | |
| 23 | struct gdbarch; |
| 24 | |
| 25 | /* All the possible MIPS ABIs. */ |
| 26 | enum mips_abi |
| 27 | { |
| 28 | MIPS_ABI_UNKNOWN = 0, |
| 29 | MIPS_ABI_N32, |
| 30 | MIPS_ABI_O32, |
| 31 | MIPS_ABI_N64, |
| 32 | MIPS_ABI_O64, |
| 33 | MIPS_ABI_EABI32, |
| 34 | MIPS_ABI_EABI64, |
| 35 | MIPS_ABI_LAST |
| 36 | }; |
| 37 | |
| 38 | /* Return the MIPS ABI associated with GDBARCH. */ |
| 39 | enum mips_abi mips_abi (struct gdbarch *gdbarch); |
| 40 | |
| 41 | /* Return the MIPS ISA's register size. Just a short cut to the BFD |
| 42 | architecture's word size. */ |
| 43 | extern int mips_isa_regsize (struct gdbarch *gdbarch); |
| 44 | |
| 45 | /* Return the current index for various MIPS registers. */ |
| 46 | struct mips_regnum |
| 47 | { |
| 48 | int pc; |
| 49 | int fp0; |
| 50 | int fp_implementation_revision; |
| 51 | int fp_control_status; |
| 52 | int badvaddr; /* Bad vaddr for addressing exception. */ |
| 53 | int cause; /* Describes last exception. */ |
| 54 | int hi; /* Multiply/divide temp. */ |
| 55 | int lo; /* ... */ |
| 56 | }; |
| 57 | extern const struct mips_regnum *mips_regnum (struct gdbarch *gdbarch); |
| 58 | |
| 59 | /* Some MIPS boards don't support floating point while others only |
| 60 | support single-precision floating-point operations. */ |
| 61 | |
| 62 | enum mips_fpu_type |
| 63 | { |
| 64 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ |
| 65 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ |
| 66 | MIPS_FPU_NONE /* No floating point. */ |
| 67 | }; |
| 68 | |
| 69 | /* MIPS specific per-architecture information */ |
| 70 | struct gdbarch_tdep |
| 71 | { |
| 72 | /* from the elf header */ |
| 73 | int elf_flags; |
| 74 | |
| 75 | /* mips options */ |
| 76 | enum mips_abi mips_abi; |
| 77 | enum mips_abi found_abi; |
| 78 | enum mips_fpu_type mips_fpu_type; |
| 79 | int mips_last_arg_regnum; |
| 80 | int mips_last_fp_arg_regnum; |
| 81 | int default_mask_address_p; |
| 82 | /* Is the target using 64-bit raw integer registers but only |
| 83 | storing a left-aligned 32-bit value in each? */ |
| 84 | int mips64_transfers_32bit_regs_p; |
| 85 | /* Indexes for various registers. IRIX and embedded have |
| 86 | different values. This contains the "public" fields. Don't |
| 87 | add any that do not need to be public. */ |
| 88 | const struct mips_regnum *regnum; |
| 89 | /* Register names table for the current register set. */ |
| 90 | const char **mips_processor_reg_names; |
| 91 | |
| 92 | /* The size of register data available from the target, if known. |
| 93 | This doesn't quite obsolete the manual |
| 94 | mips64_transfers_32bit_regs_p, since that is documented to force |
| 95 | left alignment even for big endian (very strange). */ |
| 96 | int register_size_valid_p; |
| 97 | int register_size; |
| 98 | |
| 99 | /* Return the expected next PC if FRAME is stopped at a syscall |
| 100 | instruction. */ |
| 101 | CORE_ADDR (*syscall_next_pc) (struct frame_info *frame); |
| 102 | }; |
| 103 | |
| 104 | /* Register numbers of various important registers. */ |
| 105 | |
| 106 | enum |
| 107 | { |
| 108 | MIPS_ZERO_REGNUM = 0, /* Read-only register, always 0. */ |
| 109 | MIPS_AT_REGNUM = 1, |
| 110 | MIPS_V0_REGNUM = 2, /* Function integer return value. */ |
| 111 | MIPS_A0_REGNUM = 4, /* Loc of first arg during a subr call */ |
| 112 | MIPS_T9_REGNUM = 25, /* Contains address of callee in PIC. */ |
| 113 | MIPS_SP_REGNUM = 29, |
| 114 | MIPS_RA_REGNUM = 31, |
| 115 | MIPS_PS_REGNUM = 32, /* Contains processor status. */ |
| 116 | MIPS_EMBED_LO_REGNUM = 33, |
| 117 | MIPS_EMBED_HI_REGNUM = 34, |
| 118 | MIPS_EMBED_BADVADDR_REGNUM = 35, |
| 119 | MIPS_EMBED_CAUSE_REGNUM = 36, |
| 120 | MIPS_EMBED_PC_REGNUM = 37, |
| 121 | MIPS_EMBED_FP0_REGNUM = 38, |
| 122 | MIPS_UNUSED_REGNUM = 73, /* Never used, FIXME */ |
| 123 | MIPS_FIRST_EMBED_REGNUM = 74, /* First CP0 register for embedded use. */ |
| 124 | MIPS_PRID_REGNUM = 89, /* Processor ID. */ |
| 125 | MIPS_LAST_EMBED_REGNUM = 89 /* Last one. */ |
| 126 | }; |
| 127 | |
| 128 | /* Defined in mips-tdep.c and used in remote-mips.c */ |
| 129 | extern void deprecated_mips_set_processor_regs_hack (void); |
| 130 | |
| 131 | /* Instruction sizes and other useful constants. */ |
| 132 | enum |
| 133 | { |
| 134 | MIPS_INSN16_SIZE = 2, |
| 135 | MIPS_INSN32_SIZE = 4, |
| 136 | /* The number of floating-point or integer registers. */ |
| 137 | MIPS_NUMREGS = 32 |
| 138 | }; |
| 139 | |
| 140 | /* Single step based on where the current instruction will take us. */ |
| 141 | extern int mips_software_single_step (struct frame_info *frame); |
| 142 | |
| 143 | /* Tell if the program counter value in MEMADDR is in a MIPS16 |
| 144 | function. */ |
| 145 | extern int mips_pc_is_mips16 (bfd_vma memaddr); |
| 146 | |
| 147 | /* Return the currently configured (or set) saved register size. */ |
| 148 | extern unsigned int mips_abi_regsize (struct gdbarch *gdbarch); |
| 149 | |
| 150 | /* Target descriptions which only indicate the size of general |
| 151 | registers. */ |
| 152 | extern struct target_desc *mips_tdesc_gp32; |
| 153 | extern struct target_desc *mips_tdesc_gp64; |
| 154 | |
| 155 | #endif /* MIPS_TDEP_H */ |