| 1 | /* Target-dependent code for Morpho mt processor, for GDB. |
| 2 | |
| 3 | Copyright (C) 2005, 2007 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program; if not, write to the Free Software |
| 19 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
| 20 | Boston, MA 02110-1301, USA. */ |
| 21 | |
| 22 | /* Contributed by Michael Snyder, msnyder@redhat.com. */ |
| 23 | |
| 24 | #include "defs.h" |
| 25 | #include "frame.h" |
| 26 | #include "frame-unwind.h" |
| 27 | #include "frame-base.h" |
| 28 | #include "symtab.h" |
| 29 | #include "dis-asm.h" |
| 30 | #include "arch-utils.h" |
| 31 | #include "gdbtypes.h" |
| 32 | #include "gdb_string.h" |
| 33 | #include "regcache.h" |
| 34 | #include "reggroups.h" |
| 35 | #include "gdbcore.h" |
| 36 | #include "trad-frame.h" |
| 37 | #include "inferior.h" |
| 38 | #include "dwarf2-frame.h" |
| 39 | #include "infcall.h" |
| 40 | #include "gdb_assert.h" |
| 41 | |
| 42 | enum mt_arch_constants |
| 43 | { |
| 44 | MT_MAX_STRUCT_SIZE = 16 |
| 45 | }; |
| 46 | |
| 47 | enum mt_gdb_regnums |
| 48 | { |
| 49 | MT_R0_REGNUM, /* 32 bit regs. */ |
| 50 | MT_R1_REGNUM, |
| 51 | MT_1ST_ARGREG = MT_R1_REGNUM, |
| 52 | MT_R2_REGNUM, |
| 53 | MT_R3_REGNUM, |
| 54 | MT_R4_REGNUM, |
| 55 | MT_LAST_ARGREG = MT_R4_REGNUM, |
| 56 | MT_R5_REGNUM, |
| 57 | MT_R6_REGNUM, |
| 58 | MT_R7_REGNUM, |
| 59 | MT_R8_REGNUM, |
| 60 | MT_R9_REGNUM, |
| 61 | MT_R10_REGNUM, |
| 62 | MT_R11_REGNUM, |
| 63 | MT_R12_REGNUM, |
| 64 | MT_FP_REGNUM = MT_R12_REGNUM, |
| 65 | MT_R13_REGNUM, |
| 66 | MT_SP_REGNUM = MT_R13_REGNUM, |
| 67 | MT_R14_REGNUM, |
| 68 | MT_RA_REGNUM = MT_R14_REGNUM, |
| 69 | MT_R15_REGNUM, |
| 70 | MT_IRA_REGNUM = MT_R15_REGNUM, |
| 71 | MT_PC_REGNUM, |
| 72 | |
| 73 | /* Interrupt Enable pseudo-register, exported by SID. */ |
| 74 | MT_INT_ENABLE_REGNUM, |
| 75 | /* End of CPU regs. */ |
| 76 | |
| 77 | MT_NUM_CPU_REGS, |
| 78 | |
| 79 | /* Co-processor registers. */ |
| 80 | MT_COPRO_REGNUM = MT_NUM_CPU_REGS, /* 16 bit regs. */ |
| 81 | MT_CPR0_REGNUM, |
| 82 | MT_CPR1_REGNUM, |
| 83 | MT_CPR2_REGNUM, |
| 84 | MT_CPR3_REGNUM, |
| 85 | MT_CPR4_REGNUM, |
| 86 | MT_CPR5_REGNUM, |
| 87 | MT_CPR6_REGNUM, |
| 88 | MT_CPR7_REGNUM, |
| 89 | MT_CPR8_REGNUM, |
| 90 | MT_CPR9_REGNUM, |
| 91 | MT_CPR10_REGNUM, |
| 92 | MT_CPR11_REGNUM, |
| 93 | MT_CPR12_REGNUM, |
| 94 | MT_CPR13_REGNUM, |
| 95 | MT_CPR14_REGNUM, |
| 96 | MT_CPR15_REGNUM, |
| 97 | MT_BYPA_REGNUM, /* 32 bit regs. */ |
| 98 | MT_BYPB_REGNUM, |
| 99 | MT_BYPC_REGNUM, |
| 100 | MT_FLAG_REGNUM, |
| 101 | MT_CONTEXT_REGNUM, /* 38 bits (treat as array of |
| 102 | six bytes). */ |
| 103 | MT_MAC_REGNUM, /* 32 bits. */ |
| 104 | MT_Z1_REGNUM, /* 16 bits. */ |
| 105 | MT_Z2_REGNUM, /* 16 bits. */ |
| 106 | MT_ICHANNEL_REGNUM, /* 32 bits. */ |
| 107 | MT_ISCRAMB_REGNUM, /* 32 bits. */ |
| 108 | MT_QSCRAMB_REGNUM, /* 32 bits. */ |
| 109 | MT_OUT_REGNUM, /* 16 bits. */ |
| 110 | MT_EXMAC_REGNUM, /* 32 bits (8 used). */ |
| 111 | MT_QCHANNEL_REGNUM, /* 32 bits. */ |
| 112 | MT_ZI2_REGNUM, /* 16 bits. */ |
| 113 | MT_ZQ2_REGNUM, /* 16 bits. */ |
| 114 | MT_CHANNEL2_REGNUM, /* 32 bits. */ |
| 115 | MT_ISCRAMB2_REGNUM, /* 32 bits. */ |
| 116 | MT_QSCRAMB2_REGNUM, /* 32 bits. */ |
| 117 | MT_QCHANNEL2_REGNUM, /* 32 bits. */ |
| 118 | |
| 119 | /* Number of real registers. */ |
| 120 | MT_NUM_REGS, |
| 121 | |
| 122 | /* Pseudo-registers. */ |
| 123 | MT_COPRO_PSEUDOREG_REGNUM = MT_NUM_REGS, |
| 124 | MT_MAC_PSEUDOREG_REGNUM, |
| 125 | MT_COPRO_PSEUDOREG_ARRAY, |
| 126 | |
| 127 | MT_COPRO_PSEUDOREG_DIM_1 = 2, |
| 128 | MT_COPRO_PSEUDOREG_DIM_2 = 8, |
| 129 | /* The number of pseudo-registers for each coprocessor. These |
| 130 | include the real coprocessor registers, the pseudo-registe for |
| 131 | the coprocessor number, and the pseudo-register for the MAC. */ |
| 132 | MT_COPRO_PSEUDOREG_REGS = MT_NUM_REGS - MT_NUM_CPU_REGS + 2, |
| 133 | /* The register number of the MAC, relative to a given coprocessor. */ |
| 134 | MT_COPRO_PSEUDOREG_MAC_REGNUM = MT_COPRO_PSEUDOREG_REGS - 1, |
| 135 | |
| 136 | /* Two pseudo-regs ('coprocessor' and 'mac'). */ |
| 137 | MT_NUM_PSEUDO_REGS = 2 + (MT_COPRO_PSEUDOREG_REGS |
| 138 | * MT_COPRO_PSEUDOREG_DIM_1 |
| 139 | * MT_COPRO_PSEUDOREG_DIM_2) |
| 140 | }; |
| 141 | |
| 142 | /* Return name of register number specified by REGNUM. */ |
| 143 | |
| 144 | static const char * |
| 145 | mt_register_name (int regnum) |
| 146 | { |
| 147 | static const char *const register_names[] = { |
| 148 | /* CPU regs. */ |
| 149 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 150 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 151 | "pc", "IE", |
| 152 | /* Co-processor regs. */ |
| 153 | "", /* copro register. */ |
| 154 | "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", |
| 155 | "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15", |
| 156 | "bypa", "bypb", "bypc", "flag", "context", "" /* mac. */ , "z1", "z2", |
| 157 | "Ichannel", "Iscramb", "Qscramb", "out", "" /* ex-mac. */ , "Qchannel", |
| 158 | "zi2", "zq2", "Ichannel2", "Iscramb2", "Qscramb2", "Qchannel2", |
| 159 | /* Pseudo-registers. */ |
| 160 | "coprocessor", "MAC" |
| 161 | }; |
| 162 | static const char *array_names[MT_COPRO_PSEUDOREG_REGS |
| 163 | * MT_COPRO_PSEUDOREG_DIM_1 |
| 164 | * MT_COPRO_PSEUDOREG_DIM_2]; |
| 165 | |
| 166 | if (regnum < 0) |
| 167 | return ""; |
| 168 | if (regnum < ARRAY_SIZE (register_names)) |
| 169 | return register_names[regnum]; |
| 170 | if (array_names[regnum - MT_COPRO_PSEUDOREG_ARRAY]) |
| 171 | return array_names[regnum - MT_COPRO_PSEUDOREG_ARRAY]; |
| 172 | |
| 173 | { |
| 174 | char *name; |
| 175 | const char *stub; |
| 176 | unsigned dim_1; |
| 177 | unsigned dim_2; |
| 178 | unsigned index; |
| 179 | |
| 180 | regnum -= MT_COPRO_PSEUDOREG_ARRAY; |
| 181 | index = regnum % MT_COPRO_PSEUDOREG_REGS; |
| 182 | dim_2 = (regnum / MT_COPRO_PSEUDOREG_REGS) % MT_COPRO_PSEUDOREG_DIM_2; |
| 183 | dim_1 = ((regnum / MT_COPRO_PSEUDOREG_REGS / MT_COPRO_PSEUDOREG_DIM_2) |
| 184 | % MT_COPRO_PSEUDOREG_DIM_1); |
| 185 | |
| 186 | if (index == MT_COPRO_PSEUDOREG_MAC_REGNUM) |
| 187 | stub = register_names[MT_MAC_PSEUDOREG_REGNUM]; |
| 188 | else if (index >= MT_NUM_REGS - MT_CPR0_REGNUM) |
| 189 | stub = ""; |
| 190 | else |
| 191 | stub = register_names[index + MT_CPR0_REGNUM]; |
| 192 | if (!*stub) |
| 193 | { |
| 194 | array_names[regnum] = stub; |
| 195 | return stub; |
| 196 | } |
| 197 | name = xmalloc (30); |
| 198 | sprintf (name, "copro_%d_%d_%s", dim_1, dim_2, stub); |
| 199 | array_names[regnum] = name; |
| 200 | return name; |
| 201 | } |
| 202 | } |
| 203 | |
| 204 | /* Return the type of a coprocessor register. */ |
| 205 | |
| 206 | static struct type * |
| 207 | mt_copro_register_type (struct gdbarch *arch, int regnum) |
| 208 | { |
| 209 | switch (regnum) |
| 210 | { |
| 211 | case MT_INT_ENABLE_REGNUM: |
| 212 | case MT_ICHANNEL_REGNUM: |
| 213 | case MT_QCHANNEL_REGNUM: |
| 214 | case MT_ISCRAMB_REGNUM: |
| 215 | case MT_QSCRAMB_REGNUM: |
| 216 | return builtin_type_int32; |
| 217 | case MT_BYPA_REGNUM: |
| 218 | case MT_BYPB_REGNUM: |
| 219 | case MT_BYPC_REGNUM: |
| 220 | case MT_Z1_REGNUM: |
| 221 | case MT_Z2_REGNUM: |
| 222 | case MT_OUT_REGNUM: |
| 223 | case MT_ZI2_REGNUM: |
| 224 | case MT_ZQ2_REGNUM: |
| 225 | return builtin_type_int16; |
| 226 | case MT_EXMAC_REGNUM: |
| 227 | case MT_MAC_REGNUM: |
| 228 | return builtin_type_uint32; |
| 229 | case MT_CONTEXT_REGNUM: |
| 230 | return builtin_type_long_long; |
| 231 | case MT_FLAG_REGNUM: |
| 232 | return builtin_type_unsigned_char; |
| 233 | default: |
| 234 | if (regnum >= MT_CPR0_REGNUM && regnum <= MT_CPR15_REGNUM) |
| 235 | return builtin_type_int16; |
| 236 | else if (regnum == MT_CPR0_REGNUM + MT_COPRO_PSEUDOREG_MAC_REGNUM) |
| 237 | { |
| 238 | if (gdbarch_bfd_arch_info (arch)->mach == bfd_mach_mrisc2 |
| 239 | || gdbarch_bfd_arch_info (arch)->mach == bfd_mach_ms2) |
| 240 | return builtin_type_uint64; |
| 241 | else |
| 242 | return builtin_type_uint32; |
| 243 | } |
| 244 | else |
| 245 | return builtin_type_uint32; |
| 246 | } |
| 247 | } |
| 248 | |
| 249 | /* Given ARCH and a register number specified by REGNUM, return the |
| 250 | type of that register. */ |
| 251 | |
| 252 | static struct type * |
| 253 | mt_register_type (struct gdbarch *arch, int regnum) |
| 254 | { |
| 255 | static struct type *void_func_ptr = NULL; |
| 256 | static struct type *void_ptr = NULL; |
| 257 | static struct type *copro_type; |
| 258 | |
| 259 | if (regnum >= 0 && regnum < MT_NUM_REGS + MT_NUM_PSEUDO_REGS) |
| 260 | { |
| 261 | if (void_func_ptr == NULL) |
| 262 | { |
| 263 | struct type *temp; |
| 264 | |
| 265 | void_ptr = lookup_pointer_type (builtin_type_void); |
| 266 | void_func_ptr = |
| 267 | lookup_pointer_type (lookup_function_type (builtin_type_void)); |
| 268 | temp = create_range_type (NULL, builtin_type_unsigned_int, 0, 1); |
| 269 | copro_type = create_array_type (NULL, builtin_type_int16, temp); |
| 270 | } |
| 271 | switch (regnum) |
| 272 | { |
| 273 | case MT_PC_REGNUM: |
| 274 | case MT_RA_REGNUM: |
| 275 | case MT_IRA_REGNUM: |
| 276 | return void_func_ptr; |
| 277 | case MT_SP_REGNUM: |
| 278 | case MT_FP_REGNUM: |
| 279 | return void_ptr; |
| 280 | case MT_COPRO_REGNUM: |
| 281 | case MT_COPRO_PSEUDOREG_REGNUM: |
| 282 | return copro_type; |
| 283 | case MT_MAC_PSEUDOREG_REGNUM: |
| 284 | return mt_copro_register_type (arch, |
| 285 | MT_CPR0_REGNUM |
| 286 | + MT_COPRO_PSEUDOREG_MAC_REGNUM); |
| 287 | default: |
| 288 | if (regnum >= MT_R0_REGNUM && regnum <= MT_R15_REGNUM) |
| 289 | return builtin_type_int32; |
| 290 | else if (regnum < MT_COPRO_PSEUDOREG_ARRAY) |
| 291 | return mt_copro_register_type (arch, regnum); |
| 292 | else |
| 293 | { |
| 294 | regnum -= MT_COPRO_PSEUDOREG_ARRAY; |
| 295 | regnum %= MT_COPRO_PSEUDOREG_REGS; |
| 296 | regnum += MT_CPR0_REGNUM; |
| 297 | return mt_copro_register_type (arch, regnum); |
| 298 | } |
| 299 | } |
| 300 | } |
| 301 | internal_error (__FILE__, __LINE__, |
| 302 | _("mt_register_type: illegal register number %d"), regnum); |
| 303 | } |
| 304 | |
| 305 | /* Return true if register REGNUM is a member of the register group |
| 306 | specified by GROUP. */ |
| 307 | |
| 308 | static int |
| 309 | mt_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
| 310 | struct reggroup *group) |
| 311 | { |
| 312 | /* Groups of registers that can be displayed via "info reg". */ |
| 313 | if (group == all_reggroup) |
| 314 | return (regnum >= 0 |
| 315 | && regnum < MT_NUM_REGS + MT_NUM_PSEUDO_REGS |
| 316 | && mt_register_name (regnum)[0] != '\0'); |
| 317 | |
| 318 | if (group == general_reggroup) |
| 319 | return (regnum >= MT_R0_REGNUM && regnum <= MT_R15_REGNUM); |
| 320 | |
| 321 | if (group == float_reggroup) |
| 322 | return 0; /* No float regs. */ |
| 323 | |
| 324 | if (group == vector_reggroup) |
| 325 | return 0; /* No vector regs. */ |
| 326 | |
| 327 | /* For any that are not handled above. */ |
| 328 | return default_register_reggroup_p (gdbarch, regnum, group); |
| 329 | } |
| 330 | |
| 331 | /* Return the return value convention used for a given type TYPE. |
| 332 | Optionally, fetch or set the return value via READBUF or |
| 333 | WRITEBUF respectively using REGCACHE for the register |
| 334 | values. */ |
| 335 | |
| 336 | static enum return_value_convention |
| 337 | mt_return_value (struct gdbarch *gdbarch, struct type *type, |
| 338 | struct regcache *regcache, gdb_byte *readbuf, |
| 339 | const gdb_byte *writebuf) |
| 340 | { |
| 341 | if (TYPE_LENGTH (type) > 4) |
| 342 | { |
| 343 | /* Return values > 4 bytes are returned in memory, |
| 344 | pointed to by R11. */ |
| 345 | if (readbuf) |
| 346 | { |
| 347 | ULONGEST addr; |
| 348 | |
| 349 | regcache_cooked_read_unsigned (regcache, MT_R11_REGNUM, &addr); |
| 350 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
| 351 | } |
| 352 | |
| 353 | if (writebuf) |
| 354 | { |
| 355 | ULONGEST addr; |
| 356 | |
| 357 | regcache_cooked_read_unsigned (regcache, MT_R11_REGNUM, &addr); |
| 358 | write_memory (addr, writebuf, TYPE_LENGTH (type)); |
| 359 | } |
| 360 | |
| 361 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; |
| 362 | } |
| 363 | else |
| 364 | { |
| 365 | if (readbuf) |
| 366 | { |
| 367 | ULONGEST temp; |
| 368 | |
| 369 | /* Return values of <= 4 bytes are returned in R11. */ |
| 370 | regcache_cooked_read_unsigned (regcache, MT_R11_REGNUM, &temp); |
| 371 | store_unsigned_integer (readbuf, TYPE_LENGTH (type), temp); |
| 372 | } |
| 373 | |
| 374 | if (writebuf) |
| 375 | { |
| 376 | if (TYPE_LENGTH (type) < 4) |
| 377 | { |
| 378 | gdb_byte buf[4]; |
| 379 | /* Add leading zeros to the value. */ |
| 380 | memset (buf, 0, sizeof (buf)); |
| 381 | memcpy (buf + sizeof (buf) - TYPE_LENGTH (type), |
| 382 | writebuf, TYPE_LENGTH (type)); |
| 383 | regcache_cooked_write (regcache, MT_R11_REGNUM, buf); |
| 384 | } |
| 385 | else /* (TYPE_LENGTH (type) == 4 */ |
| 386 | regcache_cooked_write (regcache, MT_R11_REGNUM, writebuf); |
| 387 | } |
| 388 | |
| 389 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 390 | } |
| 391 | } |
| 392 | |
| 393 | /* If the input address, PC, is in a function prologue, return the |
| 394 | address of the end of the prologue, otherwise return the input |
| 395 | address. |
| 396 | |
| 397 | Note: PC is likely to be the function start, since this function |
| 398 | is mainly used for advancing a breakpoint to the first line, or |
| 399 | stepping to the first line when we have stepped into a function |
| 400 | call. */ |
| 401 | |
| 402 | static CORE_ADDR |
| 403 | mt_skip_prologue (CORE_ADDR pc) |
| 404 | { |
| 405 | CORE_ADDR func_addr = 0, func_end = 0; |
| 406 | char *func_name; |
| 407 | unsigned long instr; |
| 408 | |
| 409 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
| 410 | { |
| 411 | struct symtab_and_line sal; |
| 412 | struct symbol *sym; |
| 413 | |
| 414 | /* Found a function. */ |
| 415 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL); |
| 416 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
| 417 | { |
| 418 | /* Don't use this trick for assembly source files. */ |
| 419 | sal = find_pc_line (func_addr, 0); |
| 420 | |
| 421 | if (sal.end && sal.end < func_end) |
| 422 | { |
| 423 | /* Found a line number, use it as end of prologue. */ |
| 424 | return sal.end; |
| 425 | } |
| 426 | } |
| 427 | } |
| 428 | |
| 429 | /* No function symbol, or no line symbol. Use prologue scanning method. */ |
| 430 | for (;; pc += 4) |
| 431 | { |
| 432 | instr = read_memory_unsigned_integer (pc, 4); |
| 433 | if (instr == 0x12000000) /* nop */ |
| 434 | continue; |
| 435 | if (instr == 0x12ddc000) /* copy sp into fp */ |
| 436 | continue; |
| 437 | instr >>= 16; |
| 438 | if (instr == 0x05dd) /* subi sp, sp, imm */ |
| 439 | continue; |
| 440 | if (instr >= 0x43c0 && instr <= 0x43df) /* push */ |
| 441 | continue; |
| 442 | /* Not an obvious prologue instruction. */ |
| 443 | break; |
| 444 | } |
| 445 | |
| 446 | return pc; |
| 447 | } |
| 448 | |
| 449 | /* The breakpoint instruction must be the same size as the smallest |
| 450 | instruction in the instruction set. |
| 451 | |
| 452 | The BP for ms1 is defined as 0x68000000 (BREAK). |
| 453 | The BP for ms2 is defined as 0x69000000 (illegal) */ |
| 454 | |
| 455 | static const gdb_byte * |
| 456 | mt_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) |
| 457 | { |
| 458 | static gdb_byte ms1_breakpoint[] = { 0x68, 0, 0, 0 }; |
| 459 | static gdb_byte ms2_breakpoint[] = { 0x69, 0, 0, 0 }; |
| 460 | |
| 461 | *bp_size = 4; |
| 462 | if (gdbarch_bfd_arch_info (current_gdbarch)->mach == bfd_mach_ms2) |
| 463 | return ms2_breakpoint; |
| 464 | |
| 465 | return ms1_breakpoint; |
| 466 | } |
| 467 | |
| 468 | /* Select the correct coprocessor register bank. Return the pseudo |
| 469 | regnum we really want to read. */ |
| 470 | |
| 471 | static int |
| 472 | mt_select_coprocessor (struct gdbarch *gdbarch, |
| 473 | struct regcache *regcache, int regno) |
| 474 | { |
| 475 | unsigned index, base; |
| 476 | gdb_byte copro[4]; |
| 477 | |
| 478 | /* Get the copro pseudo regnum. */ |
| 479 | regcache_raw_read (regcache, MT_COPRO_REGNUM, copro); |
| 480 | base = (extract_signed_integer (&copro[0], 2) * MT_COPRO_PSEUDOREG_DIM_2 |
| 481 | + extract_signed_integer (&copro[2], 2)); |
| 482 | |
| 483 | regno -= MT_COPRO_PSEUDOREG_ARRAY; |
| 484 | index = regno % MT_COPRO_PSEUDOREG_REGS; |
| 485 | regno /= MT_COPRO_PSEUDOREG_REGS; |
| 486 | if (base != regno) |
| 487 | { |
| 488 | /* Select the correct coprocessor register bank. Invalidate the |
| 489 | coprocessor register cache. */ |
| 490 | unsigned ix; |
| 491 | |
| 492 | store_signed_integer (&copro[0], 2, regno / MT_COPRO_PSEUDOREG_DIM_2); |
| 493 | store_signed_integer (&copro[2], 2, regno % MT_COPRO_PSEUDOREG_DIM_2); |
| 494 | regcache_raw_write (regcache, MT_COPRO_REGNUM, copro); |
| 495 | |
| 496 | /* We must flush the cache, as it is now invalid. */ |
| 497 | for (ix = MT_NUM_CPU_REGS; ix != MT_NUM_REGS; ix++) |
| 498 | regcache_invalidate (regcache, ix); |
| 499 | } |
| 500 | |
| 501 | return index; |
| 502 | } |
| 503 | |
| 504 | /* Fetch the pseudo registers: |
| 505 | |
| 506 | There are two regular pseudo-registers: |
| 507 | 1) The 'coprocessor' pseudo-register (which mirrors the |
| 508 | "real" coprocessor register sent by the target), and |
| 509 | 2) The 'MAC' pseudo-register (which represents the union |
| 510 | of the original 32 bit target MAC register and the new |
| 511 | 8-bit extended-MAC register). |
| 512 | |
| 513 | Additionally there is an array of coprocessor registers which track |
| 514 | the coprocessor registers for each coprocessor. */ |
| 515 | |
| 516 | static void |
| 517 | mt_pseudo_register_read (struct gdbarch *gdbarch, |
| 518 | struct regcache *regcache, int regno, gdb_byte *buf) |
| 519 | { |
| 520 | switch (regno) |
| 521 | { |
| 522 | case MT_COPRO_REGNUM: |
| 523 | case MT_COPRO_PSEUDOREG_REGNUM: |
| 524 | regcache_raw_read (regcache, MT_COPRO_REGNUM, buf); |
| 525 | break; |
| 526 | case MT_MAC_REGNUM: |
| 527 | case MT_MAC_PSEUDOREG_REGNUM: |
| 528 | if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2 |
| 529 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2) |
| 530 | { |
| 531 | ULONGEST oldmac = 0, ext_mac = 0; |
| 532 | ULONGEST newmac; |
| 533 | |
| 534 | regcache_cooked_read_unsigned (regcache, MT_MAC_REGNUM, &oldmac); |
| 535 | regcache_cooked_read_unsigned (regcache, MT_EXMAC_REGNUM, &ext_mac); |
| 536 | newmac = |
| 537 | (oldmac & 0xffffffff) | ((long long) (ext_mac & 0xff) << 32); |
| 538 | store_signed_integer (buf, 8, newmac); |
| 539 | } |
| 540 | else |
| 541 | regcache_raw_read (regcache, MT_MAC_REGNUM, buf); |
| 542 | break; |
| 543 | default: |
| 544 | { |
| 545 | unsigned index = mt_select_coprocessor (gdbarch, regcache, regno); |
| 546 | |
| 547 | if (index == MT_COPRO_PSEUDOREG_MAC_REGNUM) |
| 548 | mt_pseudo_register_read (gdbarch, regcache, |
| 549 | MT_MAC_PSEUDOREG_REGNUM, buf); |
| 550 | else if (index < MT_NUM_REGS - MT_CPR0_REGNUM) |
| 551 | regcache_raw_read (regcache, index + MT_CPR0_REGNUM, buf); |
| 552 | } |
| 553 | break; |
| 554 | } |
| 555 | } |
| 556 | |
| 557 | /* Write the pseudo registers: |
| 558 | |
| 559 | Mt pseudo-registers are stored directly to the target. The |
| 560 | 'coprocessor' register is special, because when it is modified, all |
| 561 | the other coprocessor regs must be flushed from the reg cache. */ |
| 562 | |
| 563 | static void |
| 564 | mt_pseudo_register_write (struct gdbarch *gdbarch, |
| 565 | struct regcache *regcache, |
| 566 | int regno, const gdb_byte *buf) |
| 567 | { |
| 568 | int i; |
| 569 | |
| 570 | switch (regno) |
| 571 | { |
| 572 | case MT_COPRO_REGNUM: |
| 573 | case MT_COPRO_PSEUDOREG_REGNUM: |
| 574 | regcache_raw_write (regcache, MT_COPRO_REGNUM, buf); |
| 575 | for (i = MT_NUM_CPU_REGS; i < MT_NUM_REGS; i++) |
| 576 | regcache_invalidate (regcache, i); |
| 577 | break; |
| 578 | case MT_MAC_REGNUM: |
| 579 | case MT_MAC_PSEUDOREG_REGNUM: |
| 580 | if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2 |
| 581 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2) |
| 582 | { |
| 583 | /* The 8-byte MAC pseudo-register must be broken down into two |
| 584 | 32-byte registers. */ |
| 585 | unsigned int oldmac, ext_mac; |
| 586 | ULONGEST newmac; |
| 587 | |
| 588 | newmac = extract_unsigned_integer (buf, 8); |
| 589 | oldmac = newmac & 0xffffffff; |
| 590 | ext_mac = (newmac >> 32) & 0xff; |
| 591 | regcache_cooked_write_unsigned (regcache, MT_MAC_REGNUM, oldmac); |
| 592 | regcache_cooked_write_unsigned (regcache, MT_EXMAC_REGNUM, ext_mac); |
| 593 | } |
| 594 | else |
| 595 | regcache_raw_write (regcache, MT_MAC_REGNUM, buf); |
| 596 | break; |
| 597 | default: |
| 598 | { |
| 599 | unsigned index = mt_select_coprocessor (gdbarch, regcache, regno); |
| 600 | |
| 601 | if (index == MT_COPRO_PSEUDOREG_MAC_REGNUM) |
| 602 | mt_pseudo_register_write (gdbarch, regcache, |
| 603 | MT_MAC_PSEUDOREG_REGNUM, buf); |
| 604 | else if (index < MT_NUM_REGS - MT_CPR0_REGNUM) |
| 605 | regcache_raw_write (regcache, index + MT_CPR0_REGNUM, buf); |
| 606 | } |
| 607 | break; |
| 608 | } |
| 609 | } |
| 610 | |
| 611 | static CORE_ADDR |
| 612 | mt_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
| 613 | { |
| 614 | /* Register size is 4 bytes. */ |
| 615 | return align_down (sp, 4); |
| 616 | } |
| 617 | |
| 618 | /* Implements the "info registers" command. When ``all'' is non-zero, |
| 619 | the coprocessor registers will be printed in addition to the rest |
| 620 | of the registers. */ |
| 621 | |
| 622 | static void |
| 623 | mt_registers_info (struct gdbarch *gdbarch, |
| 624 | struct ui_file *file, |
| 625 | struct frame_info *frame, int regnum, int all) |
| 626 | { |
| 627 | if (regnum == -1) |
| 628 | { |
| 629 | int lim; |
| 630 | |
| 631 | lim = all ? MT_NUM_REGS : MT_NUM_CPU_REGS; |
| 632 | |
| 633 | for (regnum = 0; regnum < lim; regnum++) |
| 634 | { |
| 635 | /* Don't display the Qchannel register since it will be displayed |
| 636 | along with Ichannel. (See below.) */ |
| 637 | if (regnum == MT_QCHANNEL_REGNUM) |
| 638 | continue; |
| 639 | |
| 640 | mt_registers_info (gdbarch, file, frame, regnum, all); |
| 641 | |
| 642 | /* Display the Qchannel register immediately after Ichannel. */ |
| 643 | if (regnum == MT_ICHANNEL_REGNUM) |
| 644 | mt_registers_info (gdbarch, file, frame, MT_QCHANNEL_REGNUM, all); |
| 645 | } |
| 646 | } |
| 647 | else |
| 648 | { |
| 649 | if (regnum == MT_EXMAC_REGNUM) |
| 650 | return; |
| 651 | else if (regnum == MT_CONTEXT_REGNUM) |
| 652 | { |
| 653 | /* Special output handling for 38-bit context register. */ |
| 654 | unsigned char *buff; |
| 655 | unsigned int *bytes, i, regsize; |
| 656 | |
| 657 | regsize = register_size (gdbarch, regnum); |
| 658 | |
| 659 | buff = alloca (regsize); |
| 660 | bytes = alloca (regsize * sizeof (*bytes)); |
| 661 | |
| 662 | frame_register_read (frame, regnum, buff); |
| 663 | |
| 664 | fputs_filtered (gdbarch_register_name |
| 665 | (current_gdbarch, regnum), file); |
| 666 | print_spaces_filtered (15 - strlen (gdbarch_register_name |
| 667 | (current_gdbarch, regnum)), |
| 668 | file); |
| 669 | fputs_filtered ("0x", file); |
| 670 | |
| 671 | for (i = 0; i < regsize; i++) |
| 672 | fprintf_filtered (file, "%02x", (unsigned int) |
| 673 | extract_unsigned_integer (buff + i, 1)); |
| 674 | fputs_filtered ("\t", file); |
| 675 | print_longest (file, 'd', 0, |
| 676 | extract_unsigned_integer (buff, regsize)); |
| 677 | fputs_filtered ("\n", file); |
| 678 | } |
| 679 | else if (regnum == MT_COPRO_REGNUM |
| 680 | || regnum == MT_COPRO_PSEUDOREG_REGNUM) |
| 681 | { |
| 682 | /* Special output handling for the 'coprocessor' register. */ |
| 683 | gdb_byte *buf; |
| 684 | |
| 685 | buf = alloca (register_size (gdbarch, MT_COPRO_REGNUM)); |
| 686 | frame_register_read (frame, MT_COPRO_REGNUM, buf); |
| 687 | /* And print. */ |
| 688 | regnum = MT_COPRO_PSEUDOREG_REGNUM; |
| 689 | fputs_filtered (gdbarch_register_name (current_gdbarch, regnum), |
| 690 | file); |
| 691 | print_spaces_filtered (15 - strlen (gdbarch_register_name |
| 692 | (current_gdbarch, regnum)), |
| 693 | file); |
| 694 | val_print (register_type (gdbarch, regnum), buf, |
| 695 | 0, 0, file, 0, 1, 0, Val_no_prettyprint); |
| 696 | fputs_filtered ("\n", file); |
| 697 | } |
| 698 | else if (regnum == MT_MAC_REGNUM || regnum == MT_MAC_PSEUDOREG_REGNUM) |
| 699 | { |
| 700 | ULONGEST oldmac, ext_mac, newmac; |
| 701 | gdb_byte buf[3 * sizeof (LONGEST)]; |
| 702 | |
| 703 | /* Get the two "real" mac registers. */ |
| 704 | frame_register_read (frame, MT_MAC_REGNUM, buf); |
| 705 | oldmac = extract_unsigned_integer |
| 706 | (buf, register_size (gdbarch, MT_MAC_REGNUM)); |
| 707 | if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2 |
| 708 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2) |
| 709 | { |
| 710 | frame_register_read (frame, MT_EXMAC_REGNUM, buf); |
| 711 | ext_mac = extract_unsigned_integer |
| 712 | (buf, register_size (gdbarch, MT_EXMAC_REGNUM)); |
| 713 | } |
| 714 | else |
| 715 | ext_mac = 0; |
| 716 | |
| 717 | /* Add them together. */ |
| 718 | newmac = (oldmac & 0xffffffff) + ((ext_mac & 0xff) << 32); |
| 719 | |
| 720 | /* And print. */ |
| 721 | regnum = MT_MAC_PSEUDOREG_REGNUM; |
| 722 | fputs_filtered (gdbarch_register_name (current_gdbarch, regnum), |
| 723 | file); |
| 724 | print_spaces_filtered (15 - strlen (gdbarch_register_name |
| 725 | (current_gdbarch, regnum)), |
| 726 | file); |
| 727 | fputs_filtered ("0x", file); |
| 728 | print_longest (file, 'x', 0, newmac); |
| 729 | fputs_filtered ("\t", file); |
| 730 | print_longest (file, 'u', 0, newmac); |
| 731 | fputs_filtered ("\n", file); |
| 732 | } |
| 733 | else |
| 734 | default_print_registers_info (gdbarch, file, frame, regnum, all); |
| 735 | } |
| 736 | } |
| 737 | |
| 738 | /* Set up the callee's arguments for an inferior function call. The |
| 739 | arguments are pushed on the stack or are placed in registers as |
| 740 | appropriate. It also sets up the return address (which points to |
| 741 | the call dummy breakpoint). |
| 742 | |
| 743 | Returns the updated (and aligned) stack pointer. */ |
| 744 | |
| 745 | static CORE_ADDR |
| 746 | mt_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 747 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 748 | int nargs, struct value **args, CORE_ADDR sp, |
| 749 | int struct_return, CORE_ADDR struct_addr) |
| 750 | { |
| 751 | #define wordsize 4 |
| 752 | gdb_byte buf[MT_MAX_STRUCT_SIZE]; |
| 753 | int argreg = MT_1ST_ARGREG; |
| 754 | int split_param_len = 0; |
| 755 | int stack_dest = sp; |
| 756 | int slacklen; |
| 757 | int typelen; |
| 758 | int i, j; |
| 759 | |
| 760 | /* First handle however many args we can fit into MT_1ST_ARGREG thru |
| 761 | MT_LAST_ARGREG. */ |
| 762 | for (i = 0; i < nargs && argreg <= MT_LAST_ARGREG; i++) |
| 763 | { |
| 764 | const gdb_byte *val; |
| 765 | typelen = TYPE_LENGTH (value_type (args[i])); |
| 766 | switch (typelen) |
| 767 | { |
| 768 | case 1: |
| 769 | case 2: |
| 770 | case 3: |
| 771 | case 4: |
| 772 | regcache_cooked_write_unsigned (regcache, argreg++, |
| 773 | extract_unsigned_integer |
| 774 | (value_contents (args[i]), |
| 775 | wordsize)); |
| 776 | break; |
| 777 | case 8: |
| 778 | case 12: |
| 779 | case 16: |
| 780 | val = value_contents (args[i]); |
| 781 | while (typelen > 0) |
| 782 | { |
| 783 | if (argreg <= MT_LAST_ARGREG) |
| 784 | { |
| 785 | /* This word of the argument is passed in a register. */ |
| 786 | regcache_cooked_write_unsigned (regcache, argreg++, |
| 787 | extract_unsigned_integer |
| 788 | (val, wordsize)); |
| 789 | typelen -= wordsize; |
| 790 | val += wordsize; |
| 791 | } |
| 792 | else |
| 793 | { |
| 794 | /* Remainder of this arg must be passed on the stack |
| 795 | (deferred to do later). */ |
| 796 | split_param_len = typelen; |
| 797 | memcpy (buf, val, typelen); |
| 798 | break; /* No more args can be handled in regs. */ |
| 799 | } |
| 800 | } |
| 801 | break; |
| 802 | default: |
| 803 | /* By reverse engineering of gcc output, args bigger than |
| 804 | 16 bytes go on the stack, and their address is passed |
| 805 | in the argreg. */ |
| 806 | stack_dest -= typelen; |
| 807 | write_memory (stack_dest, value_contents (args[i]), typelen); |
| 808 | regcache_cooked_write_unsigned (regcache, argreg++, stack_dest); |
| 809 | break; |
| 810 | } |
| 811 | } |
| 812 | |
| 813 | /* Next, the rest of the arguments go onto the stack, in reverse order. */ |
| 814 | for (j = nargs - 1; j >= i; j--) |
| 815 | { |
| 816 | gdb_byte *val; |
| 817 | |
| 818 | /* Right-justify the value in an aligned-length buffer. */ |
| 819 | typelen = TYPE_LENGTH (value_type (args[j])); |
| 820 | slacklen = (wordsize - (typelen % wordsize)) % wordsize; |
| 821 | val = alloca (typelen + slacklen); |
| 822 | memcpy (val, value_contents (args[j]), typelen); |
| 823 | memset (val + typelen, 0, slacklen); |
| 824 | /* Now write this data to the stack. */ |
| 825 | stack_dest -= typelen + slacklen; |
| 826 | write_memory (stack_dest, val, typelen + slacklen); |
| 827 | } |
| 828 | |
| 829 | /* Finally, if a param needs to be split between registers and stack, |
| 830 | write the second half to the stack now. */ |
| 831 | if (split_param_len != 0) |
| 832 | { |
| 833 | stack_dest -= split_param_len; |
| 834 | write_memory (stack_dest, buf, split_param_len); |
| 835 | } |
| 836 | |
| 837 | /* Set up return address (provided to us as bp_addr). */ |
| 838 | regcache_cooked_write_unsigned (regcache, MT_RA_REGNUM, bp_addr); |
| 839 | |
| 840 | /* Store struct return address, if given. */ |
| 841 | if (struct_return && struct_addr != 0) |
| 842 | regcache_cooked_write_unsigned (regcache, MT_R11_REGNUM, struct_addr); |
| 843 | |
| 844 | /* Set aside 16 bytes for the callee to save regs 1-4. */ |
| 845 | stack_dest -= 16; |
| 846 | |
| 847 | /* Update the stack pointer. */ |
| 848 | regcache_cooked_write_unsigned (regcache, MT_SP_REGNUM, stack_dest); |
| 849 | |
| 850 | /* And that should do it. Return the new stack pointer. */ |
| 851 | return stack_dest; |
| 852 | } |
| 853 | |
| 854 | |
| 855 | /* The 'unwind_cache' data structure. */ |
| 856 | |
| 857 | struct mt_unwind_cache |
| 858 | { |
| 859 | /* The previous frame's inner most stack address. |
| 860 | Used as this frame ID's stack_addr. */ |
| 861 | CORE_ADDR prev_sp; |
| 862 | CORE_ADDR frame_base; |
| 863 | int framesize; |
| 864 | int frameless_p; |
| 865 | |
| 866 | /* Table indicating the location of each and every register. */ |
| 867 | struct trad_frame_saved_reg *saved_regs; |
| 868 | }; |
| 869 | |
| 870 | /* Initialize an unwind_cache. Build up the saved_regs table etc. for |
| 871 | the frame. */ |
| 872 | |
| 873 | static struct mt_unwind_cache * |
| 874 | mt_frame_unwind_cache (struct frame_info *next_frame, |
| 875 | void **this_prologue_cache) |
| 876 | { |
| 877 | struct gdbarch *gdbarch; |
| 878 | struct mt_unwind_cache *info; |
| 879 | CORE_ADDR next_addr, start_addr, end_addr, prologue_end_addr; |
| 880 | unsigned long instr, upper_half, delayed_store = 0; |
| 881 | int regnum, offset; |
| 882 | ULONGEST sp, fp; |
| 883 | |
| 884 | if ((*this_prologue_cache)) |
| 885 | return (*this_prologue_cache); |
| 886 | |
| 887 | gdbarch = get_frame_arch (next_frame); |
| 888 | info = FRAME_OBSTACK_ZALLOC (struct mt_unwind_cache); |
| 889 | (*this_prologue_cache) = info; |
| 890 | |
| 891 | info->prev_sp = 0; |
| 892 | info->framesize = 0; |
| 893 | info->frame_base = 0; |
| 894 | info->frameless_p = 1; |
| 895 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
| 896 | |
| 897 | /* Grab the frame-relative values of SP and FP, needed below. |
| 898 | The frame_saved_register function will find them on the |
| 899 | stack or in the registers as appropriate. */ |
| 900 | frame_unwind_unsigned_register (next_frame, MT_SP_REGNUM, &sp); |
| 901 | frame_unwind_unsigned_register (next_frame, MT_FP_REGNUM, &fp); |
| 902 | |
| 903 | start_addr = frame_func_unwind (next_frame, NORMAL_FRAME); |
| 904 | |
| 905 | /* Return early if GDB couldn't find the function. */ |
| 906 | if (start_addr == 0) |
| 907 | return info; |
| 908 | |
| 909 | end_addr = frame_pc_unwind (next_frame); |
| 910 | prologue_end_addr = skip_prologue_using_sal (start_addr); |
| 911 | if (end_addr == 0) |
| 912 | for (next_addr = start_addr; next_addr < end_addr; next_addr += 4) |
| 913 | { |
| 914 | instr = get_frame_memory_unsigned (next_frame, next_addr, 4); |
| 915 | if (delayed_store) /* previous instr was a push */ |
| 916 | { |
| 917 | upper_half = delayed_store >> 16; |
| 918 | regnum = upper_half & 0xf; |
| 919 | offset = delayed_store & 0xffff; |
| 920 | switch (upper_half & 0xfff0) |
| 921 | { |
| 922 | case 0x43c0: /* push using frame pointer */ |
| 923 | info->saved_regs[regnum].addr = offset; |
| 924 | break; |
| 925 | case 0x43d0: /* push using stack pointer */ |
| 926 | info->saved_regs[regnum].addr = offset; |
| 927 | break; |
| 928 | default: /* lint */ |
| 929 | break; |
| 930 | } |
| 931 | delayed_store = 0; |
| 932 | } |
| 933 | |
| 934 | switch (instr) |
| 935 | { |
| 936 | case 0x12000000: /* NO-OP */ |
| 937 | continue; |
| 938 | case 0x12ddc000: /* copy sp into fp */ |
| 939 | info->frameless_p = 0; /* Record that the frame pointer is in use. */ |
| 940 | continue; |
| 941 | default: |
| 942 | upper_half = instr >> 16; |
| 943 | if (upper_half == 0x05dd || /* subi sp, sp, imm */ |
| 944 | upper_half == 0x07dd) /* subui sp, sp, imm */ |
| 945 | { |
| 946 | /* Record the frame size. */ |
| 947 | info->framesize = instr & 0xffff; |
| 948 | continue; |
| 949 | } |
| 950 | if ((upper_half & 0xfff0) == 0x43c0 || /* frame push */ |
| 951 | (upper_half & 0xfff0) == 0x43d0) /* stack push */ |
| 952 | { |
| 953 | /* Save this instruction, but don't record the |
| 954 | pushed register as 'saved' until we see the |
| 955 | next instruction. That's because of deferred stores |
| 956 | on this target -- GDB won't be able to read the register |
| 957 | from the stack until one instruction later. */ |
| 958 | delayed_store = instr; |
| 959 | continue; |
| 960 | } |
| 961 | /* Not a prologue instruction. Is this the end of the prologue? |
| 962 | This is the most difficult decision; when to stop scanning. |
| 963 | |
| 964 | If we have no line symbol, then the best thing we can do |
| 965 | is to stop scanning when we encounter an instruction that |
| 966 | is not likely to be a part of the prologue. |
| 967 | |
| 968 | But if we do have a line symbol, then we should |
| 969 | keep scanning until we reach it (or we reach end_addr). */ |
| 970 | |
| 971 | if (prologue_end_addr && (prologue_end_addr > (next_addr + 4))) |
| 972 | continue; /* Keep scanning, recording saved_regs etc. */ |
| 973 | else |
| 974 | break; /* Quit scanning: breakpoint can be set here. */ |
| 975 | } |
| 976 | } |
| 977 | |
| 978 | /* Special handling for the "saved" address of the SP: |
| 979 | The SP is of course never saved on the stack at all, so |
| 980 | by convention what we put here is simply the previous |
| 981 | _value_ of the SP (as opposed to an address where the |
| 982 | previous value would have been pushed). This will also |
| 983 | give us the frame base address. */ |
| 984 | |
| 985 | if (info->frameless_p) |
| 986 | { |
| 987 | info->frame_base = sp + info->framesize; |
| 988 | info->prev_sp = sp + info->framesize; |
| 989 | } |
| 990 | else |
| 991 | { |
| 992 | info->frame_base = fp + info->framesize; |
| 993 | info->prev_sp = fp + info->framesize; |
| 994 | } |
| 995 | /* Save prev_sp in saved_regs as a value, not as an address. */ |
| 996 | trad_frame_set_value (info->saved_regs, MT_SP_REGNUM, info->prev_sp); |
| 997 | |
| 998 | /* Now convert frame offsets to actual addresses (not offsets). */ |
| 999 | for (regnum = 0; regnum < MT_NUM_REGS; regnum++) |
| 1000 | if (trad_frame_addr_p (info->saved_regs, regnum)) |
| 1001 | info->saved_regs[regnum].addr += info->frame_base - info->framesize; |
| 1002 | |
| 1003 | /* The call instruction moves the caller's PC in the callee's RA reg. |
| 1004 | Since this is an unwind, do the reverse. Copy the location of RA |
| 1005 | into PC (the address / regnum) so that a request for PC will be |
| 1006 | converted into a request for the RA. */ |
| 1007 | info->saved_regs[MT_PC_REGNUM] = info->saved_regs[MT_RA_REGNUM]; |
| 1008 | |
| 1009 | return info; |
| 1010 | } |
| 1011 | |
| 1012 | static CORE_ADDR |
| 1013 | mt_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1014 | { |
| 1015 | ULONGEST pc; |
| 1016 | |
| 1017 | frame_unwind_unsigned_register (next_frame, MT_PC_REGNUM, &pc); |
| 1018 | return pc; |
| 1019 | } |
| 1020 | |
| 1021 | static CORE_ADDR |
| 1022 | mt_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1023 | { |
| 1024 | ULONGEST sp; |
| 1025 | |
| 1026 | frame_unwind_unsigned_register (next_frame, MT_SP_REGNUM, &sp); |
| 1027 | return sp; |
| 1028 | } |
| 1029 | |
| 1030 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
| 1031 | dummy frame. The frame ID's base needs to match the TOS value |
| 1032 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's |
| 1033 | breakpoint. */ |
| 1034 | |
| 1035 | static struct frame_id |
| 1036 | mt_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1037 | { |
| 1038 | return frame_id_build (mt_unwind_sp (gdbarch, next_frame), |
| 1039 | frame_pc_unwind (next_frame)); |
| 1040 | } |
| 1041 | |
| 1042 | /* Given a GDB frame, determine the address of the calling function's |
| 1043 | frame. This will be used to create a new GDB frame struct. */ |
| 1044 | |
| 1045 | static void |
| 1046 | mt_frame_this_id (struct frame_info *next_frame, |
| 1047 | void **this_prologue_cache, struct frame_id *this_id) |
| 1048 | { |
| 1049 | struct mt_unwind_cache *info = |
| 1050 | mt_frame_unwind_cache (next_frame, this_prologue_cache); |
| 1051 | |
| 1052 | if (!(info == NULL || info->prev_sp == 0)) |
| 1053 | (*this_id) = frame_id_build (info->prev_sp, |
| 1054 | frame_func_unwind (next_frame, NORMAL_FRAME)); |
| 1055 | |
| 1056 | return; |
| 1057 | } |
| 1058 | |
| 1059 | static void |
| 1060 | mt_frame_prev_register (struct frame_info *next_frame, |
| 1061 | void **this_prologue_cache, |
| 1062 | int regnum, int *optimizedp, |
| 1063 | enum lval_type *lvalp, CORE_ADDR *addrp, |
| 1064 | int *realnump, gdb_byte *bufferp) |
| 1065 | { |
| 1066 | struct mt_unwind_cache *info = |
| 1067 | mt_frame_unwind_cache (next_frame, this_prologue_cache); |
| 1068 | |
| 1069 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
| 1070 | optimizedp, lvalp, addrp, realnump, bufferp); |
| 1071 | } |
| 1072 | |
| 1073 | static CORE_ADDR |
| 1074 | mt_frame_base_address (struct frame_info *next_frame, |
| 1075 | void **this_prologue_cache) |
| 1076 | { |
| 1077 | struct mt_unwind_cache *info = |
| 1078 | mt_frame_unwind_cache (next_frame, this_prologue_cache); |
| 1079 | |
| 1080 | return info->frame_base; |
| 1081 | } |
| 1082 | |
| 1083 | /* This is a shared interface: the 'frame_unwind' object is what's |
| 1084 | returned by the 'sniffer' function, and in turn specifies how to |
| 1085 | get a frame's ID and prev_regs. |
| 1086 | |
| 1087 | This exports the 'prev_register' and 'this_id' methods. */ |
| 1088 | |
| 1089 | static const struct frame_unwind mt_frame_unwind = { |
| 1090 | NORMAL_FRAME, |
| 1091 | mt_frame_this_id, |
| 1092 | mt_frame_prev_register |
| 1093 | }; |
| 1094 | |
| 1095 | /* The sniffer is a registered function that identifies our family of |
| 1096 | frame unwind functions (this_id and prev_register). */ |
| 1097 | |
| 1098 | static const struct frame_unwind * |
| 1099 | mt_frame_sniffer (struct frame_info *next_frame) |
| 1100 | { |
| 1101 | return &mt_frame_unwind; |
| 1102 | } |
| 1103 | |
| 1104 | /* Another shared interface: the 'frame_base' object specifies how to |
| 1105 | unwind a frame and secure the base addresses for frame objects |
| 1106 | (locals, args). */ |
| 1107 | |
| 1108 | static struct frame_base mt_frame_base = { |
| 1109 | &mt_frame_unwind, |
| 1110 | mt_frame_base_address, |
| 1111 | mt_frame_base_address, |
| 1112 | mt_frame_base_address |
| 1113 | }; |
| 1114 | |
| 1115 | static struct gdbarch * |
| 1116 | mt_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 1117 | { |
| 1118 | struct gdbarch *gdbarch; |
| 1119 | |
| 1120 | /* Find a candidate among the list of pre-declared architectures. */ |
| 1121 | arches = gdbarch_list_lookup_by_info (arches, &info); |
| 1122 | if (arches != NULL) |
| 1123 | return arches->gdbarch; |
| 1124 | |
| 1125 | /* None found, create a new architecture from the information |
| 1126 | provided. */ |
| 1127 | gdbarch = gdbarch_alloc (&info, NULL); |
| 1128 | |
| 1129 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
| 1130 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); |
| 1131 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); |
| 1132 | |
| 1133 | set_gdbarch_register_name (gdbarch, mt_register_name); |
| 1134 | set_gdbarch_num_regs (gdbarch, MT_NUM_REGS); |
| 1135 | set_gdbarch_num_pseudo_regs (gdbarch, MT_NUM_PSEUDO_REGS); |
| 1136 | set_gdbarch_pc_regnum (gdbarch, MT_PC_REGNUM); |
| 1137 | set_gdbarch_sp_regnum (gdbarch, MT_SP_REGNUM); |
| 1138 | set_gdbarch_pseudo_register_read (gdbarch, mt_pseudo_register_read); |
| 1139 | set_gdbarch_pseudo_register_write (gdbarch, mt_pseudo_register_write); |
| 1140 | set_gdbarch_skip_prologue (gdbarch, mt_skip_prologue); |
| 1141 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 1142 | set_gdbarch_breakpoint_from_pc (gdbarch, mt_breakpoint_from_pc); |
| 1143 | set_gdbarch_decr_pc_after_break (gdbarch, 0); |
| 1144 | set_gdbarch_frame_args_skip (gdbarch, 0); |
| 1145 | set_gdbarch_print_insn (gdbarch, print_insn_mt); |
| 1146 | set_gdbarch_register_type (gdbarch, mt_register_type); |
| 1147 | set_gdbarch_register_reggroup_p (gdbarch, mt_register_reggroup_p); |
| 1148 | |
| 1149 | set_gdbarch_return_value (gdbarch, mt_return_value); |
| 1150 | set_gdbarch_sp_regnum (gdbarch, MT_SP_REGNUM); |
| 1151 | |
| 1152 | set_gdbarch_frame_align (gdbarch, mt_frame_align); |
| 1153 | |
| 1154 | set_gdbarch_print_registers_info (gdbarch, mt_registers_info); |
| 1155 | |
| 1156 | set_gdbarch_push_dummy_call (gdbarch, mt_push_dummy_call); |
| 1157 | |
| 1158 | /* Target builtin data types. */ |
| 1159 | set_gdbarch_short_bit (gdbarch, 16); |
| 1160 | set_gdbarch_int_bit (gdbarch, 32); |
| 1161 | set_gdbarch_long_bit (gdbarch, 32); |
| 1162 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 1163 | set_gdbarch_float_bit (gdbarch, 32); |
| 1164 | set_gdbarch_double_bit (gdbarch, 64); |
| 1165 | set_gdbarch_long_double_bit (gdbarch, 64); |
| 1166 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 1167 | |
| 1168 | /* Register the DWARF 2 sniffer first, and then the traditional prologue |
| 1169 | based sniffer. */ |
| 1170 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
| 1171 | frame_unwind_append_sniffer (gdbarch, mt_frame_sniffer); |
| 1172 | frame_base_set_default (gdbarch, &mt_frame_base); |
| 1173 | |
| 1174 | /* Register the 'unwind_pc' method. */ |
| 1175 | set_gdbarch_unwind_pc (gdbarch, mt_unwind_pc); |
| 1176 | set_gdbarch_unwind_sp (gdbarch, mt_unwind_sp); |
| 1177 | |
| 1178 | /* Methods for saving / extracting a dummy frame's ID. |
| 1179 | The ID's stack address must match the SP value returned by |
| 1180 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ |
| 1181 | set_gdbarch_unwind_dummy_id (gdbarch, mt_unwind_dummy_id); |
| 1182 | |
| 1183 | return gdbarch; |
| 1184 | } |
| 1185 | |
| 1186 | void |
| 1187 | _initialize_mt_tdep (void) |
| 1188 | { |
| 1189 | register_gdbarch_init (bfd_arch_mt, mt_gdbarch_init); |
| 1190 | } |