| 1 | /* Target-machine dependent code for Nios II, for GDB. |
| 2 | Copyright (C) 2012-2015 Free Software Foundation, Inc. |
| 3 | Contributed by Peter Brookes (pbrookes@altera.com) |
| 4 | and Andrew Draper (adraper@altera.com). |
| 5 | Contributed by Mentor Graphics, Inc. |
| 6 | |
| 7 | This file is part of GDB. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3 of the License, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 21 | |
| 22 | #include "defs.h" |
| 23 | #include "frame.h" |
| 24 | #include "frame-unwind.h" |
| 25 | #include "frame-base.h" |
| 26 | #include "trad-frame.h" |
| 27 | #include "dwarf2-frame.h" |
| 28 | #include "symtab.h" |
| 29 | #include "inferior.h" |
| 30 | #include "gdbtypes.h" |
| 31 | #include "gdbcore.h" |
| 32 | #include "gdbcmd.h" |
| 33 | #include "osabi.h" |
| 34 | #include "target.h" |
| 35 | #include "dis-asm.h" |
| 36 | #include "regcache.h" |
| 37 | #include "value.h" |
| 38 | #include "symfile.h" |
| 39 | #include "arch-utils.h" |
| 40 | #include "floatformat.h" |
| 41 | #include "infcall.h" |
| 42 | #include "regset.h" |
| 43 | #include "target-descriptions.h" |
| 44 | |
| 45 | /* To get entry_point_address. */ |
| 46 | #include "objfiles.h" |
| 47 | |
| 48 | /* Nios II ISA specific encodings and macros. */ |
| 49 | #include "opcode/nios2.h" |
| 50 | |
| 51 | /* Nios II specific header. */ |
| 52 | #include "nios2-tdep.h" |
| 53 | |
| 54 | #include "features/nios2.c" |
| 55 | |
| 56 | /* Control debugging information emitted in this file. */ |
| 57 | |
| 58 | static int nios2_debug = 0; |
| 59 | |
| 60 | /* The following structures are used in the cache for prologue |
| 61 | analysis; see the reg_value and reg_saved tables in |
| 62 | struct nios2_unwind_cache, respectively. */ |
| 63 | |
| 64 | /* struct reg_value is used to record that a register has the same value |
| 65 | as reg at the given offset from the start of a function. */ |
| 66 | |
| 67 | struct reg_value |
| 68 | { |
| 69 | int reg; |
| 70 | unsigned int offset; |
| 71 | }; |
| 72 | |
| 73 | /* struct reg_saved is used to record that a register value has been saved at |
| 74 | basereg + addr, for basereg >= 0. If basereg < 0, that indicates |
| 75 | that the register is not known to have been saved. Note that when |
| 76 | basereg == NIOS2_Z_REGNUM (that is, r0, which holds value 0), |
| 77 | addr is an absolute address. */ |
| 78 | |
| 79 | struct reg_saved |
| 80 | { |
| 81 | int basereg; |
| 82 | CORE_ADDR addr; |
| 83 | }; |
| 84 | |
| 85 | struct nios2_unwind_cache |
| 86 | { |
| 87 | /* The frame's base, optionally used by the high-level debug info. */ |
| 88 | CORE_ADDR base; |
| 89 | |
| 90 | /* The previous frame's inner most stack address. Used as this |
| 91 | frame ID's stack_addr. */ |
| 92 | CORE_ADDR cfa; |
| 93 | |
| 94 | /* The address of the first instruction in this function. */ |
| 95 | CORE_ADDR pc; |
| 96 | |
| 97 | /* Which register holds the return address for the frame. */ |
| 98 | int return_regnum; |
| 99 | |
| 100 | /* Table indicating what changes have been made to each register. */ |
| 101 | struct reg_value reg_value[NIOS2_NUM_REGS]; |
| 102 | |
| 103 | /* Table indicating where each register has been saved. */ |
| 104 | struct reg_saved reg_saved[NIOS2_NUM_REGS]; |
| 105 | }; |
| 106 | |
| 107 | |
| 108 | /* This array is a mapping from Dwarf-2 register numbering to GDB's. */ |
| 109 | |
| 110 | static int nios2_dwarf2gdb_regno_map[] = |
| 111 | { |
| 112 | 0, 1, 2, 3, |
| 113 | 4, 5, 6, 7, |
| 114 | 8, 9, 10, 11, |
| 115 | 12, 13, 14, 15, |
| 116 | 16, 17, 18, 19, |
| 117 | 20, 21, 22, 23, |
| 118 | 24, 25, |
| 119 | NIOS2_GP_REGNUM, /* 26 */ |
| 120 | NIOS2_SP_REGNUM, /* 27 */ |
| 121 | NIOS2_FP_REGNUM, /* 28 */ |
| 122 | NIOS2_EA_REGNUM, /* 29 */ |
| 123 | NIOS2_BA_REGNUM, /* 30 */ |
| 124 | NIOS2_RA_REGNUM, /* 31 */ |
| 125 | NIOS2_PC_REGNUM, /* 32 */ |
| 126 | NIOS2_STATUS_REGNUM, /* 33 */ |
| 127 | NIOS2_ESTATUS_REGNUM, /* 34 */ |
| 128 | NIOS2_BSTATUS_REGNUM, /* 35 */ |
| 129 | NIOS2_IENABLE_REGNUM, /* 36 */ |
| 130 | NIOS2_IPENDING_REGNUM, /* 37 */ |
| 131 | NIOS2_CPUID_REGNUM, /* 38 */ |
| 132 | 39, /* CTL6 */ /* 39 */ |
| 133 | NIOS2_EXCEPTION_REGNUM, /* 40 */ |
| 134 | NIOS2_PTEADDR_REGNUM, /* 41 */ |
| 135 | NIOS2_TLBACC_REGNUM, /* 42 */ |
| 136 | NIOS2_TLBMISC_REGNUM, /* 43 */ |
| 137 | NIOS2_ECCINJ_REGNUM, /* 44 */ |
| 138 | NIOS2_BADADDR_REGNUM, /* 45 */ |
| 139 | NIOS2_CONFIG_REGNUM, /* 46 */ |
| 140 | NIOS2_MPUBASE_REGNUM, /* 47 */ |
| 141 | NIOS2_MPUACC_REGNUM /* 48 */ |
| 142 | }; |
| 143 | |
| 144 | |
| 145 | /* Implement the dwarf2_reg_to_regnum gdbarch method. */ |
| 146 | |
| 147 | static int |
| 148 | nios2_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int dw_reg) |
| 149 | { |
| 150 | if (dw_reg < 0 || dw_reg > NIOS2_NUM_REGS) |
| 151 | { |
| 152 | warning (_("Dwarf-2 uses unmapped register #%d"), dw_reg); |
| 153 | return dw_reg; |
| 154 | } |
| 155 | |
| 156 | return nios2_dwarf2gdb_regno_map[dw_reg]; |
| 157 | } |
| 158 | |
| 159 | /* Canonical names for the 49 registers. */ |
| 160 | |
| 161 | static const char *const nios2_reg_names[NIOS2_NUM_REGS] = |
| 162 | { |
| 163 | "zero", "at", "r2", "r3", "r4", "r5", "r6", "r7", |
| 164 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 165 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
| 166 | "et", "bt", "gp", "sp", "fp", "ea", "sstatus", "ra", |
| 167 | "pc", |
| 168 | "status", "estatus", "bstatus", "ienable", |
| 169 | "ipending", "cpuid", "ctl6", "exception", |
| 170 | "pteaddr", "tlbacc", "tlbmisc", "eccinj", |
| 171 | "badaddr", "config", "mpubase", "mpuacc" |
| 172 | }; |
| 173 | |
| 174 | /* Implement the register_name gdbarch method. */ |
| 175 | |
| 176 | static const char * |
| 177 | nios2_register_name (struct gdbarch *gdbarch, int regno) |
| 178 | { |
| 179 | /* Use mnemonic aliases for GPRs. */ |
| 180 | if (regno >= 0 && regno < NIOS2_NUM_REGS) |
| 181 | return nios2_reg_names[regno]; |
| 182 | else |
| 183 | return tdesc_register_name (gdbarch, regno); |
| 184 | } |
| 185 | |
| 186 | /* Implement the register_type gdbarch method. */ |
| 187 | |
| 188 | static struct type * |
| 189 | nios2_register_type (struct gdbarch *gdbarch, int regno) |
| 190 | { |
| 191 | /* If the XML description has register information, use that to |
| 192 | determine the register type. */ |
| 193 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
| 194 | return tdesc_register_type (gdbarch, regno); |
| 195 | |
| 196 | if (regno == NIOS2_PC_REGNUM) |
| 197 | return builtin_type (gdbarch)->builtin_func_ptr; |
| 198 | else if (regno == NIOS2_SP_REGNUM) |
| 199 | return builtin_type (gdbarch)->builtin_data_ptr; |
| 200 | else |
| 201 | return builtin_type (gdbarch)->builtin_uint32; |
| 202 | } |
| 203 | |
| 204 | /* Given a return value in REGCACHE with a type VALTYPE, |
| 205 | extract and copy its value into VALBUF. */ |
| 206 | |
| 207 | static void |
| 208 | nios2_extract_return_value (struct gdbarch *gdbarch, struct type *valtype, |
| 209 | struct regcache *regcache, gdb_byte *valbuf) |
| 210 | { |
| 211 | int len = TYPE_LENGTH (valtype); |
| 212 | |
| 213 | /* Return values of up to 8 bytes are returned in $r2 $r3. */ |
| 214 | if (len <= register_size (gdbarch, NIOS2_R2_REGNUM)) |
| 215 | regcache_cooked_read (regcache, NIOS2_R2_REGNUM, valbuf); |
| 216 | else |
| 217 | { |
| 218 | gdb_assert (len <= (register_size (gdbarch, NIOS2_R2_REGNUM) |
| 219 | + register_size (gdbarch, NIOS2_R3_REGNUM))); |
| 220 | regcache_cooked_read (regcache, NIOS2_R2_REGNUM, valbuf); |
| 221 | regcache_cooked_read (regcache, NIOS2_R3_REGNUM, valbuf + 4); |
| 222 | } |
| 223 | } |
| 224 | |
| 225 | /* Write into appropriate registers a function return value |
| 226 | of type TYPE, given in virtual format. */ |
| 227 | |
| 228 | static void |
| 229 | nios2_store_return_value (struct gdbarch *gdbarch, struct type *valtype, |
| 230 | struct regcache *regcache, const gdb_byte *valbuf) |
| 231 | { |
| 232 | int len = TYPE_LENGTH (valtype); |
| 233 | |
| 234 | /* Return values of up to 8 bytes are returned in $r2 $r3. */ |
| 235 | if (len <= register_size (gdbarch, NIOS2_R2_REGNUM)) |
| 236 | regcache_cooked_write (regcache, NIOS2_R2_REGNUM, valbuf); |
| 237 | else |
| 238 | { |
| 239 | gdb_assert (len <= (register_size (gdbarch, NIOS2_R2_REGNUM) |
| 240 | + register_size (gdbarch, NIOS2_R3_REGNUM))); |
| 241 | regcache_cooked_write (regcache, NIOS2_R2_REGNUM, valbuf); |
| 242 | regcache_cooked_write (regcache, NIOS2_R3_REGNUM, valbuf + 4); |
| 243 | } |
| 244 | } |
| 245 | |
| 246 | |
| 247 | /* Set up the default values of the registers. */ |
| 248 | |
| 249 | static void |
| 250 | nios2_setup_default (struct nios2_unwind_cache *cache) |
| 251 | { |
| 252 | int i; |
| 253 | |
| 254 | for (i = 0; i < NIOS2_NUM_REGS; i++) |
| 255 | { |
| 256 | /* All registers start off holding their previous values. */ |
| 257 | cache->reg_value[i].reg = i; |
| 258 | cache->reg_value[i].offset = 0; |
| 259 | |
| 260 | /* All registers start off not saved. */ |
| 261 | cache->reg_saved[i].basereg = -1; |
| 262 | cache->reg_saved[i].addr = 0; |
| 263 | } |
| 264 | } |
| 265 | |
| 266 | /* Initialize the unwind cache. */ |
| 267 | |
| 268 | static void |
| 269 | nios2_init_cache (struct nios2_unwind_cache *cache, CORE_ADDR pc) |
| 270 | { |
| 271 | cache->base = 0; |
| 272 | cache->cfa = 0; |
| 273 | cache->pc = pc; |
| 274 | cache->return_regnum = NIOS2_RA_REGNUM; |
| 275 | nios2_setup_default (cache); |
| 276 | } |
| 277 | |
| 278 | /* Read and identify an instruction at PC. If INSNP is non-null, |
| 279 | store the instruction word into that location. Return the opcode |
| 280 | pointer or NULL if the memory couldn't be read or disassembled. */ |
| 281 | |
| 282 | static const struct nios2_opcode * |
| 283 | nios2_fetch_insn (struct gdbarch *gdbarch, CORE_ADDR pc, |
| 284 | unsigned int *insnp) |
| 285 | { |
| 286 | LONGEST memword; |
| 287 | unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; |
| 288 | unsigned int insn; |
| 289 | |
| 290 | if (!safe_read_memory_integer (pc, NIOS2_OPCODE_SIZE, |
| 291 | gdbarch_byte_order (gdbarch), &memword)) |
| 292 | return NULL; |
| 293 | |
| 294 | insn = (unsigned int) memword; |
| 295 | if (insnp) |
| 296 | *insnp = insn; |
| 297 | return nios2_find_opcode_hash (insn, mach); |
| 298 | } |
| 299 | |
| 300 | |
| 301 | /* Match and disassemble an ADD-type instruction, with 3 register operands. |
| 302 | Returns true on success, and fills in the operand pointers. */ |
| 303 | |
| 304 | static int |
| 305 | nios2_match_add (uint32_t insn, const struct nios2_opcode *op, |
| 306 | unsigned long mach, int *ra, int *rb, int *rc) |
| 307 | { |
| 308 | if (op->match == MATCH_R1_ADD || op->match == MATCH_R1_MOV) |
| 309 | { |
| 310 | *ra = GET_IW_R_A (insn); |
| 311 | *rb = GET_IW_R_B (insn); |
| 312 | *rc = GET_IW_R_C (insn); |
| 313 | return 1; |
| 314 | } |
| 315 | return 0; |
| 316 | } |
| 317 | |
| 318 | /* Match and disassemble a SUB-type instruction, with 3 register operands. |
| 319 | Returns true on success, and fills in the operand pointers. */ |
| 320 | |
| 321 | static int |
| 322 | nios2_match_sub (uint32_t insn, const struct nios2_opcode *op, |
| 323 | unsigned long mach, int *ra, int *rb, int *rc) |
| 324 | { |
| 325 | if (op->match == MATCH_R1_SUB) |
| 326 | { |
| 327 | *ra = GET_IW_R_A (insn); |
| 328 | *rb = GET_IW_R_B (insn); |
| 329 | *rc = GET_IW_R_C (insn); |
| 330 | return 1; |
| 331 | } |
| 332 | return 0; |
| 333 | } |
| 334 | |
| 335 | /* Match and disassemble an ADDI-type instruction, with 2 register operands |
| 336 | and one immediate operand. |
| 337 | Returns true on success, and fills in the operand pointers. */ |
| 338 | |
| 339 | static int |
| 340 | nios2_match_addi (uint32_t insn, const struct nios2_opcode *op, |
| 341 | unsigned long mach, int *ra, int *rb, int *imm) |
| 342 | { |
| 343 | if (op->match == MATCH_R1_ADDI) |
| 344 | { |
| 345 | *ra = GET_IW_I_A (insn); |
| 346 | *rb = GET_IW_I_B (insn); |
| 347 | *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16; |
| 348 | return 1; |
| 349 | } |
| 350 | return 0; |
| 351 | } |
| 352 | |
| 353 | /* Match and disassemble an ORHI-type instruction, with 2 register operands |
| 354 | and one unsigned immediate operand. |
| 355 | Returns true on success, and fills in the operand pointers. */ |
| 356 | |
| 357 | static int |
| 358 | nios2_match_orhi (uint32_t insn, const struct nios2_opcode *op, |
| 359 | unsigned long mach, int *ra, int *rb, unsigned int *uimm) |
| 360 | { |
| 361 | if (op->match == MATCH_R1_ORHI) |
| 362 | { |
| 363 | *ra = GET_IW_I_A (insn); |
| 364 | *rb = GET_IW_I_B (insn); |
| 365 | *uimm = GET_IW_I_IMM16 (insn); |
| 366 | return 1; |
| 367 | } |
| 368 | return 0; |
| 369 | } |
| 370 | |
| 371 | /* Match and disassemble a STW-type instruction, with 2 register operands |
| 372 | and one immediate operand. |
| 373 | Returns true on success, and fills in the operand pointers. */ |
| 374 | |
| 375 | static int |
| 376 | nios2_match_stw (uint32_t insn, const struct nios2_opcode *op, |
| 377 | unsigned long mach, int *ra, int *rb, int *imm) |
| 378 | { |
| 379 | if (op->match == MATCH_R1_STW || op->match == MATCH_R1_STWIO) |
| 380 | { |
| 381 | *ra = GET_IW_I_A (insn); |
| 382 | *rb = GET_IW_I_B (insn); |
| 383 | *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16; |
| 384 | return 1; |
| 385 | } |
| 386 | return 0; |
| 387 | } |
| 388 | |
| 389 | /* Match and disassemble a LDW-type instruction, with 2 register operands |
| 390 | and one immediate operand. |
| 391 | Returns true on success, and fills in the operand pointers. */ |
| 392 | |
| 393 | static int |
| 394 | nios2_match_ldw (uint32_t insn, const struct nios2_opcode *op, |
| 395 | unsigned long mach, int *ra, int *rb, int *imm) |
| 396 | { |
| 397 | if (op->match == MATCH_R1_LDW || op->match == MATCH_R1_LDWIO) |
| 398 | { |
| 399 | *ra = GET_IW_I_A (insn); |
| 400 | *rb = GET_IW_I_B (insn); |
| 401 | *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16; |
| 402 | return 1; |
| 403 | } |
| 404 | return 0; |
| 405 | } |
| 406 | |
| 407 | /* Match and disassemble a RDCTL instruction, with 2 register operands. |
| 408 | Returns true on success, and fills in the operand pointers. */ |
| 409 | |
| 410 | static int |
| 411 | nios2_match_rdctl (uint32_t insn, const struct nios2_opcode *op, |
| 412 | unsigned long mach, int *ra, int *rc) |
| 413 | { |
| 414 | if (op->match == MATCH_R1_RDCTL) |
| 415 | { |
| 416 | *ra = GET_IW_R_IMM5 (insn); |
| 417 | *rc = GET_IW_R_C (insn); |
| 418 | return 1; |
| 419 | } |
| 420 | return 0; |
| 421 | } |
| 422 | |
| 423 | |
| 424 | /* Match and disassemble a branch instruction, with (potentially) |
| 425 | 2 register operands and one immediate operand. |
| 426 | Returns true on success, and fills in the operand pointers. */ |
| 427 | |
| 428 | enum branch_condition { |
| 429 | branch_none, |
| 430 | branch_eq, |
| 431 | branch_ne, |
| 432 | branch_ge, |
| 433 | branch_geu, |
| 434 | branch_lt, |
| 435 | branch_ltu |
| 436 | }; |
| 437 | |
| 438 | static int |
| 439 | nios2_match_branch (uint32_t insn, const struct nios2_opcode *op, |
| 440 | unsigned long mach, int *ra, int *rb, int *imm, |
| 441 | enum branch_condition *cond) |
| 442 | { |
| 443 | switch (op->match) |
| 444 | { |
| 445 | case MATCH_R1_BR: |
| 446 | *cond = branch_none; |
| 447 | break; |
| 448 | case MATCH_R1_BEQ: |
| 449 | *cond = branch_eq; |
| 450 | break; |
| 451 | case MATCH_R1_BNE: |
| 452 | *cond = branch_ne; |
| 453 | break; |
| 454 | case MATCH_R1_BGE: |
| 455 | *cond = branch_ge; |
| 456 | break; |
| 457 | case MATCH_R1_BGEU: |
| 458 | *cond = branch_geu; |
| 459 | break; |
| 460 | case MATCH_R1_BLT: |
| 461 | *cond = branch_lt; |
| 462 | break; |
| 463 | case MATCH_R1_BLTU: |
| 464 | *cond = branch_ltu; |
| 465 | break; |
| 466 | default: |
| 467 | return 0; |
| 468 | } |
| 469 | *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16; |
| 470 | *ra = GET_IW_I_A (insn); |
| 471 | *rb = GET_IW_I_B (insn); |
| 472 | return 1; |
| 473 | } |
| 474 | |
| 475 | /* Match and disassemble a direct jump instruction, with an |
| 476 | unsigned operand. Returns true on success, and fills in the operand |
| 477 | pointer. */ |
| 478 | |
| 479 | static int |
| 480 | nios2_match_jmpi (uint32_t insn, const struct nios2_opcode *op, |
| 481 | unsigned long mach, unsigned int *uimm) |
| 482 | { |
| 483 | if (op->match == MATCH_R1_JMPI) |
| 484 | { |
| 485 | *uimm = GET_IW_J_IMM26 (insn) << 2; |
| 486 | return 1; |
| 487 | } |
| 488 | return 0; |
| 489 | } |
| 490 | |
| 491 | /* Match and disassemble a direct call instruction, with an |
| 492 | unsigned operand. Returns true on success, and fills in the operand |
| 493 | pointer. */ |
| 494 | |
| 495 | static int |
| 496 | nios2_match_calli (uint32_t insn, const struct nios2_opcode *op, |
| 497 | unsigned long mach, unsigned int *uimm) |
| 498 | { |
| 499 | if (op->match == MATCH_R1_CALL) |
| 500 | { |
| 501 | *uimm = GET_IW_J_IMM26 (insn) << 2; |
| 502 | return 1; |
| 503 | } |
| 504 | return 0; |
| 505 | } |
| 506 | |
| 507 | /* Match and disassemble an indirect jump instruction, with a |
| 508 | (possibly implicit) register operand. Returns true on success, and fills |
| 509 | in the operand pointer. */ |
| 510 | |
| 511 | static int |
| 512 | nios2_match_jmpr (uint32_t insn, const struct nios2_opcode *op, |
| 513 | unsigned long mach, int *ra) |
| 514 | { |
| 515 | switch (op->match) |
| 516 | { |
| 517 | case MATCH_R1_JMP: |
| 518 | *ra = GET_IW_I_A (insn); |
| 519 | return 1; |
| 520 | case MATCH_R1_RET: |
| 521 | *ra = NIOS2_RA_REGNUM; |
| 522 | return 1; |
| 523 | case MATCH_R1_ERET: |
| 524 | *ra = NIOS2_EA_REGNUM; |
| 525 | return 1; |
| 526 | case MATCH_R1_BRET: |
| 527 | *ra = NIOS2_BA_REGNUM; |
| 528 | return 1; |
| 529 | default: |
| 530 | return 0; |
| 531 | } |
| 532 | } |
| 533 | |
| 534 | /* Match and disassemble an indirect call instruction, with a register |
| 535 | operand. Returns true on success, and fills in the operand pointer. */ |
| 536 | |
| 537 | static int |
| 538 | nios2_match_callr (uint32_t insn, const struct nios2_opcode *op, |
| 539 | unsigned long mach, int *ra) |
| 540 | { |
| 541 | if (op->match == MATCH_R1_CALLR) |
| 542 | { |
| 543 | *ra = GET_IW_I_A (insn); |
| 544 | return 1; |
| 545 | } |
| 546 | return 0; |
| 547 | } |
| 548 | |
| 549 | /* Match and disassemble a break instruction, with an unsigned operand. |
| 550 | Returns true on success, and fills in the operand pointer. */ |
| 551 | |
| 552 | static int |
| 553 | nios2_match_break (uint32_t insn, const struct nios2_opcode *op, |
| 554 | unsigned long mach, unsigned int *uimm) |
| 555 | { |
| 556 | if (op->match == MATCH_R1_BREAK) |
| 557 | { |
| 558 | *uimm = GET_IW_R_IMM5 (insn); |
| 559 | return 1; |
| 560 | } |
| 561 | return 0; |
| 562 | } |
| 563 | |
| 564 | /* Match and disassemble a trap instruction, with an unsigned operand. |
| 565 | Returns true on success, and fills in the operand pointer. */ |
| 566 | |
| 567 | static int |
| 568 | nios2_match_trap (uint32_t insn, const struct nios2_opcode *op, |
| 569 | unsigned long mach, unsigned int *uimm) |
| 570 | { |
| 571 | if (op->match == MATCH_R1_TRAP) |
| 572 | { |
| 573 | *uimm = GET_IW_R_IMM5 (insn); |
| 574 | return 1; |
| 575 | } |
| 576 | return 0; |
| 577 | } |
| 578 | |
| 579 | /* Helper function to identify when we're in a function epilogue; |
| 580 | that is, the part of the function from the point at which the |
| 581 | stack adjustments are made, to the return or sibcall. |
| 582 | Note that we may have several stack adjustment instructions, and |
| 583 | this function needs to test whether the stack teardown has already |
| 584 | started before current_pc, not whether it has completed. */ |
| 585 | |
| 586 | static int |
| 587 | nios2_in_epilogue_p (struct gdbarch *gdbarch, |
| 588 | CORE_ADDR current_pc, |
| 589 | CORE_ADDR start_pc) |
| 590 | { |
| 591 | unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; |
| 592 | /* Maximum number of possibly-epilogue instructions to check. |
| 593 | Note that this number should not be too large, else we can |
| 594 | potentially end up iterating through unmapped memory. */ |
| 595 | int ninsns, max_insns = 5; |
| 596 | unsigned int insn; |
| 597 | const struct nios2_opcode *op = NULL; |
| 598 | unsigned int uimm; |
| 599 | int imm; |
| 600 | int ra, rb, rc; |
| 601 | enum branch_condition cond; |
| 602 | CORE_ADDR pc; |
| 603 | |
| 604 | /* There has to be a previous instruction in the function. */ |
| 605 | if (current_pc <= start_pc) |
| 606 | return 0; |
| 607 | |
| 608 | /* Find the previous instruction before current_pc. |
| 609 | For the moment we will assume that all instructions are the |
| 610 | same size here. */ |
| 611 | pc = current_pc - NIOS2_OPCODE_SIZE; |
| 612 | |
| 613 | /* Beginning with the previous instruction we just located, check whether |
| 614 | we are in a sequence of at least one stack adjustment instruction. |
| 615 | Possible instructions here include: |
| 616 | ADDI sp, sp, n |
| 617 | ADD sp, sp, rn |
| 618 | LDW sp, n(sp) */ |
| 619 | for (ninsns = 0; ninsns < max_insns; ninsns++) |
| 620 | { |
| 621 | int ok = 0; |
| 622 | |
| 623 | /* Fetch the insn at pc. */ |
| 624 | op = nios2_fetch_insn (gdbarch, pc, &insn); |
| 625 | if (op == NULL) |
| 626 | return 0; |
| 627 | pc += op->size; |
| 628 | |
| 629 | /* Was it a stack adjustment? */ |
| 630 | if (nios2_match_addi (insn, op, mach, &ra, &rb, &imm)) |
| 631 | ok = (rb == NIOS2_SP_REGNUM); |
| 632 | else if (nios2_match_add (insn, op, mach, &ra, &rb, &rc)) |
| 633 | ok = (rc == NIOS2_SP_REGNUM); |
| 634 | else if (nios2_match_ldw (insn, op, mach, &ra, &rb, &imm)) |
| 635 | ok = (rb == NIOS2_SP_REGNUM); |
| 636 | if (!ok) |
| 637 | break; |
| 638 | } |
| 639 | |
| 640 | /* No stack adjustments found. */ |
| 641 | if (ninsns == 0) |
| 642 | return 0; |
| 643 | |
| 644 | /* We found more stack adjustments than we expect GCC to be generating. |
| 645 | Since it looks like a stack unwind might be in progress tell GDB to |
| 646 | treat it as such. */ |
| 647 | if (ninsns == max_insns) |
| 648 | return 1; |
| 649 | |
| 650 | /* The next instruction following the stack adjustments must be a |
| 651 | return, jump, or unconditional branch. */ |
| 652 | if (nios2_match_jmpr (insn, op, mach, &ra) |
| 653 | || nios2_match_jmpi (insn, op, mach, &uimm) |
| 654 | || (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond) |
| 655 | && cond == branch_none)) |
| 656 | return 1; |
| 657 | |
| 658 | return 0; |
| 659 | } |
| 660 | |
| 661 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
| 662 | |
| 663 | static int |
| 664 | nios2_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 665 | { |
| 666 | CORE_ADDR func_addr; |
| 667 | |
| 668 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
| 669 | return nios2_in_epilogue_p (gdbarch, pc, func_addr); |
| 670 | |
| 671 | return 0; |
| 672 | } |
| 673 | |
| 674 | /* Do prologue analysis, returning the PC of the first instruction |
| 675 | after the function prologue. Assumes CACHE has already been |
| 676 | initialized. THIS_FRAME can be null, in which case we are only |
| 677 | interested in skipping the prologue. Otherwise CACHE is filled in |
| 678 | from the frame information. |
| 679 | |
| 680 | The prologue may consist of the following parts: |
| 681 | 1) Profiling instrumentation. For non-PIC code it looks like: |
| 682 | mov r8, ra |
| 683 | call mcount |
| 684 | mov ra, r8 |
| 685 | |
| 686 | 2) A stack adjustment and save of R4-R7 for varargs functions. |
| 687 | This is typically merged with item 3. |
| 688 | |
| 689 | 3) A stack adjustment and save of the callee-saved registers; |
| 690 | typically an explicit SP decrement and individual register |
| 691 | saves. |
| 692 | |
| 693 | There may also be a stack switch here in an exception handler |
| 694 | in place of a stack adjustment. It looks like: |
| 695 | movhi rx, %hiadj(newstack) |
| 696 | addhi rx, rx, %lo(newstack) |
| 697 | stw sp, constant(rx) |
| 698 | mov sp, rx |
| 699 | |
| 700 | 5) A frame pointer save, which can be either a MOV or ADDI. |
| 701 | |
| 702 | 6) A further stack pointer adjustment. This is normally included |
| 703 | adjustment in step 4 unless the total adjustment is too large |
| 704 | to be done in one step. |
| 705 | |
| 706 | 7) A stack overflow check, which can take either of these forms: |
| 707 | bgeu sp, rx, +8 |
| 708 | break 3 |
| 709 | or |
| 710 | bltu sp, rx, .Lstack_overflow |
| 711 | ... |
| 712 | .Lstack_overflow: |
| 713 | break 3 |
| 714 | If present, this is inserted after the stack pointer adjustments |
| 715 | for steps 3, 4, and 6. |
| 716 | |
| 717 | The prologue instructions may be combined or interleaved with other |
| 718 | instructions. |
| 719 | |
| 720 | To cope with all this variability we decode all the instructions |
| 721 | from the start of the prologue until we hit an instruction that |
| 722 | cannot possibly be a prologue instruction, such as a branch, call, |
| 723 | return, or epilogue instruction. The prologue is considered to end |
| 724 | at the last instruction that can definitely be considered a |
| 725 | prologue instruction. */ |
| 726 | |
| 727 | static CORE_ADDR |
| 728 | nios2_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR start_pc, |
| 729 | const CORE_ADDR current_pc, |
| 730 | struct nios2_unwind_cache *cache, |
| 731 | struct frame_info *this_frame) |
| 732 | { |
| 733 | /* Maximum number of possibly-prologue instructions to check. |
| 734 | Note that this number should not be too large, else we can |
| 735 | potentially end up iterating through unmapped memory. */ |
| 736 | int ninsns, max_insns = 50; |
| 737 | int regno; |
| 738 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 739 | unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; |
| 740 | |
| 741 | /* Does the frame set up the FP register? */ |
| 742 | int base_reg = 0; |
| 743 | |
| 744 | struct reg_value *value = cache->reg_value; |
| 745 | struct reg_value temp_value[NIOS2_NUM_REGS]; |
| 746 | |
| 747 | int i; |
| 748 | |
| 749 | /* Save the starting PC so we can correct the pc after running |
| 750 | through the prolog, using symbol info. */ |
| 751 | CORE_ADDR pc = start_pc; |
| 752 | |
| 753 | /* Is this an exception handler? */ |
| 754 | int exception_handler = 0; |
| 755 | |
| 756 | /* What was the original value of SP (or fake original value for |
| 757 | functions which switch stacks? */ |
| 758 | CORE_ADDR frame_high; |
| 759 | |
| 760 | /* The last definitely-prologue instruction seen. */ |
| 761 | CORE_ADDR prologue_end; |
| 762 | |
| 763 | /* Is this the innermost function? */ |
| 764 | int innermost = (this_frame ? (frame_relative_level (this_frame) == 0) : 1); |
| 765 | |
| 766 | if (nios2_debug) |
| 767 | fprintf_unfiltered (gdb_stdlog, |
| 768 | "{ nios2_analyze_prologue start=%s, current=%s ", |
| 769 | paddress (gdbarch, start_pc), |
| 770 | paddress (gdbarch, current_pc)); |
| 771 | |
| 772 | /* Set up the default values of the registers. */ |
| 773 | nios2_setup_default (cache); |
| 774 | |
| 775 | /* Find the prologue instructions. */ |
| 776 | prologue_end = start_pc; |
| 777 | for (ninsns = 0; ninsns < max_insns; ninsns++) |
| 778 | { |
| 779 | /* Present instruction. */ |
| 780 | uint32_t insn; |
| 781 | const struct nios2_opcode *op; |
| 782 | int ra, rb, rc, imm; |
| 783 | unsigned int uimm; |
| 784 | unsigned int reglist; |
| 785 | int wb, ret; |
| 786 | enum branch_condition cond; |
| 787 | |
| 788 | if (pc == current_pc) |
| 789 | { |
| 790 | /* When we reach the current PC we must save the current |
| 791 | register state (for the backtrace) but keep analysing |
| 792 | because there might be more to find out (eg. is this an |
| 793 | exception handler). */ |
| 794 | memcpy (temp_value, value, sizeof (temp_value)); |
| 795 | value = temp_value; |
| 796 | if (nios2_debug) |
| 797 | fprintf_unfiltered (gdb_stdlog, "*"); |
| 798 | } |
| 799 | |
| 800 | op = nios2_fetch_insn (gdbarch, pc, &insn); |
| 801 | |
| 802 | /* Unknown opcode? Stop scanning. */ |
| 803 | if (op == NULL) |
| 804 | break; |
| 805 | pc += op->size; |
| 806 | |
| 807 | if (nios2_debug) |
| 808 | fprintf_unfiltered (gdb_stdlog, "[%08X]", insn); |
| 809 | |
| 810 | /* The following instructions can appear in the prologue. */ |
| 811 | |
| 812 | if (nios2_match_add (insn, op, mach, &ra, &rb, &rc)) |
| 813 | { |
| 814 | /* ADD rc, ra, rb (also used for MOV) */ |
| 815 | if (rc == NIOS2_SP_REGNUM |
| 816 | && rb == 0 |
| 817 | && value[ra].reg == cache->reg_saved[NIOS2_SP_REGNUM].basereg) |
| 818 | { |
| 819 | /* If the previous value of SP is available somewhere |
| 820 | near the new stack pointer value then this is a |
| 821 | stack switch. */ |
| 822 | |
| 823 | /* If any registers were saved on the stack before then |
| 824 | we can't backtrace into them now. */ |
| 825 | for (i = 0 ; i < NIOS2_NUM_REGS ; i++) |
| 826 | { |
| 827 | if (cache->reg_saved[i].basereg == NIOS2_SP_REGNUM) |
| 828 | cache->reg_saved[i].basereg = -1; |
| 829 | if (value[i].reg == NIOS2_SP_REGNUM) |
| 830 | value[i].reg = -1; |
| 831 | } |
| 832 | |
| 833 | /* Create a fake "high water mark" 4 bytes above where SP |
| 834 | was stored and fake up the registers to be consistent |
| 835 | with that. */ |
| 836 | value[NIOS2_SP_REGNUM].reg = NIOS2_SP_REGNUM; |
| 837 | value[NIOS2_SP_REGNUM].offset |
| 838 | = (value[ra].offset |
| 839 | - cache->reg_saved[NIOS2_SP_REGNUM].addr |
| 840 | - 4); |
| 841 | cache->reg_saved[NIOS2_SP_REGNUM].basereg = NIOS2_SP_REGNUM; |
| 842 | cache->reg_saved[NIOS2_SP_REGNUM].addr = -4; |
| 843 | } |
| 844 | |
| 845 | else if (rc == NIOS2_SP_REGNUM && ra == NIOS2_FP_REGNUM) |
| 846 | /* This is setting SP from FP. This only happens in the |
| 847 | function epilogue. */ |
| 848 | break; |
| 849 | |
| 850 | else if (rc != 0) |
| 851 | { |
| 852 | if (value[rb].reg == 0) |
| 853 | value[rc].reg = value[ra].reg; |
| 854 | else if (value[ra].reg == 0) |
| 855 | value[rc].reg = value[rb].reg; |
| 856 | else |
| 857 | value[rc].reg = -1; |
| 858 | value[rc].offset = value[ra].offset + value[rb].offset; |
| 859 | } |
| 860 | |
| 861 | /* The add/move is only considered a prologue instruction |
| 862 | if the destination is SP or FP. */ |
| 863 | if (rc == NIOS2_SP_REGNUM || rc == NIOS2_FP_REGNUM) |
| 864 | prologue_end = pc; |
| 865 | } |
| 866 | |
| 867 | else if (nios2_match_sub (insn, op, mach, &ra, &rb, &rc)) |
| 868 | { |
| 869 | /* SUB rc, ra, rb */ |
| 870 | if (rc == NIOS2_SP_REGNUM && rb == NIOS2_SP_REGNUM |
| 871 | && value[rc].reg != 0) |
| 872 | /* If we are decrementing the SP by a non-constant amount, |
| 873 | this is alloca, not part of the prologue. */ |
| 874 | break; |
| 875 | else if (rc != 0) |
| 876 | { |
| 877 | if (value[rb].reg == 0) |
| 878 | value[rc].reg = value[ra].reg; |
| 879 | else |
| 880 | value[rc].reg = -1; |
| 881 | value[rc].offset = value[ra].offset - value[rb].offset; |
| 882 | } |
| 883 | } |
| 884 | |
| 885 | else if (nios2_match_addi (insn, op, mach, &ra, &rb, &imm)) |
| 886 | { |
| 887 | /* ADDI rb, ra, imm */ |
| 888 | |
| 889 | /* A positive stack adjustment has to be part of the epilogue. */ |
| 890 | if (rb == NIOS2_SP_REGNUM |
| 891 | && (imm > 0 || value[ra].reg != NIOS2_SP_REGNUM)) |
| 892 | break; |
| 893 | |
| 894 | /* Likewise restoring SP from FP. */ |
| 895 | else if (rb == NIOS2_SP_REGNUM && ra == NIOS2_FP_REGNUM) |
| 896 | break; |
| 897 | |
| 898 | if (rb != 0) |
| 899 | { |
| 900 | value[rb].reg = value[ra].reg; |
| 901 | value[rb].offset = value[ra].offset + imm; |
| 902 | } |
| 903 | |
| 904 | /* The add is only considered a prologue instruction |
| 905 | if the destination is SP or FP. */ |
| 906 | if (rb == NIOS2_SP_REGNUM || rb == NIOS2_FP_REGNUM) |
| 907 | prologue_end = pc; |
| 908 | } |
| 909 | |
| 910 | else if (nios2_match_orhi (insn, op, mach, &ra, &rb, &uimm)) |
| 911 | { |
| 912 | /* ORHI rb, ra, uimm (also used for MOVHI) */ |
| 913 | if (rb != 0) |
| 914 | { |
| 915 | value[rb].reg = (value[ra].reg == 0) ? 0 : -1; |
| 916 | value[rb].offset = value[ra].offset | (uimm << 16); |
| 917 | } |
| 918 | } |
| 919 | |
| 920 | else if (nios2_match_stw (insn, op, mach, &ra, &rb, &imm)) |
| 921 | { |
| 922 | /* STW rb, imm(ra) */ |
| 923 | |
| 924 | /* Are we storing the original value of a register to the stack? |
| 925 | For exception handlers the value of EA-4 (return |
| 926 | address from interrupts etc) is sometimes stored. */ |
| 927 | int orig = value[rb].reg; |
| 928 | if (orig > 0 |
| 929 | && (value[rb].offset == 0 |
| 930 | || (orig == NIOS2_EA_REGNUM && value[rb].offset == -4)) |
| 931 | && ((value[ra].reg == NIOS2_SP_REGNUM |
| 932 | && cache->reg_saved[orig].basereg != NIOS2_SP_REGNUM) |
| 933 | || cache->reg_saved[orig].basereg == -1)) |
| 934 | { |
| 935 | if (pc < current_pc) |
| 936 | { |
| 937 | /* Save off callee saved registers. */ |
| 938 | cache->reg_saved[orig].basereg = value[ra].reg; |
| 939 | cache->reg_saved[orig].addr = value[ra].offset + imm; |
| 940 | } |
| 941 | |
| 942 | prologue_end = pc; |
| 943 | |
| 944 | if (orig == NIOS2_EA_REGNUM || orig == NIOS2_ESTATUS_REGNUM) |
| 945 | exception_handler = 1; |
| 946 | } |
| 947 | else |
| 948 | /* Non-stack memory writes cannot appear in the prologue. */ |
| 949 | break; |
| 950 | } |
| 951 | |
| 952 | else if (nios2_match_rdctl (insn, op, mach, &ra, &rc)) |
| 953 | { |
| 954 | /* RDCTL rC, ctlN |
| 955 | This can appear in exception handlers in combination with |
| 956 | a subsequent save to the stack frame. */ |
| 957 | if (rc != 0) |
| 958 | { |
| 959 | value[rc].reg = NIOS2_STATUS_REGNUM + ra; |
| 960 | value[rc].offset = 0; |
| 961 | } |
| 962 | } |
| 963 | |
| 964 | else if (nios2_match_calli (insn, op, mach, &uimm)) |
| 965 | { |
| 966 | if (value[8].reg == NIOS2_RA_REGNUM |
| 967 | && value[8].offset == 0 |
| 968 | && value[NIOS2_SP_REGNUM].reg == NIOS2_SP_REGNUM |
| 969 | && value[NIOS2_SP_REGNUM].offset == 0) |
| 970 | { |
| 971 | /* A CALL instruction. This is treated as a call to mcount |
| 972 | if ra has been stored into r8 beforehand and if it's |
| 973 | before the stack adjust. |
| 974 | Note mcount corrupts r2-r3, r9-r15 & ra. */ |
| 975 | for (i = 2 ; i <= 3 ; i++) |
| 976 | value[i].reg = -1; |
| 977 | for (i = 9 ; i <= 15 ; i++) |
| 978 | value[i].reg = -1; |
| 979 | value[NIOS2_RA_REGNUM].reg = -1; |
| 980 | |
| 981 | prologue_end = pc; |
| 982 | } |
| 983 | |
| 984 | /* Other calls are not part of the prologue. */ |
| 985 | else |
| 986 | break; |
| 987 | } |
| 988 | |
| 989 | else if (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond)) |
| 990 | { |
| 991 | /* Branches not involving a stack overflow check aren't part of |
| 992 | the prologue. */ |
| 993 | if (ra != NIOS2_SP_REGNUM) |
| 994 | break; |
| 995 | else if (cond == branch_geu) |
| 996 | { |
| 997 | /* BGEU sp, rx, +8 |
| 998 | BREAK 3 |
| 999 | This instruction sequence is used in stack checking; |
| 1000 | we can ignore it. */ |
| 1001 | unsigned int next_insn; |
| 1002 | const struct nios2_opcode *next_op |
| 1003 | = nios2_fetch_insn (gdbarch, pc, &next_insn); |
| 1004 | if (next_op != NULL |
| 1005 | && nios2_match_break (next_insn, op, mach, &uimm)) |
| 1006 | pc += next_op->size; |
| 1007 | else |
| 1008 | break; |
| 1009 | } |
| 1010 | else if (cond == branch_ltu) |
| 1011 | { |
| 1012 | /* BLTU sp, rx, .Lstackoverflow |
| 1013 | If the location branched to holds a BREAK 3 instruction |
| 1014 | then this is also stack overflow detection. */ |
| 1015 | unsigned int next_insn; |
| 1016 | const struct nios2_opcode *next_op |
| 1017 | = nios2_fetch_insn (gdbarch, pc + imm, &next_insn); |
| 1018 | if (next_op != NULL |
| 1019 | && nios2_match_break (next_insn, op, mach, &uimm)) |
| 1020 | ; |
| 1021 | else |
| 1022 | break; |
| 1023 | } |
| 1024 | else |
| 1025 | break; |
| 1026 | } |
| 1027 | |
| 1028 | /* All other calls or jumps (including returns) terminate |
| 1029 | the prologue. */ |
| 1030 | else if (nios2_match_callr (insn, op, mach, &ra) |
| 1031 | || nios2_match_jmpr (insn, op, mach, &ra) |
| 1032 | || nios2_match_jmpi (insn, op, mach, &uimm)) |
| 1033 | break; |
| 1034 | } |
| 1035 | |
| 1036 | /* If THIS_FRAME is NULL, we are being called from skip_prologue |
| 1037 | and are only interested in the PROLOGUE_END value, so just |
| 1038 | return that now and skip over the cache updates, which depend |
| 1039 | on having frame information. */ |
| 1040 | if (this_frame == NULL) |
| 1041 | return prologue_end; |
| 1042 | |
| 1043 | /* If we are in the function epilogue and have already popped |
| 1044 | registers off the stack in preparation for returning, then we |
| 1045 | want to go back to the original register values. */ |
| 1046 | if (innermost && nios2_in_epilogue_p (gdbarch, current_pc, start_pc)) |
| 1047 | nios2_setup_default (cache); |
| 1048 | |
| 1049 | /* Exception handlers use a different return address register. */ |
| 1050 | if (exception_handler) |
| 1051 | cache->return_regnum = NIOS2_EA_REGNUM; |
| 1052 | |
| 1053 | if (nios2_debug) |
| 1054 | fprintf_unfiltered (gdb_stdlog, "\n-> retreg=%d, ", cache->return_regnum); |
| 1055 | |
| 1056 | if (cache->reg_value[NIOS2_FP_REGNUM].reg == NIOS2_SP_REGNUM) |
| 1057 | /* If the FP now holds an offset from the CFA then this is a |
| 1058 | normal frame which uses the frame pointer. */ |
| 1059 | base_reg = NIOS2_FP_REGNUM; |
| 1060 | else if (cache->reg_value[NIOS2_SP_REGNUM].reg == NIOS2_SP_REGNUM) |
| 1061 | /* FP doesn't hold an offset from the CFA. If SP still holds an |
| 1062 | offset from the CFA then we might be in a function which omits |
| 1063 | the frame pointer, or we might be partway through the prologue. |
| 1064 | In both cases we can find the CFA using SP. */ |
| 1065 | base_reg = NIOS2_SP_REGNUM; |
| 1066 | else |
| 1067 | { |
| 1068 | /* Somehow the stack pointer has been corrupted. |
| 1069 | We can't return. */ |
| 1070 | if (nios2_debug) |
| 1071 | fprintf_unfiltered (gdb_stdlog, "<can't reach cfa> }\n"); |
| 1072 | return 0; |
| 1073 | } |
| 1074 | |
| 1075 | if (cache->reg_value[base_reg].offset == 0 |
| 1076 | || cache->reg_saved[NIOS2_RA_REGNUM].basereg != NIOS2_SP_REGNUM |
| 1077 | || cache->reg_saved[cache->return_regnum].basereg != NIOS2_SP_REGNUM) |
| 1078 | { |
| 1079 | /* If the frame didn't adjust the stack, didn't save RA or |
| 1080 | didn't save EA in an exception handler then it must either |
| 1081 | be a leaf function (doesn't call any other functions) or it |
| 1082 | can't return. If it has called another function then it |
| 1083 | can't be a leaf, so set base == 0 to indicate that we can't |
| 1084 | backtrace past it. */ |
| 1085 | |
| 1086 | if (!innermost) |
| 1087 | { |
| 1088 | /* If it isn't the innermost function then it can't be a |
| 1089 | leaf, unless it was interrupted. Check whether RA for |
| 1090 | this frame is the same as PC. If so then it probably |
| 1091 | wasn't interrupted. */ |
| 1092 | CORE_ADDR ra |
| 1093 | = get_frame_register_unsigned (this_frame, NIOS2_RA_REGNUM); |
| 1094 | |
| 1095 | if (ra == current_pc) |
| 1096 | { |
| 1097 | if (nios2_debug) |
| 1098 | fprintf_unfiltered |
| 1099 | (gdb_stdlog, |
| 1100 | "<noreturn ADJUST %s, r31@r%d+?>, r%d@r%d+?> }\n", |
| 1101 | paddress (gdbarch, cache->reg_value[base_reg].offset), |
| 1102 | cache->reg_saved[NIOS2_RA_REGNUM].basereg, |
| 1103 | cache->return_regnum, |
| 1104 | cache->reg_saved[cache->return_regnum].basereg); |
| 1105 | return 0; |
| 1106 | } |
| 1107 | } |
| 1108 | } |
| 1109 | |
| 1110 | /* Get the value of whichever register we are using for the |
| 1111 | base. */ |
| 1112 | cache->base = get_frame_register_unsigned (this_frame, base_reg); |
| 1113 | |
| 1114 | /* What was the value of SP at the start of this function (or just |
| 1115 | after the stack switch). */ |
| 1116 | frame_high = cache->base - cache->reg_value[base_reg].offset; |
| 1117 | |
| 1118 | /* Adjust all the saved registers such that they contain addresses |
| 1119 | instead of offsets. */ |
| 1120 | for (i = 0; i < NIOS2_NUM_REGS; i++) |
| 1121 | if (cache->reg_saved[i].basereg == NIOS2_SP_REGNUM) |
| 1122 | { |
| 1123 | cache->reg_saved[i].basereg = NIOS2_Z_REGNUM; |
| 1124 | cache->reg_saved[i].addr += frame_high; |
| 1125 | } |
| 1126 | |
| 1127 | for (i = 0; i < NIOS2_NUM_REGS; i++) |
| 1128 | if (cache->reg_saved[i].basereg == NIOS2_GP_REGNUM) |
| 1129 | { |
| 1130 | CORE_ADDR gp = get_frame_register_unsigned (this_frame, |
| 1131 | NIOS2_GP_REGNUM); |
| 1132 | |
| 1133 | for ( ; i < NIOS2_NUM_REGS; i++) |
| 1134 | if (cache->reg_saved[i].basereg == NIOS2_GP_REGNUM) |
| 1135 | { |
| 1136 | cache->reg_saved[i].basereg = NIOS2_Z_REGNUM; |
| 1137 | cache->reg_saved[i].addr += gp; |
| 1138 | } |
| 1139 | } |
| 1140 | |
| 1141 | /* Work out what the value of SP was on the first instruction of |
| 1142 | this function. If we didn't switch stacks then this can be |
| 1143 | trivially computed from the base address. */ |
| 1144 | if (cache->reg_saved[NIOS2_SP_REGNUM].basereg == NIOS2_Z_REGNUM) |
| 1145 | cache->cfa |
| 1146 | = read_memory_unsigned_integer (cache->reg_saved[NIOS2_SP_REGNUM].addr, |
| 1147 | 4, byte_order); |
| 1148 | else |
| 1149 | cache->cfa = frame_high; |
| 1150 | |
| 1151 | /* Exception handlers restore ESTATUS into STATUS. */ |
| 1152 | if (exception_handler) |
| 1153 | { |
| 1154 | cache->reg_saved[NIOS2_STATUS_REGNUM] |
| 1155 | = cache->reg_saved[NIOS2_ESTATUS_REGNUM]; |
| 1156 | cache->reg_saved[NIOS2_ESTATUS_REGNUM].basereg = -1; |
| 1157 | } |
| 1158 | |
| 1159 | if (nios2_debug) |
| 1160 | fprintf_unfiltered (gdb_stdlog, "cfa=%s }\n", |
| 1161 | paddress (gdbarch, cache->cfa)); |
| 1162 | |
| 1163 | return prologue_end; |
| 1164 | } |
| 1165 | |
| 1166 | /* Implement the skip_prologue gdbarch hook. */ |
| 1167 | |
| 1168 | static CORE_ADDR |
| 1169 | nios2_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
| 1170 | { |
| 1171 | CORE_ADDR func_addr; |
| 1172 | |
| 1173 | struct nios2_unwind_cache cache; |
| 1174 | |
| 1175 | /* See if we can determine the end of the prologue via the symbol |
| 1176 | table. If so, then return either PC, or the PC after the |
| 1177 | prologue, whichever is greater. */ |
| 1178 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) |
| 1179 | { |
| 1180 | CORE_ADDR post_prologue_pc |
| 1181 | = skip_prologue_using_sal (gdbarch, func_addr); |
| 1182 | |
| 1183 | if (post_prologue_pc != 0) |
| 1184 | return max (start_pc, post_prologue_pc); |
| 1185 | } |
| 1186 | |
| 1187 | /* Prologue analysis does the rest.... */ |
| 1188 | nios2_init_cache (&cache, start_pc); |
| 1189 | return nios2_analyze_prologue (gdbarch, start_pc, start_pc, &cache, NULL); |
| 1190 | } |
| 1191 | |
| 1192 | /* Implement the breakpoint_from_pc gdbarch hook. |
| 1193 | |
| 1194 | The Nios II ABI for Linux says: "Userspace programs should not use |
| 1195 | the break instruction and userspace debuggers should not insert |
| 1196 | one." and "Userspace breakpoints are accomplished using the trap |
| 1197 | instruction with immediate operand 31 (all ones)." |
| 1198 | |
| 1199 | So, we use "trap 31" consistently as the breakpoint on bare-metal |
| 1200 | as well as Linux targets. */ |
| 1201 | |
| 1202 | static const gdb_byte* |
| 1203 | nios2_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr, |
| 1204 | int *bp_size) |
| 1205 | { |
| 1206 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
| 1207 | unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; |
| 1208 | |
| 1209 | /* R1 trap encoding: |
| 1210 | ((0x1d << 17) | (0x2d << 11) | (0x1f << 6) | (0x3a << 0)) |
| 1211 | 0x003b6ffa */ |
| 1212 | static const gdb_byte r1_breakpoint_le[] = {0xfa, 0x6f, 0x3b, 0x0}; |
| 1213 | static const gdb_byte r1_breakpoint_be[] = {0x0, 0x3b, 0x6f, 0xfa}; |
| 1214 | *bp_size = NIOS2_OPCODE_SIZE; |
| 1215 | if (byte_order_for_code == BFD_ENDIAN_BIG) |
| 1216 | return r1_breakpoint_be; |
| 1217 | else |
| 1218 | return r1_breakpoint_le; |
| 1219 | } |
| 1220 | |
| 1221 | /* Implement the print_insn gdbarch method. */ |
| 1222 | |
| 1223 | static int |
| 1224 | nios2_print_insn (bfd_vma memaddr, disassemble_info *info) |
| 1225 | { |
| 1226 | if (info->endian == BFD_ENDIAN_BIG) |
| 1227 | return print_insn_big_nios2 (memaddr, info); |
| 1228 | else |
| 1229 | return print_insn_little_nios2 (memaddr, info); |
| 1230 | } |
| 1231 | |
| 1232 | |
| 1233 | /* Implement the frame_align gdbarch method. */ |
| 1234 | |
| 1235 | static CORE_ADDR |
| 1236 | nios2_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 1237 | { |
| 1238 | return align_down (addr, 4); |
| 1239 | } |
| 1240 | |
| 1241 | |
| 1242 | /* Implement the return_value gdbarch method. */ |
| 1243 | |
| 1244 | static enum return_value_convention |
| 1245 | nios2_return_value (struct gdbarch *gdbarch, struct value *function, |
| 1246 | struct type *type, struct regcache *regcache, |
| 1247 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 1248 | { |
| 1249 | if (TYPE_LENGTH (type) > 8) |
| 1250 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 1251 | |
| 1252 | if (readbuf) |
| 1253 | nios2_extract_return_value (gdbarch, type, regcache, readbuf); |
| 1254 | if (writebuf) |
| 1255 | nios2_store_return_value (gdbarch, type, regcache, writebuf); |
| 1256 | |
| 1257 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 1258 | } |
| 1259 | |
| 1260 | /* Implement the dummy_id gdbarch method. */ |
| 1261 | |
| 1262 | static struct frame_id |
| 1263 | nios2_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1264 | { |
| 1265 | return frame_id_build |
| 1266 | (get_frame_register_unsigned (this_frame, NIOS2_SP_REGNUM), |
| 1267 | get_frame_pc (this_frame)); |
| 1268 | } |
| 1269 | |
| 1270 | /* Implement the push_dummy_call gdbarch method. */ |
| 1271 | |
| 1272 | static CORE_ADDR |
| 1273 | nios2_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 1274 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 1275 | int nargs, struct value **args, CORE_ADDR sp, |
| 1276 | int struct_return, CORE_ADDR struct_addr) |
| 1277 | { |
| 1278 | int argreg; |
| 1279 | int float_argreg; |
| 1280 | int argnum; |
| 1281 | int len = 0; |
| 1282 | int stack_offset = 0; |
| 1283 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
| 1284 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1285 | |
| 1286 | /* Set the return address register to point to the entry point of |
| 1287 | the program, where a breakpoint lies in wait. */ |
| 1288 | regcache_cooked_write_signed (regcache, NIOS2_RA_REGNUM, bp_addr); |
| 1289 | |
| 1290 | /* Now make space on the stack for the args. */ |
| 1291 | for (argnum = 0; argnum < nargs; argnum++) |
| 1292 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), 4); |
| 1293 | sp -= len; |
| 1294 | |
| 1295 | /* Initialize the register pointer. */ |
| 1296 | argreg = NIOS2_FIRST_ARGREG; |
| 1297 | |
| 1298 | /* The struct_return pointer occupies the first parameter-passing |
| 1299 | register. */ |
| 1300 | if (struct_return) |
| 1301 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
| 1302 | |
| 1303 | /* Now load as many as possible of the first arguments into |
| 1304 | registers, and push the rest onto the stack. Loop through args |
| 1305 | from first to last. */ |
| 1306 | for (argnum = 0; argnum < nargs; argnum++) |
| 1307 | { |
| 1308 | const gdb_byte *val; |
| 1309 | gdb_byte valbuf[MAX_REGISTER_SIZE]; |
| 1310 | struct value *arg = args[argnum]; |
| 1311 | struct type *arg_type = check_typedef (value_type (arg)); |
| 1312 | int len = TYPE_LENGTH (arg_type); |
| 1313 | enum type_code typecode = TYPE_CODE (arg_type); |
| 1314 | |
| 1315 | val = value_contents (arg); |
| 1316 | |
| 1317 | /* Copy the argument to general registers or the stack in |
| 1318 | register-sized pieces. Large arguments are split between |
| 1319 | registers and stack. */ |
| 1320 | while (len > 0) |
| 1321 | { |
| 1322 | int partial_len = (len < 4 ? len : 4); |
| 1323 | |
| 1324 | if (argreg <= NIOS2_LAST_ARGREG) |
| 1325 | { |
| 1326 | /* The argument is being passed in a register. */ |
| 1327 | CORE_ADDR regval = extract_unsigned_integer (val, partial_len, |
| 1328 | byte_order); |
| 1329 | |
| 1330 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 1331 | argreg++; |
| 1332 | } |
| 1333 | else |
| 1334 | { |
| 1335 | /* The argument is being passed on the stack. */ |
| 1336 | CORE_ADDR addr = sp + stack_offset; |
| 1337 | |
| 1338 | write_memory (addr, val, partial_len); |
| 1339 | stack_offset += align_up (partial_len, 4); |
| 1340 | } |
| 1341 | |
| 1342 | len -= partial_len; |
| 1343 | val += partial_len; |
| 1344 | } |
| 1345 | } |
| 1346 | |
| 1347 | regcache_cooked_write_signed (regcache, NIOS2_SP_REGNUM, sp); |
| 1348 | |
| 1349 | /* Return adjusted stack pointer. */ |
| 1350 | return sp; |
| 1351 | } |
| 1352 | |
| 1353 | /* Implement the unwind_pc gdbarch method. */ |
| 1354 | |
| 1355 | static CORE_ADDR |
| 1356 | nios2_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1357 | { |
| 1358 | gdb_byte buf[4]; |
| 1359 | |
| 1360 | frame_unwind_register (next_frame, NIOS2_PC_REGNUM, buf); |
| 1361 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
| 1362 | } |
| 1363 | |
| 1364 | /* Implement the unwind_sp gdbarch method. */ |
| 1365 | |
| 1366 | static CORE_ADDR |
| 1367 | nios2_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1368 | { |
| 1369 | return frame_unwind_register_unsigned (this_frame, NIOS2_SP_REGNUM); |
| 1370 | } |
| 1371 | |
| 1372 | /* Use prologue analysis to fill in the register cache |
| 1373 | *THIS_PROLOGUE_CACHE for THIS_FRAME. This function initializes |
| 1374 | *THIS_PROLOGUE_CACHE first. */ |
| 1375 | |
| 1376 | static struct nios2_unwind_cache * |
| 1377 | nios2_frame_unwind_cache (struct frame_info *this_frame, |
| 1378 | void **this_prologue_cache) |
| 1379 | { |
| 1380 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1381 | CORE_ADDR current_pc; |
| 1382 | struct nios2_unwind_cache *cache; |
| 1383 | int i; |
| 1384 | |
| 1385 | if (*this_prologue_cache) |
| 1386 | return *this_prologue_cache; |
| 1387 | |
| 1388 | cache = FRAME_OBSTACK_ZALLOC (struct nios2_unwind_cache); |
| 1389 | *this_prologue_cache = cache; |
| 1390 | |
| 1391 | /* Zero all fields. */ |
| 1392 | nios2_init_cache (cache, get_frame_func (this_frame)); |
| 1393 | |
| 1394 | /* Prologue analysis does the rest... */ |
| 1395 | current_pc = get_frame_pc (this_frame); |
| 1396 | if (cache->pc != 0) |
| 1397 | nios2_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame); |
| 1398 | |
| 1399 | return cache; |
| 1400 | } |
| 1401 | |
| 1402 | /* Implement the this_id function for the normal unwinder. */ |
| 1403 | |
| 1404 | static void |
| 1405 | nios2_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 1406 | struct frame_id *this_id) |
| 1407 | { |
| 1408 | struct nios2_unwind_cache *cache = |
| 1409 | nios2_frame_unwind_cache (this_frame, this_cache); |
| 1410 | |
| 1411 | /* This marks the outermost frame. */ |
| 1412 | if (cache->base == 0) |
| 1413 | return; |
| 1414 | |
| 1415 | *this_id = frame_id_build (cache->cfa, cache->pc); |
| 1416 | } |
| 1417 | |
| 1418 | /* Implement the prev_register function for the normal unwinder. */ |
| 1419 | |
| 1420 | static struct value * |
| 1421 | nios2_frame_prev_register (struct frame_info *this_frame, void **this_cache, |
| 1422 | int regnum) |
| 1423 | { |
| 1424 | struct nios2_unwind_cache *cache = |
| 1425 | nios2_frame_unwind_cache (this_frame, this_cache); |
| 1426 | |
| 1427 | gdb_assert (regnum >= 0 && regnum < NIOS2_NUM_REGS); |
| 1428 | |
| 1429 | /* The PC of the previous frame is stored in the RA register of |
| 1430 | the current frame. Frob regnum so that we pull the value from |
| 1431 | the correct place. */ |
| 1432 | if (regnum == NIOS2_PC_REGNUM) |
| 1433 | regnum = cache->return_regnum; |
| 1434 | |
| 1435 | if (regnum == NIOS2_SP_REGNUM && cache->cfa) |
| 1436 | return frame_unwind_got_constant (this_frame, regnum, cache->cfa); |
| 1437 | |
| 1438 | /* If we've worked out where a register is stored then load it from |
| 1439 | there. */ |
| 1440 | if (cache->reg_saved[regnum].basereg == NIOS2_Z_REGNUM) |
| 1441 | return frame_unwind_got_memory (this_frame, regnum, |
| 1442 | cache->reg_saved[regnum].addr); |
| 1443 | |
| 1444 | return frame_unwind_got_register (this_frame, regnum, regnum); |
| 1445 | } |
| 1446 | |
| 1447 | /* Implement the this_base, this_locals, and this_args hooks |
| 1448 | for the normal unwinder. */ |
| 1449 | |
| 1450 | static CORE_ADDR |
| 1451 | nios2_frame_base_address (struct frame_info *this_frame, void **this_cache) |
| 1452 | { |
| 1453 | struct nios2_unwind_cache *info |
| 1454 | = nios2_frame_unwind_cache (this_frame, this_cache); |
| 1455 | |
| 1456 | return info->base; |
| 1457 | } |
| 1458 | |
| 1459 | /* Data structures for the normal prologue-analysis-based |
| 1460 | unwinder. */ |
| 1461 | |
| 1462 | static const struct frame_unwind nios2_frame_unwind = |
| 1463 | { |
| 1464 | NORMAL_FRAME, |
| 1465 | default_frame_unwind_stop_reason, |
| 1466 | nios2_frame_this_id, |
| 1467 | nios2_frame_prev_register, |
| 1468 | NULL, |
| 1469 | default_frame_sniffer |
| 1470 | }; |
| 1471 | |
| 1472 | static const struct frame_base nios2_frame_base = |
| 1473 | { |
| 1474 | &nios2_frame_unwind, |
| 1475 | nios2_frame_base_address, |
| 1476 | nios2_frame_base_address, |
| 1477 | nios2_frame_base_address |
| 1478 | }; |
| 1479 | |
| 1480 | /* Fill in the register cache *THIS_CACHE for THIS_FRAME for use |
| 1481 | in the stub unwinder. */ |
| 1482 | |
| 1483 | static struct trad_frame_cache * |
| 1484 | nios2_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 1485 | { |
| 1486 | CORE_ADDR pc; |
| 1487 | CORE_ADDR start_addr; |
| 1488 | CORE_ADDR stack_addr; |
| 1489 | struct trad_frame_cache *this_trad_cache; |
| 1490 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1491 | int num_regs = gdbarch_num_regs (gdbarch); |
| 1492 | |
| 1493 | if (*this_cache != NULL) |
| 1494 | return *this_cache; |
| 1495 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
| 1496 | *this_cache = this_trad_cache; |
| 1497 | |
| 1498 | /* The return address is in the link register. */ |
| 1499 | trad_frame_set_reg_realreg (this_trad_cache, |
| 1500 | gdbarch_pc_regnum (gdbarch), |
| 1501 | NIOS2_RA_REGNUM); |
| 1502 | |
| 1503 | /* Frame ID, since it's a frameless / stackless function, no stack |
| 1504 | space is allocated and SP on entry is the current SP. */ |
| 1505 | pc = get_frame_pc (this_frame); |
| 1506 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
| 1507 | stack_addr = get_frame_register_unsigned (this_frame, NIOS2_SP_REGNUM); |
| 1508 | trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr)); |
| 1509 | /* Assume that the frame's base is the same as the stack pointer. */ |
| 1510 | trad_frame_set_this_base (this_trad_cache, stack_addr); |
| 1511 | |
| 1512 | return this_trad_cache; |
| 1513 | } |
| 1514 | |
| 1515 | /* Implement the this_id function for the stub unwinder. */ |
| 1516 | |
| 1517 | static void |
| 1518 | nios2_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 1519 | struct frame_id *this_id) |
| 1520 | { |
| 1521 | struct trad_frame_cache *this_trad_cache |
| 1522 | = nios2_stub_frame_cache (this_frame, this_cache); |
| 1523 | |
| 1524 | trad_frame_get_id (this_trad_cache, this_id); |
| 1525 | } |
| 1526 | |
| 1527 | /* Implement the prev_register function for the stub unwinder. */ |
| 1528 | |
| 1529 | static struct value * |
| 1530 | nios2_stub_frame_prev_register (struct frame_info *this_frame, |
| 1531 | void **this_cache, int regnum) |
| 1532 | { |
| 1533 | struct trad_frame_cache *this_trad_cache |
| 1534 | = nios2_stub_frame_cache (this_frame, this_cache); |
| 1535 | |
| 1536 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); |
| 1537 | } |
| 1538 | |
| 1539 | /* Implement the sniffer function for the stub unwinder. |
| 1540 | This unwinder is used for cases where the normal |
| 1541 | prologue-analysis-based unwinder can't work, |
| 1542 | such as PLT stubs. */ |
| 1543 | |
| 1544 | static int |
| 1545 | nios2_stub_frame_sniffer (const struct frame_unwind *self, |
| 1546 | struct frame_info *this_frame, void **cache) |
| 1547 | { |
| 1548 | gdb_byte dummy[4]; |
| 1549 | struct obj_section *s; |
| 1550 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
| 1551 | |
| 1552 | /* Use the stub unwinder for unreadable code. */ |
| 1553 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
| 1554 | return 1; |
| 1555 | |
| 1556 | if (in_plt_section (pc)) |
| 1557 | return 1; |
| 1558 | |
| 1559 | return 0; |
| 1560 | } |
| 1561 | |
| 1562 | /* Define the data structures for the stub unwinder. */ |
| 1563 | |
| 1564 | static const struct frame_unwind nios2_stub_frame_unwind = |
| 1565 | { |
| 1566 | NORMAL_FRAME, |
| 1567 | default_frame_unwind_stop_reason, |
| 1568 | nios2_stub_frame_this_id, |
| 1569 | nios2_stub_frame_prev_register, |
| 1570 | NULL, |
| 1571 | nios2_stub_frame_sniffer |
| 1572 | }; |
| 1573 | |
| 1574 | |
| 1575 | |
| 1576 | /* Determine where to set a single step breakpoint while considering |
| 1577 | branch prediction. */ |
| 1578 | |
| 1579 | static CORE_ADDR |
| 1580 | nios2_get_next_pc (struct frame_info *frame, CORE_ADDR pc) |
| 1581 | { |
| 1582 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 1583 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1584 | unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; |
| 1585 | unsigned int insn; |
| 1586 | const struct nios2_opcode *op = nios2_fetch_insn (gdbarch, pc, &insn); |
| 1587 | int ra; |
| 1588 | int rb; |
| 1589 | int imm; |
| 1590 | unsigned int uimm; |
| 1591 | int wb, ret; |
| 1592 | enum branch_condition cond; |
| 1593 | |
| 1594 | /* Do something stupid if we can't disassemble the insn at pc. */ |
| 1595 | if (op == NULL) |
| 1596 | return pc + NIOS2_OPCODE_SIZE; |
| 1597 | |
| 1598 | if (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond)) |
| 1599 | { |
| 1600 | int ras = get_frame_register_signed (frame, ra); |
| 1601 | int rbs = get_frame_register_signed (frame, rb); |
| 1602 | unsigned int rau = get_frame_register_unsigned (frame, ra); |
| 1603 | unsigned int rbu = get_frame_register_unsigned (frame, rb); |
| 1604 | |
| 1605 | pc += op->size; |
| 1606 | switch (cond) |
| 1607 | { |
| 1608 | case branch_none: |
| 1609 | pc += imm; |
| 1610 | break; |
| 1611 | case branch_eq: |
| 1612 | if (ras == rbs) |
| 1613 | pc += imm; |
| 1614 | break; |
| 1615 | case branch_ne: |
| 1616 | if (ras != rbs) |
| 1617 | pc += imm; |
| 1618 | break; |
| 1619 | case branch_ge: |
| 1620 | if (ras >= rbs) |
| 1621 | pc += imm; |
| 1622 | break; |
| 1623 | case branch_geu: |
| 1624 | if (rau >= rbu) |
| 1625 | pc += imm; |
| 1626 | break; |
| 1627 | case branch_lt: |
| 1628 | if (ras < rbs) |
| 1629 | pc += imm; |
| 1630 | break; |
| 1631 | case branch_ltu: |
| 1632 | if (rau < rbu) |
| 1633 | pc += imm; |
| 1634 | break; |
| 1635 | default: |
| 1636 | break; |
| 1637 | } |
| 1638 | } |
| 1639 | |
| 1640 | else if (nios2_match_jmpi (insn, op, mach, &uimm) |
| 1641 | || nios2_match_calli (insn, op, mach, &uimm)) |
| 1642 | pc = (pc & 0xf0000000) | uimm; |
| 1643 | |
| 1644 | else if (nios2_match_jmpr (insn, op, mach, &ra) |
| 1645 | || nios2_match_callr (insn, op, mach, &ra)) |
| 1646 | pc = get_frame_register_unsigned (frame, ra); |
| 1647 | |
| 1648 | else if (nios2_match_trap (insn, op, mach, &uimm)) |
| 1649 | { |
| 1650 | if (tdep->syscall_next_pc != NULL) |
| 1651 | return tdep->syscall_next_pc (frame); |
| 1652 | } |
| 1653 | |
| 1654 | else |
| 1655 | pc += op->size; |
| 1656 | |
| 1657 | return pc; |
| 1658 | } |
| 1659 | |
| 1660 | /* Implement the software_single_step gdbarch method. */ |
| 1661 | |
| 1662 | static int |
| 1663 | nios2_software_single_step (struct frame_info *frame) |
| 1664 | { |
| 1665 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 1666 | struct address_space *aspace = get_frame_address_space (frame); |
| 1667 | CORE_ADDR next_pc = nios2_get_next_pc (frame, get_frame_pc (frame)); |
| 1668 | |
| 1669 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
| 1670 | |
| 1671 | return 1; |
| 1672 | } |
| 1673 | |
| 1674 | /* Implement the get_longjump_target gdbarch method. */ |
| 1675 | |
| 1676 | static int |
| 1677 | nios2_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
| 1678 | { |
| 1679 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 1680 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1681 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1682 | CORE_ADDR jb_addr = get_frame_register_unsigned (frame, NIOS2_R4_REGNUM); |
| 1683 | gdb_byte buf[4]; |
| 1684 | |
| 1685 | if (target_read_memory (jb_addr + (tdep->jb_pc * 4), buf, 4)) |
| 1686 | return 0; |
| 1687 | |
| 1688 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
| 1689 | return 1; |
| 1690 | } |
| 1691 | |
| 1692 | /* Initialize the Nios II gdbarch. */ |
| 1693 | |
| 1694 | static struct gdbarch * |
| 1695 | nios2_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 1696 | { |
| 1697 | struct gdbarch *gdbarch; |
| 1698 | struct gdbarch_tdep *tdep; |
| 1699 | int register_bytes, i; |
| 1700 | struct tdesc_arch_data *tdesc_data = NULL; |
| 1701 | const struct target_desc *tdesc = info.target_desc; |
| 1702 | |
| 1703 | if (!tdesc_has_registers (tdesc)) |
| 1704 | /* Pick a default target description. */ |
| 1705 | tdesc = tdesc_nios2; |
| 1706 | |
| 1707 | /* Check any target description for validity. */ |
| 1708 | if (tdesc_has_registers (tdesc)) |
| 1709 | { |
| 1710 | const struct tdesc_feature *feature; |
| 1711 | int valid_p; |
| 1712 | |
| 1713 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nios2.cpu"); |
| 1714 | if (feature == NULL) |
| 1715 | return NULL; |
| 1716 | |
| 1717 | tdesc_data = tdesc_data_alloc (); |
| 1718 | |
| 1719 | valid_p = 1; |
| 1720 | |
| 1721 | for (i = 0; i < NIOS2_NUM_REGS; i++) |
| 1722 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, |
| 1723 | nios2_reg_names[i]); |
| 1724 | |
| 1725 | if (!valid_p) |
| 1726 | { |
| 1727 | tdesc_data_cleanup (tdesc_data); |
| 1728 | return NULL; |
| 1729 | } |
| 1730 | } |
| 1731 | |
| 1732 | /* Find a candidate among the list of pre-declared architectures. */ |
| 1733 | arches = gdbarch_list_lookup_by_info (arches, &info); |
| 1734 | if (arches != NULL) |
| 1735 | return arches->gdbarch; |
| 1736 | |
| 1737 | /* None found, create a new architecture from the information |
| 1738 | provided. */ |
| 1739 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); |
| 1740 | gdbarch = gdbarch_alloc (&info, tdep); |
| 1741 | |
| 1742 | /* longjmp support not enabled by default. */ |
| 1743 | tdep->jb_pc = -1; |
| 1744 | |
| 1745 | /* Data type sizes. */ |
| 1746 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 1747 | set_gdbarch_addr_bit (gdbarch, 32); |
| 1748 | set_gdbarch_short_bit (gdbarch, 16); |
| 1749 | set_gdbarch_int_bit (gdbarch, 32); |
| 1750 | set_gdbarch_long_bit (gdbarch, 32); |
| 1751 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 1752 | set_gdbarch_float_bit (gdbarch, 32); |
| 1753 | set_gdbarch_double_bit (gdbarch, 64); |
| 1754 | |
| 1755 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
| 1756 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); |
| 1757 | |
| 1758 | /* The register set. */ |
| 1759 | set_gdbarch_num_regs (gdbarch, NIOS2_NUM_REGS); |
| 1760 | set_gdbarch_sp_regnum (gdbarch, NIOS2_SP_REGNUM); |
| 1761 | set_gdbarch_pc_regnum (gdbarch, NIOS2_PC_REGNUM); /* Pseudo register PC */ |
| 1762 | |
| 1763 | set_gdbarch_register_name (gdbarch, nios2_register_name); |
| 1764 | set_gdbarch_register_type (gdbarch, nios2_register_type); |
| 1765 | |
| 1766 | /* Provide register mappings for stabs and dwarf2. */ |
| 1767 | set_gdbarch_stab_reg_to_regnum (gdbarch, nios2_dwarf_reg_to_regnum); |
| 1768 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nios2_dwarf_reg_to_regnum); |
| 1769 | |
| 1770 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 1771 | |
| 1772 | /* Call dummy code. */ |
| 1773 | set_gdbarch_frame_align (gdbarch, nios2_frame_align); |
| 1774 | |
| 1775 | set_gdbarch_return_value (gdbarch, nios2_return_value); |
| 1776 | |
| 1777 | set_gdbarch_skip_prologue (gdbarch, nios2_skip_prologue); |
| 1778 | set_gdbarch_stack_frame_destroyed_p (gdbarch, nios2_stack_frame_destroyed_p); |
| 1779 | set_gdbarch_breakpoint_from_pc (gdbarch, nios2_breakpoint_from_pc); |
| 1780 | |
| 1781 | set_gdbarch_dummy_id (gdbarch, nios2_dummy_id); |
| 1782 | set_gdbarch_unwind_pc (gdbarch, nios2_unwind_pc); |
| 1783 | set_gdbarch_unwind_sp (gdbarch, nios2_unwind_sp); |
| 1784 | |
| 1785 | /* The dwarf2 unwinder will normally produce the best results if |
| 1786 | the debug information is available, so register it first. */ |
| 1787 | dwarf2_append_unwinders (gdbarch); |
| 1788 | frame_unwind_append_unwinder (gdbarch, &nios2_stub_frame_unwind); |
| 1789 | frame_unwind_append_unwinder (gdbarch, &nios2_frame_unwind); |
| 1790 | |
| 1791 | /* Single stepping. */ |
| 1792 | set_gdbarch_software_single_step (gdbarch, nios2_software_single_step); |
| 1793 | |
| 1794 | /* Hook in ABI-specific overrides, if they have been registered. */ |
| 1795 | gdbarch_init_osabi (info, gdbarch); |
| 1796 | |
| 1797 | if (tdep->jb_pc >= 0) |
| 1798 | set_gdbarch_get_longjmp_target (gdbarch, nios2_get_longjmp_target); |
| 1799 | |
| 1800 | frame_base_set_default (gdbarch, &nios2_frame_base); |
| 1801 | |
| 1802 | set_gdbarch_print_insn (gdbarch, nios2_print_insn); |
| 1803 | |
| 1804 | /* Enable inferior call support. */ |
| 1805 | set_gdbarch_push_dummy_call (gdbarch, nios2_push_dummy_call); |
| 1806 | |
| 1807 | if (tdesc_data) |
| 1808 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
| 1809 | |
| 1810 | return gdbarch; |
| 1811 | } |
| 1812 | |
| 1813 | extern initialize_file_ftype _initialize_nios2_tdep; /* -Wmissing-prototypes */ |
| 1814 | |
| 1815 | void |
| 1816 | _initialize_nios2_tdep (void) |
| 1817 | { |
| 1818 | gdbarch_register (bfd_arch_nios2, nios2_gdbarch_init, NULL); |
| 1819 | initialize_tdesc_nios2 (); |
| 1820 | |
| 1821 | /* Allow debugging this file's internals. */ |
| 1822 | add_setshow_boolean_cmd ("nios2", class_maintenance, &nios2_debug, |
| 1823 | _("Set Nios II debugging."), |
| 1824 | _("Show Nios II debugging."), |
| 1825 | _("When on, Nios II specific debugging is enabled."), |
| 1826 | NULL, |
| 1827 | NULL, |
| 1828 | &setdebuglist, &showdebuglist); |
| 1829 | } |