| 1 | /* Target-dependent code for the 32-bit OpenRISC 1000, for the GDB. |
| 2 | Copyright (C) 2008-2020 Free Software Foundation, Inc. |
| 3 | |
| 4 | This file is part of GDB. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 3 of the License, or |
| 9 | (at your option) any later version. |
| 10 | |
| 11 | This program is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | GNU General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 18 | |
| 19 | #include "defs.h" |
| 20 | #include "frame.h" |
| 21 | #include "inferior.h" |
| 22 | #include "symtab.h" |
| 23 | #include "value.h" |
| 24 | #include "gdbcmd.h" |
| 25 | #include "language.h" |
| 26 | #include "gdbcore.h" |
| 27 | #include "symfile.h" |
| 28 | #include "objfiles.h" |
| 29 | #include "gdbtypes.h" |
| 30 | #include "target.h" |
| 31 | #include "regcache.h" |
| 32 | #include "safe-ctype.h" |
| 33 | #include "block.h" |
| 34 | #include "reggroups.h" |
| 35 | #include "arch-utils.h" |
| 36 | #include "frame-unwind.h" |
| 37 | #include "frame-base.h" |
| 38 | #include "dwarf2/frame.h" |
| 39 | #include "trad-frame.h" |
| 40 | #include "regset.h" |
| 41 | #include "remote.h" |
| 42 | #include "target-descriptions.h" |
| 43 | #include <inttypes.h> |
| 44 | #include "dis-asm.h" |
| 45 | |
| 46 | /* OpenRISC specific includes. */ |
| 47 | #include "or1k-tdep.h" |
| 48 | #include "features/or1k.c" |
| 49 | \f |
| 50 | |
| 51 | /* Global debug flag. */ |
| 52 | |
| 53 | static bool or1k_debug = false; |
| 54 | |
| 55 | static void |
| 56 | show_or1k_debug (struct ui_file *file, int from_tty, |
| 57 | struct cmd_list_element *c, const char *value) |
| 58 | { |
| 59 | fprintf_filtered (file, _("OpenRISC debugging is %s.\n"), value); |
| 60 | } |
| 61 | |
| 62 | |
| 63 | /* The target-dependent structure for gdbarch. */ |
| 64 | |
| 65 | struct gdbarch_tdep |
| 66 | { |
| 67 | int bytes_per_word; |
| 68 | int bytes_per_address; |
| 69 | CGEN_CPU_DESC gdb_cgen_cpu_desc; |
| 70 | }; |
| 71 | |
| 72 | /* Support functions for the architecture definition. */ |
| 73 | |
| 74 | /* Get an instruction from memory. */ |
| 75 | |
| 76 | static ULONGEST |
| 77 | or1k_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 78 | { |
| 79 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 80 | gdb_byte buf[OR1K_INSTLEN]; |
| 81 | |
| 82 | if (target_read_code (addr, buf, OR1K_INSTLEN)) { |
| 83 | memory_error (TARGET_XFER_E_IO, addr); |
| 84 | } |
| 85 | |
| 86 | return extract_unsigned_integer (buf, OR1K_INSTLEN, byte_order); |
| 87 | } |
| 88 | |
| 89 | /* Generic function to read bits from an instruction. */ |
| 90 | |
| 91 | static bool |
| 92 | or1k_analyse_inst (uint32_t inst, const char *format, ...) |
| 93 | { |
| 94 | /* Break out each field in turn, validating as we go. */ |
| 95 | va_list ap; |
| 96 | int i; |
| 97 | int iptr = 0; /* Instruction pointer */ |
| 98 | |
| 99 | va_start (ap, format); |
| 100 | |
| 101 | for (i = 0; 0 != format[i];) |
| 102 | { |
| 103 | const char *start_ptr; |
| 104 | char *end_ptr; |
| 105 | |
| 106 | uint32_t bits; /* Bit substring of interest */ |
| 107 | uint32_t width; /* Substring width */ |
| 108 | uint32_t *arg_ptr; |
| 109 | |
| 110 | switch (format[i]) |
| 111 | { |
| 112 | case ' ': |
| 113 | i++; |
| 114 | break; /* Formatting: ignored */ |
| 115 | |
| 116 | case '0': |
| 117 | case '1': /* Constant bit field */ |
| 118 | bits = (inst >> (OR1K_INSTBITLEN - iptr - 1)) & 0x1; |
| 119 | |
| 120 | if ((format[i] - '0') != bits) |
| 121 | return false; |
| 122 | |
| 123 | iptr++; |
| 124 | i++; |
| 125 | break; |
| 126 | |
| 127 | case '%': /* Bit field */ |
| 128 | i++; |
| 129 | start_ptr = &(format[i]); |
| 130 | width = strtoul (start_ptr, &end_ptr, 10); |
| 131 | |
| 132 | /* Check we got something, and if so skip on. */ |
| 133 | if (start_ptr == end_ptr) |
| 134 | error (_("bitstring \"%s\" at offset %d has no length field."), |
| 135 | format, i); |
| 136 | |
| 137 | i += end_ptr - start_ptr; |
| 138 | |
| 139 | /* Look for and skip the terminating 'b'. If it's not there, we |
| 140 | still give a fatal error, because these are fixed strings that |
| 141 | just should not be wrong. */ |
| 142 | if ('b' != format[i++]) |
| 143 | error (_("bitstring \"%s\" at offset %d has no terminating 'b'."), |
| 144 | format, i); |
| 145 | |
| 146 | /* Break out the field. There is a special case with a bit width |
| 147 | of 32. */ |
| 148 | if (32 == width) |
| 149 | bits = inst; |
| 150 | else |
| 151 | bits = |
| 152 | (inst >> (OR1K_INSTBITLEN - iptr - width)) & ((1 << width) - 1); |
| 153 | |
| 154 | arg_ptr = va_arg (ap, uint32_t *); |
| 155 | *arg_ptr = bits; |
| 156 | iptr += width; |
| 157 | break; |
| 158 | |
| 159 | default: |
| 160 | error (_("invalid character in bitstring \"%s\" at offset %d."), |
| 161 | format, i); |
| 162 | break; |
| 163 | } |
| 164 | } |
| 165 | |
| 166 | /* Is the length OK? */ |
| 167 | gdb_assert (OR1K_INSTBITLEN == iptr); |
| 168 | |
| 169 | return true; /* Success */ |
| 170 | } |
| 171 | |
| 172 | /* This is used to parse l.addi instructions during various prologue |
| 173 | analysis routines. The l.addi instruction has semantics: |
| 174 | |
| 175 | assembly: l.addi rD,rA,I |
| 176 | implementation: rD = rA + sign_extend(Immediate) |
| 177 | |
| 178 | The rd_ptr, ra_ptr and simm_ptr must be non NULL pointers and are used |
| 179 | to store the parse results. Upon successful parsing true is returned, |
| 180 | false on failure. */ |
| 181 | |
| 182 | static bool |
| 183 | or1k_analyse_l_addi (uint32_t inst, unsigned int *rd_ptr, |
| 184 | unsigned int *ra_ptr, int *simm_ptr) |
| 185 | { |
| 186 | /* Instruction fields */ |
| 187 | uint32_t rd, ra, i; |
| 188 | |
| 189 | if (or1k_analyse_inst (inst, "10 0111 %5b %5b %16b", &rd, &ra, &i)) |
| 190 | { |
| 191 | /* Found it. Construct the result fields. */ |
| 192 | *rd_ptr = (unsigned int) rd; |
| 193 | *ra_ptr = (unsigned int) ra; |
| 194 | *simm_ptr = (int) (((i & 0x8000) == 0x8000) ? 0xffff0000 | i : i); |
| 195 | |
| 196 | return true; /* Success */ |
| 197 | } |
| 198 | else |
| 199 | return false; /* Failure */ |
| 200 | } |
| 201 | |
| 202 | /* This is used to to parse store instructions during various prologue |
| 203 | analysis routines. The l.sw instruction has semantics: |
| 204 | |
| 205 | assembly: l.sw I(rA),rB |
| 206 | implementation: store rB contents to memory at effective address of |
| 207 | rA + sign_extend(Immediate) |
| 208 | |
| 209 | The simm_ptr, ra_ptr and rb_ptr must be non NULL pointers and are used |
| 210 | to store the parse results. Upon successful parsing true is returned, |
| 211 | false on failure. */ |
| 212 | |
| 213 | static bool |
| 214 | or1k_analyse_l_sw (uint32_t inst, int *simm_ptr, unsigned int *ra_ptr, |
| 215 | unsigned int *rb_ptr) |
| 216 | { |
| 217 | /* Instruction fields */ |
| 218 | uint32_t ihi, ilo, ra, rb; |
| 219 | |
| 220 | if (or1k_analyse_inst (inst, "11 0101 %5b %5b %5b %11b", &ihi, &ra, &rb, |
| 221 | &ilo)) |
| 222 | |
| 223 | { |
| 224 | /* Found it. Construct the result fields. */ |
| 225 | *simm_ptr = (int) ((ihi << 11) | ilo); |
| 226 | *simm_ptr |= ((ihi & 0x10) == 0x10) ? 0xffff0000 : 0; |
| 227 | |
| 228 | *ra_ptr = (unsigned int) ra; |
| 229 | *rb_ptr = (unsigned int) rb; |
| 230 | |
| 231 | return true; /* Success */ |
| 232 | } |
| 233 | else |
| 234 | return false; /* Failure */ |
| 235 | } |
| 236 | \f |
| 237 | |
| 238 | /* Functions defining the architecture. */ |
| 239 | |
| 240 | /* Implement the return_value gdbarch method. */ |
| 241 | |
| 242 | static enum return_value_convention |
| 243 | or1k_return_value (struct gdbarch *gdbarch, struct value *functype, |
| 244 | struct type *valtype, struct regcache *regcache, |
| 245 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 246 | { |
| 247 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 248 | enum type_code rv_type = TYPE_CODE (valtype); |
| 249 | unsigned int rv_size = TYPE_LENGTH (valtype); |
| 250 | int bpw = (gdbarch_tdep (gdbarch))->bytes_per_word; |
| 251 | |
| 252 | /* Deal with struct/union as addresses. If an array won't fit in a |
| 253 | single register it is returned as address. Anything larger than 2 |
| 254 | registers needs to also be passed as address (matches gcc |
| 255 | default_return_in_memory). */ |
| 256 | if ((TYPE_CODE_STRUCT == rv_type) || (TYPE_CODE_UNION == rv_type) |
| 257 | || ((TYPE_CODE_ARRAY == rv_type) && (rv_size > bpw)) |
| 258 | || (rv_size > 2 * bpw)) |
| 259 | { |
| 260 | if (readbuf != NULL) |
| 261 | { |
| 262 | ULONGEST tmp; |
| 263 | |
| 264 | regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM, &tmp); |
| 265 | read_memory (tmp, readbuf, rv_size); |
| 266 | } |
| 267 | if (writebuf != NULL) |
| 268 | { |
| 269 | ULONGEST tmp; |
| 270 | |
| 271 | regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM, &tmp); |
| 272 | write_memory (tmp, writebuf, rv_size); |
| 273 | } |
| 274 | |
| 275 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; |
| 276 | } |
| 277 | |
| 278 | if (rv_size <= bpw) |
| 279 | { |
| 280 | /* Up to one word scalars are returned in R11. */ |
| 281 | if (readbuf != NULL) |
| 282 | { |
| 283 | ULONGEST tmp; |
| 284 | |
| 285 | regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM, &tmp); |
| 286 | store_unsigned_integer (readbuf, rv_size, byte_order, tmp); |
| 287 | |
| 288 | } |
| 289 | if (writebuf != NULL) |
| 290 | { |
| 291 | gdb_byte *buf = XCNEWVEC(gdb_byte, bpw); |
| 292 | |
| 293 | if (BFD_ENDIAN_BIG == byte_order) |
| 294 | memcpy (buf + (sizeof (gdb_byte) * bpw) - rv_size, writebuf, |
| 295 | rv_size); |
| 296 | else |
| 297 | memcpy (buf, writebuf, rv_size); |
| 298 | |
| 299 | regcache->cooked_write (OR1K_RV_REGNUM, buf); |
| 300 | |
| 301 | free (buf); |
| 302 | } |
| 303 | } |
| 304 | else |
| 305 | { |
| 306 | /* 2 word scalars are returned in r11/r12 (with the MS word in r11). */ |
| 307 | if (readbuf != NULL) |
| 308 | { |
| 309 | ULONGEST tmp_lo; |
| 310 | ULONGEST tmp_hi; |
| 311 | ULONGEST tmp; |
| 312 | |
| 313 | regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM, |
| 314 | &tmp_hi); |
| 315 | regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM + 1, |
| 316 | &tmp_lo); |
| 317 | tmp = (tmp_hi << (bpw * 8)) | tmp_lo; |
| 318 | |
| 319 | store_unsigned_integer (readbuf, rv_size, byte_order, tmp); |
| 320 | } |
| 321 | if (writebuf != NULL) |
| 322 | { |
| 323 | gdb_byte *buf_lo = XCNEWVEC(gdb_byte, bpw); |
| 324 | gdb_byte *buf_hi = XCNEWVEC(gdb_byte, bpw); |
| 325 | |
| 326 | /* This is cheating. We assume that we fit in 2 words exactly, |
| 327 | which wouldn't work if we had (say) a 6-byte scalar type on a |
| 328 | big endian architecture (with the OpenRISC 1000 usually is). */ |
| 329 | memcpy (buf_hi, writebuf, rv_size - bpw); |
| 330 | memcpy (buf_lo, writebuf + bpw, bpw); |
| 331 | |
| 332 | regcache->cooked_write (OR1K_RV_REGNUM, buf_hi); |
| 333 | regcache->cooked_write (OR1K_RV_REGNUM + 1, buf_lo); |
| 334 | |
| 335 | free (buf_lo); |
| 336 | free (buf_hi); |
| 337 | } |
| 338 | } |
| 339 | |
| 340 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 341 | } |
| 342 | |
| 343 | /* OR1K always uses a l.trap instruction for breakpoints. */ |
| 344 | |
| 345 | constexpr gdb_byte or1k_break_insn[] = {0x21, 0x00, 0x00, 0x01}; |
| 346 | |
| 347 | typedef BP_MANIPULATION (or1k_break_insn) or1k_breakpoint; |
| 348 | |
| 349 | /* Implement the single_step_through_delay gdbarch method. */ |
| 350 | |
| 351 | static int |
| 352 | or1k_single_step_through_delay (struct gdbarch *gdbarch, |
| 353 | struct frame_info *this_frame) |
| 354 | { |
| 355 | ULONGEST val; |
| 356 | CORE_ADDR ppc; |
| 357 | CORE_ADDR npc; |
| 358 | CGEN_FIELDS tmp_fields; |
| 359 | const CGEN_INSN *insn; |
| 360 | struct regcache *regcache = get_current_regcache (); |
| 361 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 362 | |
| 363 | /* Get the previous and current instruction addresses. If they are not |
| 364 | adjacent, we cannot be in a delay slot. */ |
| 365 | regcache_cooked_read_unsigned (regcache, OR1K_PPC_REGNUM, &val); |
| 366 | ppc = (CORE_ADDR) val; |
| 367 | regcache_cooked_read_unsigned (regcache, OR1K_NPC_REGNUM, &val); |
| 368 | npc = (CORE_ADDR) val; |
| 369 | |
| 370 | if (0x4 != (npc - ppc)) |
| 371 | return 0; |
| 372 | |
| 373 | insn = cgen_lookup_insn (tdep->gdb_cgen_cpu_desc, |
| 374 | NULL, |
| 375 | or1k_fetch_instruction (gdbarch, ppc), |
| 376 | NULL, 32, &tmp_fields, 0); |
| 377 | |
| 378 | /* NULL here would mean the last instruction was not understood by cgen. |
| 379 | This should not usually happen, but if does its not a delay slot. */ |
| 380 | if (insn == NULL) |
| 381 | return 0; |
| 382 | |
| 383 | /* TODO: we should add a delay slot flag to the CGEN_INSN and remove |
| 384 | this hard coded test. */ |
| 385 | return ((CGEN_INSN_NUM (insn) == OR1K_INSN_L_J) |
| 386 | || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_JAL) |
| 387 | || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_JR) |
| 388 | || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_JALR) |
| 389 | || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_BNF) |
| 390 | || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_BF)); |
| 391 | } |
| 392 | |
| 393 | /* Name for or1k general registers. */ |
| 394 | |
| 395 | static const char *const or1k_reg_names[OR1K_NUM_REGS] = { |
| 396 | /* general purpose registers */ |
| 397 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 398 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 399 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
| 400 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
| 401 | |
| 402 | /* previous program counter, next program counter and status register */ |
| 403 | "ppc", "npc", "sr" |
| 404 | }; |
| 405 | |
| 406 | static int |
| 407 | or1k_is_arg_reg (unsigned int regnum) |
| 408 | { |
| 409 | return (OR1K_FIRST_ARG_REGNUM <= regnum) |
| 410 | && (regnum <= OR1K_LAST_ARG_REGNUM); |
| 411 | } |
| 412 | |
| 413 | static int |
| 414 | or1k_is_callee_saved_reg (unsigned int regnum) |
| 415 | { |
| 416 | return (OR1K_FIRST_SAVED_REGNUM <= regnum) && (0 == regnum % 2); |
| 417 | } |
| 418 | |
| 419 | /* Implement the skip_prologue gdbarch method. */ |
| 420 | |
| 421 | static CORE_ADDR |
| 422 | or1k_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 423 | { |
| 424 | CORE_ADDR start_pc; |
| 425 | CORE_ADDR addr; |
| 426 | uint32_t inst; |
| 427 | |
| 428 | unsigned int ra, rb, rd; /* for instruction analysis */ |
| 429 | int simm; |
| 430 | |
| 431 | int frame_size = 0; |
| 432 | |
| 433 | /* Try using SAL first if we have symbolic information available. This |
| 434 | only works for DWARF 2, not STABS. */ |
| 435 | |
| 436 | if (find_pc_partial_function (pc, NULL, &start_pc, NULL)) |
| 437 | { |
| 438 | CORE_ADDR prologue_end = skip_prologue_using_sal (gdbarch, pc); |
| 439 | |
| 440 | if (0 != prologue_end) |
| 441 | { |
| 442 | struct symtab_and_line prologue_sal = find_pc_line (start_pc, 0); |
| 443 | struct compunit_symtab *compunit |
| 444 | = SYMTAB_COMPUNIT (prologue_sal.symtab); |
| 445 | const char *debug_format = COMPUNIT_DEBUGFORMAT (compunit); |
| 446 | |
| 447 | if ((NULL != debug_format) |
| 448 | && (strlen ("dwarf") <= strlen (debug_format)) |
| 449 | && (0 == strncasecmp ("dwarf", debug_format, strlen ("dwarf")))) |
| 450 | return (prologue_end > pc) ? prologue_end : pc; |
| 451 | } |
| 452 | } |
| 453 | |
| 454 | /* Look to see if we can find any of the standard prologue sequence. All |
| 455 | quite difficult, since any or all of it may be missing. So this is |
| 456 | just a best guess! */ |
| 457 | |
| 458 | addr = pc; /* Where we have got to */ |
| 459 | inst = or1k_fetch_instruction (gdbarch, addr); |
| 460 | |
| 461 | /* Look for the new stack pointer being set up. */ |
| 462 | if (or1k_analyse_l_addi (inst, &rd, &ra, &simm) |
| 463 | && (OR1K_SP_REGNUM == rd) && (OR1K_SP_REGNUM == ra) |
| 464 | && (simm < 0) && (0 == (simm % 4))) |
| 465 | { |
| 466 | frame_size = -simm; |
| 467 | addr += OR1K_INSTLEN; |
| 468 | inst = or1k_fetch_instruction (gdbarch, addr); |
| 469 | } |
| 470 | |
| 471 | /* Look for the frame pointer being manipulated. */ |
| 472 | if (or1k_analyse_l_sw (inst, &simm, &ra, &rb) |
| 473 | && (OR1K_SP_REGNUM == ra) && (OR1K_FP_REGNUM == rb) |
| 474 | && (simm >= 0) && (0 == (simm % 4))) |
| 475 | { |
| 476 | addr += OR1K_INSTLEN; |
| 477 | inst = or1k_fetch_instruction (gdbarch, addr); |
| 478 | |
| 479 | gdb_assert (or1k_analyse_l_addi (inst, &rd, &ra, &simm) |
| 480 | && (OR1K_FP_REGNUM == rd) && (OR1K_SP_REGNUM == ra) |
| 481 | && (simm == frame_size)); |
| 482 | |
| 483 | addr += OR1K_INSTLEN; |
| 484 | inst = or1k_fetch_instruction (gdbarch, addr); |
| 485 | } |
| 486 | |
| 487 | /* Look for the link register being saved. */ |
| 488 | if (or1k_analyse_l_sw (inst, &simm, &ra, &rb) |
| 489 | && (OR1K_SP_REGNUM == ra) && (OR1K_LR_REGNUM == rb) |
| 490 | && (simm >= 0) && (0 == (simm % 4))) |
| 491 | { |
| 492 | addr += OR1K_INSTLEN; |
| 493 | inst = or1k_fetch_instruction (gdbarch, addr); |
| 494 | } |
| 495 | |
| 496 | /* Look for arguments or callee-saved register being saved. The register |
| 497 | must be one of the arguments (r3-r8) or the 10 callee saved registers |
| 498 | (r10, r12, r14, r16, r18, r20, r22, r24, r26, r28, r30). The base |
| 499 | register must be the FP (for the args) or the SP (for the callee_saved |
| 500 | registers). */ |
| 501 | while (1) |
| 502 | { |
| 503 | if (or1k_analyse_l_sw (inst, &simm, &ra, &rb) |
| 504 | && (((OR1K_FP_REGNUM == ra) && or1k_is_arg_reg (rb)) |
| 505 | || ((OR1K_SP_REGNUM == ra) && or1k_is_callee_saved_reg (rb))) |
| 506 | && (0 == (simm % 4))) |
| 507 | { |
| 508 | addr += OR1K_INSTLEN; |
| 509 | inst = or1k_fetch_instruction (gdbarch, addr); |
| 510 | } |
| 511 | else |
| 512 | { |
| 513 | /* Nothing else to look for. We have found the end of the |
| 514 | prologue. */ |
| 515 | break; |
| 516 | } |
| 517 | } |
| 518 | return addr; |
| 519 | } |
| 520 | |
| 521 | /* Implement the frame_align gdbarch method. */ |
| 522 | |
| 523 | static CORE_ADDR |
| 524 | or1k_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
| 525 | { |
| 526 | return align_down (sp, OR1K_STACK_ALIGN); |
| 527 | } |
| 528 | |
| 529 | /* Implement the unwind_pc gdbarch method. */ |
| 530 | |
| 531 | static CORE_ADDR |
| 532 | or1k_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 533 | { |
| 534 | CORE_ADDR pc; |
| 535 | |
| 536 | if (or1k_debug) |
| 537 | fprintf_unfiltered (gdb_stdlog, "or1k_unwind_pc, next_frame=%d\n", |
| 538 | frame_relative_level (next_frame)); |
| 539 | |
| 540 | pc = frame_unwind_register_unsigned (next_frame, OR1K_NPC_REGNUM); |
| 541 | |
| 542 | if (or1k_debug) |
| 543 | fprintf_unfiltered (gdb_stdlog, "or1k_unwind_pc, pc=%s\n", |
| 544 | paddress (gdbarch, pc)); |
| 545 | |
| 546 | return pc; |
| 547 | } |
| 548 | |
| 549 | /* Implement the unwind_sp gdbarch method. */ |
| 550 | |
| 551 | static CORE_ADDR |
| 552 | or1k_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 553 | { |
| 554 | CORE_ADDR sp; |
| 555 | |
| 556 | if (or1k_debug) |
| 557 | fprintf_unfiltered (gdb_stdlog, "or1k_unwind_sp, next_frame=%d\n", |
| 558 | frame_relative_level (next_frame)); |
| 559 | |
| 560 | sp = frame_unwind_register_unsigned (next_frame, OR1K_SP_REGNUM); |
| 561 | |
| 562 | if (or1k_debug) |
| 563 | fprintf_unfiltered (gdb_stdlog, "or1k_unwind_sp, sp=%s\n", |
| 564 | paddress (gdbarch, sp)); |
| 565 | |
| 566 | return sp; |
| 567 | } |
| 568 | |
| 569 | /* Implement the push_dummy_code gdbarch method. */ |
| 570 | |
| 571 | static CORE_ADDR |
| 572 | or1k_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, |
| 573 | CORE_ADDR function, struct value **args, int nargs, |
| 574 | struct type *value_type, CORE_ADDR * real_pc, |
| 575 | CORE_ADDR * bp_addr, struct regcache *regcache) |
| 576 | { |
| 577 | CORE_ADDR bp_slot; |
| 578 | |
| 579 | /* Reserve enough room on the stack for our breakpoint instruction. */ |
| 580 | bp_slot = sp - 4; |
| 581 | /* Store the address of that breakpoint. */ |
| 582 | *bp_addr = bp_slot; |
| 583 | /* keeping the stack aligned. */ |
| 584 | sp = or1k_frame_align (gdbarch, bp_slot); |
| 585 | /* The call starts at the callee's entry point. */ |
| 586 | *real_pc = function; |
| 587 | |
| 588 | return sp; |
| 589 | } |
| 590 | |
| 591 | /* Implement the push_dummy_call gdbarch method. */ |
| 592 | |
| 593 | static CORE_ADDR |
| 594 | or1k_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 595 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 596 | int nargs, struct value **args, CORE_ADDR sp, |
| 597 | function_call_return_method return_method, |
| 598 | CORE_ADDR struct_addr) |
| 599 | { |
| 600 | |
| 601 | int argreg; |
| 602 | int argnum; |
| 603 | int first_stack_arg; |
| 604 | int stack_offset = 0; |
| 605 | int heap_offset = 0; |
| 606 | CORE_ADDR heap_sp = sp - 128; |
| 607 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 608 | int bpa = (gdbarch_tdep (gdbarch))->bytes_per_address; |
| 609 | int bpw = (gdbarch_tdep (gdbarch))->bytes_per_word; |
| 610 | struct type *func_type = value_type (function); |
| 611 | |
| 612 | /* Return address */ |
| 613 | regcache_cooked_write_unsigned (regcache, OR1K_LR_REGNUM, bp_addr); |
| 614 | |
| 615 | /* Register for the next argument. */ |
| 616 | argreg = OR1K_FIRST_ARG_REGNUM; |
| 617 | |
| 618 | /* Location for a returned structure. This is passed as a silent first |
| 619 | argument. */ |
| 620 | if (return_method == return_method_struct) |
| 621 | { |
| 622 | regcache_cooked_write_unsigned (regcache, OR1K_FIRST_ARG_REGNUM, |
| 623 | struct_addr); |
| 624 | argreg++; |
| 625 | } |
| 626 | |
| 627 | /* Put as many args as possible in registers. */ |
| 628 | for (argnum = 0; argnum < nargs; argnum++) |
| 629 | { |
| 630 | const gdb_byte *val; |
| 631 | gdb_byte valbuf[sizeof (ULONGEST)]; |
| 632 | |
| 633 | struct value *arg = args[argnum]; |
| 634 | struct type *arg_type = check_typedef (value_type (arg)); |
| 635 | int len = TYPE_LENGTH (arg_type); |
| 636 | enum type_code typecode = TYPE_CODE (arg_type); |
| 637 | |
| 638 | if (TYPE_VARARGS (func_type) && argnum >= TYPE_NFIELDS (func_type)) |
| 639 | break; /* end or regular args, varargs go to stack. */ |
| 640 | |
| 641 | /* Extract the value, either a reference or the data. */ |
| 642 | if ((TYPE_CODE_STRUCT == typecode) || (TYPE_CODE_UNION == typecode) |
| 643 | || (len > bpw * 2)) |
| 644 | { |
| 645 | CORE_ADDR valaddr = value_address (arg); |
| 646 | |
| 647 | /* If the arg is fabricated (i.e. 3*i, instead of i) valaddr is |
| 648 | undefined. */ |
| 649 | if (valaddr == 0) |
| 650 | { |
| 651 | /* The argument needs to be copied into the target space. |
| 652 | Since the bottom of the stack is reserved for function |
| 653 | arguments we store this at the these at the top growing |
| 654 | down. */ |
| 655 | heap_offset += align_up (len, bpw); |
| 656 | valaddr = heap_sp + heap_offset; |
| 657 | |
| 658 | write_memory (valaddr, value_contents (arg), len); |
| 659 | } |
| 660 | |
| 661 | /* The ABI passes all structures by reference, so get its |
| 662 | address. */ |
| 663 | store_unsigned_integer (valbuf, bpa, byte_order, valaddr); |
| 664 | len = bpa; |
| 665 | val = valbuf; |
| 666 | } |
| 667 | else |
| 668 | { |
| 669 | /* Everything else, we just get the value. */ |
| 670 | val = value_contents (arg); |
| 671 | } |
| 672 | |
| 673 | /* Stick the value in a register. */ |
| 674 | if (len > bpw) |
| 675 | { |
| 676 | /* Big scalars use two registers, but need NOT be pair aligned. */ |
| 677 | |
| 678 | if (argreg <= (OR1K_LAST_ARG_REGNUM - 1)) |
| 679 | { |
| 680 | ULONGEST regval = extract_unsigned_integer (val, len, |
| 681 | byte_order); |
| 682 | |
| 683 | unsigned int bits_per_word = bpw * 8; |
| 684 | ULONGEST mask = (((ULONGEST) 1) << bits_per_word) - 1; |
| 685 | ULONGEST lo = regval & mask; |
| 686 | ULONGEST hi = regval >> bits_per_word; |
| 687 | |
| 688 | regcache_cooked_write_unsigned (regcache, argreg, hi); |
| 689 | regcache_cooked_write_unsigned (regcache, argreg + 1, lo); |
| 690 | argreg += 2; |
| 691 | } |
| 692 | else |
| 693 | { |
| 694 | /* Run out of regs */ |
| 695 | break; |
| 696 | } |
| 697 | } |
| 698 | else if (argreg <= OR1K_LAST_ARG_REGNUM) |
| 699 | { |
| 700 | /* Smaller scalars fit in a single register. */ |
| 701 | regcache_cooked_write_unsigned |
| 702 | (regcache, argreg, extract_unsigned_integer (val, len, |
| 703 | byte_order)); |
| 704 | argreg++; |
| 705 | } |
| 706 | else |
| 707 | { |
| 708 | /* Ran out of regs. */ |
| 709 | break; |
| 710 | } |
| 711 | } |
| 712 | |
| 713 | first_stack_arg = argnum; |
| 714 | |
| 715 | /* If we get here with argnum < nargs, then arguments remain to be |
| 716 | placed on the stack. This is tricky, since they must be pushed in |
| 717 | reverse order and the stack in the end must be aligned. The only |
| 718 | solution is to do it in two stages, the first to compute the stack |
| 719 | size, the second to save the args. */ |
| 720 | |
| 721 | for (argnum = first_stack_arg; argnum < nargs; argnum++) |
| 722 | { |
| 723 | struct value *arg = args[argnum]; |
| 724 | struct type *arg_type = check_typedef (value_type (arg)); |
| 725 | int len = TYPE_LENGTH (arg_type); |
| 726 | enum type_code typecode = TYPE_CODE (arg_type); |
| 727 | |
| 728 | if ((TYPE_CODE_STRUCT == typecode) || (TYPE_CODE_UNION == typecode) |
| 729 | || (len > bpw * 2)) |
| 730 | { |
| 731 | /* Structures are passed as addresses. */ |
| 732 | sp -= bpa; |
| 733 | } |
| 734 | else |
| 735 | { |
| 736 | /* Big scalars use more than one word. Code here allows for |
| 737 | future quad-word entities (e.g. long double.) */ |
| 738 | sp -= align_up (len, bpw); |
| 739 | } |
| 740 | |
| 741 | /* Ensure our dummy heap doesn't touch the stack, this could only |
| 742 | happen if we have many arguments including fabricated arguments. */ |
| 743 | gdb_assert (heap_offset == 0 || ((heap_sp + heap_offset) < sp)); |
| 744 | } |
| 745 | |
| 746 | sp = gdbarch_frame_align (gdbarch, sp); |
| 747 | stack_offset = 0; |
| 748 | |
| 749 | /* Push the remaining args on the stack. */ |
| 750 | for (argnum = first_stack_arg; argnum < nargs; argnum++) |
| 751 | { |
| 752 | const gdb_byte *val; |
| 753 | gdb_byte valbuf[sizeof (ULONGEST)]; |
| 754 | |
| 755 | struct value *arg = args[argnum]; |
| 756 | struct type *arg_type = check_typedef (value_type (arg)); |
| 757 | int len = TYPE_LENGTH (arg_type); |
| 758 | enum type_code typecode = TYPE_CODE (arg_type); |
| 759 | /* The EABI passes structures that do not fit in a register by |
| 760 | reference. In all other cases, pass the structure by value. */ |
| 761 | if ((TYPE_CODE_STRUCT == typecode) || (TYPE_CODE_UNION == typecode) |
| 762 | || (len > bpw * 2)) |
| 763 | { |
| 764 | store_unsigned_integer (valbuf, bpa, byte_order, |
| 765 | value_address (arg)); |
| 766 | len = bpa; |
| 767 | val = valbuf; |
| 768 | } |
| 769 | else |
| 770 | val = value_contents (arg); |
| 771 | |
| 772 | while (len > 0) |
| 773 | { |
| 774 | int partial_len = (len < bpw ? len : bpw); |
| 775 | |
| 776 | write_memory (sp + stack_offset, val, partial_len); |
| 777 | stack_offset += align_up (partial_len, bpw); |
| 778 | len -= partial_len; |
| 779 | val += partial_len; |
| 780 | } |
| 781 | } |
| 782 | |
| 783 | /* Save the updated stack pointer. */ |
| 784 | regcache_cooked_write_unsigned (regcache, OR1K_SP_REGNUM, sp); |
| 785 | |
| 786 | if (heap_offset > 0) |
| 787 | sp = heap_sp; |
| 788 | |
| 789 | return sp; |
| 790 | } |
| 791 | |
| 792 | \f |
| 793 | |
| 794 | /* Support functions for frame handling. */ |
| 795 | |
| 796 | /* Initialize a prologue cache |
| 797 | |
| 798 | We build a cache, saying where registers of the prev frame can be found |
| 799 | from the data so far set up in this this. |
| 800 | |
| 801 | We also compute a unique ID for this frame, based on the function start |
| 802 | address and the stack pointer (as it will be, even if it has yet to be |
| 803 | computed. |
| 804 | |
| 805 | STACK FORMAT |
| 806 | ============ |
| 807 | |
| 808 | The OR1K has a falling stack frame and a simple prolog. The Stack |
| 809 | pointer is R1 and the frame pointer R2. The frame base is therefore the |
| 810 | address held in R2 and the stack pointer (R1) is the frame base of the |
| 811 | next frame. |
| 812 | |
| 813 | l.addi r1,r1,-frame_size # SP now points to end of new stack frame |
| 814 | |
| 815 | The stack pointer may not be set up in a frameless function (e.g. a |
| 816 | simple leaf function). |
| 817 | |
| 818 | l.sw fp_loc(r1),r2 # old FP saved in new stack frame |
| 819 | l.addi r2,r1,frame_size # FP now points to base of new stack frame |
| 820 | |
| 821 | The frame pointer is not necessarily saved right at the end of the stack |
| 822 | frame - OR1K saves enough space for any args to called functions right |
| 823 | at the end (this is a difference from the Architecture Manual). |
| 824 | |
| 825 | l.sw lr_loc(r1),r9 # Link (return) address |
| 826 | |
| 827 | The link register is usually saved at fp_loc - 4. It may not be saved at |
| 828 | all in a leaf function. |
| 829 | |
| 830 | l.sw reg_loc(r1),ry # Save any callee saved regs |
| 831 | |
| 832 | The offsets x for the callee saved registers generally (always?) rise in |
| 833 | increments of 4, starting at fp_loc + 4. If the frame pointer is |
| 834 | omitted (an option to GCC), then it may not be saved at all. There may |
| 835 | be no callee saved registers. |
| 836 | |
| 837 | So in summary none of this may be present. However what is present |
| 838 | seems always to follow this fixed order, and occur before any |
| 839 | substantive code (it is possible for GCC to have more flexible |
| 840 | scheduling of the prologue, but this does not seem to occur for OR1K). |
| 841 | |
| 842 | ANALYSIS |
| 843 | ======== |
| 844 | |
| 845 | This prolog is used, even for -O3 with GCC. |
| 846 | |
| 847 | All this analysis must allow for the possibility that the PC is in the |
| 848 | middle of the prologue. Data in the cache should only be set up insofar |
| 849 | as it has been computed. |
| 850 | |
| 851 | HOWEVER. The frame_id must be created with the SP *as it will be* at |
| 852 | the end of the Prologue. Otherwise a recursive call, checking the frame |
| 853 | with the PC at the start address will end up with the same frame_id as |
| 854 | the caller. |
| 855 | |
| 856 | A suite of "helper" routines are used, allowing reuse for |
| 857 | or1k_skip_prologue(). |
| 858 | |
| 859 | Reportedly, this is only valid for frames less than 0x7fff in size. */ |
| 860 | |
| 861 | static struct trad_frame_cache * |
| 862 | or1k_frame_cache (struct frame_info *this_frame, void **prologue_cache) |
| 863 | { |
| 864 | struct gdbarch *gdbarch; |
| 865 | struct trad_frame_cache *info; |
| 866 | |
| 867 | CORE_ADDR this_pc; |
| 868 | CORE_ADDR this_sp; |
| 869 | CORE_ADDR this_sp_for_id; |
| 870 | int frame_size = 0; |
| 871 | |
| 872 | CORE_ADDR start_addr; |
| 873 | CORE_ADDR end_addr; |
| 874 | |
| 875 | if (or1k_debug) |
| 876 | fprintf_unfiltered (gdb_stdlog, |
| 877 | "or1k_frame_cache, prologue_cache = %s\n", |
| 878 | host_address_to_string (*prologue_cache)); |
| 879 | |
| 880 | /* Nothing to do if we already have this info. */ |
| 881 | if (NULL != *prologue_cache) |
| 882 | return (struct trad_frame_cache *) *prologue_cache; |
| 883 | |
| 884 | /* Get a new prologue cache and populate it with default values. */ |
| 885 | info = trad_frame_cache_zalloc (this_frame); |
| 886 | *prologue_cache = info; |
| 887 | |
| 888 | /* Find the start address of this function (which is a normal frame, even |
| 889 | if the next frame is the sentinel frame) and the end of its prologue. */ |
| 890 | this_pc = get_frame_pc (this_frame); |
| 891 | find_pc_partial_function (this_pc, NULL, &start_addr, NULL); |
| 892 | |
| 893 | /* Get the stack pointer if we have one (if there's no process executing |
| 894 | yet we won't have a frame. */ |
| 895 | this_sp = (NULL == this_frame) ? 0 : |
| 896 | get_frame_register_unsigned (this_frame, OR1K_SP_REGNUM); |
| 897 | |
| 898 | /* Return early if GDB couldn't find the function. */ |
| 899 | if (start_addr == 0) |
| 900 | { |
| 901 | if (or1k_debug) |
| 902 | fprintf_unfiltered (gdb_stdlog, " couldn't find function\n"); |
| 903 | |
| 904 | /* JPB: 28-Apr-11. This is a temporary patch, to get round GDB |
| 905 | crashing right at the beginning. Build the frame ID as best we |
| 906 | can. */ |
| 907 | trad_frame_set_id (info, frame_id_build (this_sp, this_pc)); |
| 908 | |
| 909 | return info; |
| 910 | } |
| 911 | |
| 912 | /* The default frame base of this frame (for ID purposes only - frame |
| 913 | base is an overloaded term) is its stack pointer. For now we use the |
| 914 | value of the SP register in this frame. However if the PC is in the |
| 915 | prologue of this frame, before the SP has been set up, then the value |
| 916 | will actually be that of the prev frame, and we'll need to adjust it |
| 917 | later. */ |
| 918 | trad_frame_set_this_base (info, this_sp); |
| 919 | this_sp_for_id = this_sp; |
| 920 | |
| 921 | /* The default is to find the PC of the previous frame in the link |
| 922 | register of this frame. This may be changed if we find the link |
| 923 | register was saved on the stack. */ |
| 924 | trad_frame_set_reg_realreg (info, OR1K_NPC_REGNUM, OR1K_LR_REGNUM); |
| 925 | |
| 926 | /* We should only examine code that is in the prologue. This is all code |
| 927 | up to (but not including) end_addr. We should only populate the cache |
| 928 | while the address is up to (but not including) the PC or end_addr, |
| 929 | whichever is first. */ |
| 930 | gdbarch = get_frame_arch (this_frame); |
| 931 | end_addr = or1k_skip_prologue (gdbarch, start_addr); |
| 932 | |
| 933 | /* All the following analysis only occurs if we are in the prologue and |
| 934 | have executed the code. Check we have a sane prologue size, and if |
| 935 | zero we are frameless and can give up here. */ |
| 936 | if (end_addr < start_addr) |
| 937 | error (_("end addr %s is less than start addr %s"), |
| 938 | paddress (gdbarch, end_addr), paddress (gdbarch, start_addr)); |
| 939 | |
| 940 | if (end_addr == start_addr) |
| 941 | frame_size = 0; |
| 942 | else |
| 943 | { |
| 944 | /* We have a frame. Look for the various components. */ |
| 945 | CORE_ADDR addr = start_addr; /* Where we have got to */ |
| 946 | uint32_t inst = or1k_fetch_instruction (gdbarch, addr); |
| 947 | |
| 948 | unsigned int ra, rb, rd; /* for instruction analysis */ |
| 949 | int simm; |
| 950 | |
| 951 | /* Look for the new stack pointer being set up. */ |
| 952 | if (or1k_analyse_l_addi (inst, &rd, &ra, &simm) |
| 953 | && (OR1K_SP_REGNUM == rd) && (OR1K_SP_REGNUM == ra) |
| 954 | && (simm < 0) && (0 == (simm % 4))) |
| 955 | { |
| 956 | frame_size = -simm; |
| 957 | addr += OR1K_INSTLEN; |
| 958 | inst = or1k_fetch_instruction (gdbarch, addr); |
| 959 | |
| 960 | /* If the PC has not actually got to this point, then the frame |
| 961 | base will be wrong, and we adjust it. |
| 962 | |
| 963 | If we are past this point, then we need to populate the stack |
| 964 | accordingly. */ |
| 965 | if (this_pc <= addr) |
| 966 | { |
| 967 | /* Only do if executing. */ |
| 968 | if (0 != this_sp) |
| 969 | { |
| 970 | this_sp_for_id = this_sp + frame_size; |
| 971 | trad_frame_set_this_base (info, this_sp_for_id); |
| 972 | } |
| 973 | } |
| 974 | else |
| 975 | { |
| 976 | /* We are past this point, so the stack pointer of the prev |
| 977 | frame is frame_size greater than the stack pointer of this |
| 978 | frame. */ |
| 979 | trad_frame_set_reg_value (info, OR1K_SP_REGNUM, |
| 980 | this_sp + frame_size); |
| 981 | } |
| 982 | } |
| 983 | |
| 984 | /* From now on we are only populating the cache, so we stop once we |
| 985 | get to either the end OR the current PC. */ |
| 986 | end_addr = (this_pc < end_addr) ? this_pc : end_addr; |
| 987 | |
| 988 | /* Look for the frame pointer being manipulated. */ |
| 989 | if ((addr < end_addr) |
| 990 | && or1k_analyse_l_sw (inst, &simm, &ra, &rb) |
| 991 | && (OR1K_SP_REGNUM == ra) && (OR1K_FP_REGNUM == rb) |
| 992 | && (simm >= 0) && (0 == (simm % 4))) |
| 993 | { |
| 994 | addr += OR1K_INSTLEN; |
| 995 | inst = or1k_fetch_instruction (gdbarch, addr); |
| 996 | |
| 997 | /* At this stage, we can find the frame pointer of the previous |
| 998 | frame on the stack of the current frame. */ |
| 999 | trad_frame_set_reg_addr (info, OR1K_FP_REGNUM, this_sp + simm); |
| 1000 | |
| 1001 | /* Look for the new frame pointer being set up. */ |
| 1002 | if ((addr < end_addr) |
| 1003 | && or1k_analyse_l_addi (inst, &rd, &ra, &simm) |
| 1004 | && (OR1K_FP_REGNUM == rd) && (OR1K_SP_REGNUM == ra) |
| 1005 | && (simm == frame_size)) |
| 1006 | { |
| 1007 | addr += OR1K_INSTLEN; |
| 1008 | inst = or1k_fetch_instruction (gdbarch, addr); |
| 1009 | |
| 1010 | /* If we have got this far, the stack pointer of the previous |
| 1011 | frame is the frame pointer of this frame. */ |
| 1012 | trad_frame_set_reg_realreg (info, OR1K_SP_REGNUM, |
| 1013 | OR1K_FP_REGNUM); |
| 1014 | } |
| 1015 | } |
| 1016 | |
| 1017 | /* Look for the link register being saved. */ |
| 1018 | if ((addr < end_addr) |
| 1019 | && or1k_analyse_l_sw (inst, &simm, &ra, &rb) |
| 1020 | && (OR1K_SP_REGNUM == ra) && (OR1K_LR_REGNUM == rb) |
| 1021 | && (simm >= 0) && (0 == (simm % 4))) |
| 1022 | { |
| 1023 | addr += OR1K_INSTLEN; |
| 1024 | inst = or1k_fetch_instruction (gdbarch, addr); |
| 1025 | |
| 1026 | /* If the link register is saved in the this frame, it holds the |
| 1027 | value of the PC in the previous frame. This overwrites the |
| 1028 | previous information about finding the PC in the link |
| 1029 | register. */ |
| 1030 | trad_frame_set_reg_addr (info, OR1K_NPC_REGNUM, this_sp + simm); |
| 1031 | } |
| 1032 | |
| 1033 | /* Look for arguments or callee-saved register being saved. The |
| 1034 | register must be one of the arguments (r3-r8) or the 10 callee |
| 1035 | saved registers (r10, r12, r14, r16, r18, r20, r22, r24, r26, r28, |
| 1036 | r30). The base register must be the FP (for the args) or the SP |
| 1037 | (for the callee_saved registers). */ |
| 1038 | while (addr < end_addr) |
| 1039 | { |
| 1040 | if (or1k_analyse_l_sw (inst, &simm, &ra, &rb) |
| 1041 | && (((OR1K_FP_REGNUM == ra) && or1k_is_arg_reg (rb)) |
| 1042 | || ((OR1K_SP_REGNUM == ra) |
| 1043 | && or1k_is_callee_saved_reg (rb))) |
| 1044 | && (0 == (simm % 4))) |
| 1045 | { |
| 1046 | addr += OR1K_INSTLEN; |
| 1047 | inst = or1k_fetch_instruction (gdbarch, addr); |
| 1048 | |
| 1049 | /* The register in the previous frame can be found at this |
| 1050 | location in this frame. */ |
| 1051 | trad_frame_set_reg_addr (info, rb, this_sp + simm); |
| 1052 | } |
| 1053 | else |
| 1054 | break; /* Not a register save instruction. */ |
| 1055 | } |
| 1056 | } |
| 1057 | |
| 1058 | /* Build the frame ID */ |
| 1059 | trad_frame_set_id (info, frame_id_build (this_sp_for_id, start_addr)); |
| 1060 | |
| 1061 | if (or1k_debug) |
| 1062 | { |
| 1063 | fprintf_unfiltered (gdb_stdlog, " this_sp_for_id = %s\n", |
| 1064 | paddress (gdbarch, this_sp_for_id)); |
| 1065 | fprintf_unfiltered (gdb_stdlog, " start_addr = %s\n", |
| 1066 | paddress (gdbarch, start_addr)); |
| 1067 | } |
| 1068 | |
| 1069 | return info; |
| 1070 | } |
| 1071 | |
| 1072 | /* Implement the this_id function for the stub unwinder. */ |
| 1073 | |
| 1074 | static void |
| 1075 | or1k_frame_this_id (struct frame_info *this_frame, |
| 1076 | void **prologue_cache, struct frame_id *this_id) |
| 1077 | { |
| 1078 | struct trad_frame_cache *info = or1k_frame_cache (this_frame, |
| 1079 | prologue_cache); |
| 1080 | |
| 1081 | trad_frame_get_id (info, this_id); |
| 1082 | } |
| 1083 | |
| 1084 | /* Implement the prev_register function for the stub unwinder. */ |
| 1085 | |
| 1086 | static struct value * |
| 1087 | or1k_frame_prev_register (struct frame_info *this_frame, |
| 1088 | void **prologue_cache, int regnum) |
| 1089 | { |
| 1090 | struct trad_frame_cache *info = or1k_frame_cache (this_frame, |
| 1091 | prologue_cache); |
| 1092 | |
| 1093 | return trad_frame_get_register (info, this_frame, regnum); |
| 1094 | } |
| 1095 | |
| 1096 | /* Data structures for the normal prologue-analysis-based unwinder. */ |
| 1097 | |
| 1098 | static const struct frame_unwind or1k_frame_unwind = { |
| 1099 | NORMAL_FRAME, |
| 1100 | default_frame_unwind_stop_reason, |
| 1101 | or1k_frame_this_id, |
| 1102 | or1k_frame_prev_register, |
| 1103 | NULL, |
| 1104 | default_frame_sniffer, |
| 1105 | NULL, |
| 1106 | }; |
| 1107 | |
| 1108 | /* Architecture initialization for OpenRISC 1000. */ |
| 1109 | |
| 1110 | static struct gdbarch * |
| 1111 | or1k_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 1112 | { |
| 1113 | struct gdbarch *gdbarch; |
| 1114 | struct gdbarch_tdep *tdep; |
| 1115 | const struct bfd_arch_info *binfo; |
| 1116 | struct tdesc_arch_data *tdesc_data = NULL; |
| 1117 | const struct target_desc *tdesc = info.target_desc; |
| 1118 | |
| 1119 | /* Find a candidate among the list of pre-declared architectures. */ |
| 1120 | arches = gdbarch_list_lookup_by_info (arches, &info); |
| 1121 | if (NULL != arches) |
| 1122 | return arches->gdbarch; |
| 1123 | |
| 1124 | /* None found, create a new architecture from the information |
| 1125 | provided. Can't initialize all the target dependencies until we |
| 1126 | actually know which target we are talking to, but put in some defaults |
| 1127 | for now. */ |
| 1128 | binfo = info.bfd_arch_info; |
| 1129 | tdep = XCNEW (struct gdbarch_tdep); |
| 1130 | tdep->bytes_per_word = binfo->bits_per_word / binfo->bits_per_byte; |
| 1131 | tdep->bytes_per_address = binfo->bits_per_address / binfo->bits_per_byte; |
| 1132 | gdbarch = gdbarch_alloc (&info, tdep); |
| 1133 | |
| 1134 | /* Target data types */ |
| 1135 | set_gdbarch_short_bit (gdbarch, 16); |
| 1136 | set_gdbarch_int_bit (gdbarch, 32); |
| 1137 | set_gdbarch_long_bit (gdbarch, 32); |
| 1138 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 1139 | set_gdbarch_float_bit (gdbarch, 32); |
| 1140 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
| 1141 | set_gdbarch_double_bit (gdbarch, 64); |
| 1142 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); |
| 1143 | set_gdbarch_long_double_bit (gdbarch, 64); |
| 1144 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); |
| 1145 | set_gdbarch_ptr_bit (gdbarch, binfo->bits_per_address); |
| 1146 | set_gdbarch_addr_bit (gdbarch, binfo->bits_per_address); |
| 1147 | set_gdbarch_char_signed (gdbarch, 1); |
| 1148 | |
| 1149 | /* Information about the target architecture */ |
| 1150 | set_gdbarch_return_value (gdbarch, or1k_return_value); |
| 1151 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
| 1152 | or1k_breakpoint::kind_from_pc); |
| 1153 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, |
| 1154 | or1k_breakpoint::bp_from_kind); |
| 1155 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
| 1156 | |
| 1157 | /* Register architecture */ |
| 1158 | set_gdbarch_num_regs (gdbarch, OR1K_NUM_REGS); |
| 1159 | set_gdbarch_num_pseudo_regs (gdbarch, OR1K_NUM_PSEUDO_REGS); |
| 1160 | set_gdbarch_sp_regnum (gdbarch, OR1K_SP_REGNUM); |
| 1161 | set_gdbarch_pc_regnum (gdbarch, OR1K_NPC_REGNUM); |
| 1162 | set_gdbarch_ps_regnum (gdbarch, OR1K_SR_REGNUM); |
| 1163 | set_gdbarch_deprecated_fp_regnum (gdbarch, OR1K_FP_REGNUM); |
| 1164 | |
| 1165 | /* Functions to analyse frames */ |
| 1166 | set_gdbarch_skip_prologue (gdbarch, or1k_skip_prologue); |
| 1167 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 1168 | set_gdbarch_frame_align (gdbarch, or1k_frame_align); |
| 1169 | set_gdbarch_frame_red_zone_size (gdbarch, OR1K_FRAME_RED_ZONE_SIZE); |
| 1170 | |
| 1171 | /* Functions to access frame data */ |
| 1172 | set_gdbarch_unwind_pc (gdbarch, or1k_unwind_pc); |
| 1173 | set_gdbarch_unwind_sp (gdbarch, or1k_unwind_sp); |
| 1174 | |
| 1175 | /* Functions handling dummy frames */ |
| 1176 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
| 1177 | set_gdbarch_push_dummy_code (gdbarch, or1k_push_dummy_code); |
| 1178 | set_gdbarch_push_dummy_call (gdbarch, or1k_push_dummy_call); |
| 1179 | |
| 1180 | /* Frame unwinders. Use DWARF debug info if available, otherwise use our |
| 1181 | own unwinder. */ |
| 1182 | dwarf2_append_unwinders (gdbarch); |
| 1183 | frame_unwind_append_unwinder (gdbarch, &or1k_frame_unwind); |
| 1184 | |
| 1185 | /* Get a CGEN CPU descriptor for this architecture. */ |
| 1186 | { |
| 1187 | |
| 1188 | const char *mach_name = binfo->printable_name; |
| 1189 | enum cgen_endian endian = (info.byte_order == BFD_ENDIAN_BIG |
| 1190 | ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); |
| 1191 | |
| 1192 | tdep->gdb_cgen_cpu_desc = |
| 1193 | or1k_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, |
| 1194 | CGEN_CPU_OPEN_ENDIAN, endian, CGEN_CPU_OPEN_END); |
| 1195 | |
| 1196 | or1k_cgen_init_asm (tdep->gdb_cgen_cpu_desc); |
| 1197 | } |
| 1198 | |
| 1199 | /* If this mach has a delay slot. */ |
| 1200 | if (binfo->mach == bfd_mach_or1k) |
| 1201 | set_gdbarch_single_step_through_delay (gdbarch, |
| 1202 | or1k_single_step_through_delay); |
| 1203 | |
| 1204 | if (!tdesc_has_registers (info.target_desc)) |
| 1205 | /* Pick a default target description. */ |
| 1206 | tdesc = tdesc_or1k; |
| 1207 | |
| 1208 | /* Check any target description for validity. */ |
| 1209 | if (tdesc_has_registers (tdesc)) |
| 1210 | { |
| 1211 | const struct tdesc_feature *feature; |
| 1212 | int valid_p; |
| 1213 | int i; |
| 1214 | |
| 1215 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.or1k.group0"); |
| 1216 | if (feature == NULL) |
| 1217 | return NULL; |
| 1218 | |
| 1219 | tdesc_data = tdesc_data_alloc (); |
| 1220 | |
| 1221 | valid_p = 1; |
| 1222 | |
| 1223 | for (i = 0; i < OR1K_NUM_REGS; i++) |
| 1224 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, |
| 1225 | or1k_reg_names[i]); |
| 1226 | |
| 1227 | if (!valid_p) |
| 1228 | { |
| 1229 | tdesc_data_cleanup (tdesc_data); |
| 1230 | return NULL; |
| 1231 | } |
| 1232 | } |
| 1233 | |
| 1234 | if (tdesc_data != NULL) |
| 1235 | { |
| 1236 | /* If we are using tdesc, register our own reggroups, otherwise we |
| 1237 | will used the defaults. */ |
| 1238 | reggroup_add (gdbarch, general_reggroup); |
| 1239 | reggroup_add (gdbarch, system_reggroup); |
| 1240 | reggroup_add (gdbarch, float_reggroup); |
| 1241 | reggroup_add (gdbarch, vector_reggroup); |
| 1242 | reggroup_add (gdbarch, all_reggroup); |
| 1243 | reggroup_add (gdbarch, save_reggroup); |
| 1244 | reggroup_add (gdbarch, restore_reggroup); |
| 1245 | |
| 1246 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
| 1247 | } |
| 1248 | |
| 1249 | /* Hook in ABI-specific overrides, if they have been registered. */ |
| 1250 | gdbarch_init_osabi (info, gdbarch); |
| 1251 | |
| 1252 | return gdbarch; |
| 1253 | } |
| 1254 | |
| 1255 | /* Dump the target specific data for this architecture. */ |
| 1256 | |
| 1257 | static void |
| 1258 | or1k_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
| 1259 | { |
| 1260 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1261 | |
| 1262 | if (NULL == tdep) |
| 1263 | return; /* Nothing to report */ |
| 1264 | |
| 1265 | fprintf_unfiltered (file, "or1k_dump_tdep: %d bytes per word\n", |
| 1266 | tdep->bytes_per_word); |
| 1267 | fprintf_unfiltered (file, "or1k_dump_tdep: %d bytes per address\n", |
| 1268 | tdep->bytes_per_address); |
| 1269 | } |
| 1270 | \f |
| 1271 | |
| 1272 | void _initialize_or1k_tdep (); |
| 1273 | void |
| 1274 | _initialize_or1k_tdep () |
| 1275 | { |
| 1276 | /* Register this architecture. */ |
| 1277 | gdbarch_register (bfd_arch_or1k, or1k_gdbarch_init, or1k_dump_tdep); |
| 1278 | |
| 1279 | initialize_tdesc_or1k (); |
| 1280 | |
| 1281 | /* Debugging flag. */ |
| 1282 | add_setshow_boolean_cmd ("or1k", class_maintenance, &or1k_debug, |
| 1283 | _("Set OpenRISC debugging."), |
| 1284 | _("Show OpenRISC debugging."), |
| 1285 | _("When on, OpenRISC specific debugging is enabled."), |
| 1286 | NULL, |
| 1287 | show_or1k_debug, |
| 1288 | &setdebuglist, &showdebuglist); |
| 1289 | } |