| 1 | /* PPC GNU/Linux native support. |
| 2 | |
| 3 | Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, 2003, |
| 4 | 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. |
| 5 | |
| 6 | This file is part of GDB. |
| 7 | |
| 8 | This program is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 3 of the License, or |
| 11 | (at your option) any later version. |
| 12 | |
| 13 | This program is distributed in the hope that it will be useful, |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 20 | |
| 21 | #include "defs.h" |
| 22 | #include "gdb_string.h" |
| 23 | #include "frame.h" |
| 24 | #include "inferior.h" |
| 25 | #include "gdbcore.h" |
| 26 | #include "regcache.h" |
| 27 | #include "gdb_assert.h" |
| 28 | #include "target.h" |
| 29 | #include "linux-nat.h" |
| 30 | |
| 31 | #include <stdint.h> |
| 32 | #include <sys/types.h> |
| 33 | #include <sys/param.h> |
| 34 | #include <signal.h> |
| 35 | #include <sys/user.h> |
| 36 | #include <sys/ioctl.h> |
| 37 | #include "gdb_wait.h" |
| 38 | #include <fcntl.h> |
| 39 | #include <sys/procfs.h> |
| 40 | #include <sys/ptrace.h> |
| 41 | |
| 42 | /* Prototypes for supply_gregset etc. */ |
| 43 | #include "gregset.h" |
| 44 | #include "ppc-tdep.h" |
| 45 | #include "ppc-linux-tdep.h" |
| 46 | |
| 47 | /* Required when using the AUXV. */ |
| 48 | #include "elf/common.h" |
| 49 | #include "auxv.h" |
| 50 | |
| 51 | /* This sometimes isn't defined. */ |
| 52 | #ifndef PT_ORIG_R3 |
| 53 | #define PT_ORIG_R3 34 |
| 54 | #endif |
| 55 | #ifndef PT_TRAP |
| 56 | #define PT_TRAP 40 |
| 57 | #endif |
| 58 | |
| 59 | /* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>. |
| 60 | If they aren't, we can provide them ourselves (their values are fixed |
| 61 | because they are part of the kernel ABI). They are used in the AT_HWCAP |
| 62 | entry of the AUXV. */ |
| 63 | #ifndef PPC_FEATURE_BOOKE |
| 64 | #define PPC_FEATURE_BOOKE 0x00008000 |
| 65 | #endif |
| 66 | #ifndef PPC_FEATURE_ARCH_2_05 |
| 67 | #define PPC_FEATURE_ARCH_2_05 0x00001000 /* ISA 2.05 */ |
| 68 | #endif |
| 69 | |
| 70 | /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a |
| 71 | configure time check. Some older glibc's (for instance 2.2.1) |
| 72 | don't have a specific powerpc version of ptrace.h, and fall back on |
| 73 | a generic one. In such cases, sys/ptrace.h defines |
| 74 | PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that |
| 75 | ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and |
| 76 | PTRACE_SETVRREGS to be. This also makes a configury check pretty |
| 77 | much useless. */ |
| 78 | |
| 79 | /* These definitions should really come from the glibc header files, |
| 80 | but Glibc doesn't know about the vrregs yet. */ |
| 81 | #ifndef PTRACE_GETVRREGS |
| 82 | #define PTRACE_GETVRREGS 18 |
| 83 | #define PTRACE_SETVRREGS 19 |
| 84 | #endif |
| 85 | |
| 86 | /* PTRACE requests for POWER7 VSX registers. */ |
| 87 | #ifndef PTRACE_GETVSXREGS |
| 88 | #define PTRACE_GETVSXREGS 27 |
| 89 | #define PTRACE_SETVSXREGS 28 |
| 90 | #endif |
| 91 | |
| 92 | /* Similarly for the ptrace requests for getting / setting the SPE |
| 93 | registers (ev0 -- ev31, acc, and spefscr). See the description of |
| 94 | gdb_evrregset_t for details. */ |
| 95 | #ifndef PTRACE_GETEVRREGS |
| 96 | #define PTRACE_GETEVRREGS 20 |
| 97 | #define PTRACE_SETEVRREGS 21 |
| 98 | #endif |
| 99 | |
| 100 | /* Similarly for the hardware watchpoint support. */ |
| 101 | #ifndef PTRACE_GET_DEBUGREG |
| 102 | #define PTRACE_GET_DEBUGREG 25 |
| 103 | #endif |
| 104 | #ifndef PTRACE_SET_DEBUGREG |
| 105 | #define PTRACE_SET_DEBUGREG 26 |
| 106 | #endif |
| 107 | #ifndef PTRACE_GETSIGINFO |
| 108 | #define PTRACE_GETSIGINFO 0x4202 |
| 109 | #endif |
| 110 | |
| 111 | /* This oddity is because the Linux kernel defines elf_vrregset_t as |
| 112 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. |
| 113 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return |
| 114 | the vrsave as an extra 4 bytes at the end. I opted for creating a |
| 115 | flat array of chars, so that it is easier to manipulate for gdb. |
| 116 | |
| 117 | There are 32 vector registers 16 bytes longs, plus a VSCR register |
| 118 | which is only 4 bytes long, but is fetched as a 16 bytes |
| 119 | quantity. Up to here we have the elf_vrregset_t structure. |
| 120 | Appended to this there is space for the VRSAVE register: 4 bytes. |
| 121 | Even though this vrsave register is not included in the regset |
| 122 | typedef, it is handled by the ptrace requests. |
| 123 | |
| 124 | Note that GNU/Linux doesn't support little endian PPC hardware, |
| 125 | therefore the offset at which the real value of the VSCR register |
| 126 | is located will be always 12 bytes. |
| 127 | |
| 128 | The layout is like this (where x is the actual value of the vscr reg): */ |
| 129 | |
| 130 | /* *INDENT-OFF* */ |
| 131 | /* |
| 132 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| |
| 133 | <-------> <-------><-------><-> |
| 134 | VR0 VR31 VSCR VRSAVE |
| 135 | */ |
| 136 | /* *INDENT-ON* */ |
| 137 | |
| 138 | #define SIZEOF_VRREGS 33*16+4 |
| 139 | |
| 140 | typedef char gdb_vrregset_t[SIZEOF_VRREGS]; |
| 141 | |
| 142 | /* This is the layout of the POWER7 VSX registers and the way they overlap |
| 143 | with the existing FPR and VMX registers. |
| 144 | |
| 145 | VSR doubleword 0 VSR doubleword 1 |
| 146 | ---------------------------------------------------------------- |
| 147 | VSR[0] | FPR[0] | | |
| 148 | ---------------------------------------------------------------- |
| 149 | VSR[1] | FPR[1] | | |
| 150 | ---------------------------------------------------------------- |
| 151 | | ... | | |
| 152 | | ... | | |
| 153 | ---------------------------------------------------------------- |
| 154 | VSR[30] | FPR[30] | | |
| 155 | ---------------------------------------------------------------- |
| 156 | VSR[31] | FPR[31] | | |
| 157 | ---------------------------------------------------------------- |
| 158 | VSR[32] | VR[0] | |
| 159 | ---------------------------------------------------------------- |
| 160 | VSR[33] | VR[1] | |
| 161 | ---------------------------------------------------------------- |
| 162 | | ... | |
| 163 | | ... | |
| 164 | ---------------------------------------------------------------- |
| 165 | VSR[62] | VR[30] | |
| 166 | ---------------------------------------------------------------- |
| 167 | VSR[63] | VR[31] | |
| 168 | ---------------------------------------------------------------- |
| 169 | |
| 170 | VSX has 64 128bit registers. The first 32 registers overlap with |
| 171 | the FP registers (doubleword 0) and hence extend them with additional |
| 172 | 64 bits (doubleword 1). The other 32 regs overlap with the VMX |
| 173 | registers. */ |
| 174 | #define SIZEOF_VSXREGS 32*8 |
| 175 | |
| 176 | typedef char gdb_vsxregset_t[SIZEOF_VSXREGS]; |
| 177 | |
| 178 | /* On PPC processors that support the the Signal Processing Extension |
| 179 | (SPE) APU, the general-purpose registers are 64 bits long. |
| 180 | However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER |
| 181 | ptrace calls only access the lower half of each register, to allow |
| 182 | them to behave the same way they do on non-SPE systems. There's a |
| 183 | separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that |
| 184 | read and write the top halves of all the general-purpose registers |
| 185 | at once, along with some SPE-specific registers. |
| 186 | |
| 187 | GDB itself continues to claim the general-purpose registers are 32 |
| 188 | bits long. It has unnamed raw registers that hold the upper halves |
| 189 | of the gprs, and the the full 64-bit SIMD views of the registers, |
| 190 | 'ev0' -- 'ev31', are pseudo-registers that splice the top and |
| 191 | bottom halves together. |
| 192 | |
| 193 | This is the structure filled in by PTRACE_GETEVRREGS and written to |
| 194 | the inferior's registers by PTRACE_SETEVRREGS. */ |
| 195 | struct gdb_evrregset_t |
| 196 | { |
| 197 | unsigned long evr[32]; |
| 198 | unsigned long long acc; |
| 199 | unsigned long spefscr; |
| 200 | }; |
| 201 | |
| 202 | /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and |
| 203 | PTRACE_SETVSXREGS requests, for reading and writing the VSX |
| 204 | POWER7 registers 0 through 31. Zero if we've tried one of them and |
| 205 | gotten an error. Note that VSX registers 32 through 63 overlap |
| 206 | with VR registers 0 through 31. */ |
| 207 | int have_ptrace_getsetvsxregs = 1; |
| 208 | |
| 209 | /* Non-zero if our kernel may support the PTRACE_GETVRREGS and |
| 210 | PTRACE_SETVRREGS requests, for reading and writing the Altivec |
| 211 | registers. Zero if we've tried one of them and gotten an |
| 212 | error. */ |
| 213 | int have_ptrace_getvrregs = 1; |
| 214 | |
| 215 | /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and |
| 216 | PTRACE_SETEVRREGS requests, for reading and writing the SPE |
| 217 | registers. Zero if we've tried one of them and gotten an |
| 218 | error. */ |
| 219 | int have_ptrace_getsetevrregs = 1; |
| 220 | |
| 221 | /* *INDENT-OFF* */ |
| 222 | /* registers layout, as presented by the ptrace interface: |
| 223 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, |
| 224 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, |
| 225 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, |
| 226 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, |
| 227 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, |
| 228 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, |
| 229 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, |
| 230 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, |
| 231 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ |
| 232 | /* *INDENT_ON * */ |
| 233 | |
| 234 | static int |
| 235 | ppc_register_u_addr (struct gdbarch *gdbarch, int regno) |
| 236 | { |
| 237 | int u_addr = -1; |
| 238 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 239 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
| 240 | interface, and not the wordsize of the program's ABI. */ |
| 241 | int wordsize = sizeof (long); |
| 242 | |
| 243 | /* General purpose registers occupy 1 slot each in the buffer */ |
| 244 | if (regno >= tdep->ppc_gp0_regnum |
| 245 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) |
| 246 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
| 247 | |
| 248 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
| 249 | ptrace interfaces. Thus, two slots each in 32-bit interface, one |
| 250 | slot each in 64-bit interface. */ |
| 251 | if (tdep->ppc_fp0_regnum >= 0 |
| 252 | && regno >= tdep->ppc_fp0_regnum |
| 253 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
| 254 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); |
| 255 | |
| 256 | /* UISA special purpose registers: 1 slot each */ |
| 257 | if (regno == gdbarch_pc_regnum (gdbarch)) |
| 258 | u_addr = PT_NIP * wordsize; |
| 259 | if (regno == tdep->ppc_lr_regnum) |
| 260 | u_addr = PT_LNK * wordsize; |
| 261 | if (regno == tdep->ppc_cr_regnum) |
| 262 | u_addr = PT_CCR * wordsize; |
| 263 | if (regno == tdep->ppc_xer_regnum) |
| 264 | u_addr = PT_XER * wordsize; |
| 265 | if (regno == tdep->ppc_ctr_regnum) |
| 266 | u_addr = PT_CTR * wordsize; |
| 267 | #ifdef PT_MQ |
| 268 | if (regno == tdep->ppc_mq_regnum) |
| 269 | u_addr = PT_MQ * wordsize; |
| 270 | #endif |
| 271 | if (regno == tdep->ppc_ps_regnum) |
| 272 | u_addr = PT_MSR * wordsize; |
| 273 | if (regno == PPC_ORIG_R3_REGNUM) |
| 274 | u_addr = PT_ORIG_R3 * wordsize; |
| 275 | if (regno == PPC_TRAP_REGNUM) |
| 276 | u_addr = PT_TRAP * wordsize; |
| 277 | if (tdep->ppc_fpscr_regnum >= 0 |
| 278 | && regno == tdep->ppc_fpscr_regnum) |
| 279 | { |
| 280 | /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the |
| 281 | kernel headers incorrectly contained the 32-bit definition of |
| 282 | PT_FPSCR. For the 32-bit definition, floating-point |
| 283 | registers occupy two 32-bit "slots", and the FPSCR lives in |
| 284 | the second half of such a slot-pair (hence +1). For 64-bit, |
| 285 | the FPSCR instead occupies the full 64-bit 2-word-slot and |
| 286 | hence no adjustment is necessary. Hack around this. */ |
| 287 | if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) |
| 288 | u_addr = (48 + 32) * wordsize; |
| 289 | /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit |
| 290 | slot and not just its second word. The PT_FPSCR supplied when |
| 291 | GDB is compiled as a 32-bit app doesn't reflect this. */ |
| 292 | else if (wordsize == 4 && register_size (gdbarch, regno) == 8 |
| 293 | && PT_FPSCR == (48 + 2*32 + 1)) |
| 294 | u_addr = (48 + 2*32) * wordsize; |
| 295 | else |
| 296 | u_addr = PT_FPSCR * wordsize; |
| 297 | } |
| 298 | return u_addr; |
| 299 | } |
| 300 | |
| 301 | /* The Linux kernel ptrace interface for POWER7 VSX registers uses the |
| 302 | registers set mechanism, as opposed to the interface for all the |
| 303 | other registers, that stores/fetches each register individually. */ |
| 304 | static void |
| 305 | fetch_vsx_register (struct regcache *regcache, int tid, int regno) |
| 306 | { |
| 307 | int ret; |
| 308 | gdb_vsxregset_t regs; |
| 309 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 310 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 311 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); |
| 312 | |
| 313 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); |
| 314 | if (ret < 0) |
| 315 | { |
| 316 | if (errno == EIO) |
| 317 | { |
| 318 | have_ptrace_getsetvsxregs = 0; |
| 319 | return; |
| 320 | } |
| 321 | perror_with_name (_("Unable to fetch VSX register")); |
| 322 | } |
| 323 | |
| 324 | regcache_raw_supply (regcache, regno, |
| 325 | regs + (regno - tdep->ppc_vsr0_upper_regnum) |
| 326 | * vsxregsize); |
| 327 | } |
| 328 | |
| 329 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
| 330 | registers set mechanism, as opposed to the interface for all the |
| 331 | other registers, that stores/fetches each register individually. */ |
| 332 | static void |
| 333 | fetch_altivec_register (struct regcache *regcache, int tid, int regno) |
| 334 | { |
| 335 | int ret; |
| 336 | int offset = 0; |
| 337 | gdb_vrregset_t regs; |
| 338 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 339 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 340 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
| 341 | |
| 342 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
| 343 | if (ret < 0) |
| 344 | { |
| 345 | if (errno == EIO) |
| 346 | { |
| 347 | have_ptrace_getvrregs = 0; |
| 348 | return; |
| 349 | } |
| 350 | perror_with_name (_("Unable to fetch AltiVec register")); |
| 351 | } |
| 352 | |
| 353 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes |
| 354 | long on the hardware. We deal only with the lower 4 bytes of the |
| 355 | vector. VRSAVE is at the end of the array in a 4 bytes slot, so |
| 356 | there is no need to define an offset for it. */ |
| 357 | if (regno == (tdep->ppc_vrsave_regnum - 1)) |
| 358 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
| 359 | |
| 360 | regcache_raw_supply (regcache, regno, |
| 361 | regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); |
| 362 | } |
| 363 | |
| 364 | /* Fetch the top 32 bits of TID's general-purpose registers and the |
| 365 | SPE-specific registers, and place the results in EVRREGSET. If we |
| 366 | don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with |
| 367 | zeros. |
| 368 | |
| 369 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and |
| 370 | PTRACE_SETEVRREGS requests are supported is isolated here, and in |
| 371 | set_spe_registers. */ |
| 372 | static void |
| 373 | get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) |
| 374 | { |
| 375 | if (have_ptrace_getsetevrregs) |
| 376 | { |
| 377 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) |
| 378 | return; |
| 379 | else |
| 380 | { |
| 381 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported; |
| 382 | we just return zeros. */ |
| 383 | if (errno == EIO) |
| 384 | have_ptrace_getsetevrregs = 0; |
| 385 | else |
| 386 | /* Anything else needs to be reported. */ |
| 387 | perror_with_name (_("Unable to fetch SPE registers")); |
| 388 | } |
| 389 | } |
| 390 | |
| 391 | memset (evrregset, 0, sizeof (*evrregset)); |
| 392 | } |
| 393 | |
| 394 | /* Supply values from TID for SPE-specific raw registers: the upper |
| 395 | halves of the GPRs, the accumulator, and the spefscr. REGNO must |
| 396 | be the number of an upper half register, acc, spefscr, or -1 to |
| 397 | supply the values of all registers. */ |
| 398 | static void |
| 399 | fetch_spe_register (struct regcache *regcache, int tid, int regno) |
| 400 | { |
| 401 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 402 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 403 | struct gdb_evrregset_t evrregs; |
| 404 | |
| 405 | gdb_assert (sizeof (evrregs.evr[0]) |
| 406 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
| 407 | gdb_assert (sizeof (evrregs.acc) |
| 408 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
| 409 | gdb_assert (sizeof (evrregs.spefscr) |
| 410 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
| 411 | |
| 412 | get_spe_registers (tid, &evrregs); |
| 413 | |
| 414 | if (regno == -1) |
| 415 | { |
| 416 | int i; |
| 417 | |
| 418 | for (i = 0; i < ppc_num_gprs; i++) |
| 419 | regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i, |
| 420 | &evrregs.evr[i]); |
| 421 | } |
| 422 | else if (tdep->ppc_ev0_upper_regnum <= regno |
| 423 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) |
| 424 | regcache_raw_supply (regcache, regno, |
| 425 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
| 426 | |
| 427 | if (regno == -1 |
| 428 | || regno == tdep->ppc_acc_regnum) |
| 429 | regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc); |
| 430 | |
| 431 | if (regno == -1 |
| 432 | || regno == tdep->ppc_spefscr_regnum) |
| 433 | regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum, |
| 434 | &evrregs.spefscr); |
| 435 | } |
| 436 | |
| 437 | static void |
| 438 | fetch_register (struct regcache *regcache, int tid, int regno) |
| 439 | { |
| 440 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 441 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 442 | /* This isn't really an address. But ptrace thinks of it as one. */ |
| 443 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
| 444 | int bytes_transferred; |
| 445 | unsigned int offset; /* Offset of registers within the u area. */ |
| 446 | char buf[MAX_REGISTER_SIZE]; |
| 447 | |
| 448 | if (altivec_register_p (gdbarch, regno)) |
| 449 | { |
| 450 | /* If this is the first time through, or if it is not the first |
| 451 | time through, and we have comfirmed that there is kernel |
| 452 | support for such a ptrace request, then go and fetch the |
| 453 | register. */ |
| 454 | if (have_ptrace_getvrregs) |
| 455 | { |
| 456 | fetch_altivec_register (regcache, tid, regno); |
| 457 | return; |
| 458 | } |
| 459 | /* If we have discovered that there is no ptrace support for |
| 460 | AltiVec registers, fall through and return zeroes, because |
| 461 | regaddr will be -1 in this case. */ |
| 462 | } |
| 463 | if (vsx_register_p (gdbarch, regno)) |
| 464 | { |
| 465 | if (have_ptrace_getsetvsxregs) |
| 466 | { |
| 467 | fetch_vsx_register (regcache, tid, regno); |
| 468 | return; |
| 469 | } |
| 470 | } |
| 471 | else if (spe_register_p (gdbarch, regno)) |
| 472 | { |
| 473 | fetch_spe_register (regcache, tid, regno); |
| 474 | return; |
| 475 | } |
| 476 | |
| 477 | if (regaddr == -1) |
| 478 | { |
| 479 | memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ |
| 480 | regcache_raw_supply (regcache, regno, buf); |
| 481 | return; |
| 482 | } |
| 483 | |
| 484 | /* Read the raw register using sizeof(long) sized chunks. On a |
| 485 | 32-bit platform, 64-bit floating-point registers will require two |
| 486 | transfers. */ |
| 487 | for (bytes_transferred = 0; |
| 488 | bytes_transferred < register_size (gdbarch, regno); |
| 489 | bytes_transferred += sizeof (long)) |
| 490 | { |
| 491 | errno = 0; |
| 492 | *(long *) &buf[bytes_transferred] |
| 493 | = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); |
| 494 | regaddr += sizeof (long); |
| 495 | if (errno != 0) |
| 496 | { |
| 497 | char message[128]; |
| 498 | sprintf (message, "reading register %s (#%d)", |
| 499 | gdbarch_register_name (gdbarch, regno), regno); |
| 500 | perror_with_name (message); |
| 501 | } |
| 502 | } |
| 503 | |
| 504 | /* Now supply the register. Keep in mind that the regcache's idea |
| 505 | of the register's size may not be a multiple of sizeof |
| 506 | (long). */ |
| 507 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
| 508 | { |
| 509 | /* Little-endian values are always found at the left end of the |
| 510 | bytes transferred. */ |
| 511 | regcache_raw_supply (regcache, regno, buf); |
| 512 | } |
| 513 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 514 | { |
| 515 | /* Big-endian values are found at the right end of the bytes |
| 516 | transferred. */ |
| 517 | size_t padding = (bytes_transferred - register_size (gdbarch, regno)); |
| 518 | regcache_raw_supply (regcache, regno, buf + padding); |
| 519 | } |
| 520 | else |
| 521 | internal_error (__FILE__, __LINE__, |
| 522 | _("fetch_register: unexpected byte order: %d"), |
| 523 | gdbarch_byte_order (gdbarch)); |
| 524 | } |
| 525 | |
| 526 | static void |
| 527 | supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) |
| 528 | { |
| 529 | int i; |
| 530 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 531 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 532 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); |
| 533 | |
| 534 | for (i = 0; i < ppc_num_vshrs; i++) |
| 535 | { |
| 536 | regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i, |
| 537 | *vsxregsetp + i * vsxregsize); |
| 538 | } |
| 539 | } |
| 540 | |
| 541 | static void |
| 542 | supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
| 543 | { |
| 544 | int i; |
| 545 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 546 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 547 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
| 548 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
| 549 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
| 550 | |
| 551 | for (i = 0; i < num_of_vrregs; i++) |
| 552 | { |
| 553 | /* The last 2 registers of this set are only 32 bit long, not |
| 554 | 128. However an offset is necessary only for VSCR because it |
| 555 | occupies a whole vector, while VRSAVE occupies a full 4 bytes |
| 556 | slot. */ |
| 557 | if (i == (num_of_vrregs - 2)) |
| 558 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
| 559 | *vrregsetp + i * vrregsize + offset); |
| 560 | else |
| 561 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
| 562 | *vrregsetp + i * vrregsize); |
| 563 | } |
| 564 | } |
| 565 | |
| 566 | static void |
| 567 | fetch_vsx_registers (struct regcache *regcache, int tid) |
| 568 | { |
| 569 | int ret; |
| 570 | gdb_vsxregset_t regs; |
| 571 | |
| 572 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); |
| 573 | if (ret < 0) |
| 574 | { |
| 575 | if (errno == EIO) |
| 576 | { |
| 577 | have_ptrace_getsetvsxregs = 0; |
| 578 | return; |
| 579 | } |
| 580 | perror_with_name (_("Unable to fetch VSX registers")); |
| 581 | } |
| 582 | supply_vsxregset (regcache, ®s); |
| 583 | } |
| 584 | |
| 585 | static void |
| 586 | fetch_altivec_registers (struct regcache *regcache, int tid) |
| 587 | { |
| 588 | int ret; |
| 589 | gdb_vrregset_t regs; |
| 590 | |
| 591 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
| 592 | if (ret < 0) |
| 593 | { |
| 594 | if (errno == EIO) |
| 595 | { |
| 596 | have_ptrace_getvrregs = 0; |
| 597 | return; |
| 598 | } |
| 599 | perror_with_name (_("Unable to fetch AltiVec registers")); |
| 600 | } |
| 601 | supply_vrregset (regcache, ®s); |
| 602 | } |
| 603 | |
| 604 | static void |
| 605 | fetch_ppc_registers (struct regcache *regcache, int tid) |
| 606 | { |
| 607 | int i; |
| 608 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 609 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 610 | |
| 611 | for (i = 0; i < ppc_num_gprs; i++) |
| 612 | fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
| 613 | if (tdep->ppc_fp0_regnum >= 0) |
| 614 | for (i = 0; i < ppc_num_fprs; i++) |
| 615 | fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i); |
| 616 | fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
| 617 | if (tdep->ppc_ps_regnum != -1) |
| 618 | fetch_register (regcache, tid, tdep->ppc_ps_regnum); |
| 619 | if (tdep->ppc_cr_regnum != -1) |
| 620 | fetch_register (regcache, tid, tdep->ppc_cr_regnum); |
| 621 | if (tdep->ppc_lr_regnum != -1) |
| 622 | fetch_register (regcache, tid, tdep->ppc_lr_regnum); |
| 623 | if (tdep->ppc_ctr_regnum != -1) |
| 624 | fetch_register (regcache, tid, tdep->ppc_ctr_regnum); |
| 625 | if (tdep->ppc_xer_regnum != -1) |
| 626 | fetch_register (regcache, tid, tdep->ppc_xer_regnum); |
| 627 | if (tdep->ppc_mq_regnum != -1) |
| 628 | fetch_register (regcache, tid, tdep->ppc_mq_regnum); |
| 629 | if (ppc_linux_trap_reg_p (gdbarch)) |
| 630 | { |
| 631 | fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM); |
| 632 | fetch_register (regcache, tid, PPC_TRAP_REGNUM); |
| 633 | } |
| 634 | if (tdep->ppc_fpscr_regnum != -1) |
| 635 | fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); |
| 636 | if (have_ptrace_getvrregs) |
| 637 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) |
| 638 | fetch_altivec_registers (regcache, tid); |
| 639 | if (have_ptrace_getsetvsxregs) |
| 640 | if (tdep->ppc_vsr0_upper_regnum != -1) |
| 641 | fetch_vsx_registers (regcache, tid); |
| 642 | if (tdep->ppc_ev0_upper_regnum >= 0) |
| 643 | fetch_spe_register (regcache, tid, -1); |
| 644 | } |
| 645 | |
| 646 | /* Fetch registers from the child process. Fetch all registers if |
| 647 | regno == -1, otherwise fetch all general registers or all floating |
| 648 | point registers depending upon the value of regno. */ |
| 649 | static void |
| 650 | ppc_linux_fetch_inferior_registers (struct regcache *regcache, int regno) |
| 651 | { |
| 652 | /* Overload thread id onto process id */ |
| 653 | int tid = TIDGET (inferior_ptid); |
| 654 | |
| 655 | /* No thread id, just use process id */ |
| 656 | if (tid == 0) |
| 657 | tid = PIDGET (inferior_ptid); |
| 658 | |
| 659 | if (regno == -1) |
| 660 | fetch_ppc_registers (regcache, tid); |
| 661 | else |
| 662 | fetch_register (regcache, tid, regno); |
| 663 | } |
| 664 | |
| 665 | /* Store one VSX register. */ |
| 666 | static void |
| 667 | store_vsx_register (const struct regcache *regcache, int tid, int regno) |
| 668 | { |
| 669 | int ret; |
| 670 | gdb_vsxregset_t regs; |
| 671 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 672 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 673 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); |
| 674 | |
| 675 | ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); |
| 676 | if (ret < 0) |
| 677 | { |
| 678 | if (errno == EIO) |
| 679 | { |
| 680 | have_ptrace_getsetvsxregs = 0; |
| 681 | return; |
| 682 | } |
| 683 | perror_with_name (_("Unable to fetch VSX register")); |
| 684 | } |
| 685 | |
| 686 | regcache_raw_collect (regcache, regno, regs + |
| 687 | (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize); |
| 688 | |
| 689 | ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); |
| 690 | if (ret < 0) |
| 691 | perror_with_name (_("Unable to store VSX register")); |
| 692 | } |
| 693 | |
| 694 | /* Store one register. */ |
| 695 | static void |
| 696 | store_altivec_register (const struct regcache *regcache, int tid, int regno) |
| 697 | { |
| 698 | int ret; |
| 699 | int offset = 0; |
| 700 | gdb_vrregset_t regs; |
| 701 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 702 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 703 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
| 704 | |
| 705 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
| 706 | if (ret < 0) |
| 707 | { |
| 708 | if (errno == EIO) |
| 709 | { |
| 710 | have_ptrace_getvrregs = 0; |
| 711 | return; |
| 712 | } |
| 713 | perror_with_name (_("Unable to fetch AltiVec register")); |
| 714 | } |
| 715 | |
| 716 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes |
| 717 | long on the hardware. */ |
| 718 | if (regno == (tdep->ppc_vrsave_regnum - 1)) |
| 719 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
| 720 | |
| 721 | regcache_raw_collect (regcache, regno, |
| 722 | regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); |
| 723 | |
| 724 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); |
| 725 | if (ret < 0) |
| 726 | perror_with_name (_("Unable to store AltiVec register")); |
| 727 | } |
| 728 | |
| 729 | /* Assuming TID referrs to an SPE process, set the top halves of TID's |
| 730 | general-purpose registers and its SPE-specific registers to the |
| 731 | values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do |
| 732 | nothing. |
| 733 | |
| 734 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and |
| 735 | PTRACE_SETEVRREGS requests are supported is isolated here, and in |
| 736 | get_spe_registers. */ |
| 737 | static void |
| 738 | set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) |
| 739 | { |
| 740 | if (have_ptrace_getsetevrregs) |
| 741 | { |
| 742 | if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) |
| 743 | return; |
| 744 | else |
| 745 | { |
| 746 | /* EIO means that the PTRACE_SETEVRREGS request isn't |
| 747 | supported; we fail silently, and don't try the call |
| 748 | again. */ |
| 749 | if (errno == EIO) |
| 750 | have_ptrace_getsetevrregs = 0; |
| 751 | else |
| 752 | /* Anything else needs to be reported. */ |
| 753 | perror_with_name (_("Unable to set SPE registers")); |
| 754 | } |
| 755 | } |
| 756 | } |
| 757 | |
| 758 | /* Write GDB's value for the SPE-specific raw register REGNO to TID. |
| 759 | If REGNO is -1, write the values of all the SPE-specific |
| 760 | registers. */ |
| 761 | static void |
| 762 | store_spe_register (const struct regcache *regcache, int tid, int regno) |
| 763 | { |
| 764 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 765 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 766 | struct gdb_evrregset_t evrregs; |
| 767 | |
| 768 | gdb_assert (sizeof (evrregs.evr[0]) |
| 769 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
| 770 | gdb_assert (sizeof (evrregs.acc) |
| 771 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
| 772 | gdb_assert (sizeof (evrregs.spefscr) |
| 773 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
| 774 | |
| 775 | if (regno == -1) |
| 776 | /* Since we're going to write out every register, the code below |
| 777 | should store to every field of evrregs; if that doesn't happen, |
| 778 | make it obvious by initializing it with suspicious values. */ |
| 779 | memset (&evrregs, 42, sizeof (evrregs)); |
| 780 | else |
| 781 | /* We can only read and write the entire EVR register set at a |
| 782 | time, so to write just a single register, we do a |
| 783 | read-modify-write maneuver. */ |
| 784 | get_spe_registers (tid, &evrregs); |
| 785 | |
| 786 | if (regno == -1) |
| 787 | { |
| 788 | int i; |
| 789 | |
| 790 | for (i = 0; i < ppc_num_gprs; i++) |
| 791 | regcache_raw_collect (regcache, |
| 792 | tdep->ppc_ev0_upper_regnum + i, |
| 793 | &evrregs.evr[i]); |
| 794 | } |
| 795 | else if (tdep->ppc_ev0_upper_regnum <= regno |
| 796 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) |
| 797 | regcache_raw_collect (regcache, regno, |
| 798 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
| 799 | |
| 800 | if (regno == -1 |
| 801 | || regno == tdep->ppc_acc_regnum) |
| 802 | regcache_raw_collect (regcache, |
| 803 | tdep->ppc_acc_regnum, |
| 804 | &evrregs.acc); |
| 805 | |
| 806 | if (regno == -1 |
| 807 | || regno == tdep->ppc_spefscr_regnum) |
| 808 | regcache_raw_collect (regcache, |
| 809 | tdep->ppc_spefscr_regnum, |
| 810 | &evrregs.spefscr); |
| 811 | |
| 812 | /* Write back the modified register set. */ |
| 813 | set_spe_registers (tid, &evrregs); |
| 814 | } |
| 815 | |
| 816 | static void |
| 817 | store_register (const struct regcache *regcache, int tid, int regno) |
| 818 | { |
| 819 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 820 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 821 | /* This isn't really an address. But ptrace thinks of it as one. */ |
| 822 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
| 823 | int i; |
| 824 | size_t bytes_to_transfer; |
| 825 | char buf[MAX_REGISTER_SIZE]; |
| 826 | |
| 827 | if (altivec_register_p (gdbarch, regno)) |
| 828 | { |
| 829 | store_altivec_register (regcache, tid, regno); |
| 830 | return; |
| 831 | } |
| 832 | if (vsx_register_p (gdbarch, regno)) |
| 833 | { |
| 834 | store_vsx_register (regcache, tid, regno); |
| 835 | return; |
| 836 | } |
| 837 | else if (spe_register_p (gdbarch, regno)) |
| 838 | { |
| 839 | store_spe_register (regcache, tid, regno); |
| 840 | return; |
| 841 | } |
| 842 | |
| 843 | if (regaddr == -1) |
| 844 | return; |
| 845 | |
| 846 | /* First collect the register. Keep in mind that the regcache's |
| 847 | idea of the register's size may not be a multiple of sizeof |
| 848 | (long). */ |
| 849 | memset (buf, 0, sizeof buf); |
| 850 | bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); |
| 851 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
| 852 | { |
| 853 | /* Little-endian values always sit at the left end of the buffer. */ |
| 854 | regcache_raw_collect (regcache, regno, buf); |
| 855 | } |
| 856 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 857 | { |
| 858 | /* Big-endian values sit at the right end of the buffer. */ |
| 859 | size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); |
| 860 | regcache_raw_collect (regcache, regno, buf + padding); |
| 861 | } |
| 862 | |
| 863 | for (i = 0; i < bytes_to_transfer; i += sizeof (long)) |
| 864 | { |
| 865 | errno = 0; |
| 866 | ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, |
| 867 | *(long *) &buf[i]); |
| 868 | regaddr += sizeof (long); |
| 869 | |
| 870 | if (errno == EIO |
| 871 | && (regno == tdep->ppc_fpscr_regnum |
| 872 | || regno == PPC_ORIG_R3_REGNUM |
| 873 | || regno == PPC_TRAP_REGNUM)) |
| 874 | { |
| 875 | /* Some older kernel versions don't allow fpscr, orig_r3 |
| 876 | or trap to be written. */ |
| 877 | continue; |
| 878 | } |
| 879 | |
| 880 | if (errno != 0) |
| 881 | { |
| 882 | char message[128]; |
| 883 | sprintf (message, "writing register %s (#%d)", |
| 884 | gdbarch_register_name (gdbarch, regno), regno); |
| 885 | perror_with_name (message); |
| 886 | } |
| 887 | } |
| 888 | } |
| 889 | |
| 890 | static void |
| 891 | fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) |
| 892 | { |
| 893 | int i; |
| 894 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 895 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 896 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); |
| 897 | |
| 898 | for (i = 0; i < ppc_num_vshrs; i++) |
| 899 | regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i, |
| 900 | *vsxregsetp + i * vsxregsize); |
| 901 | } |
| 902 | |
| 903 | static void |
| 904 | fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
| 905 | { |
| 906 | int i; |
| 907 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 908 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 909 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
| 910 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
| 911 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
| 912 | |
| 913 | for (i = 0; i < num_of_vrregs; i++) |
| 914 | { |
| 915 | /* The last 2 registers of this set are only 32 bit long, not |
| 916 | 128, but only VSCR is fetched as a 16 bytes quantity. */ |
| 917 | if (i == (num_of_vrregs - 2)) |
| 918 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
| 919 | *vrregsetp + i * vrregsize + offset); |
| 920 | else |
| 921 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
| 922 | *vrregsetp + i * vrregsize); |
| 923 | } |
| 924 | } |
| 925 | |
| 926 | static void |
| 927 | store_vsx_registers (const struct regcache *regcache, int tid) |
| 928 | { |
| 929 | int ret; |
| 930 | gdb_vsxregset_t regs; |
| 931 | |
| 932 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); |
| 933 | if (ret < 0) |
| 934 | { |
| 935 | if (errno == EIO) |
| 936 | { |
| 937 | have_ptrace_getsetvsxregs = 0; |
| 938 | return; |
| 939 | } |
| 940 | perror_with_name (_("Couldn't get VSX registers")); |
| 941 | } |
| 942 | |
| 943 | fill_vsxregset (regcache, ®s); |
| 944 | |
| 945 | if (ptrace (PTRACE_SETVSXREGS, tid, 0, ®s) < 0) |
| 946 | perror_with_name (_("Couldn't write VSX registers")); |
| 947 | } |
| 948 | |
| 949 | static void |
| 950 | store_altivec_registers (const struct regcache *regcache, int tid) |
| 951 | { |
| 952 | int ret; |
| 953 | gdb_vrregset_t regs; |
| 954 | |
| 955 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
| 956 | if (ret < 0) |
| 957 | { |
| 958 | if (errno == EIO) |
| 959 | { |
| 960 | have_ptrace_getvrregs = 0; |
| 961 | return; |
| 962 | } |
| 963 | perror_with_name (_("Couldn't get AltiVec registers")); |
| 964 | } |
| 965 | |
| 966 | fill_vrregset (regcache, ®s); |
| 967 | |
| 968 | if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0) |
| 969 | perror_with_name (_("Couldn't write AltiVec registers")); |
| 970 | } |
| 971 | |
| 972 | static void |
| 973 | store_ppc_registers (const struct regcache *regcache, int tid) |
| 974 | { |
| 975 | int i; |
| 976 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 977 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 978 | |
| 979 | for (i = 0; i < ppc_num_gprs; i++) |
| 980 | store_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
| 981 | if (tdep->ppc_fp0_regnum >= 0) |
| 982 | for (i = 0; i < ppc_num_fprs; i++) |
| 983 | store_register (regcache, tid, tdep->ppc_fp0_regnum + i); |
| 984 | store_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
| 985 | if (tdep->ppc_ps_regnum != -1) |
| 986 | store_register (regcache, tid, tdep->ppc_ps_regnum); |
| 987 | if (tdep->ppc_cr_regnum != -1) |
| 988 | store_register (regcache, tid, tdep->ppc_cr_regnum); |
| 989 | if (tdep->ppc_lr_regnum != -1) |
| 990 | store_register (regcache, tid, tdep->ppc_lr_regnum); |
| 991 | if (tdep->ppc_ctr_regnum != -1) |
| 992 | store_register (regcache, tid, tdep->ppc_ctr_regnum); |
| 993 | if (tdep->ppc_xer_regnum != -1) |
| 994 | store_register (regcache, tid, tdep->ppc_xer_regnum); |
| 995 | if (tdep->ppc_mq_regnum != -1) |
| 996 | store_register (regcache, tid, tdep->ppc_mq_regnum); |
| 997 | if (tdep->ppc_fpscr_regnum != -1) |
| 998 | store_register (regcache, tid, tdep->ppc_fpscr_regnum); |
| 999 | if (ppc_linux_trap_reg_p (gdbarch)) |
| 1000 | { |
| 1001 | store_register (regcache, tid, PPC_ORIG_R3_REGNUM); |
| 1002 | store_register (regcache, tid, PPC_TRAP_REGNUM); |
| 1003 | } |
| 1004 | if (have_ptrace_getvrregs) |
| 1005 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) |
| 1006 | store_altivec_registers (regcache, tid); |
| 1007 | if (have_ptrace_getsetvsxregs) |
| 1008 | if (tdep->ppc_vsr0_upper_regnum != -1) |
| 1009 | store_vsx_registers (regcache, tid); |
| 1010 | if (tdep->ppc_ev0_upper_regnum >= 0) |
| 1011 | store_spe_register (regcache, tid, -1); |
| 1012 | } |
| 1013 | |
| 1014 | static int |
| 1015 | ppc_linux_check_watch_resources (int type, int cnt, int ot) |
| 1016 | { |
| 1017 | int tid; |
| 1018 | ptid_t ptid = inferior_ptid; |
| 1019 | |
| 1020 | /* DABR (data address breakpoint register) is optional for PPC variants. |
| 1021 | Some variants have one DABR, others have none. So CNT can't be larger |
| 1022 | than 1. */ |
| 1023 | if (cnt > 1) |
| 1024 | return 0; |
| 1025 | |
| 1026 | /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG and whether |
| 1027 | the target has DABR. If either answer is no, the ptrace call will |
| 1028 | return -1. Fail in that case. */ |
| 1029 | tid = TIDGET (ptid); |
| 1030 | if (tid == 0) |
| 1031 | tid = PIDGET (ptid); |
| 1032 | |
| 1033 | if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) |
| 1034 | return 0; |
| 1035 | return 1; |
| 1036 | } |
| 1037 | |
| 1038 | /* Fetch the AT_HWCAP entry from the aux vector. */ |
| 1039 | unsigned long ppc_linux_get_hwcap (void) |
| 1040 | { |
| 1041 | CORE_ADDR field; |
| 1042 | |
| 1043 | if (target_auxv_search (¤t_target, AT_HWCAP, &field)) |
| 1044 | return (unsigned long) field; |
| 1045 | |
| 1046 | return 0; |
| 1047 | } |
| 1048 | |
| 1049 | static int |
| 1050 | ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) |
| 1051 | { |
| 1052 | /* Handle sub-8-byte quantities. */ |
| 1053 | if (len <= 0) |
| 1054 | return 0; |
| 1055 | |
| 1056 | /* addr+len must fall in the 8 byte watchable region for DABR-based |
| 1057 | processors. DAC-based processors, like the PowerPC 440, will use |
| 1058 | addresses aligned to 4-bytes due to the way the read/write flags are |
| 1059 | passed at the moment. */ |
| 1060 | if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
| 1061 | && (addr + len) > (addr & ~3) + 4) |
| 1062 | || (addr + len) > (addr & ~7) + 8) |
| 1063 | return 0; |
| 1064 | |
| 1065 | return 1; |
| 1066 | } |
| 1067 | |
| 1068 | /* The cached DABR value, to install in new threads. */ |
| 1069 | static long saved_dabr_value; |
| 1070 | |
| 1071 | /* Set a watchpoint of type TYPE at address ADDR. */ |
| 1072 | static int |
| 1073 | ppc_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw) |
| 1074 | { |
| 1075 | struct lwp_info *lp; |
| 1076 | ptid_t ptid; |
| 1077 | long dabr_value; |
| 1078 | long read_mode, write_mode; |
| 1079 | |
| 1080 | if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
| 1081 | { |
| 1082 | /* PowerPC 440 requires only the read/write flags to be passed |
| 1083 | to the kernel. */ |
| 1084 | read_mode = 1; |
| 1085 | write_mode = 2; |
| 1086 | } |
| 1087 | else |
| 1088 | { |
| 1089 | /* PowerPC 970 and other DABR-based processors are required to pass |
| 1090 | the Breakpoint Translation bit together with the flags. */ |
| 1091 | read_mode = 5; |
| 1092 | write_mode = 6; |
| 1093 | } |
| 1094 | |
| 1095 | dabr_value = addr & ~(read_mode | write_mode); |
| 1096 | switch (rw) |
| 1097 | { |
| 1098 | case hw_read: |
| 1099 | /* Set read and translate bits. */ |
| 1100 | dabr_value |= read_mode; |
| 1101 | break; |
| 1102 | case hw_write: |
| 1103 | /* Set write and translate bits. */ |
| 1104 | dabr_value |= write_mode; |
| 1105 | break; |
| 1106 | case hw_access: |
| 1107 | /* Set read, write and translate bits. */ |
| 1108 | dabr_value |= read_mode | write_mode; |
| 1109 | break; |
| 1110 | } |
| 1111 | |
| 1112 | saved_dabr_value = dabr_value; |
| 1113 | |
| 1114 | ALL_LWPS (lp, ptid) |
| 1115 | if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value) < 0) |
| 1116 | return -1; |
| 1117 | |
| 1118 | return 0; |
| 1119 | } |
| 1120 | |
| 1121 | static int |
| 1122 | ppc_linux_remove_watchpoint (CORE_ADDR addr, int len, int rw) |
| 1123 | { |
| 1124 | struct lwp_info *lp; |
| 1125 | ptid_t ptid; |
| 1126 | long dabr_value = 0; |
| 1127 | |
| 1128 | saved_dabr_value = 0; |
| 1129 | ALL_LWPS (lp, ptid) |
| 1130 | if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value) < 0) |
| 1131 | return -1; |
| 1132 | return 0; |
| 1133 | } |
| 1134 | |
| 1135 | static void |
| 1136 | ppc_linux_new_thread (ptid_t ptid) |
| 1137 | { |
| 1138 | ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value); |
| 1139 | } |
| 1140 | |
| 1141 | static int |
| 1142 | ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) |
| 1143 | { |
| 1144 | struct siginfo *siginfo_p; |
| 1145 | |
| 1146 | siginfo_p = linux_nat_get_siginfo (inferior_ptid); |
| 1147 | |
| 1148 | if (siginfo_p->si_signo != SIGTRAP |
| 1149 | || (siginfo_p->si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) |
| 1150 | return 0; |
| 1151 | |
| 1152 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo_p->si_addr; |
| 1153 | return 1; |
| 1154 | } |
| 1155 | |
| 1156 | static int |
| 1157 | ppc_linux_stopped_by_watchpoint (void) |
| 1158 | { |
| 1159 | CORE_ADDR addr; |
| 1160 | return ppc_linux_stopped_data_address (¤t_target, &addr); |
| 1161 | } |
| 1162 | |
| 1163 | static int |
| 1164 | ppc_linux_watchpoint_addr_within_range (struct target_ops *target, |
| 1165 | CORE_ADDR addr, |
| 1166 | CORE_ADDR start, int length) |
| 1167 | { |
| 1168 | int mask; |
| 1169 | |
| 1170 | if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
| 1171 | mask = 3; |
| 1172 | else |
| 1173 | mask = 7; |
| 1174 | |
| 1175 | addr &= ~mask; |
| 1176 | |
| 1177 | /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */ |
| 1178 | return start <= addr + mask && start + length - 1 >= addr; |
| 1179 | } |
| 1180 | |
| 1181 | static void |
| 1182 | ppc_linux_store_inferior_registers (struct regcache *regcache, int regno) |
| 1183 | { |
| 1184 | /* Overload thread id onto process id */ |
| 1185 | int tid = TIDGET (inferior_ptid); |
| 1186 | |
| 1187 | /* No thread id, just use process id */ |
| 1188 | if (tid == 0) |
| 1189 | tid = PIDGET (inferior_ptid); |
| 1190 | |
| 1191 | if (regno >= 0) |
| 1192 | store_register (regcache, tid, regno); |
| 1193 | else |
| 1194 | store_ppc_registers (regcache, tid); |
| 1195 | } |
| 1196 | |
| 1197 | /* Functions for transferring registers between a gregset_t or fpregset_t |
| 1198 | (see sys/ucontext.h) and gdb's regcache. The word size is that used |
| 1199 | by the ptrace interface, not the current program's ABI. eg. If a |
| 1200 | powerpc64-linux gdb is being used to debug a powerpc32-linux app, we |
| 1201 | read or write 64-bit gregsets. This is to suit the host libthread_db. */ |
| 1202 | |
| 1203 | void |
| 1204 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
| 1205 | { |
| 1206 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
| 1207 | |
| 1208 | ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp)); |
| 1209 | } |
| 1210 | |
| 1211 | void |
| 1212 | fill_gregset (const struct regcache *regcache, |
| 1213 | gdb_gregset_t *gregsetp, int regno) |
| 1214 | { |
| 1215 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
| 1216 | |
| 1217 | if (regno == -1) |
| 1218 | memset (gregsetp, 0, sizeof (*gregsetp)); |
| 1219 | ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp)); |
| 1220 | } |
| 1221 | |
| 1222 | void |
| 1223 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp) |
| 1224 | { |
| 1225 | const struct regset *regset = ppc_linux_fpregset (); |
| 1226 | |
| 1227 | ppc_supply_fpregset (regset, regcache, -1, |
| 1228 | fpregsetp, sizeof (*fpregsetp)); |
| 1229 | } |
| 1230 | |
| 1231 | void |
| 1232 | fill_fpregset (const struct regcache *regcache, |
| 1233 | gdb_fpregset_t *fpregsetp, int regno) |
| 1234 | { |
| 1235 | const struct regset *regset = ppc_linux_fpregset (); |
| 1236 | |
| 1237 | ppc_collect_fpregset (regset, regcache, regno, |
| 1238 | fpregsetp, sizeof (*fpregsetp)); |
| 1239 | } |
| 1240 | |
| 1241 | static const struct target_desc * |
| 1242 | ppc_linux_read_description (struct target_ops *ops) |
| 1243 | { |
| 1244 | int altivec = 0; |
| 1245 | int vsx = 0; |
| 1246 | int isa205 = 0; |
| 1247 | |
| 1248 | int tid = TIDGET (inferior_ptid); |
| 1249 | if (tid == 0) |
| 1250 | tid = PIDGET (inferior_ptid); |
| 1251 | |
| 1252 | if (have_ptrace_getsetevrregs) |
| 1253 | { |
| 1254 | struct gdb_evrregset_t evrregset; |
| 1255 | |
| 1256 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0) |
| 1257 | return tdesc_powerpc_e500l; |
| 1258 | |
| 1259 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported. |
| 1260 | Anything else needs to be reported. */ |
| 1261 | else if (errno != EIO) |
| 1262 | perror_with_name (_("Unable to fetch SPE registers")); |
| 1263 | } |
| 1264 | |
| 1265 | if (have_ptrace_getsetvsxregs) |
| 1266 | { |
| 1267 | gdb_vsxregset_t vsxregset; |
| 1268 | |
| 1269 | if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0) |
| 1270 | vsx = 1; |
| 1271 | |
| 1272 | /* EIO means that the PTRACE_GETVSXREGS request isn't supported. |
| 1273 | Anything else needs to be reported. */ |
| 1274 | else if (errno != EIO) |
| 1275 | perror_with_name (_("Unable to fetch VSX registers")); |
| 1276 | } |
| 1277 | |
| 1278 | if (have_ptrace_getvrregs) |
| 1279 | { |
| 1280 | gdb_vrregset_t vrregset; |
| 1281 | |
| 1282 | if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0) |
| 1283 | altivec = 1; |
| 1284 | |
| 1285 | /* EIO means that the PTRACE_GETVRREGS request isn't supported. |
| 1286 | Anything else needs to be reported. */ |
| 1287 | else if (errno != EIO) |
| 1288 | perror_with_name (_("Unable to fetch AltiVec registers")); |
| 1289 | } |
| 1290 | |
| 1291 | if (ppc_linux_get_hwcap () & PPC_FEATURE_ARCH_2_05) |
| 1292 | isa205 = 1; |
| 1293 | |
| 1294 | /* Check for 64-bit inferior process. This is the case when the host is |
| 1295 | 64-bit, and in addition the top bit of the MSR register is set. */ |
| 1296 | #ifdef __powerpc64__ |
| 1297 | { |
| 1298 | long msr; |
| 1299 | errno = 0; |
| 1300 | msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0); |
| 1301 | if (errno == 0 && msr < 0) |
| 1302 | { |
| 1303 | if (vsx) |
| 1304 | return isa205? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l; |
| 1305 | else if (altivec) |
| 1306 | return isa205? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l; |
| 1307 | |
| 1308 | return isa205? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l; |
| 1309 | } |
| 1310 | } |
| 1311 | #endif |
| 1312 | |
| 1313 | if (vsx) |
| 1314 | return isa205? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l; |
| 1315 | else if (altivec) |
| 1316 | return isa205? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l; |
| 1317 | |
| 1318 | return isa205? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l; |
| 1319 | } |
| 1320 | |
| 1321 | void _initialize_ppc_linux_nat (void); |
| 1322 | |
| 1323 | void |
| 1324 | _initialize_ppc_linux_nat (void) |
| 1325 | { |
| 1326 | struct target_ops *t; |
| 1327 | |
| 1328 | /* Fill in the generic GNU/Linux methods. */ |
| 1329 | t = linux_target (); |
| 1330 | |
| 1331 | /* Add our register access methods. */ |
| 1332 | t->to_fetch_registers = ppc_linux_fetch_inferior_registers; |
| 1333 | t->to_store_registers = ppc_linux_store_inferior_registers; |
| 1334 | |
| 1335 | /* Add our watchpoint methods. */ |
| 1336 | t->to_can_use_hw_breakpoint = ppc_linux_check_watch_resources; |
| 1337 | t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint; |
| 1338 | t->to_insert_watchpoint = ppc_linux_insert_watchpoint; |
| 1339 | t->to_remove_watchpoint = ppc_linux_remove_watchpoint; |
| 1340 | t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint; |
| 1341 | t->to_stopped_data_address = ppc_linux_stopped_data_address; |
| 1342 | t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range; |
| 1343 | |
| 1344 | t->to_read_description = ppc_linux_read_description; |
| 1345 | |
| 1346 | /* Register the target. */ |
| 1347 | linux_nat_add_target (t); |
| 1348 | linux_nat_set_new_thread (t, ppc_linux_new_thread); |
| 1349 | } |