| 1 | /* PPC GNU/Linux native support. |
| 2 | |
| 3 | Copyright (C) 1988-2015 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #include "defs.h" |
| 21 | #include "observer.h" |
| 22 | #include "frame.h" |
| 23 | #include "inferior.h" |
| 24 | #include "gdbthread.h" |
| 25 | #include "gdbcore.h" |
| 26 | #include "regcache.h" |
| 27 | #include "target.h" |
| 28 | #include "linux-nat.h" |
| 29 | #include <sys/types.h> |
| 30 | #include <signal.h> |
| 31 | #include <sys/user.h> |
| 32 | #include <sys/ioctl.h> |
| 33 | #include "gdb_wait.h" |
| 34 | #include <fcntl.h> |
| 35 | #include <sys/procfs.h> |
| 36 | #include "nat/gdb_ptrace.h" |
| 37 | |
| 38 | /* Prototypes for supply_gregset etc. */ |
| 39 | #include "gregset.h" |
| 40 | #include "ppc-tdep.h" |
| 41 | #include "ppc-linux-tdep.h" |
| 42 | |
| 43 | /* Required when using the AUXV. */ |
| 44 | #include "elf/common.h" |
| 45 | #include "auxv.h" |
| 46 | |
| 47 | #include "nat/ppc-linux.h" |
| 48 | |
| 49 | /* Similarly for the hardware watchpoint support. These requests are used |
| 50 | when the PowerPC HWDEBUG ptrace interface is not available. */ |
| 51 | #ifndef PTRACE_GET_DEBUGREG |
| 52 | #define PTRACE_GET_DEBUGREG 25 |
| 53 | #endif |
| 54 | #ifndef PTRACE_SET_DEBUGREG |
| 55 | #define PTRACE_SET_DEBUGREG 26 |
| 56 | #endif |
| 57 | #ifndef PTRACE_GETSIGINFO |
| 58 | #define PTRACE_GETSIGINFO 0x4202 |
| 59 | #endif |
| 60 | |
| 61 | /* These requests are used when the PowerPC HWDEBUG ptrace interface is |
| 62 | available. It exposes the debug facilities of PowerPC processors, as well |
| 63 | as additional features of BookE processors, such as ranged breakpoints and |
| 64 | watchpoints and hardware-accelerated condition evaluation. */ |
| 65 | #ifndef PPC_PTRACE_GETHWDBGINFO |
| 66 | |
| 67 | /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG |
| 68 | ptrace interface is not present in ptrace.h, so we'll have to pretty much |
| 69 | include it all here so that the code at least compiles on older systems. */ |
| 70 | #define PPC_PTRACE_GETHWDBGINFO 0x89 |
| 71 | #define PPC_PTRACE_SETHWDEBUG 0x88 |
| 72 | #define PPC_PTRACE_DELHWDEBUG 0x87 |
| 73 | |
| 74 | struct ppc_debug_info |
| 75 | { |
| 76 | uint32_t version; /* Only version 1 exists to date. */ |
| 77 | uint32_t num_instruction_bps; |
| 78 | uint32_t num_data_bps; |
| 79 | uint32_t num_condition_regs; |
| 80 | uint32_t data_bp_alignment; |
| 81 | uint32_t sizeof_condition; /* size of the DVC register. */ |
| 82 | uint64_t features; |
| 83 | }; |
| 84 | |
| 85 | /* Features will have bits indicating whether there is support for: */ |
| 86 | #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1 |
| 87 | #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2 |
| 88 | #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4 |
| 89 | #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8 |
| 90 | |
| 91 | struct ppc_hw_breakpoint |
| 92 | { |
| 93 | uint32_t version; /* currently, version must be 1 */ |
| 94 | uint32_t trigger_type; /* only some combinations allowed */ |
| 95 | uint32_t addr_mode; /* address match mode */ |
| 96 | uint32_t condition_mode; /* break/watchpoint condition flags */ |
| 97 | uint64_t addr; /* break/watchpoint address */ |
| 98 | uint64_t addr2; /* range end or mask */ |
| 99 | uint64_t condition_value; /* contents of the DVC register */ |
| 100 | }; |
| 101 | |
| 102 | /* Trigger type. */ |
| 103 | #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1 |
| 104 | #define PPC_BREAKPOINT_TRIGGER_READ 0x2 |
| 105 | #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4 |
| 106 | #define PPC_BREAKPOINT_TRIGGER_RW 0x6 |
| 107 | |
| 108 | /* Address mode. */ |
| 109 | #define PPC_BREAKPOINT_MODE_EXACT 0x0 |
| 110 | #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1 |
| 111 | #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2 |
| 112 | #define PPC_BREAKPOINT_MODE_MASK 0x3 |
| 113 | |
| 114 | /* Condition mode. */ |
| 115 | #define PPC_BREAKPOINT_CONDITION_NONE 0x0 |
| 116 | #define PPC_BREAKPOINT_CONDITION_AND 0x1 |
| 117 | #define PPC_BREAKPOINT_CONDITION_EXACT 0x1 |
| 118 | #define PPC_BREAKPOINT_CONDITION_OR 0x2 |
| 119 | #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3 |
| 120 | #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 |
| 121 | #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16 |
| 122 | #define PPC_BREAKPOINT_CONDITION_BE(n) \ |
| 123 | (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT)) |
| 124 | #endif /* PPC_PTRACE_GETHWDBGINFO */ |
| 125 | |
| 126 | /* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider |
| 127 | watchpoint (up to 512 bytes). */ |
| 128 | #ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR |
| 129 | #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10 |
| 130 | #endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */ |
| 131 | |
| 132 | /* Similarly for the general-purpose (gp0 -- gp31) |
| 133 | and floating-point registers (fp0 -- fp31). */ |
| 134 | #ifndef PTRACE_GETREGS |
| 135 | #define PTRACE_GETREGS 12 |
| 136 | #endif |
| 137 | #ifndef PTRACE_SETREGS |
| 138 | #define PTRACE_SETREGS 13 |
| 139 | #endif |
| 140 | #ifndef PTRACE_GETFPREGS |
| 141 | #define PTRACE_GETFPREGS 14 |
| 142 | #endif |
| 143 | #ifndef PTRACE_SETFPREGS |
| 144 | #define PTRACE_SETFPREGS 15 |
| 145 | #endif |
| 146 | |
| 147 | /* This oddity is because the Linux kernel defines elf_vrregset_t as |
| 148 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. |
| 149 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return |
| 150 | the vrsave as an extra 4 bytes at the end. I opted for creating a |
| 151 | flat array of chars, so that it is easier to manipulate for gdb. |
| 152 | |
| 153 | There are 32 vector registers 16 bytes longs, plus a VSCR register |
| 154 | which is only 4 bytes long, but is fetched as a 16 bytes |
| 155 | quantity. Up to here we have the elf_vrregset_t structure. |
| 156 | Appended to this there is space for the VRSAVE register: 4 bytes. |
| 157 | Even though this vrsave register is not included in the regset |
| 158 | typedef, it is handled by the ptrace requests. |
| 159 | |
| 160 | Note that GNU/Linux doesn't support little endian PPC hardware, |
| 161 | therefore the offset at which the real value of the VSCR register |
| 162 | is located will be always 12 bytes. |
| 163 | |
| 164 | The layout is like this (where x is the actual value of the vscr reg): */ |
| 165 | |
| 166 | /* *INDENT-OFF* */ |
| 167 | /* |
| 168 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| |
| 169 | <-------> <-------><-------><-> |
| 170 | VR0 VR31 VSCR VRSAVE |
| 171 | */ |
| 172 | /* *INDENT-ON* */ |
| 173 | |
| 174 | #define SIZEOF_VRREGS 33*16+4 |
| 175 | |
| 176 | typedef char gdb_vrregset_t[SIZEOF_VRREGS]; |
| 177 | |
| 178 | /* This is the layout of the POWER7 VSX registers and the way they overlap |
| 179 | with the existing FPR and VMX registers. |
| 180 | |
| 181 | VSR doubleword 0 VSR doubleword 1 |
| 182 | ---------------------------------------------------------------- |
| 183 | VSR[0] | FPR[0] | | |
| 184 | ---------------------------------------------------------------- |
| 185 | VSR[1] | FPR[1] | | |
| 186 | ---------------------------------------------------------------- |
| 187 | | ... | | |
| 188 | | ... | | |
| 189 | ---------------------------------------------------------------- |
| 190 | VSR[30] | FPR[30] | | |
| 191 | ---------------------------------------------------------------- |
| 192 | VSR[31] | FPR[31] | | |
| 193 | ---------------------------------------------------------------- |
| 194 | VSR[32] | VR[0] | |
| 195 | ---------------------------------------------------------------- |
| 196 | VSR[33] | VR[1] | |
| 197 | ---------------------------------------------------------------- |
| 198 | | ... | |
| 199 | | ... | |
| 200 | ---------------------------------------------------------------- |
| 201 | VSR[62] | VR[30] | |
| 202 | ---------------------------------------------------------------- |
| 203 | VSR[63] | VR[31] | |
| 204 | ---------------------------------------------------------------- |
| 205 | |
| 206 | VSX has 64 128bit registers. The first 32 registers overlap with |
| 207 | the FP registers (doubleword 0) and hence extend them with additional |
| 208 | 64 bits (doubleword 1). The other 32 regs overlap with the VMX |
| 209 | registers. */ |
| 210 | #define SIZEOF_VSXREGS 32*8 |
| 211 | |
| 212 | typedef char gdb_vsxregset_t[SIZEOF_VSXREGS]; |
| 213 | |
| 214 | /* On PPC processors that support the Signal Processing Extension |
| 215 | (SPE) APU, the general-purpose registers are 64 bits long. |
| 216 | However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER |
| 217 | ptrace calls only access the lower half of each register, to allow |
| 218 | them to behave the same way they do on non-SPE systems. There's a |
| 219 | separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that |
| 220 | read and write the top halves of all the general-purpose registers |
| 221 | at once, along with some SPE-specific registers. |
| 222 | |
| 223 | GDB itself continues to claim the general-purpose registers are 32 |
| 224 | bits long. It has unnamed raw registers that hold the upper halves |
| 225 | of the gprs, and the full 64-bit SIMD views of the registers, |
| 226 | 'ev0' -- 'ev31', are pseudo-registers that splice the top and |
| 227 | bottom halves together. |
| 228 | |
| 229 | This is the structure filled in by PTRACE_GETEVRREGS and written to |
| 230 | the inferior's registers by PTRACE_SETEVRREGS. */ |
| 231 | struct gdb_evrregset_t |
| 232 | { |
| 233 | unsigned long evr[32]; |
| 234 | unsigned long long acc; |
| 235 | unsigned long spefscr; |
| 236 | }; |
| 237 | |
| 238 | /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and |
| 239 | PTRACE_SETVSXREGS requests, for reading and writing the VSX |
| 240 | POWER7 registers 0 through 31. Zero if we've tried one of them and |
| 241 | gotten an error. Note that VSX registers 32 through 63 overlap |
| 242 | with VR registers 0 through 31. */ |
| 243 | int have_ptrace_getsetvsxregs = 1; |
| 244 | |
| 245 | /* Non-zero if our kernel may support the PTRACE_GETVRREGS and |
| 246 | PTRACE_SETVRREGS requests, for reading and writing the Altivec |
| 247 | registers. Zero if we've tried one of them and gotten an |
| 248 | error. */ |
| 249 | int have_ptrace_getvrregs = 1; |
| 250 | |
| 251 | /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and |
| 252 | PTRACE_SETEVRREGS requests, for reading and writing the SPE |
| 253 | registers. Zero if we've tried one of them and gotten an |
| 254 | error. */ |
| 255 | int have_ptrace_getsetevrregs = 1; |
| 256 | |
| 257 | /* Non-zero if our kernel may support the PTRACE_GETREGS and |
| 258 | PTRACE_SETREGS requests, for reading and writing the |
| 259 | general-purpose registers. Zero if we've tried one of |
| 260 | them and gotten an error. */ |
| 261 | int have_ptrace_getsetregs = 1; |
| 262 | |
| 263 | /* Non-zero if our kernel may support the PTRACE_GETFPREGS and |
| 264 | PTRACE_SETFPREGS requests, for reading and writing the |
| 265 | floating-pointers registers. Zero if we've tried one of |
| 266 | them and gotten an error. */ |
| 267 | int have_ptrace_getsetfpregs = 1; |
| 268 | |
| 269 | /* *INDENT-OFF* */ |
| 270 | /* registers layout, as presented by the ptrace interface: |
| 271 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, |
| 272 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, |
| 273 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, |
| 274 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, |
| 275 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, |
| 276 | PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, |
| 277 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, |
| 278 | PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, |
| 279 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, |
| 280 | PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, |
| 281 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, |
| 282 | PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, |
| 283 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ |
| 284 | /* *INDENT_ON * */ |
| 285 | |
| 286 | static int |
| 287 | ppc_register_u_addr (struct gdbarch *gdbarch, int regno) |
| 288 | { |
| 289 | int u_addr = -1; |
| 290 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 291 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
| 292 | interface, and not the wordsize of the program's ABI. */ |
| 293 | int wordsize = sizeof (long); |
| 294 | |
| 295 | /* General purpose registers occupy 1 slot each in the buffer. */ |
| 296 | if (regno >= tdep->ppc_gp0_regnum |
| 297 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) |
| 298 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
| 299 | |
| 300 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
| 301 | ptrace interfaces. Thus, two slots each in 32-bit interface, one |
| 302 | slot each in 64-bit interface. */ |
| 303 | if (tdep->ppc_fp0_regnum >= 0 |
| 304 | && regno >= tdep->ppc_fp0_regnum |
| 305 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
| 306 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); |
| 307 | |
| 308 | /* UISA special purpose registers: 1 slot each. */ |
| 309 | if (regno == gdbarch_pc_regnum (gdbarch)) |
| 310 | u_addr = PT_NIP * wordsize; |
| 311 | if (regno == tdep->ppc_lr_regnum) |
| 312 | u_addr = PT_LNK * wordsize; |
| 313 | if (regno == tdep->ppc_cr_regnum) |
| 314 | u_addr = PT_CCR * wordsize; |
| 315 | if (regno == tdep->ppc_xer_regnum) |
| 316 | u_addr = PT_XER * wordsize; |
| 317 | if (regno == tdep->ppc_ctr_regnum) |
| 318 | u_addr = PT_CTR * wordsize; |
| 319 | #ifdef PT_MQ |
| 320 | if (regno == tdep->ppc_mq_regnum) |
| 321 | u_addr = PT_MQ * wordsize; |
| 322 | #endif |
| 323 | if (regno == tdep->ppc_ps_regnum) |
| 324 | u_addr = PT_MSR * wordsize; |
| 325 | if (regno == PPC_ORIG_R3_REGNUM) |
| 326 | u_addr = PT_ORIG_R3 * wordsize; |
| 327 | if (regno == PPC_TRAP_REGNUM) |
| 328 | u_addr = PT_TRAP * wordsize; |
| 329 | if (tdep->ppc_fpscr_regnum >= 0 |
| 330 | && regno == tdep->ppc_fpscr_regnum) |
| 331 | { |
| 332 | /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the |
| 333 | kernel headers incorrectly contained the 32-bit definition of |
| 334 | PT_FPSCR. For the 32-bit definition, floating-point |
| 335 | registers occupy two 32-bit "slots", and the FPSCR lives in |
| 336 | the second half of such a slot-pair (hence +1). For 64-bit, |
| 337 | the FPSCR instead occupies the full 64-bit 2-word-slot and |
| 338 | hence no adjustment is necessary. Hack around this. */ |
| 339 | if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) |
| 340 | u_addr = (48 + 32) * wordsize; |
| 341 | /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit |
| 342 | slot and not just its second word. The PT_FPSCR supplied when |
| 343 | GDB is compiled as a 32-bit app doesn't reflect this. */ |
| 344 | else if (wordsize == 4 && register_size (gdbarch, regno) == 8 |
| 345 | && PT_FPSCR == (48 + 2*32 + 1)) |
| 346 | u_addr = (48 + 2*32) * wordsize; |
| 347 | else |
| 348 | u_addr = PT_FPSCR * wordsize; |
| 349 | } |
| 350 | return u_addr; |
| 351 | } |
| 352 | |
| 353 | /* The Linux kernel ptrace interface for POWER7 VSX registers uses the |
| 354 | registers set mechanism, as opposed to the interface for all the |
| 355 | other registers, that stores/fetches each register individually. */ |
| 356 | static void |
| 357 | fetch_vsx_register (struct regcache *regcache, int tid, int regno) |
| 358 | { |
| 359 | int ret; |
| 360 | gdb_vsxregset_t regs; |
| 361 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 362 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 363 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); |
| 364 | |
| 365 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); |
| 366 | if (ret < 0) |
| 367 | { |
| 368 | if (errno == EIO) |
| 369 | { |
| 370 | have_ptrace_getsetvsxregs = 0; |
| 371 | return; |
| 372 | } |
| 373 | perror_with_name (_("Unable to fetch VSX register")); |
| 374 | } |
| 375 | |
| 376 | regcache_raw_supply (regcache, regno, |
| 377 | regs + (regno - tdep->ppc_vsr0_upper_regnum) |
| 378 | * vsxregsize); |
| 379 | } |
| 380 | |
| 381 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
| 382 | registers set mechanism, as opposed to the interface for all the |
| 383 | other registers, that stores/fetches each register individually. */ |
| 384 | static void |
| 385 | fetch_altivec_register (struct regcache *regcache, int tid, int regno) |
| 386 | { |
| 387 | int ret; |
| 388 | int offset = 0; |
| 389 | gdb_vrregset_t regs; |
| 390 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 391 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 392 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
| 393 | |
| 394 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
| 395 | if (ret < 0) |
| 396 | { |
| 397 | if (errno == EIO) |
| 398 | { |
| 399 | have_ptrace_getvrregs = 0; |
| 400 | return; |
| 401 | } |
| 402 | perror_with_name (_("Unable to fetch AltiVec register")); |
| 403 | } |
| 404 | |
| 405 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes |
| 406 | long on the hardware. We deal only with the lower 4 bytes of the |
| 407 | vector. VRSAVE is at the end of the array in a 4 bytes slot, so |
| 408 | there is no need to define an offset for it. */ |
| 409 | if (regno == (tdep->ppc_vrsave_regnum - 1)) |
| 410 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
| 411 | |
| 412 | regcache_raw_supply (regcache, regno, |
| 413 | regs + (regno |
| 414 | - tdep->ppc_vr0_regnum) * vrregsize + offset); |
| 415 | } |
| 416 | |
| 417 | /* Fetch the top 32 bits of TID's general-purpose registers and the |
| 418 | SPE-specific registers, and place the results in EVRREGSET. If we |
| 419 | don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with |
| 420 | zeros. |
| 421 | |
| 422 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and |
| 423 | PTRACE_SETEVRREGS requests are supported is isolated here, and in |
| 424 | set_spe_registers. */ |
| 425 | static void |
| 426 | get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) |
| 427 | { |
| 428 | if (have_ptrace_getsetevrregs) |
| 429 | { |
| 430 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) |
| 431 | return; |
| 432 | else |
| 433 | { |
| 434 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported; |
| 435 | we just return zeros. */ |
| 436 | if (errno == EIO) |
| 437 | have_ptrace_getsetevrregs = 0; |
| 438 | else |
| 439 | /* Anything else needs to be reported. */ |
| 440 | perror_with_name (_("Unable to fetch SPE registers")); |
| 441 | } |
| 442 | } |
| 443 | |
| 444 | memset (evrregset, 0, sizeof (*evrregset)); |
| 445 | } |
| 446 | |
| 447 | /* Supply values from TID for SPE-specific raw registers: the upper |
| 448 | halves of the GPRs, the accumulator, and the spefscr. REGNO must |
| 449 | be the number of an upper half register, acc, spefscr, or -1 to |
| 450 | supply the values of all registers. */ |
| 451 | static void |
| 452 | fetch_spe_register (struct regcache *regcache, int tid, int regno) |
| 453 | { |
| 454 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 455 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 456 | struct gdb_evrregset_t evrregs; |
| 457 | |
| 458 | gdb_assert (sizeof (evrregs.evr[0]) |
| 459 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
| 460 | gdb_assert (sizeof (evrregs.acc) |
| 461 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
| 462 | gdb_assert (sizeof (evrregs.spefscr) |
| 463 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
| 464 | |
| 465 | get_spe_registers (tid, &evrregs); |
| 466 | |
| 467 | if (regno == -1) |
| 468 | { |
| 469 | int i; |
| 470 | |
| 471 | for (i = 0; i < ppc_num_gprs; i++) |
| 472 | regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i, |
| 473 | &evrregs.evr[i]); |
| 474 | } |
| 475 | else if (tdep->ppc_ev0_upper_regnum <= regno |
| 476 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) |
| 477 | regcache_raw_supply (regcache, regno, |
| 478 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
| 479 | |
| 480 | if (regno == -1 |
| 481 | || regno == tdep->ppc_acc_regnum) |
| 482 | regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc); |
| 483 | |
| 484 | if (regno == -1 |
| 485 | || regno == tdep->ppc_spefscr_regnum) |
| 486 | regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum, |
| 487 | &evrregs.spefscr); |
| 488 | } |
| 489 | |
| 490 | static void |
| 491 | fetch_register (struct regcache *regcache, int tid, int regno) |
| 492 | { |
| 493 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 494 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 495 | /* This isn't really an address. But ptrace thinks of it as one. */ |
| 496 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
| 497 | int bytes_transferred; |
| 498 | unsigned int offset; /* Offset of registers within the u area. */ |
| 499 | gdb_byte buf[MAX_REGISTER_SIZE]; |
| 500 | |
| 501 | if (altivec_register_p (gdbarch, regno)) |
| 502 | { |
| 503 | /* If this is the first time through, or if it is not the first |
| 504 | time through, and we have comfirmed that there is kernel |
| 505 | support for such a ptrace request, then go and fetch the |
| 506 | register. */ |
| 507 | if (have_ptrace_getvrregs) |
| 508 | { |
| 509 | fetch_altivec_register (regcache, tid, regno); |
| 510 | return; |
| 511 | } |
| 512 | /* If we have discovered that there is no ptrace support for |
| 513 | AltiVec registers, fall through and return zeroes, because |
| 514 | regaddr will be -1 in this case. */ |
| 515 | } |
| 516 | if (vsx_register_p (gdbarch, regno)) |
| 517 | { |
| 518 | if (have_ptrace_getsetvsxregs) |
| 519 | { |
| 520 | fetch_vsx_register (regcache, tid, regno); |
| 521 | return; |
| 522 | } |
| 523 | } |
| 524 | else if (spe_register_p (gdbarch, regno)) |
| 525 | { |
| 526 | fetch_spe_register (regcache, tid, regno); |
| 527 | return; |
| 528 | } |
| 529 | |
| 530 | if (regaddr == -1) |
| 531 | { |
| 532 | memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ |
| 533 | regcache_raw_supply (regcache, regno, buf); |
| 534 | return; |
| 535 | } |
| 536 | |
| 537 | /* Read the raw register using sizeof(long) sized chunks. On a |
| 538 | 32-bit platform, 64-bit floating-point registers will require two |
| 539 | transfers. */ |
| 540 | for (bytes_transferred = 0; |
| 541 | bytes_transferred < register_size (gdbarch, regno); |
| 542 | bytes_transferred += sizeof (long)) |
| 543 | { |
| 544 | long l; |
| 545 | |
| 546 | errno = 0; |
| 547 | l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); |
| 548 | regaddr += sizeof (long); |
| 549 | if (errno != 0) |
| 550 | { |
| 551 | char message[128]; |
| 552 | xsnprintf (message, sizeof (message), "reading register %s (#%d)", |
| 553 | gdbarch_register_name (gdbarch, regno), regno); |
| 554 | perror_with_name (message); |
| 555 | } |
| 556 | memcpy (&buf[bytes_transferred], &l, sizeof (l)); |
| 557 | } |
| 558 | |
| 559 | /* Now supply the register. Keep in mind that the regcache's idea |
| 560 | of the register's size may not be a multiple of sizeof |
| 561 | (long). */ |
| 562 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
| 563 | { |
| 564 | /* Little-endian values are always found at the left end of the |
| 565 | bytes transferred. */ |
| 566 | regcache_raw_supply (regcache, regno, buf); |
| 567 | } |
| 568 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 569 | { |
| 570 | /* Big-endian values are found at the right end of the bytes |
| 571 | transferred. */ |
| 572 | size_t padding = (bytes_transferred - register_size (gdbarch, regno)); |
| 573 | regcache_raw_supply (regcache, regno, buf + padding); |
| 574 | } |
| 575 | else |
| 576 | internal_error (__FILE__, __LINE__, |
| 577 | _("fetch_register: unexpected byte order: %d"), |
| 578 | gdbarch_byte_order (gdbarch)); |
| 579 | } |
| 580 | |
| 581 | static void |
| 582 | supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) |
| 583 | { |
| 584 | int i; |
| 585 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 586 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 587 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); |
| 588 | |
| 589 | for (i = 0; i < ppc_num_vshrs; i++) |
| 590 | { |
| 591 | regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i, |
| 592 | *vsxregsetp + i * vsxregsize); |
| 593 | } |
| 594 | } |
| 595 | |
| 596 | static void |
| 597 | supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
| 598 | { |
| 599 | int i; |
| 600 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 601 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 602 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
| 603 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
| 604 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
| 605 | |
| 606 | for (i = 0; i < num_of_vrregs; i++) |
| 607 | { |
| 608 | /* The last 2 registers of this set are only 32 bit long, not |
| 609 | 128. However an offset is necessary only for VSCR because it |
| 610 | occupies a whole vector, while VRSAVE occupies a full 4 bytes |
| 611 | slot. */ |
| 612 | if (i == (num_of_vrregs - 2)) |
| 613 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
| 614 | *vrregsetp + i * vrregsize + offset); |
| 615 | else |
| 616 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
| 617 | *vrregsetp + i * vrregsize); |
| 618 | } |
| 619 | } |
| 620 | |
| 621 | static void |
| 622 | fetch_vsx_registers (struct regcache *regcache, int tid) |
| 623 | { |
| 624 | int ret; |
| 625 | gdb_vsxregset_t regs; |
| 626 | |
| 627 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); |
| 628 | if (ret < 0) |
| 629 | { |
| 630 | if (errno == EIO) |
| 631 | { |
| 632 | have_ptrace_getsetvsxregs = 0; |
| 633 | return; |
| 634 | } |
| 635 | perror_with_name (_("Unable to fetch VSX registers")); |
| 636 | } |
| 637 | supply_vsxregset (regcache, ®s); |
| 638 | } |
| 639 | |
| 640 | static void |
| 641 | fetch_altivec_registers (struct regcache *regcache, int tid) |
| 642 | { |
| 643 | int ret; |
| 644 | gdb_vrregset_t regs; |
| 645 | |
| 646 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
| 647 | if (ret < 0) |
| 648 | { |
| 649 | if (errno == EIO) |
| 650 | { |
| 651 | have_ptrace_getvrregs = 0; |
| 652 | return; |
| 653 | } |
| 654 | perror_with_name (_("Unable to fetch AltiVec registers")); |
| 655 | } |
| 656 | supply_vrregset (regcache, ®s); |
| 657 | } |
| 658 | |
| 659 | /* This function actually issues the request to ptrace, telling |
| 660 | it to get all general-purpose registers and put them into the |
| 661 | specified regset. |
| 662 | |
| 663 | If the ptrace request does not exist, this function returns 0 |
| 664 | and properly sets the have_ptrace_* flag. If the request fails, |
| 665 | this function calls perror_with_name. Otherwise, if the request |
| 666 | succeeds, then the regcache gets filled and 1 is returned. */ |
| 667 | static int |
| 668 | fetch_all_gp_regs (struct regcache *regcache, int tid) |
| 669 | { |
| 670 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 671 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 672 | gdb_gregset_t gregset; |
| 673 | |
| 674 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) |
| 675 | { |
| 676 | if (errno == EIO) |
| 677 | { |
| 678 | have_ptrace_getsetregs = 0; |
| 679 | return 0; |
| 680 | } |
| 681 | perror_with_name (_("Couldn't get general-purpose registers.")); |
| 682 | } |
| 683 | |
| 684 | supply_gregset (regcache, (const gdb_gregset_t *) &gregset); |
| 685 | |
| 686 | return 1; |
| 687 | } |
| 688 | |
| 689 | /* This is a wrapper for the fetch_all_gp_regs function. It is |
| 690 | responsible for verifying if this target has the ptrace request |
| 691 | that can be used to fetch all general-purpose registers at one |
| 692 | shot. If it doesn't, then we should fetch them using the |
| 693 | old-fashioned way, which is to iterate over the registers and |
| 694 | request them one by one. */ |
| 695 | static void |
| 696 | fetch_gp_regs (struct regcache *regcache, int tid) |
| 697 | { |
| 698 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 699 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 700 | int i; |
| 701 | |
| 702 | if (have_ptrace_getsetregs) |
| 703 | if (fetch_all_gp_regs (regcache, tid)) |
| 704 | return; |
| 705 | |
| 706 | /* If we've hit this point, it doesn't really matter which |
| 707 | architecture we are using. We just need to read the |
| 708 | registers in the "old-fashioned way". */ |
| 709 | for (i = 0; i < ppc_num_gprs; i++) |
| 710 | fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
| 711 | } |
| 712 | |
| 713 | /* This function actually issues the request to ptrace, telling |
| 714 | it to get all floating-point registers and put them into the |
| 715 | specified regset. |
| 716 | |
| 717 | If the ptrace request does not exist, this function returns 0 |
| 718 | and properly sets the have_ptrace_* flag. If the request fails, |
| 719 | this function calls perror_with_name. Otherwise, if the request |
| 720 | succeeds, then the regcache gets filled and 1 is returned. */ |
| 721 | static int |
| 722 | fetch_all_fp_regs (struct regcache *regcache, int tid) |
| 723 | { |
| 724 | gdb_fpregset_t fpregs; |
| 725 | |
| 726 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) |
| 727 | { |
| 728 | if (errno == EIO) |
| 729 | { |
| 730 | have_ptrace_getsetfpregs = 0; |
| 731 | return 0; |
| 732 | } |
| 733 | perror_with_name (_("Couldn't get floating-point registers.")); |
| 734 | } |
| 735 | |
| 736 | supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs); |
| 737 | |
| 738 | return 1; |
| 739 | } |
| 740 | |
| 741 | /* This is a wrapper for the fetch_all_fp_regs function. It is |
| 742 | responsible for verifying if this target has the ptrace request |
| 743 | that can be used to fetch all floating-point registers at one |
| 744 | shot. If it doesn't, then we should fetch them using the |
| 745 | old-fashioned way, which is to iterate over the registers and |
| 746 | request them one by one. */ |
| 747 | static void |
| 748 | fetch_fp_regs (struct regcache *regcache, int tid) |
| 749 | { |
| 750 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 751 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 752 | int i; |
| 753 | |
| 754 | if (have_ptrace_getsetfpregs) |
| 755 | if (fetch_all_fp_regs (regcache, tid)) |
| 756 | return; |
| 757 | |
| 758 | /* If we've hit this point, it doesn't really matter which |
| 759 | architecture we are using. We just need to read the |
| 760 | registers in the "old-fashioned way". */ |
| 761 | for (i = 0; i < ppc_num_fprs; i++) |
| 762 | fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i); |
| 763 | } |
| 764 | |
| 765 | static void |
| 766 | fetch_ppc_registers (struct regcache *regcache, int tid) |
| 767 | { |
| 768 | int i; |
| 769 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 770 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 771 | |
| 772 | fetch_gp_regs (regcache, tid); |
| 773 | if (tdep->ppc_fp0_regnum >= 0) |
| 774 | fetch_fp_regs (regcache, tid); |
| 775 | fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
| 776 | if (tdep->ppc_ps_regnum != -1) |
| 777 | fetch_register (regcache, tid, tdep->ppc_ps_regnum); |
| 778 | if (tdep->ppc_cr_regnum != -1) |
| 779 | fetch_register (regcache, tid, tdep->ppc_cr_regnum); |
| 780 | if (tdep->ppc_lr_regnum != -1) |
| 781 | fetch_register (regcache, tid, tdep->ppc_lr_regnum); |
| 782 | if (tdep->ppc_ctr_regnum != -1) |
| 783 | fetch_register (regcache, tid, tdep->ppc_ctr_regnum); |
| 784 | if (tdep->ppc_xer_regnum != -1) |
| 785 | fetch_register (regcache, tid, tdep->ppc_xer_regnum); |
| 786 | if (tdep->ppc_mq_regnum != -1) |
| 787 | fetch_register (regcache, tid, tdep->ppc_mq_regnum); |
| 788 | if (ppc_linux_trap_reg_p (gdbarch)) |
| 789 | { |
| 790 | fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM); |
| 791 | fetch_register (regcache, tid, PPC_TRAP_REGNUM); |
| 792 | } |
| 793 | if (tdep->ppc_fpscr_regnum != -1) |
| 794 | fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); |
| 795 | if (have_ptrace_getvrregs) |
| 796 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) |
| 797 | fetch_altivec_registers (regcache, tid); |
| 798 | if (have_ptrace_getsetvsxregs) |
| 799 | if (tdep->ppc_vsr0_upper_regnum != -1) |
| 800 | fetch_vsx_registers (regcache, tid); |
| 801 | if (tdep->ppc_ev0_upper_regnum >= 0) |
| 802 | fetch_spe_register (regcache, tid, -1); |
| 803 | } |
| 804 | |
| 805 | /* Fetch registers from the child process. Fetch all registers if |
| 806 | regno == -1, otherwise fetch all general registers or all floating |
| 807 | point registers depending upon the value of regno. */ |
| 808 | static void |
| 809 | ppc_linux_fetch_inferior_registers (struct target_ops *ops, |
| 810 | struct regcache *regcache, int regno) |
| 811 | { |
| 812 | /* Overload thread id onto process id. */ |
| 813 | int tid = ptid_get_lwp (inferior_ptid); |
| 814 | |
| 815 | /* No thread id, just use process id. */ |
| 816 | if (tid == 0) |
| 817 | tid = ptid_get_pid (inferior_ptid); |
| 818 | |
| 819 | if (regno == -1) |
| 820 | fetch_ppc_registers (regcache, tid); |
| 821 | else |
| 822 | fetch_register (regcache, tid, regno); |
| 823 | } |
| 824 | |
| 825 | /* Store one VSX register. */ |
| 826 | static void |
| 827 | store_vsx_register (const struct regcache *regcache, int tid, int regno) |
| 828 | { |
| 829 | int ret; |
| 830 | gdb_vsxregset_t regs; |
| 831 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 832 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 833 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); |
| 834 | |
| 835 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); |
| 836 | if (ret < 0) |
| 837 | { |
| 838 | if (errno == EIO) |
| 839 | { |
| 840 | have_ptrace_getsetvsxregs = 0; |
| 841 | return; |
| 842 | } |
| 843 | perror_with_name (_("Unable to fetch VSX register")); |
| 844 | } |
| 845 | |
| 846 | regcache_raw_collect (regcache, regno, regs + |
| 847 | (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize); |
| 848 | |
| 849 | ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); |
| 850 | if (ret < 0) |
| 851 | perror_with_name (_("Unable to store VSX register")); |
| 852 | } |
| 853 | |
| 854 | /* Store one register. */ |
| 855 | static void |
| 856 | store_altivec_register (const struct regcache *regcache, int tid, int regno) |
| 857 | { |
| 858 | int ret; |
| 859 | int offset = 0; |
| 860 | gdb_vrregset_t regs; |
| 861 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 862 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 863 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
| 864 | |
| 865 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
| 866 | if (ret < 0) |
| 867 | { |
| 868 | if (errno == EIO) |
| 869 | { |
| 870 | have_ptrace_getvrregs = 0; |
| 871 | return; |
| 872 | } |
| 873 | perror_with_name (_("Unable to fetch AltiVec register")); |
| 874 | } |
| 875 | |
| 876 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes |
| 877 | long on the hardware. */ |
| 878 | if (regno == (tdep->ppc_vrsave_regnum - 1)) |
| 879 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
| 880 | |
| 881 | regcache_raw_collect (regcache, regno, |
| 882 | regs + (regno |
| 883 | - tdep->ppc_vr0_regnum) * vrregsize + offset); |
| 884 | |
| 885 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); |
| 886 | if (ret < 0) |
| 887 | perror_with_name (_("Unable to store AltiVec register")); |
| 888 | } |
| 889 | |
| 890 | /* Assuming TID referrs to an SPE process, set the top halves of TID's |
| 891 | general-purpose registers and its SPE-specific registers to the |
| 892 | values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do |
| 893 | nothing. |
| 894 | |
| 895 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and |
| 896 | PTRACE_SETEVRREGS requests are supported is isolated here, and in |
| 897 | get_spe_registers. */ |
| 898 | static void |
| 899 | set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) |
| 900 | { |
| 901 | if (have_ptrace_getsetevrregs) |
| 902 | { |
| 903 | if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) |
| 904 | return; |
| 905 | else |
| 906 | { |
| 907 | /* EIO means that the PTRACE_SETEVRREGS request isn't |
| 908 | supported; we fail silently, and don't try the call |
| 909 | again. */ |
| 910 | if (errno == EIO) |
| 911 | have_ptrace_getsetevrregs = 0; |
| 912 | else |
| 913 | /* Anything else needs to be reported. */ |
| 914 | perror_with_name (_("Unable to set SPE registers")); |
| 915 | } |
| 916 | } |
| 917 | } |
| 918 | |
| 919 | /* Write GDB's value for the SPE-specific raw register REGNO to TID. |
| 920 | If REGNO is -1, write the values of all the SPE-specific |
| 921 | registers. */ |
| 922 | static void |
| 923 | store_spe_register (const struct regcache *regcache, int tid, int regno) |
| 924 | { |
| 925 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 926 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 927 | struct gdb_evrregset_t evrregs; |
| 928 | |
| 929 | gdb_assert (sizeof (evrregs.evr[0]) |
| 930 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
| 931 | gdb_assert (sizeof (evrregs.acc) |
| 932 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
| 933 | gdb_assert (sizeof (evrregs.spefscr) |
| 934 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
| 935 | |
| 936 | if (regno == -1) |
| 937 | /* Since we're going to write out every register, the code below |
| 938 | should store to every field of evrregs; if that doesn't happen, |
| 939 | make it obvious by initializing it with suspicious values. */ |
| 940 | memset (&evrregs, 42, sizeof (evrregs)); |
| 941 | else |
| 942 | /* We can only read and write the entire EVR register set at a |
| 943 | time, so to write just a single register, we do a |
| 944 | read-modify-write maneuver. */ |
| 945 | get_spe_registers (tid, &evrregs); |
| 946 | |
| 947 | if (regno == -1) |
| 948 | { |
| 949 | int i; |
| 950 | |
| 951 | for (i = 0; i < ppc_num_gprs; i++) |
| 952 | regcache_raw_collect (regcache, |
| 953 | tdep->ppc_ev0_upper_regnum + i, |
| 954 | &evrregs.evr[i]); |
| 955 | } |
| 956 | else if (tdep->ppc_ev0_upper_regnum <= regno |
| 957 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) |
| 958 | regcache_raw_collect (regcache, regno, |
| 959 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
| 960 | |
| 961 | if (regno == -1 |
| 962 | || regno == tdep->ppc_acc_regnum) |
| 963 | regcache_raw_collect (regcache, |
| 964 | tdep->ppc_acc_regnum, |
| 965 | &evrregs.acc); |
| 966 | |
| 967 | if (regno == -1 |
| 968 | || regno == tdep->ppc_spefscr_regnum) |
| 969 | regcache_raw_collect (regcache, |
| 970 | tdep->ppc_spefscr_regnum, |
| 971 | &evrregs.spefscr); |
| 972 | |
| 973 | /* Write back the modified register set. */ |
| 974 | set_spe_registers (tid, &evrregs); |
| 975 | } |
| 976 | |
| 977 | static void |
| 978 | store_register (const struct regcache *regcache, int tid, int regno) |
| 979 | { |
| 980 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 981 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 982 | /* This isn't really an address. But ptrace thinks of it as one. */ |
| 983 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
| 984 | int i; |
| 985 | size_t bytes_to_transfer; |
| 986 | gdb_byte buf[MAX_REGISTER_SIZE]; |
| 987 | |
| 988 | if (altivec_register_p (gdbarch, regno)) |
| 989 | { |
| 990 | store_altivec_register (regcache, tid, regno); |
| 991 | return; |
| 992 | } |
| 993 | if (vsx_register_p (gdbarch, regno)) |
| 994 | { |
| 995 | store_vsx_register (regcache, tid, regno); |
| 996 | return; |
| 997 | } |
| 998 | else if (spe_register_p (gdbarch, regno)) |
| 999 | { |
| 1000 | store_spe_register (regcache, tid, regno); |
| 1001 | return; |
| 1002 | } |
| 1003 | |
| 1004 | if (regaddr == -1) |
| 1005 | return; |
| 1006 | |
| 1007 | /* First collect the register. Keep in mind that the regcache's |
| 1008 | idea of the register's size may not be a multiple of sizeof |
| 1009 | (long). */ |
| 1010 | memset (buf, 0, sizeof buf); |
| 1011 | bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); |
| 1012 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
| 1013 | { |
| 1014 | /* Little-endian values always sit at the left end of the buffer. */ |
| 1015 | regcache_raw_collect (regcache, regno, buf); |
| 1016 | } |
| 1017 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 1018 | { |
| 1019 | /* Big-endian values sit at the right end of the buffer. */ |
| 1020 | size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); |
| 1021 | regcache_raw_collect (regcache, regno, buf + padding); |
| 1022 | } |
| 1023 | |
| 1024 | for (i = 0; i < bytes_to_transfer; i += sizeof (long)) |
| 1025 | { |
| 1026 | long l; |
| 1027 | |
| 1028 | memcpy (&l, &buf[i], sizeof (l)); |
| 1029 | errno = 0; |
| 1030 | ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l); |
| 1031 | regaddr += sizeof (long); |
| 1032 | |
| 1033 | if (errno == EIO |
| 1034 | && (regno == tdep->ppc_fpscr_regnum |
| 1035 | || regno == PPC_ORIG_R3_REGNUM |
| 1036 | || regno == PPC_TRAP_REGNUM)) |
| 1037 | { |
| 1038 | /* Some older kernel versions don't allow fpscr, orig_r3 |
| 1039 | or trap to be written. */ |
| 1040 | continue; |
| 1041 | } |
| 1042 | |
| 1043 | if (errno != 0) |
| 1044 | { |
| 1045 | char message[128]; |
| 1046 | xsnprintf (message, sizeof (message), "writing register %s (#%d)", |
| 1047 | gdbarch_register_name (gdbarch, regno), regno); |
| 1048 | perror_with_name (message); |
| 1049 | } |
| 1050 | } |
| 1051 | } |
| 1052 | |
| 1053 | static void |
| 1054 | fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) |
| 1055 | { |
| 1056 | int i; |
| 1057 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 1058 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1059 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); |
| 1060 | |
| 1061 | for (i = 0; i < ppc_num_vshrs; i++) |
| 1062 | regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i, |
| 1063 | *vsxregsetp + i * vsxregsize); |
| 1064 | } |
| 1065 | |
| 1066 | static void |
| 1067 | fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
| 1068 | { |
| 1069 | int i; |
| 1070 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 1071 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1072 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
| 1073 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
| 1074 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
| 1075 | |
| 1076 | for (i = 0; i < num_of_vrregs; i++) |
| 1077 | { |
| 1078 | /* The last 2 registers of this set are only 32 bit long, not |
| 1079 | 128, but only VSCR is fetched as a 16 bytes quantity. */ |
| 1080 | if (i == (num_of_vrregs - 2)) |
| 1081 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
| 1082 | *vrregsetp + i * vrregsize + offset); |
| 1083 | else |
| 1084 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
| 1085 | *vrregsetp + i * vrregsize); |
| 1086 | } |
| 1087 | } |
| 1088 | |
| 1089 | static void |
| 1090 | store_vsx_registers (const struct regcache *regcache, int tid) |
| 1091 | { |
| 1092 | int ret; |
| 1093 | gdb_vsxregset_t regs; |
| 1094 | |
| 1095 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); |
| 1096 | if (ret < 0) |
| 1097 | { |
| 1098 | if (errno == EIO) |
| 1099 | { |
| 1100 | have_ptrace_getsetvsxregs = 0; |
| 1101 | return; |
| 1102 | } |
| 1103 | perror_with_name (_("Couldn't get VSX registers")); |
| 1104 | } |
| 1105 | |
| 1106 | fill_vsxregset (regcache, ®s); |
| 1107 | |
| 1108 | if (ptrace (PTRACE_SETVSXREGS, tid, 0, ®s) < 0) |
| 1109 | perror_with_name (_("Couldn't write VSX registers")); |
| 1110 | } |
| 1111 | |
| 1112 | static void |
| 1113 | store_altivec_registers (const struct regcache *regcache, int tid) |
| 1114 | { |
| 1115 | int ret; |
| 1116 | gdb_vrregset_t regs; |
| 1117 | |
| 1118 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
| 1119 | if (ret < 0) |
| 1120 | { |
| 1121 | if (errno == EIO) |
| 1122 | { |
| 1123 | have_ptrace_getvrregs = 0; |
| 1124 | return; |
| 1125 | } |
| 1126 | perror_with_name (_("Couldn't get AltiVec registers")); |
| 1127 | } |
| 1128 | |
| 1129 | fill_vrregset (regcache, ®s); |
| 1130 | |
| 1131 | if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0) |
| 1132 | perror_with_name (_("Couldn't write AltiVec registers")); |
| 1133 | } |
| 1134 | |
| 1135 | /* This function actually issues the request to ptrace, telling |
| 1136 | it to store all general-purpose registers present in the specified |
| 1137 | regset. |
| 1138 | |
| 1139 | If the ptrace request does not exist, this function returns 0 |
| 1140 | and properly sets the have_ptrace_* flag. If the request fails, |
| 1141 | this function calls perror_with_name. Otherwise, if the request |
| 1142 | succeeds, then the regcache is stored and 1 is returned. */ |
| 1143 | static int |
| 1144 | store_all_gp_regs (const struct regcache *regcache, int tid, int regno) |
| 1145 | { |
| 1146 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 1147 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1148 | gdb_gregset_t gregset; |
| 1149 | |
| 1150 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) |
| 1151 | { |
| 1152 | if (errno == EIO) |
| 1153 | { |
| 1154 | have_ptrace_getsetregs = 0; |
| 1155 | return 0; |
| 1156 | } |
| 1157 | perror_with_name (_("Couldn't get general-purpose registers.")); |
| 1158 | } |
| 1159 | |
| 1160 | fill_gregset (regcache, &gregset, regno); |
| 1161 | |
| 1162 | if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0) |
| 1163 | { |
| 1164 | if (errno == EIO) |
| 1165 | { |
| 1166 | have_ptrace_getsetregs = 0; |
| 1167 | return 0; |
| 1168 | } |
| 1169 | perror_with_name (_("Couldn't set general-purpose registers.")); |
| 1170 | } |
| 1171 | |
| 1172 | return 1; |
| 1173 | } |
| 1174 | |
| 1175 | /* This is a wrapper for the store_all_gp_regs function. It is |
| 1176 | responsible for verifying if this target has the ptrace request |
| 1177 | that can be used to store all general-purpose registers at one |
| 1178 | shot. If it doesn't, then we should store them using the |
| 1179 | old-fashioned way, which is to iterate over the registers and |
| 1180 | store them one by one. */ |
| 1181 | static void |
| 1182 | store_gp_regs (const struct regcache *regcache, int tid, int regno) |
| 1183 | { |
| 1184 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 1185 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1186 | int i; |
| 1187 | |
| 1188 | if (have_ptrace_getsetregs) |
| 1189 | if (store_all_gp_regs (regcache, tid, regno)) |
| 1190 | return; |
| 1191 | |
| 1192 | /* If we hit this point, it doesn't really matter which |
| 1193 | architecture we are using. We just need to store the |
| 1194 | registers in the "old-fashioned way". */ |
| 1195 | for (i = 0; i < ppc_num_gprs; i++) |
| 1196 | store_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
| 1197 | } |
| 1198 | |
| 1199 | /* This function actually issues the request to ptrace, telling |
| 1200 | it to store all floating-point registers present in the specified |
| 1201 | regset. |
| 1202 | |
| 1203 | If the ptrace request does not exist, this function returns 0 |
| 1204 | and properly sets the have_ptrace_* flag. If the request fails, |
| 1205 | this function calls perror_with_name. Otherwise, if the request |
| 1206 | succeeds, then the regcache is stored and 1 is returned. */ |
| 1207 | static int |
| 1208 | store_all_fp_regs (const struct regcache *regcache, int tid, int regno) |
| 1209 | { |
| 1210 | gdb_fpregset_t fpregs; |
| 1211 | |
| 1212 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) |
| 1213 | { |
| 1214 | if (errno == EIO) |
| 1215 | { |
| 1216 | have_ptrace_getsetfpregs = 0; |
| 1217 | return 0; |
| 1218 | } |
| 1219 | perror_with_name (_("Couldn't get floating-point registers.")); |
| 1220 | } |
| 1221 | |
| 1222 | fill_fpregset (regcache, &fpregs, regno); |
| 1223 | |
| 1224 | if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0) |
| 1225 | { |
| 1226 | if (errno == EIO) |
| 1227 | { |
| 1228 | have_ptrace_getsetfpregs = 0; |
| 1229 | return 0; |
| 1230 | } |
| 1231 | perror_with_name (_("Couldn't set floating-point registers.")); |
| 1232 | } |
| 1233 | |
| 1234 | return 1; |
| 1235 | } |
| 1236 | |
| 1237 | /* This is a wrapper for the store_all_fp_regs function. It is |
| 1238 | responsible for verifying if this target has the ptrace request |
| 1239 | that can be used to store all floating-point registers at one |
| 1240 | shot. If it doesn't, then we should store them using the |
| 1241 | old-fashioned way, which is to iterate over the registers and |
| 1242 | store them one by one. */ |
| 1243 | static void |
| 1244 | store_fp_regs (const struct regcache *regcache, int tid, int regno) |
| 1245 | { |
| 1246 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 1247 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1248 | int i; |
| 1249 | |
| 1250 | if (have_ptrace_getsetfpregs) |
| 1251 | if (store_all_fp_regs (regcache, tid, regno)) |
| 1252 | return; |
| 1253 | |
| 1254 | /* If we hit this point, it doesn't really matter which |
| 1255 | architecture we are using. We just need to store the |
| 1256 | registers in the "old-fashioned way". */ |
| 1257 | for (i = 0; i < ppc_num_fprs; i++) |
| 1258 | store_register (regcache, tid, tdep->ppc_fp0_regnum + i); |
| 1259 | } |
| 1260 | |
| 1261 | static void |
| 1262 | store_ppc_registers (const struct regcache *regcache, int tid) |
| 1263 | { |
| 1264 | int i; |
| 1265 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 1266 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1267 | |
| 1268 | store_gp_regs (regcache, tid, -1); |
| 1269 | if (tdep->ppc_fp0_regnum >= 0) |
| 1270 | store_fp_regs (regcache, tid, -1); |
| 1271 | store_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
| 1272 | if (tdep->ppc_ps_regnum != -1) |
| 1273 | store_register (regcache, tid, tdep->ppc_ps_regnum); |
| 1274 | if (tdep->ppc_cr_regnum != -1) |
| 1275 | store_register (regcache, tid, tdep->ppc_cr_regnum); |
| 1276 | if (tdep->ppc_lr_regnum != -1) |
| 1277 | store_register (regcache, tid, tdep->ppc_lr_regnum); |
| 1278 | if (tdep->ppc_ctr_regnum != -1) |
| 1279 | store_register (regcache, tid, tdep->ppc_ctr_regnum); |
| 1280 | if (tdep->ppc_xer_regnum != -1) |
| 1281 | store_register (regcache, tid, tdep->ppc_xer_regnum); |
| 1282 | if (tdep->ppc_mq_regnum != -1) |
| 1283 | store_register (regcache, tid, tdep->ppc_mq_regnum); |
| 1284 | if (tdep->ppc_fpscr_regnum != -1) |
| 1285 | store_register (regcache, tid, tdep->ppc_fpscr_regnum); |
| 1286 | if (ppc_linux_trap_reg_p (gdbarch)) |
| 1287 | { |
| 1288 | store_register (regcache, tid, PPC_ORIG_R3_REGNUM); |
| 1289 | store_register (regcache, tid, PPC_TRAP_REGNUM); |
| 1290 | } |
| 1291 | if (have_ptrace_getvrregs) |
| 1292 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) |
| 1293 | store_altivec_registers (regcache, tid); |
| 1294 | if (have_ptrace_getsetvsxregs) |
| 1295 | if (tdep->ppc_vsr0_upper_regnum != -1) |
| 1296 | store_vsx_registers (regcache, tid); |
| 1297 | if (tdep->ppc_ev0_upper_regnum >= 0) |
| 1298 | store_spe_register (regcache, tid, -1); |
| 1299 | } |
| 1300 | |
| 1301 | /* Fetch the AT_HWCAP entry from the aux vector. */ |
| 1302 | static unsigned long |
| 1303 | ppc_linux_get_hwcap (void) |
| 1304 | { |
| 1305 | CORE_ADDR field; |
| 1306 | |
| 1307 | if (target_auxv_search (¤t_target, AT_HWCAP, &field)) |
| 1308 | return (unsigned long) field; |
| 1309 | |
| 1310 | return 0; |
| 1311 | } |
| 1312 | |
| 1313 | /* The cached DABR value, to install in new threads. |
| 1314 | This variable is used when the PowerPC HWDEBUG ptrace |
| 1315 | interface is not available. */ |
| 1316 | static long saved_dabr_value; |
| 1317 | |
| 1318 | /* Global structure that will store information about the available |
| 1319 | features provided by the PowerPC HWDEBUG ptrace interface. */ |
| 1320 | static struct ppc_debug_info hwdebug_info; |
| 1321 | |
| 1322 | /* Global variable that holds the maximum number of slots that the |
| 1323 | kernel will use. This is only used when PowerPC HWDEBUG ptrace interface |
| 1324 | is available. */ |
| 1325 | static size_t max_slots_number = 0; |
| 1326 | |
| 1327 | struct hw_break_tuple |
| 1328 | { |
| 1329 | long slot; |
| 1330 | struct ppc_hw_breakpoint *hw_break; |
| 1331 | }; |
| 1332 | |
| 1333 | /* This is an internal VEC created to store information about *points inserted |
| 1334 | for each thread. This is used when PowerPC HWDEBUG ptrace interface is |
| 1335 | available. */ |
| 1336 | typedef struct thread_points |
| 1337 | { |
| 1338 | /* The TID to which this *point relates. */ |
| 1339 | int tid; |
| 1340 | /* Information about the *point, such as its address, type, etc. |
| 1341 | |
| 1342 | Each element inside this vector corresponds to a hardware |
| 1343 | breakpoint or watchpoint in the thread represented by TID. The maximum |
| 1344 | size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of |
| 1345 | the tuple is NULL, then the position in the vector is free. */ |
| 1346 | struct hw_break_tuple *hw_breaks; |
| 1347 | } *thread_points_p; |
| 1348 | DEF_VEC_P (thread_points_p); |
| 1349 | |
| 1350 | VEC(thread_points_p) *ppc_threads = NULL; |
| 1351 | |
| 1352 | /* The version of the PowerPC HWDEBUG kernel interface that we will use, if |
| 1353 | available. */ |
| 1354 | #define PPC_DEBUG_CURRENT_VERSION 1 |
| 1355 | |
| 1356 | /* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface. */ |
| 1357 | static int |
| 1358 | have_ptrace_hwdebug_interface (void) |
| 1359 | { |
| 1360 | static int have_ptrace_hwdebug_interface = -1; |
| 1361 | |
| 1362 | if (have_ptrace_hwdebug_interface == -1) |
| 1363 | { |
| 1364 | int tid; |
| 1365 | |
| 1366 | tid = ptid_get_lwp (inferior_ptid); |
| 1367 | if (tid == 0) |
| 1368 | tid = ptid_get_pid (inferior_ptid); |
| 1369 | |
| 1370 | /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */ |
| 1371 | if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &hwdebug_info) >= 0) |
| 1372 | { |
| 1373 | /* Check whether PowerPC HWDEBUG ptrace interface is functional and |
| 1374 | provides any supported feature. */ |
| 1375 | if (hwdebug_info.features != 0) |
| 1376 | { |
| 1377 | have_ptrace_hwdebug_interface = 1; |
| 1378 | max_slots_number = hwdebug_info.num_instruction_bps |
| 1379 | + hwdebug_info.num_data_bps |
| 1380 | + hwdebug_info.num_condition_regs; |
| 1381 | return have_ptrace_hwdebug_interface; |
| 1382 | } |
| 1383 | } |
| 1384 | /* Old school interface and no PowerPC HWDEBUG ptrace support. */ |
| 1385 | have_ptrace_hwdebug_interface = 0; |
| 1386 | memset (&hwdebug_info, 0, sizeof (struct ppc_debug_info)); |
| 1387 | } |
| 1388 | |
| 1389 | return have_ptrace_hwdebug_interface; |
| 1390 | } |
| 1391 | |
| 1392 | static int |
| 1393 | ppc_linux_can_use_hw_breakpoint (struct target_ops *self, |
| 1394 | enum bptype type, int cnt, int ot) |
| 1395 | { |
| 1396 | int total_hw_wp, total_hw_bp; |
| 1397 | |
| 1398 | if (have_ptrace_hwdebug_interface ()) |
| 1399 | { |
| 1400 | /* When PowerPC HWDEBUG ptrace interface is available, the number of |
| 1401 | available hardware watchpoints and breakpoints is stored at the |
| 1402 | hwdebug_info struct. */ |
| 1403 | total_hw_bp = hwdebug_info.num_instruction_bps; |
| 1404 | total_hw_wp = hwdebug_info.num_data_bps; |
| 1405 | } |
| 1406 | else |
| 1407 | { |
| 1408 | /* When we do not have PowerPC HWDEBUG ptrace interface, we should |
| 1409 | consider having 1 hardware watchpoint and no hardware breakpoints. */ |
| 1410 | total_hw_bp = 0; |
| 1411 | total_hw_wp = 1; |
| 1412 | } |
| 1413 | |
| 1414 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint |
| 1415 | || type == bp_access_watchpoint || type == bp_watchpoint) |
| 1416 | { |
| 1417 | if (cnt + ot > total_hw_wp) |
| 1418 | return -1; |
| 1419 | } |
| 1420 | else if (type == bp_hardware_breakpoint) |
| 1421 | { |
| 1422 | if (total_hw_bp == 0) |
| 1423 | { |
| 1424 | /* No hardware breakpoint support. */ |
| 1425 | return 0; |
| 1426 | } |
| 1427 | if (cnt > total_hw_bp) |
| 1428 | return -1; |
| 1429 | } |
| 1430 | |
| 1431 | if (!have_ptrace_hwdebug_interface ()) |
| 1432 | { |
| 1433 | int tid; |
| 1434 | ptid_t ptid = inferior_ptid; |
| 1435 | |
| 1436 | /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG |
| 1437 | and whether the target has DABR. If either answer is no, the |
| 1438 | ptrace call will return -1. Fail in that case. */ |
| 1439 | tid = ptid_get_lwp (ptid); |
| 1440 | if (tid == 0) |
| 1441 | tid = ptid_get_pid (ptid); |
| 1442 | |
| 1443 | if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) |
| 1444 | return 0; |
| 1445 | } |
| 1446 | |
| 1447 | return 1; |
| 1448 | } |
| 1449 | |
| 1450 | static int |
| 1451 | ppc_linux_region_ok_for_hw_watchpoint (struct target_ops *self, |
| 1452 | CORE_ADDR addr, int len) |
| 1453 | { |
| 1454 | /* Handle sub-8-byte quantities. */ |
| 1455 | if (len <= 0) |
| 1456 | return 0; |
| 1457 | |
| 1458 | /* The PowerPC HWDEBUG ptrace interface tells if there are alignment |
| 1459 | restrictions for watchpoints in the processors. In that case, we use that |
| 1460 | information to determine the hardcoded watchable region for |
| 1461 | watchpoints. */ |
| 1462 | if (have_ptrace_hwdebug_interface ()) |
| 1463 | { |
| 1464 | int region_size; |
| 1465 | /* Embedded DAC-based processors, like the PowerPC 440 have ranged |
| 1466 | watchpoints and can watch any access within an arbitrary memory |
| 1467 | region. This is useful to watch arrays and structs, for instance. It |
| 1468 | takes two hardware watchpoints though. */ |
| 1469 | if (len > 1 |
| 1470 | && hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE |
| 1471 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
| 1472 | return 2; |
| 1473 | /* Check if the processor provides DAWR interface. */ |
| 1474 | if (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_DAWR) |
| 1475 | /* DAWR interface allows to watch up to 512 byte wide ranges which |
| 1476 | can't cross a 512 byte boundary. */ |
| 1477 | region_size = 512; |
| 1478 | else |
| 1479 | region_size = hwdebug_info.data_bp_alignment; |
| 1480 | /* Server processors provide one hardware watchpoint and addr+len should |
| 1481 | fall in the watchable region provided by the ptrace interface. */ |
| 1482 | if (region_size |
| 1483 | && (addr + len > (addr & ~(region_size - 1)) + region_size)) |
| 1484 | return 0; |
| 1485 | } |
| 1486 | /* addr+len must fall in the 8 byte watchable region for DABR-based |
| 1487 | processors (i.e., server processors). Without the new PowerPC HWDEBUG |
| 1488 | ptrace interface, DAC-based processors (i.e., embedded processors) will |
| 1489 | use addresses aligned to 4-bytes due to the way the read/write flags are |
| 1490 | passed in the old ptrace interface. */ |
| 1491 | else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
| 1492 | && (addr + len) > (addr & ~3) + 4) |
| 1493 | || (addr + len) > (addr & ~7) + 8) |
| 1494 | return 0; |
| 1495 | |
| 1496 | return 1; |
| 1497 | } |
| 1498 | |
| 1499 | /* This function compares two ppc_hw_breakpoint structs field-by-field. */ |
| 1500 | static int |
| 1501 | hwdebug_point_cmp (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b) |
| 1502 | { |
| 1503 | return (a->trigger_type == b->trigger_type |
| 1504 | && a->addr_mode == b->addr_mode |
| 1505 | && a->condition_mode == b->condition_mode |
| 1506 | && a->addr == b->addr |
| 1507 | && a->addr2 == b->addr2 |
| 1508 | && a->condition_value == b->condition_value); |
| 1509 | } |
| 1510 | |
| 1511 | /* This function can be used to retrieve a thread_points by the TID of the |
| 1512 | related process/thread. If nothing has been found, and ALLOC_NEW is 0, |
| 1513 | it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the |
| 1514 | provided TID will be created and returned. */ |
| 1515 | static struct thread_points * |
| 1516 | hwdebug_find_thread_points_by_tid (int tid, int alloc_new) |
| 1517 | { |
| 1518 | int i; |
| 1519 | struct thread_points *t; |
| 1520 | |
| 1521 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++) |
| 1522 | if (t->tid == tid) |
| 1523 | return t; |
| 1524 | |
| 1525 | t = NULL; |
| 1526 | |
| 1527 | /* Do we need to allocate a new point_item |
| 1528 | if the wanted one does not exist? */ |
| 1529 | if (alloc_new) |
| 1530 | { |
| 1531 | t = XNEW (struct thread_points); |
| 1532 | t->hw_breaks = XCNEWVEC (struct hw_break_tuple, max_slots_number); |
| 1533 | t->tid = tid; |
| 1534 | VEC_safe_push (thread_points_p, ppc_threads, t); |
| 1535 | } |
| 1536 | |
| 1537 | return t; |
| 1538 | } |
| 1539 | |
| 1540 | /* This function is a generic wrapper that is responsible for inserting a |
| 1541 | *point (i.e., calling `ptrace' in order to issue the request to the |
| 1542 | kernel) and registering it internally in GDB. */ |
| 1543 | static void |
| 1544 | hwdebug_insert_point (struct ppc_hw_breakpoint *b, int tid) |
| 1545 | { |
| 1546 | int i; |
| 1547 | long slot; |
| 1548 | struct ppc_hw_breakpoint *p = XNEW (struct ppc_hw_breakpoint); |
| 1549 | struct hw_break_tuple *hw_breaks; |
| 1550 | struct cleanup *c = make_cleanup (xfree, p); |
| 1551 | struct thread_points *t; |
| 1552 | struct hw_break_tuple *tuple; |
| 1553 | |
| 1554 | memcpy (p, b, sizeof (struct ppc_hw_breakpoint)); |
| 1555 | |
| 1556 | errno = 0; |
| 1557 | slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p); |
| 1558 | if (slot < 0) |
| 1559 | perror_with_name (_("Unexpected error setting breakpoint or watchpoint")); |
| 1560 | |
| 1561 | /* Everything went fine, so we have to register this *point. */ |
| 1562 | t = hwdebug_find_thread_points_by_tid (tid, 1); |
| 1563 | gdb_assert (t != NULL); |
| 1564 | hw_breaks = t->hw_breaks; |
| 1565 | |
| 1566 | /* Find a free element in the hw_breaks vector. */ |
| 1567 | for (i = 0; i < max_slots_number; i++) |
| 1568 | if (hw_breaks[i].hw_break == NULL) |
| 1569 | { |
| 1570 | hw_breaks[i].slot = slot; |
| 1571 | hw_breaks[i].hw_break = p; |
| 1572 | break; |
| 1573 | } |
| 1574 | |
| 1575 | gdb_assert (i != max_slots_number); |
| 1576 | |
| 1577 | discard_cleanups (c); |
| 1578 | } |
| 1579 | |
| 1580 | /* This function is a generic wrapper that is responsible for removing a |
| 1581 | *point (i.e., calling `ptrace' in order to issue the request to the |
| 1582 | kernel), and unregistering it internally at GDB. */ |
| 1583 | static void |
| 1584 | hwdebug_remove_point (struct ppc_hw_breakpoint *b, int tid) |
| 1585 | { |
| 1586 | int i; |
| 1587 | struct hw_break_tuple *hw_breaks; |
| 1588 | struct thread_points *t; |
| 1589 | |
| 1590 | t = hwdebug_find_thread_points_by_tid (tid, 0); |
| 1591 | gdb_assert (t != NULL); |
| 1592 | hw_breaks = t->hw_breaks; |
| 1593 | |
| 1594 | for (i = 0; i < max_slots_number; i++) |
| 1595 | if (hw_breaks[i].hw_break && hwdebug_point_cmp (hw_breaks[i].hw_break, b)) |
| 1596 | break; |
| 1597 | |
| 1598 | gdb_assert (i != max_slots_number); |
| 1599 | |
| 1600 | /* We have to ignore ENOENT errors because the kernel implements hardware |
| 1601 | breakpoints/watchpoints as "one-shot", that is, they are automatically |
| 1602 | deleted when hit. */ |
| 1603 | errno = 0; |
| 1604 | if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0) |
| 1605 | if (errno != ENOENT) |
| 1606 | perror_with_name (_("Unexpected error deleting " |
| 1607 | "breakpoint or watchpoint")); |
| 1608 | |
| 1609 | xfree (hw_breaks[i].hw_break); |
| 1610 | hw_breaks[i].hw_break = NULL; |
| 1611 | } |
| 1612 | |
| 1613 | /* Return the number of registers needed for a ranged breakpoint. */ |
| 1614 | |
| 1615 | static int |
| 1616 | ppc_linux_ranged_break_num_registers (struct target_ops *target) |
| 1617 | { |
| 1618 | return ((have_ptrace_hwdebug_interface () |
| 1619 | && hwdebug_info.features & PPC_DEBUG_FEATURE_INSN_BP_RANGE)? |
| 1620 | 2 : -1); |
| 1621 | } |
| 1622 | |
| 1623 | /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for |
| 1624 | success, 1 if hardware breakpoints are not supported or -1 for failure. */ |
| 1625 | |
| 1626 | static int |
| 1627 | ppc_linux_insert_hw_breakpoint (struct target_ops *self, |
| 1628 | struct gdbarch *gdbarch, |
| 1629 | struct bp_target_info *bp_tgt) |
| 1630 | { |
| 1631 | struct lwp_info *lp; |
| 1632 | struct ppc_hw_breakpoint p; |
| 1633 | |
| 1634 | if (!have_ptrace_hwdebug_interface ()) |
| 1635 | return -1; |
| 1636 | |
| 1637 | p.version = PPC_DEBUG_CURRENT_VERSION; |
| 1638 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; |
| 1639 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
| 1640 | p.addr = (uint64_t) (bp_tgt->placed_address = bp_tgt->reqstd_address); |
| 1641 | p.condition_value = 0; |
| 1642 | |
| 1643 | if (bp_tgt->length) |
| 1644 | { |
| 1645 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; |
| 1646 | |
| 1647 | /* The breakpoint will trigger if the address of the instruction is |
| 1648 | within the defined range, as follows: p.addr <= address < p.addr2. */ |
| 1649 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; |
| 1650 | } |
| 1651 | else |
| 1652 | { |
| 1653 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; |
| 1654 | p.addr2 = 0; |
| 1655 | } |
| 1656 | |
| 1657 | ALL_LWPS (lp) |
| 1658 | hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid)); |
| 1659 | |
| 1660 | return 0; |
| 1661 | } |
| 1662 | |
| 1663 | static int |
| 1664 | ppc_linux_remove_hw_breakpoint (struct target_ops *self, |
| 1665 | struct gdbarch *gdbarch, |
| 1666 | struct bp_target_info *bp_tgt) |
| 1667 | { |
| 1668 | struct lwp_info *lp; |
| 1669 | struct ppc_hw_breakpoint p; |
| 1670 | |
| 1671 | if (!have_ptrace_hwdebug_interface ()) |
| 1672 | return -1; |
| 1673 | |
| 1674 | p.version = PPC_DEBUG_CURRENT_VERSION; |
| 1675 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; |
| 1676 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
| 1677 | p.addr = (uint64_t) bp_tgt->placed_address; |
| 1678 | p.condition_value = 0; |
| 1679 | |
| 1680 | if (bp_tgt->length) |
| 1681 | { |
| 1682 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; |
| 1683 | |
| 1684 | /* The breakpoint will trigger if the address of the instruction is within |
| 1685 | the defined range, as follows: p.addr <= address < p.addr2. */ |
| 1686 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; |
| 1687 | } |
| 1688 | else |
| 1689 | { |
| 1690 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; |
| 1691 | p.addr2 = 0; |
| 1692 | } |
| 1693 | |
| 1694 | ALL_LWPS (lp) |
| 1695 | hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid)); |
| 1696 | |
| 1697 | return 0; |
| 1698 | } |
| 1699 | |
| 1700 | static int |
| 1701 | get_trigger_type (enum target_hw_bp_type type) |
| 1702 | { |
| 1703 | int t; |
| 1704 | |
| 1705 | if (type == hw_read) |
| 1706 | t = PPC_BREAKPOINT_TRIGGER_READ; |
| 1707 | else if (type == hw_write) |
| 1708 | t = PPC_BREAKPOINT_TRIGGER_WRITE; |
| 1709 | else |
| 1710 | t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE; |
| 1711 | |
| 1712 | return t; |
| 1713 | } |
| 1714 | |
| 1715 | /* Insert a new masked watchpoint at ADDR using the mask MASK. |
| 1716 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint |
| 1717 | or hw_access for an access watchpoint. Returns 0 on success and throws |
| 1718 | an error on failure. */ |
| 1719 | |
| 1720 | static int |
| 1721 | ppc_linux_insert_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr, |
| 1722 | CORE_ADDR mask, int rw) |
| 1723 | { |
| 1724 | struct lwp_info *lp; |
| 1725 | struct ppc_hw_breakpoint p; |
| 1726 | |
| 1727 | gdb_assert (have_ptrace_hwdebug_interface ()); |
| 1728 | |
| 1729 | p.version = PPC_DEBUG_CURRENT_VERSION; |
| 1730 | p.trigger_type = get_trigger_type (rw); |
| 1731 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; |
| 1732 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
| 1733 | p.addr = addr; |
| 1734 | p.addr2 = mask; |
| 1735 | p.condition_value = 0; |
| 1736 | |
| 1737 | ALL_LWPS (lp) |
| 1738 | hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid)); |
| 1739 | |
| 1740 | return 0; |
| 1741 | } |
| 1742 | |
| 1743 | /* Remove a masked watchpoint at ADDR with the mask MASK. |
| 1744 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint |
| 1745 | or hw_access for an access watchpoint. Returns 0 on success and throws |
| 1746 | an error on failure. */ |
| 1747 | |
| 1748 | static int |
| 1749 | ppc_linux_remove_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr, |
| 1750 | CORE_ADDR mask, int rw) |
| 1751 | { |
| 1752 | struct lwp_info *lp; |
| 1753 | struct ppc_hw_breakpoint p; |
| 1754 | |
| 1755 | gdb_assert (have_ptrace_hwdebug_interface ()); |
| 1756 | |
| 1757 | p.version = PPC_DEBUG_CURRENT_VERSION; |
| 1758 | p.trigger_type = get_trigger_type (rw); |
| 1759 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; |
| 1760 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
| 1761 | p.addr = addr; |
| 1762 | p.addr2 = mask; |
| 1763 | p.condition_value = 0; |
| 1764 | |
| 1765 | ALL_LWPS (lp) |
| 1766 | hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid)); |
| 1767 | |
| 1768 | return 0; |
| 1769 | } |
| 1770 | |
| 1771 | /* Check whether we have at least one free DVC register. */ |
| 1772 | static int |
| 1773 | can_use_watchpoint_cond_accel (void) |
| 1774 | { |
| 1775 | struct thread_points *p; |
| 1776 | int tid = ptid_get_lwp (inferior_ptid); |
| 1777 | int cnt = hwdebug_info.num_condition_regs, i; |
| 1778 | CORE_ADDR tmp_value; |
| 1779 | |
| 1780 | if (!have_ptrace_hwdebug_interface () || cnt == 0) |
| 1781 | return 0; |
| 1782 | |
| 1783 | p = hwdebug_find_thread_points_by_tid (tid, 0); |
| 1784 | |
| 1785 | if (p) |
| 1786 | { |
| 1787 | for (i = 0; i < max_slots_number; i++) |
| 1788 | if (p->hw_breaks[i].hw_break != NULL |
| 1789 | && (p->hw_breaks[i].hw_break->condition_mode |
| 1790 | != PPC_BREAKPOINT_CONDITION_NONE)) |
| 1791 | cnt--; |
| 1792 | |
| 1793 | /* There are no available slots now. */ |
| 1794 | if (cnt <= 0) |
| 1795 | return 0; |
| 1796 | } |
| 1797 | |
| 1798 | return 1; |
| 1799 | } |
| 1800 | |
| 1801 | /* Calculate the enable bits and the contents of the Data Value Compare |
| 1802 | debug register present in BookE processors. |
| 1803 | |
| 1804 | ADDR is the address to be watched, LEN is the length of watched data |
| 1805 | and DATA_VALUE is the value which will trigger the watchpoint. |
| 1806 | On exit, CONDITION_MODE will hold the enable bits for the DVC, and |
| 1807 | CONDITION_VALUE will hold the value which should be put in the |
| 1808 | DVC register. */ |
| 1809 | static void |
| 1810 | calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value, |
| 1811 | uint32_t *condition_mode, uint64_t *condition_value) |
| 1812 | { |
| 1813 | int i, num_byte_enable, align_offset, num_bytes_off_dvc, |
| 1814 | rightmost_enabled_byte; |
| 1815 | CORE_ADDR addr_end_data, addr_end_dvc; |
| 1816 | |
| 1817 | /* The DVC register compares bytes within fixed-length windows which |
| 1818 | are word-aligned, with length equal to that of the DVC register. |
| 1819 | We need to calculate where our watch region is relative to that |
| 1820 | window and enable comparison of the bytes which fall within it. */ |
| 1821 | |
| 1822 | align_offset = addr % hwdebug_info.sizeof_condition; |
| 1823 | addr_end_data = addr + len; |
| 1824 | addr_end_dvc = (addr - align_offset |
| 1825 | + hwdebug_info.sizeof_condition); |
| 1826 | num_bytes_off_dvc = (addr_end_data > addr_end_dvc)? |
| 1827 | addr_end_data - addr_end_dvc : 0; |
| 1828 | num_byte_enable = len - num_bytes_off_dvc; |
| 1829 | /* Here, bytes are numbered from right to left. */ |
| 1830 | rightmost_enabled_byte = (addr_end_data < addr_end_dvc)? |
| 1831 | addr_end_dvc - addr_end_data : 0; |
| 1832 | |
| 1833 | *condition_mode = PPC_BREAKPOINT_CONDITION_AND; |
| 1834 | for (i = 0; i < num_byte_enable; i++) |
| 1835 | *condition_mode |
| 1836 | |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte); |
| 1837 | |
| 1838 | /* Now we need to match the position within the DVC of the comparison |
| 1839 | value with where the watch region is relative to the window |
| 1840 | (i.e., the ALIGN_OFFSET). */ |
| 1841 | |
| 1842 | *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8 |
| 1843 | << rightmost_enabled_byte * 8); |
| 1844 | } |
| 1845 | |
| 1846 | /* Return the number of memory locations that need to be accessed to |
| 1847 | evaluate the expression which generated the given value chain. |
| 1848 | Returns -1 if there's any register access involved, or if there are |
| 1849 | other kinds of values which are not acceptable in a condition |
| 1850 | expression (e.g., lval_computed or lval_internalvar). */ |
| 1851 | static int |
| 1852 | num_memory_accesses (struct value *v) |
| 1853 | { |
| 1854 | int found_memory_cnt = 0; |
| 1855 | struct value *head = v; |
| 1856 | |
| 1857 | /* The idea here is that evaluating an expression generates a series |
| 1858 | of values, one holding the value of every subexpression. (The |
| 1859 | expression a*b+c has five subexpressions: a, b, a*b, c, and |
| 1860 | a*b+c.) GDB's values hold almost enough information to establish |
| 1861 | the criteria given above --- they identify memory lvalues, |
| 1862 | register lvalues, computed values, etcetera. So we can evaluate |
| 1863 | the expression, and then scan the chain of values that leaves |
| 1864 | behind to determine the memory locations involved in the evaluation |
| 1865 | of an expression. |
| 1866 | |
| 1867 | However, I don't think that the values returned by inferior |
| 1868 | function calls are special in any way. So this function may not |
| 1869 | notice that an expression contains an inferior function call. |
| 1870 | FIXME. */ |
| 1871 | |
| 1872 | for (; v; v = value_next (v)) |
| 1873 | { |
| 1874 | /* Constants and values from the history are fine. */ |
| 1875 | if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0) |
| 1876 | continue; |
| 1877 | else if (VALUE_LVAL (v) == lval_memory) |
| 1878 | { |
| 1879 | /* A lazy memory lvalue is one that GDB never needed to fetch; |
| 1880 | we either just used its address (e.g., `a' in `a.b') or |
| 1881 | we never needed it at all (e.g., `a' in `a,b'). */ |
| 1882 | if (!value_lazy (v)) |
| 1883 | found_memory_cnt++; |
| 1884 | } |
| 1885 | /* Other kinds of values are not fine. */ |
| 1886 | else |
| 1887 | return -1; |
| 1888 | } |
| 1889 | |
| 1890 | return found_memory_cnt; |
| 1891 | } |
| 1892 | |
| 1893 | /* Verifies whether the expression COND can be implemented using the |
| 1894 | DVC (Data Value Compare) register in BookE processors. The expression |
| 1895 | must test the watch value for equality with a constant expression. |
| 1896 | If the function returns 1, DATA_VALUE will contain the constant against |
| 1897 | which the watch value should be compared and LEN will contain the size |
| 1898 | of the constant. */ |
| 1899 | static int |
| 1900 | check_condition (CORE_ADDR watch_addr, struct expression *cond, |
| 1901 | CORE_ADDR *data_value, int *len) |
| 1902 | { |
| 1903 | int pc = 1, num_accesses_left, num_accesses_right; |
| 1904 | struct value *left_val, *right_val, *left_chain, *right_chain; |
| 1905 | |
| 1906 | if (cond->elts[0].opcode != BINOP_EQUAL) |
| 1907 | return 0; |
| 1908 | |
| 1909 | fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain, 0); |
| 1910 | num_accesses_left = num_memory_accesses (left_chain); |
| 1911 | |
| 1912 | if (left_val == NULL || num_accesses_left < 0) |
| 1913 | { |
| 1914 | free_value_chain (left_chain); |
| 1915 | |
| 1916 | return 0; |
| 1917 | } |
| 1918 | |
| 1919 | fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain, 0); |
| 1920 | num_accesses_right = num_memory_accesses (right_chain); |
| 1921 | |
| 1922 | if (right_val == NULL || num_accesses_right < 0) |
| 1923 | { |
| 1924 | free_value_chain (left_chain); |
| 1925 | free_value_chain (right_chain); |
| 1926 | |
| 1927 | return 0; |
| 1928 | } |
| 1929 | |
| 1930 | if (num_accesses_left == 1 && num_accesses_right == 0 |
| 1931 | && VALUE_LVAL (left_val) == lval_memory |
| 1932 | && value_address (left_val) == watch_addr) |
| 1933 | { |
| 1934 | *data_value = value_as_long (right_val); |
| 1935 | |
| 1936 | /* DATA_VALUE is the constant in RIGHT_VAL, but actually has |
| 1937 | the same type as the memory region referenced by LEFT_VAL. */ |
| 1938 | *len = TYPE_LENGTH (check_typedef (value_type (left_val))); |
| 1939 | } |
| 1940 | else if (num_accesses_left == 0 && num_accesses_right == 1 |
| 1941 | && VALUE_LVAL (right_val) == lval_memory |
| 1942 | && value_address (right_val) == watch_addr) |
| 1943 | { |
| 1944 | *data_value = value_as_long (left_val); |
| 1945 | |
| 1946 | /* DATA_VALUE is the constant in LEFT_VAL, but actually has |
| 1947 | the same type as the memory region referenced by RIGHT_VAL. */ |
| 1948 | *len = TYPE_LENGTH (check_typedef (value_type (right_val))); |
| 1949 | } |
| 1950 | else |
| 1951 | { |
| 1952 | free_value_chain (left_chain); |
| 1953 | free_value_chain (right_chain); |
| 1954 | |
| 1955 | return 0; |
| 1956 | } |
| 1957 | |
| 1958 | free_value_chain (left_chain); |
| 1959 | free_value_chain (right_chain); |
| 1960 | |
| 1961 | return 1; |
| 1962 | } |
| 1963 | |
| 1964 | /* Return non-zero if the target is capable of using hardware to evaluate |
| 1965 | the condition expression, thus only triggering the watchpoint when it is |
| 1966 | true. */ |
| 1967 | static int |
| 1968 | ppc_linux_can_accel_watchpoint_condition (struct target_ops *self, |
| 1969 | CORE_ADDR addr, int len, int rw, |
| 1970 | struct expression *cond) |
| 1971 | { |
| 1972 | CORE_ADDR data_value; |
| 1973 | |
| 1974 | return (have_ptrace_hwdebug_interface () |
| 1975 | && hwdebug_info.num_condition_regs > 0 |
| 1976 | && check_condition (addr, cond, &data_value, &len)); |
| 1977 | } |
| 1978 | |
| 1979 | /* Set up P with the parameters necessary to request a watchpoint covering |
| 1980 | LEN bytes starting at ADDR and if possible with condition expression COND |
| 1981 | evaluated by hardware. INSERT tells if we are creating a request for |
| 1982 | inserting or removing the watchpoint. */ |
| 1983 | |
| 1984 | static void |
| 1985 | create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr, |
| 1986 | int len, enum target_hw_bp_type type, |
| 1987 | struct expression *cond, int insert) |
| 1988 | { |
| 1989 | if (len == 1 |
| 1990 | || !(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE)) |
| 1991 | { |
| 1992 | int use_condition; |
| 1993 | CORE_ADDR data_value; |
| 1994 | |
| 1995 | use_condition = (insert? can_use_watchpoint_cond_accel () |
| 1996 | : hwdebug_info.num_condition_regs > 0); |
| 1997 | if (cond && use_condition && check_condition (addr, cond, |
| 1998 | &data_value, &len)) |
| 1999 | calculate_dvc (addr, len, data_value, &p->condition_mode, |
| 2000 | &p->condition_value); |
| 2001 | else |
| 2002 | { |
| 2003 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
| 2004 | p->condition_value = 0; |
| 2005 | } |
| 2006 | |
| 2007 | p->addr_mode = PPC_BREAKPOINT_MODE_EXACT; |
| 2008 | p->addr2 = 0; |
| 2009 | } |
| 2010 | else |
| 2011 | { |
| 2012 | p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; |
| 2013 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
| 2014 | p->condition_value = 0; |
| 2015 | |
| 2016 | /* The watchpoint will trigger if the address of the memory access is |
| 2017 | within the defined range, as follows: p->addr <= address < p->addr2. |
| 2018 | |
| 2019 | Note that the above sentence just documents how ptrace interprets |
| 2020 | its arguments; the watchpoint is set to watch the range defined by |
| 2021 | the user _inclusively_, as specified by the user interface. */ |
| 2022 | p->addr2 = (uint64_t) addr + len; |
| 2023 | } |
| 2024 | |
| 2025 | p->version = PPC_DEBUG_CURRENT_VERSION; |
| 2026 | p->trigger_type = get_trigger_type (type); |
| 2027 | p->addr = (uint64_t) addr; |
| 2028 | } |
| 2029 | |
| 2030 | static int |
| 2031 | ppc_linux_insert_watchpoint (struct target_ops *self, CORE_ADDR addr, int len, |
| 2032 | enum target_hw_bp_type type, |
| 2033 | struct expression *cond) |
| 2034 | { |
| 2035 | struct lwp_info *lp; |
| 2036 | int ret = -1; |
| 2037 | |
| 2038 | if (have_ptrace_hwdebug_interface ()) |
| 2039 | { |
| 2040 | struct ppc_hw_breakpoint p; |
| 2041 | |
| 2042 | create_watchpoint_request (&p, addr, len, type, cond, 1); |
| 2043 | |
| 2044 | ALL_LWPS (lp) |
| 2045 | hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid)); |
| 2046 | |
| 2047 | ret = 0; |
| 2048 | } |
| 2049 | else |
| 2050 | { |
| 2051 | long dabr_value; |
| 2052 | long read_mode, write_mode; |
| 2053 | |
| 2054 | if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
| 2055 | { |
| 2056 | /* PowerPC 440 requires only the read/write flags to be passed |
| 2057 | to the kernel. */ |
| 2058 | read_mode = 1; |
| 2059 | write_mode = 2; |
| 2060 | } |
| 2061 | else |
| 2062 | { |
| 2063 | /* PowerPC 970 and other DABR-based processors are required to pass |
| 2064 | the Breakpoint Translation bit together with the flags. */ |
| 2065 | read_mode = 5; |
| 2066 | write_mode = 6; |
| 2067 | } |
| 2068 | |
| 2069 | dabr_value = addr & ~(read_mode | write_mode); |
| 2070 | switch (type) |
| 2071 | { |
| 2072 | case hw_read: |
| 2073 | /* Set read and translate bits. */ |
| 2074 | dabr_value |= read_mode; |
| 2075 | break; |
| 2076 | case hw_write: |
| 2077 | /* Set write and translate bits. */ |
| 2078 | dabr_value |= write_mode; |
| 2079 | break; |
| 2080 | case hw_access: |
| 2081 | /* Set read, write and translate bits. */ |
| 2082 | dabr_value |= read_mode | write_mode; |
| 2083 | break; |
| 2084 | } |
| 2085 | |
| 2086 | saved_dabr_value = dabr_value; |
| 2087 | |
| 2088 | ALL_LWPS (lp) |
| 2089 | if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0, |
| 2090 | saved_dabr_value) < 0) |
| 2091 | return -1; |
| 2092 | |
| 2093 | ret = 0; |
| 2094 | } |
| 2095 | |
| 2096 | return ret; |
| 2097 | } |
| 2098 | |
| 2099 | static int |
| 2100 | ppc_linux_remove_watchpoint (struct target_ops *self, CORE_ADDR addr, int len, |
| 2101 | enum target_hw_bp_type type, |
| 2102 | struct expression *cond) |
| 2103 | { |
| 2104 | struct lwp_info *lp; |
| 2105 | int ret = -1; |
| 2106 | |
| 2107 | if (have_ptrace_hwdebug_interface ()) |
| 2108 | { |
| 2109 | struct ppc_hw_breakpoint p; |
| 2110 | |
| 2111 | create_watchpoint_request (&p, addr, len, type, cond, 0); |
| 2112 | |
| 2113 | ALL_LWPS (lp) |
| 2114 | hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid)); |
| 2115 | |
| 2116 | ret = 0; |
| 2117 | } |
| 2118 | else |
| 2119 | { |
| 2120 | saved_dabr_value = 0; |
| 2121 | ALL_LWPS (lp) |
| 2122 | if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0, |
| 2123 | saved_dabr_value) < 0) |
| 2124 | return -1; |
| 2125 | |
| 2126 | ret = 0; |
| 2127 | } |
| 2128 | |
| 2129 | return ret; |
| 2130 | } |
| 2131 | |
| 2132 | static void |
| 2133 | ppc_linux_new_thread (struct lwp_info *lp) |
| 2134 | { |
| 2135 | int tid = ptid_get_lwp (lp->ptid); |
| 2136 | |
| 2137 | if (have_ptrace_hwdebug_interface ()) |
| 2138 | { |
| 2139 | int i; |
| 2140 | struct thread_points *p; |
| 2141 | struct hw_break_tuple *hw_breaks; |
| 2142 | |
| 2143 | if (VEC_empty (thread_points_p, ppc_threads)) |
| 2144 | return; |
| 2145 | |
| 2146 | /* Get a list of breakpoints from any thread. */ |
| 2147 | p = VEC_last (thread_points_p, ppc_threads); |
| 2148 | hw_breaks = p->hw_breaks; |
| 2149 | |
| 2150 | /* Copy that thread's breakpoints and watchpoints to the new thread. */ |
| 2151 | for (i = 0; i < max_slots_number; i++) |
| 2152 | if (hw_breaks[i].hw_break) |
| 2153 | { |
| 2154 | /* Older kernels did not make new threads inherit their parent |
| 2155 | thread's debug state, so we always clear the slot and replicate |
| 2156 | the debug state ourselves, ensuring compatibility with all |
| 2157 | kernels. */ |
| 2158 | |
| 2159 | /* The ppc debug resource accounting is done through "slots". |
| 2160 | Ask the kernel the deallocate this specific *point's slot. */ |
| 2161 | ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot); |
| 2162 | |
| 2163 | hwdebug_insert_point (hw_breaks[i].hw_break, tid); |
| 2164 | } |
| 2165 | } |
| 2166 | else |
| 2167 | ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value); |
| 2168 | } |
| 2169 | |
| 2170 | static void |
| 2171 | ppc_linux_thread_exit (struct thread_info *tp, int silent) |
| 2172 | { |
| 2173 | int i; |
| 2174 | int tid = ptid_get_lwp (tp->ptid); |
| 2175 | struct hw_break_tuple *hw_breaks; |
| 2176 | struct thread_points *t = NULL, *p; |
| 2177 | |
| 2178 | if (!have_ptrace_hwdebug_interface ()) |
| 2179 | return; |
| 2180 | |
| 2181 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++) |
| 2182 | if (p->tid == tid) |
| 2183 | { |
| 2184 | t = p; |
| 2185 | break; |
| 2186 | } |
| 2187 | |
| 2188 | if (t == NULL) |
| 2189 | return; |
| 2190 | |
| 2191 | VEC_unordered_remove (thread_points_p, ppc_threads, i); |
| 2192 | |
| 2193 | hw_breaks = t->hw_breaks; |
| 2194 | |
| 2195 | for (i = 0; i < max_slots_number; i++) |
| 2196 | if (hw_breaks[i].hw_break) |
| 2197 | xfree (hw_breaks[i].hw_break); |
| 2198 | |
| 2199 | xfree (t->hw_breaks); |
| 2200 | xfree (t); |
| 2201 | } |
| 2202 | |
| 2203 | static int |
| 2204 | ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) |
| 2205 | { |
| 2206 | siginfo_t siginfo; |
| 2207 | |
| 2208 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) |
| 2209 | return 0; |
| 2210 | |
| 2211 | if (siginfo.si_signo != SIGTRAP |
| 2212 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) |
| 2213 | return 0; |
| 2214 | |
| 2215 | if (have_ptrace_hwdebug_interface ()) |
| 2216 | { |
| 2217 | int i; |
| 2218 | struct thread_points *t; |
| 2219 | struct hw_break_tuple *hw_breaks; |
| 2220 | /* The index (or slot) of the *point is passed in the si_errno field. */ |
| 2221 | int slot = siginfo.si_errno; |
| 2222 | |
| 2223 | t = hwdebug_find_thread_points_by_tid (ptid_get_lwp (inferior_ptid), 0); |
| 2224 | |
| 2225 | /* Find out if this *point is a hardware breakpoint. |
| 2226 | If so, we should return 0. */ |
| 2227 | if (t) |
| 2228 | { |
| 2229 | hw_breaks = t->hw_breaks; |
| 2230 | for (i = 0; i < max_slots_number; i++) |
| 2231 | if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot |
| 2232 | && hw_breaks[i].hw_break->trigger_type |
| 2233 | == PPC_BREAKPOINT_TRIGGER_EXECUTE) |
| 2234 | return 0; |
| 2235 | } |
| 2236 | } |
| 2237 | |
| 2238 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
| 2239 | return 1; |
| 2240 | } |
| 2241 | |
| 2242 | static int |
| 2243 | ppc_linux_stopped_by_watchpoint (struct target_ops *ops) |
| 2244 | { |
| 2245 | CORE_ADDR addr; |
| 2246 | return ppc_linux_stopped_data_address (ops, &addr); |
| 2247 | } |
| 2248 | |
| 2249 | static int |
| 2250 | ppc_linux_watchpoint_addr_within_range (struct target_ops *target, |
| 2251 | CORE_ADDR addr, |
| 2252 | CORE_ADDR start, int length) |
| 2253 | { |
| 2254 | int mask; |
| 2255 | |
| 2256 | if (have_ptrace_hwdebug_interface () |
| 2257 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
| 2258 | return start <= addr && start + length >= addr; |
| 2259 | else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
| 2260 | mask = 3; |
| 2261 | else |
| 2262 | mask = 7; |
| 2263 | |
| 2264 | addr &= ~mask; |
| 2265 | |
| 2266 | /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */ |
| 2267 | return start <= addr + mask && start + length - 1 >= addr; |
| 2268 | } |
| 2269 | |
| 2270 | /* Return the number of registers needed for a masked hardware watchpoint. */ |
| 2271 | |
| 2272 | static int |
| 2273 | ppc_linux_masked_watch_num_registers (struct target_ops *target, |
| 2274 | CORE_ADDR addr, CORE_ADDR mask) |
| 2275 | { |
| 2276 | if (!have_ptrace_hwdebug_interface () |
| 2277 | || (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0) |
| 2278 | return -1; |
| 2279 | else if ((mask & 0xC0000000) != 0xC0000000) |
| 2280 | { |
| 2281 | warning (_("The given mask covers kernel address space " |
| 2282 | "and cannot be used.\n")); |
| 2283 | |
| 2284 | return -2; |
| 2285 | } |
| 2286 | else |
| 2287 | return 2; |
| 2288 | } |
| 2289 | |
| 2290 | static void |
| 2291 | ppc_linux_store_inferior_registers (struct target_ops *ops, |
| 2292 | struct regcache *regcache, int regno) |
| 2293 | { |
| 2294 | /* Overload thread id onto process id. */ |
| 2295 | int tid = ptid_get_lwp (inferior_ptid); |
| 2296 | |
| 2297 | /* No thread id, just use process id. */ |
| 2298 | if (tid == 0) |
| 2299 | tid = ptid_get_pid (inferior_ptid); |
| 2300 | |
| 2301 | if (regno >= 0) |
| 2302 | store_register (regcache, tid, regno); |
| 2303 | else |
| 2304 | store_ppc_registers (regcache, tid); |
| 2305 | } |
| 2306 | |
| 2307 | /* Functions for transferring registers between a gregset_t or fpregset_t |
| 2308 | (see sys/ucontext.h) and gdb's regcache. The word size is that used |
| 2309 | by the ptrace interface, not the current program's ABI. Eg. if a |
| 2310 | powerpc64-linux gdb is being used to debug a powerpc32-linux app, we |
| 2311 | read or write 64-bit gregsets. This is to suit the host libthread_db. */ |
| 2312 | |
| 2313 | void |
| 2314 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
| 2315 | { |
| 2316 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
| 2317 | |
| 2318 | ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp)); |
| 2319 | } |
| 2320 | |
| 2321 | void |
| 2322 | fill_gregset (const struct regcache *regcache, |
| 2323 | gdb_gregset_t *gregsetp, int regno) |
| 2324 | { |
| 2325 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
| 2326 | |
| 2327 | if (regno == -1) |
| 2328 | memset (gregsetp, 0, sizeof (*gregsetp)); |
| 2329 | ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp)); |
| 2330 | } |
| 2331 | |
| 2332 | void |
| 2333 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp) |
| 2334 | { |
| 2335 | const struct regset *regset = ppc_linux_fpregset (); |
| 2336 | |
| 2337 | ppc_supply_fpregset (regset, regcache, -1, |
| 2338 | fpregsetp, sizeof (*fpregsetp)); |
| 2339 | } |
| 2340 | |
| 2341 | void |
| 2342 | fill_fpregset (const struct regcache *regcache, |
| 2343 | gdb_fpregset_t *fpregsetp, int regno) |
| 2344 | { |
| 2345 | const struct regset *regset = ppc_linux_fpregset (); |
| 2346 | |
| 2347 | ppc_collect_fpregset (regset, regcache, regno, |
| 2348 | fpregsetp, sizeof (*fpregsetp)); |
| 2349 | } |
| 2350 | |
| 2351 | static int |
| 2352 | ppc_linux_target_wordsize (void) |
| 2353 | { |
| 2354 | int wordsize = 4; |
| 2355 | |
| 2356 | /* Check for 64-bit inferior process. This is the case when the host is |
| 2357 | 64-bit, and in addition the top bit of the MSR register is set. */ |
| 2358 | #ifdef __powerpc64__ |
| 2359 | long msr; |
| 2360 | |
| 2361 | int tid = ptid_get_lwp (inferior_ptid); |
| 2362 | if (tid == 0) |
| 2363 | tid = ptid_get_pid (inferior_ptid); |
| 2364 | |
| 2365 | errno = 0; |
| 2366 | msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0); |
| 2367 | if (errno == 0 && ppc64_64bit_inferior_p (msr)) |
| 2368 | wordsize = 8; |
| 2369 | #endif |
| 2370 | |
| 2371 | return wordsize; |
| 2372 | } |
| 2373 | |
| 2374 | static int |
| 2375 | ppc_linux_auxv_parse (struct target_ops *ops, gdb_byte **readptr, |
| 2376 | gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp) |
| 2377 | { |
| 2378 | int sizeof_auxv_field = ppc_linux_target_wordsize (); |
| 2379 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); |
| 2380 | gdb_byte *ptr = *readptr; |
| 2381 | |
| 2382 | if (endptr == ptr) |
| 2383 | return 0; |
| 2384 | |
| 2385 | if (endptr - ptr < sizeof_auxv_field * 2) |
| 2386 | return -1; |
| 2387 | |
| 2388 | *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
| 2389 | ptr += sizeof_auxv_field; |
| 2390 | *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
| 2391 | ptr += sizeof_auxv_field; |
| 2392 | |
| 2393 | *readptr = ptr; |
| 2394 | return 1; |
| 2395 | } |
| 2396 | |
| 2397 | static const struct target_desc * |
| 2398 | ppc_linux_read_description (struct target_ops *ops) |
| 2399 | { |
| 2400 | int altivec = 0; |
| 2401 | int vsx = 0; |
| 2402 | int isa205 = 0; |
| 2403 | int cell = 0; |
| 2404 | |
| 2405 | int tid = ptid_get_lwp (inferior_ptid); |
| 2406 | if (tid == 0) |
| 2407 | tid = ptid_get_pid (inferior_ptid); |
| 2408 | |
| 2409 | if (have_ptrace_getsetevrregs) |
| 2410 | { |
| 2411 | struct gdb_evrregset_t evrregset; |
| 2412 | |
| 2413 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0) |
| 2414 | return tdesc_powerpc_e500l; |
| 2415 | |
| 2416 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported. |
| 2417 | Anything else needs to be reported. */ |
| 2418 | else if (errno != EIO) |
| 2419 | perror_with_name (_("Unable to fetch SPE registers")); |
| 2420 | } |
| 2421 | |
| 2422 | if (have_ptrace_getsetvsxregs) |
| 2423 | { |
| 2424 | gdb_vsxregset_t vsxregset; |
| 2425 | |
| 2426 | if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0) |
| 2427 | vsx = 1; |
| 2428 | |
| 2429 | /* EIO means that the PTRACE_GETVSXREGS request isn't supported. |
| 2430 | Anything else needs to be reported. */ |
| 2431 | else if (errno != EIO) |
| 2432 | perror_with_name (_("Unable to fetch VSX registers")); |
| 2433 | } |
| 2434 | |
| 2435 | if (have_ptrace_getvrregs) |
| 2436 | { |
| 2437 | gdb_vrregset_t vrregset; |
| 2438 | |
| 2439 | if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0) |
| 2440 | altivec = 1; |
| 2441 | |
| 2442 | /* EIO means that the PTRACE_GETVRREGS request isn't supported. |
| 2443 | Anything else needs to be reported. */ |
| 2444 | else if (errno != EIO) |
| 2445 | perror_with_name (_("Unable to fetch AltiVec registers")); |
| 2446 | } |
| 2447 | |
| 2448 | /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases |
| 2449 | the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this |
| 2450 | ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only |
| 2451 | PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher |
| 2452 | half of the register are for Decimal Floating Point, we check if that |
| 2453 | feature is available to decide the size of the FPSCR. */ |
| 2454 | if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP) |
| 2455 | isa205 = 1; |
| 2456 | |
| 2457 | if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL) |
| 2458 | cell = 1; |
| 2459 | |
| 2460 | if (ppc_linux_target_wordsize () == 8) |
| 2461 | { |
| 2462 | if (cell) |
| 2463 | return tdesc_powerpc_cell64l; |
| 2464 | else if (vsx) |
| 2465 | return isa205? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l; |
| 2466 | else if (altivec) |
| 2467 | return isa205 |
| 2468 | ? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l; |
| 2469 | |
| 2470 | return isa205? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l; |
| 2471 | } |
| 2472 | |
| 2473 | if (cell) |
| 2474 | return tdesc_powerpc_cell32l; |
| 2475 | else if (vsx) |
| 2476 | return isa205? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l; |
| 2477 | else if (altivec) |
| 2478 | return isa205? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l; |
| 2479 | |
| 2480 | return isa205? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l; |
| 2481 | } |
| 2482 | |
| 2483 | void _initialize_ppc_linux_nat (void); |
| 2484 | |
| 2485 | void |
| 2486 | _initialize_ppc_linux_nat (void) |
| 2487 | { |
| 2488 | struct target_ops *t; |
| 2489 | |
| 2490 | /* Fill in the generic GNU/Linux methods. */ |
| 2491 | t = linux_target (); |
| 2492 | |
| 2493 | /* Add our register access methods. */ |
| 2494 | t->to_fetch_registers = ppc_linux_fetch_inferior_registers; |
| 2495 | t->to_store_registers = ppc_linux_store_inferior_registers; |
| 2496 | |
| 2497 | /* Add our breakpoint/watchpoint methods. */ |
| 2498 | t->to_can_use_hw_breakpoint = ppc_linux_can_use_hw_breakpoint; |
| 2499 | t->to_insert_hw_breakpoint = ppc_linux_insert_hw_breakpoint; |
| 2500 | t->to_remove_hw_breakpoint = ppc_linux_remove_hw_breakpoint; |
| 2501 | t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint; |
| 2502 | t->to_insert_watchpoint = ppc_linux_insert_watchpoint; |
| 2503 | t->to_remove_watchpoint = ppc_linux_remove_watchpoint; |
| 2504 | t->to_insert_mask_watchpoint = ppc_linux_insert_mask_watchpoint; |
| 2505 | t->to_remove_mask_watchpoint = ppc_linux_remove_mask_watchpoint; |
| 2506 | t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint; |
| 2507 | t->to_stopped_data_address = ppc_linux_stopped_data_address; |
| 2508 | t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range; |
| 2509 | t->to_can_accel_watchpoint_condition |
| 2510 | = ppc_linux_can_accel_watchpoint_condition; |
| 2511 | t->to_masked_watch_num_registers = ppc_linux_masked_watch_num_registers; |
| 2512 | t->to_ranged_break_num_registers = ppc_linux_ranged_break_num_registers; |
| 2513 | |
| 2514 | t->to_read_description = ppc_linux_read_description; |
| 2515 | t->to_auxv_parse = ppc_linux_auxv_parse; |
| 2516 | |
| 2517 | observer_attach_thread_exit (ppc_linux_thread_exit); |
| 2518 | |
| 2519 | /* Register the target. */ |
| 2520 | linux_nat_add_target (t); |
| 2521 | linux_nat_set_new_thread (t, ppc_linux_new_thread); |
| 2522 | } |