| 1 | /* Target-dependent code for the RISC-V architecture, for GDB. |
| 2 | |
| 3 | Copyright (C) 2018 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #include "defs.h" |
| 21 | #include "frame.h" |
| 22 | #include "inferior.h" |
| 23 | #include "symtab.h" |
| 24 | #include "value.h" |
| 25 | #include "gdbcmd.h" |
| 26 | #include "language.h" |
| 27 | #include "gdbcore.h" |
| 28 | #include "symfile.h" |
| 29 | #include "objfiles.h" |
| 30 | #include "gdbtypes.h" |
| 31 | #include "target.h" |
| 32 | #include "arch-utils.h" |
| 33 | #include "regcache.h" |
| 34 | #include "osabi.h" |
| 35 | #include "riscv-tdep.h" |
| 36 | #include "block.h" |
| 37 | #include "reggroups.h" |
| 38 | #include "opcode/riscv.h" |
| 39 | #include "elf/riscv.h" |
| 40 | #include "elf-bfd.h" |
| 41 | #include "symcat.h" |
| 42 | #include "dis-asm.h" |
| 43 | #include "frame-unwind.h" |
| 44 | #include "frame-base.h" |
| 45 | #include "trad-frame.h" |
| 46 | #include "infcall.h" |
| 47 | #include "floatformat.h" |
| 48 | #include "remote.h" |
| 49 | #include "target-descriptions.h" |
| 50 | #include "dwarf2-frame.h" |
| 51 | #include "user-regs.h" |
| 52 | #include "valprint.h" |
| 53 | #include "common-defs.h" |
| 54 | #include "opcode/riscv-opc.h" |
| 55 | #include "cli/cli-decode.h" |
| 56 | #include "observable.h" |
| 57 | |
| 58 | /* The stack must be 16-byte aligned. */ |
| 59 | #define SP_ALIGNMENT 16 |
| 60 | |
| 61 | /* Forward declarations. */ |
| 62 | static bool riscv_has_feature (struct gdbarch *gdbarch, char feature); |
| 63 | struct riscv_inferior_data; |
| 64 | struct riscv_inferior_data * riscv_inferior_data (struct inferior *const inf); |
| 65 | |
| 66 | /* Define a series of is_XXX_insn functions to check if the value INSN |
| 67 | is an instance of instruction XXX. */ |
| 68 | #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \ |
| 69 | static inline bool is_ ## INSN_NAME ## _insn (long insn) \ |
| 70 | { \ |
| 71 | return (insn & INSN_MASK) == INSN_MATCH; \ |
| 72 | } |
| 73 | #include "opcode/riscv-opc.h" |
| 74 | #undef DECLARE_INSN |
| 75 | |
| 76 | /* Per inferior information for RiscV. */ |
| 77 | |
| 78 | struct riscv_inferior_data |
| 79 | { |
| 80 | /* True when MISA_VALUE is valid, otherwise false. */ |
| 81 | bool misa_read; |
| 82 | |
| 83 | /* If MISA_READ is true then MISA_VALUE holds the value of the MISA |
| 84 | register read from the target. */ |
| 85 | uint32_t misa_value; |
| 86 | }; |
| 87 | |
| 88 | /* Key created when the RiscV per-inferior data is registered. */ |
| 89 | |
| 90 | static const struct inferior_data *riscv_inferior_data_reg; |
| 91 | |
| 92 | /* Architectural name for core registers. */ |
| 93 | |
| 94 | static const char * const riscv_gdb_reg_names[RISCV_LAST_FP_REGNUM + 1] = |
| 95 | { |
| 96 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", |
| 97 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", |
| 98 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", |
| 99 | "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", |
| 100 | "pc", |
| 101 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 102 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 103 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 104 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 105 | }; |
| 106 | |
| 107 | /* Maps "pretty" register names onto their GDB register number. */ |
| 108 | |
| 109 | struct register_alias |
| 110 | { |
| 111 | /* The register alias. Usually more descriptive than the |
| 112 | architectural name of the register. */ |
| 113 | const char *name; |
| 114 | |
| 115 | /* The GDB register number. */ |
| 116 | int regnum; |
| 117 | }; |
| 118 | |
| 119 | /* Table of register aliases. */ |
| 120 | |
| 121 | static const struct register_alias riscv_register_aliases[] = |
| 122 | { |
| 123 | { "zero", 0 }, |
| 124 | { "ra", 1 }, |
| 125 | { "sp", 2 }, |
| 126 | { "gp", 3 }, |
| 127 | { "tp", 4 }, |
| 128 | { "t0", 5 }, |
| 129 | { "t1", 6 }, |
| 130 | { "t2", 7 }, |
| 131 | { "fp", 8 }, |
| 132 | { "s0", 8 }, |
| 133 | { "s1", 9 }, |
| 134 | { "a0", 10 }, |
| 135 | { "a1", 11 }, |
| 136 | { "a2", 12 }, |
| 137 | { "a3", 13 }, |
| 138 | { "a4", 14 }, |
| 139 | { "a5", 15 }, |
| 140 | { "a6", 16 }, |
| 141 | { "a7", 17 }, |
| 142 | { "s2", 18 }, |
| 143 | { "s3", 19 }, |
| 144 | { "s4", 20 }, |
| 145 | { "s5", 21 }, |
| 146 | { "s6", 22 }, |
| 147 | { "s7", 23 }, |
| 148 | { "s8", 24 }, |
| 149 | { "s9", 25 }, |
| 150 | { "s10", 26 }, |
| 151 | { "s11", 27 }, |
| 152 | { "t3", 28 }, |
| 153 | { "t4", 29 }, |
| 154 | { "t5", 30 }, |
| 155 | { "t6", 31 }, |
| 156 | /* pc is 32. */ |
| 157 | { "ft0", 33 }, |
| 158 | { "ft1", 34 }, |
| 159 | { "ft2", 35 }, |
| 160 | { "ft3", 36 }, |
| 161 | { "ft4", 37 }, |
| 162 | { "ft5", 38 }, |
| 163 | { "ft6", 39 }, |
| 164 | { "ft7", 40 }, |
| 165 | { "fs0", 41 }, |
| 166 | { "fs1", 42 }, |
| 167 | { "fa0", 43 }, |
| 168 | { "fa1", 44 }, |
| 169 | { "fa2", 45 }, |
| 170 | { "fa3", 46 }, |
| 171 | { "fa4", 47 }, |
| 172 | { "fa5", 48 }, |
| 173 | { "fa6", 49 }, |
| 174 | { "fa7", 50 }, |
| 175 | { "fs2", 51 }, |
| 176 | { "fs3", 52 }, |
| 177 | { "fs4", 53 }, |
| 178 | { "fs5", 54 }, |
| 179 | { "fs6", 55 }, |
| 180 | { "fs7", 56 }, |
| 181 | { "fs8", 57 }, |
| 182 | { "fs9", 58 }, |
| 183 | { "fs10", 59 }, |
| 184 | { "fs11", 60 }, |
| 185 | { "ft8", 61 }, |
| 186 | { "ft9", 62 }, |
| 187 | { "ft10", 63 }, |
| 188 | { "ft11", 64 }, |
| 189 | #define DECLARE_CSR(name, num) { #name, (num) + 65 }, |
| 190 | #include "opcode/riscv-opc.h" |
| 191 | #undef DECLARE_CSR |
| 192 | }; |
| 193 | |
| 194 | /* Controls whether we place compressed breakpoints or not. When in auto |
| 195 | mode GDB tries to determine if the target supports compressed |
| 196 | breakpoints, and uses them if it does. */ |
| 197 | |
| 198 | static enum auto_boolean use_compressed_breakpoints; |
| 199 | |
| 200 | /* The show callback for 'show riscv use-compressed-breakpoints'. */ |
| 201 | |
| 202 | static void |
| 203 | show_use_compressed_breakpoints (struct ui_file *file, int from_tty, |
| 204 | struct cmd_list_element *c, |
| 205 | const char *value) |
| 206 | { |
| 207 | const char *additional_info; |
| 208 | struct gdbarch *gdbarch = target_gdbarch (); |
| 209 | |
| 210 | if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO) |
| 211 | if (riscv_has_feature (gdbarch, 'C')) |
| 212 | additional_info = _(" (currently on)"); |
| 213 | else |
| 214 | additional_info = _(" (currently off)"); |
| 215 | else |
| 216 | additional_info = ""; |
| 217 | |
| 218 | fprintf_filtered (file, |
| 219 | _("Debugger's use of compressed breakpoints is set " |
| 220 | "to %s%s.\n"), value, additional_info); |
| 221 | } |
| 222 | |
| 223 | /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */ |
| 224 | |
| 225 | static struct cmd_list_element *setriscvcmdlist = NULL; |
| 226 | static struct cmd_list_element *showriscvcmdlist = NULL; |
| 227 | |
| 228 | /* The show callback for the 'show riscv' prefix command. */ |
| 229 | |
| 230 | static void |
| 231 | show_riscv_command (const char *args, int from_tty) |
| 232 | { |
| 233 | help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout); |
| 234 | } |
| 235 | |
| 236 | /* The set callback for the 'set riscv' prefix command. */ |
| 237 | |
| 238 | static void |
| 239 | set_riscv_command (const char *args, int from_tty) |
| 240 | { |
| 241 | printf_unfiltered |
| 242 | (_("\"set riscv\" must be followed by an appropriate subcommand.\n")); |
| 243 | help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout); |
| 244 | } |
| 245 | |
| 246 | /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */ |
| 247 | |
| 248 | static struct cmd_list_element *setdebugriscvcmdlist = NULL; |
| 249 | static struct cmd_list_element *showdebugriscvcmdlist = NULL; |
| 250 | |
| 251 | /* The show callback for the 'show debug riscv' prefix command. */ |
| 252 | |
| 253 | static void |
| 254 | show_debug_riscv_command (const char *args, int from_tty) |
| 255 | { |
| 256 | help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout); |
| 257 | } |
| 258 | |
| 259 | /* The set callback for the 'set debug riscv' prefix command. */ |
| 260 | |
| 261 | static void |
| 262 | set_debug_riscv_command (const char *args, int from_tty) |
| 263 | { |
| 264 | printf_unfiltered |
| 265 | (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n")); |
| 266 | help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout); |
| 267 | } |
| 268 | |
| 269 | /* The show callback for all 'show debug riscv VARNAME' variables. */ |
| 270 | |
| 271 | static void |
| 272 | show_riscv_debug_variable (struct ui_file *file, int from_tty, |
| 273 | struct cmd_list_element *c, |
| 274 | const char *value) |
| 275 | { |
| 276 | fprintf_filtered (file, |
| 277 | _("RiscV debug variable `%s' is set to: %s\n"), |
| 278 | c->name, value); |
| 279 | } |
| 280 | |
| 281 | /* When this is set to non-zero debugging information about inferior calls |
| 282 | will be printed. */ |
| 283 | |
| 284 | static unsigned int riscv_debug_infcall = 0; |
| 285 | |
| 286 | /* Read the MISA register from the target. The register will only be read |
| 287 | once, and the value read will be cached. If the register can't be read |
| 288 | from the target then a default value (0) will be returned. If the |
| 289 | pointer READ_P is not null, then the bool pointed to is updated to |
| 290 | indicate if the value returned was read from the target (true) or is the |
| 291 | default (false). */ |
| 292 | |
| 293 | static uint32_t |
| 294 | riscv_read_misa_reg (bool *read_p) |
| 295 | { |
| 296 | struct riscv_inferior_data *inf_data |
| 297 | = riscv_inferior_data (current_inferior ()); |
| 298 | |
| 299 | if (!inf_data->misa_read && target_has_registers) |
| 300 | { |
| 301 | uint32_t value = 0; |
| 302 | struct frame_info *frame = get_current_frame (); |
| 303 | |
| 304 | TRY |
| 305 | { |
| 306 | value = get_frame_register_unsigned (frame, RISCV_CSR_MISA_REGNUM); |
| 307 | } |
| 308 | CATCH (ex, RETURN_MASK_ERROR) |
| 309 | { |
| 310 | /* Old cores might have MISA located at a different offset. */ |
| 311 | value = get_frame_register_unsigned (frame, |
| 312 | RISCV_CSR_LEGACY_MISA_REGNUM); |
| 313 | } |
| 314 | END_CATCH |
| 315 | |
| 316 | inf_data->misa_read = true; |
| 317 | inf_data->misa_value = value; |
| 318 | } |
| 319 | |
| 320 | if (read_p != nullptr) |
| 321 | *read_p = inf_data->misa_read; |
| 322 | |
| 323 | return inf_data->misa_value; |
| 324 | } |
| 325 | |
| 326 | /* Return true if FEATURE is available for the architecture GDBARCH. The |
| 327 | FEATURE should be one of the single character feature codes described in |
| 328 | the RiscV ISA manual, these are between 'A' and 'Z'. */ |
| 329 | |
| 330 | static bool |
| 331 | riscv_has_feature (struct gdbarch *gdbarch, char feature) |
| 332 | { |
| 333 | bool have_read_misa = false; |
| 334 | uint32_t misa; |
| 335 | |
| 336 | gdb_assert (feature >= 'A' && feature <= 'Z'); |
| 337 | |
| 338 | /* It would be nice to always check with the real target where possible, |
| 339 | however, for compressed instructions this is a bad idea. |
| 340 | |
| 341 | The call to `set_gdbarch_decr_pc_after_break' is made just once per |
| 342 | GDBARCH and we decide at that point if we should decrement by 2 or 4 |
| 343 | bytes based on whether the BFD has compressed instruction support or |
| 344 | not. |
| 345 | |
| 346 | If the BFD was not compiled with compressed instruction support, but we |
| 347 | are running on a target with compressed instructions then we might |
| 348 | place a 4-byte breakpoint, then decrement the $pc by 2 bytes leading to |
| 349 | confusion. |
| 350 | |
| 351 | It's safer if we just make decisions about compressed instruction |
| 352 | support based on the BFD. */ |
| 353 | if (feature != 'C') |
| 354 | misa = riscv_read_misa_reg (&have_read_misa); |
| 355 | if (!have_read_misa || misa == 0) |
| 356 | misa = gdbarch_tdep (gdbarch)->core_features; |
| 357 | |
| 358 | return (misa & (1 << (feature - 'A'))) != 0; |
| 359 | } |
| 360 | |
| 361 | /* Return the width in bytes of the general purpose registers for GDBARCH. |
| 362 | Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or |
| 363 | RV128. */ |
| 364 | |
| 365 | static int |
| 366 | riscv_isa_xlen (struct gdbarch *gdbarch) |
| 367 | { |
| 368 | switch (gdbarch_tdep (gdbarch)->abi.fields.base_len) |
| 369 | { |
| 370 | default: |
| 371 | warning (_("unknown xlen size, assuming 4 bytes")); |
| 372 | case 1: |
| 373 | return 4; |
| 374 | case 2: |
| 375 | return 8; |
| 376 | case 3: |
| 377 | return 16; |
| 378 | } |
| 379 | } |
| 380 | |
| 381 | /* Return the width in bytes of the floating point registers for GDBARCH. |
| 382 | If this architecture has no floating point registers, then return 0. |
| 383 | Possible values are 4, 8, or 16 for depending on which of single, double |
| 384 | or quad floating point support is available. */ |
| 385 | |
| 386 | static int |
| 387 | riscv_isa_flen (struct gdbarch *gdbarch) |
| 388 | { |
| 389 | if (riscv_has_feature (gdbarch, 'Q')) |
| 390 | return 16; |
| 391 | else if (riscv_has_feature (gdbarch, 'D')) |
| 392 | return 8; |
| 393 | else if (riscv_has_feature (gdbarch, 'F')) |
| 394 | return 4; |
| 395 | |
| 396 | return 0; |
| 397 | } |
| 398 | |
| 399 | /* Return true if the target for GDBARCH has floating point hardware. */ |
| 400 | |
| 401 | static bool |
| 402 | riscv_has_fp_regs (struct gdbarch *gdbarch) |
| 403 | { |
| 404 | return (riscv_isa_flen (gdbarch) > 0); |
| 405 | } |
| 406 | |
| 407 | /* Return true if GDBARCH is using any of the floating point hardware ABIs. */ |
| 408 | |
| 409 | static bool |
| 410 | riscv_has_fp_abi (struct gdbarch *gdbarch) |
| 411 | { |
| 412 | return (gdbarch_tdep (gdbarch)->abi.fields.float_abi != 0); |
| 413 | } |
| 414 | |
| 415 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
| 416 | |
| 417 | static int |
| 418 | riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) |
| 419 | { |
| 420 | if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO) |
| 421 | { |
| 422 | if (riscv_has_feature (gdbarch, 'C')) |
| 423 | return 2; |
| 424 | else |
| 425 | return 4; |
| 426 | } |
| 427 | else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE) |
| 428 | return 2; |
| 429 | else |
| 430 | return 4; |
| 431 | } |
| 432 | |
| 433 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
| 434 | |
| 435 | static const gdb_byte * |
| 436 | riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) |
| 437 | { |
| 438 | static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, }; |
| 439 | static const gdb_byte c_ebreak[] = { 0x02, 0x90 }; |
| 440 | |
| 441 | *size = kind; |
| 442 | switch (kind) |
| 443 | { |
| 444 | case 2: |
| 445 | return c_ebreak; |
| 446 | case 4: |
| 447 | return ebreak; |
| 448 | default: |
| 449 | gdb_assert_not_reached (_("unhandled breakpoint kind")); |
| 450 | } |
| 451 | } |
| 452 | |
| 453 | /* Callback function for user_reg_add. */ |
| 454 | |
| 455 | static struct value * |
| 456 | value_of_riscv_user_reg (struct frame_info *frame, const void *baton) |
| 457 | { |
| 458 | const int *reg_p = (const int *) baton; |
| 459 | return value_of_register (*reg_p, frame); |
| 460 | } |
| 461 | |
| 462 | /* Implement the register_name gdbarch method. */ |
| 463 | |
| 464 | static const char * |
| 465 | riscv_register_name (struct gdbarch *gdbarch, int regnum) |
| 466 | { |
| 467 | /* Prefer to use the alias. */ |
| 468 | if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_REGNUM) |
| 469 | { |
| 470 | int i; |
| 471 | |
| 472 | for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) |
| 473 | if (regnum == riscv_register_aliases[i].regnum) |
| 474 | return riscv_register_aliases[i].name; |
| 475 | } |
| 476 | |
| 477 | if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_FP_REGNUM) |
| 478 | return riscv_gdb_reg_names[regnum]; |
| 479 | |
| 480 | if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM) |
| 481 | { |
| 482 | static char buf[20]; |
| 483 | |
| 484 | xsnprintf (buf, sizeof (buf), "csr%d", |
| 485 | regnum - RISCV_FIRST_CSR_REGNUM); |
| 486 | return buf; |
| 487 | } |
| 488 | |
| 489 | if (regnum == RISCV_PRIV_REGNUM) |
| 490 | return "priv"; |
| 491 | |
| 492 | return NULL; |
| 493 | } |
| 494 | |
| 495 | /* Implement the register_type gdbarch method. */ |
| 496 | |
| 497 | static struct type * |
| 498 | riscv_register_type (struct gdbarch *gdbarch, int regnum) |
| 499 | { |
| 500 | int regsize; |
| 501 | |
| 502 | if (regnum < RISCV_FIRST_FP_REGNUM) |
| 503 | { |
| 504 | if (regnum == gdbarch_pc_regnum (gdbarch) |
| 505 | || regnum == RISCV_RA_REGNUM) |
| 506 | return builtin_type (gdbarch)->builtin_func_ptr; |
| 507 | |
| 508 | if (regnum == RISCV_FP_REGNUM |
| 509 | || regnum == RISCV_SP_REGNUM |
| 510 | || regnum == RISCV_GP_REGNUM |
| 511 | || regnum == RISCV_TP_REGNUM) |
| 512 | return builtin_type (gdbarch)->builtin_data_ptr; |
| 513 | |
| 514 | /* Remaining GPRs vary in size based on the current ISA. */ |
| 515 | regsize = riscv_isa_xlen (gdbarch); |
| 516 | switch (regsize) |
| 517 | { |
| 518 | case 4: |
| 519 | return builtin_type (gdbarch)->builtin_uint32; |
| 520 | case 8: |
| 521 | return builtin_type (gdbarch)->builtin_uint64; |
| 522 | case 16: |
| 523 | return builtin_type (gdbarch)->builtin_uint128; |
| 524 | default: |
| 525 | internal_error (__FILE__, __LINE__, |
| 526 | _("unknown isa regsize %i"), regsize); |
| 527 | } |
| 528 | } |
| 529 | else if (regnum <= RISCV_LAST_FP_REGNUM) |
| 530 | { |
| 531 | regsize = riscv_isa_xlen (gdbarch); |
| 532 | switch (regsize) |
| 533 | { |
| 534 | case 4: |
| 535 | return builtin_type (gdbarch)->builtin_float; |
| 536 | case 8: |
| 537 | return builtin_type (gdbarch)->builtin_double; |
| 538 | case 16: |
| 539 | return builtin_type (gdbarch)->builtin_long_double; |
| 540 | default: |
| 541 | internal_error (__FILE__, __LINE__, |
| 542 | _("unknown isa regsize %i"), regsize); |
| 543 | } |
| 544 | } |
| 545 | else if (regnum == RISCV_PRIV_REGNUM) |
| 546 | return builtin_type (gdbarch)->builtin_int8; |
| 547 | else |
| 548 | { |
| 549 | if (regnum == RISCV_CSR_FFLAGS_REGNUM |
| 550 | || regnum == RISCV_CSR_FRM_REGNUM |
| 551 | || regnum == RISCV_CSR_FCSR_REGNUM) |
| 552 | return builtin_type (gdbarch)->builtin_int32; |
| 553 | |
| 554 | regsize = riscv_isa_xlen (gdbarch); |
| 555 | switch (regsize) |
| 556 | { |
| 557 | case 4: |
| 558 | return builtin_type (gdbarch)->builtin_int32; |
| 559 | case 8: |
| 560 | return builtin_type (gdbarch)->builtin_int64; |
| 561 | case 16: |
| 562 | return builtin_type (gdbarch)->builtin_int128; |
| 563 | default: |
| 564 | internal_error (__FILE__, __LINE__, |
| 565 | _("unknown isa regsize %i"), regsize); |
| 566 | } |
| 567 | } |
| 568 | } |
| 569 | |
| 570 | /* Helper for riscv_print_registers_info, prints info for a single register |
| 571 | REGNUM. */ |
| 572 | |
| 573 | static void |
| 574 | riscv_print_one_register_info (struct gdbarch *gdbarch, |
| 575 | struct ui_file *file, |
| 576 | struct frame_info *frame, |
| 577 | int regnum) |
| 578 | { |
| 579 | const char *name = gdbarch_register_name (gdbarch, regnum); |
| 580 | struct value *val = value_of_register (regnum, frame); |
| 581 | struct type *regtype = value_type (val); |
| 582 | int print_raw_format; |
| 583 | enum tab_stops { value_column_1 = 15 }; |
| 584 | |
| 585 | fputs_filtered (name, file); |
| 586 | print_spaces_filtered (value_column_1 - strlen (name), file); |
| 587 | |
| 588 | print_raw_format = (value_entirely_available (val) |
| 589 | && !value_optimized_out (val)); |
| 590 | |
| 591 | if (TYPE_CODE (regtype) == TYPE_CODE_FLT) |
| 592 | { |
| 593 | struct value_print_options opts; |
| 594 | const gdb_byte *valaddr = value_contents_for_printing (val); |
| 595 | enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (regtype)); |
| 596 | |
| 597 | get_user_print_options (&opts); |
| 598 | opts.deref_ref = 1; |
| 599 | |
| 600 | val_print (regtype, |
| 601 | value_embedded_offset (val), 0, |
| 602 | file, 0, val, &opts, current_language); |
| 603 | |
| 604 | if (print_raw_format) |
| 605 | { |
| 606 | fprintf_filtered (file, "\t(raw "); |
| 607 | print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order, |
| 608 | true); |
| 609 | fprintf_filtered (file, ")"); |
| 610 | } |
| 611 | } |
| 612 | else |
| 613 | { |
| 614 | struct value_print_options opts; |
| 615 | |
| 616 | /* Print the register in hex. */ |
| 617 | get_formatted_print_options (&opts, 'x'); |
| 618 | opts.deref_ref = 1; |
| 619 | val_print (regtype, |
| 620 | value_embedded_offset (val), 0, |
| 621 | file, 0, val, &opts, current_language); |
| 622 | |
| 623 | if (print_raw_format) |
| 624 | { |
| 625 | if (regnum == RISCV_CSR_MSTATUS_REGNUM) |
| 626 | { |
| 627 | LONGEST d; |
| 628 | int size = register_size (gdbarch, regnum); |
| 629 | unsigned xlen; |
| 630 | |
| 631 | d = value_as_long (val); |
| 632 | xlen = size * 4; |
| 633 | fprintf_filtered (file, |
| 634 | "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X " |
| 635 | "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X " |
| 636 | "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X", |
| 637 | (int) ((d >> (xlen - 1)) & 0x1), |
| 638 | (int) ((d >> 24) & 0x1f), |
| 639 | (int) ((d >> 19) & 0x1), |
| 640 | (int) ((d >> 18) & 0x1), |
| 641 | (int) ((d >> 17) & 0x1), |
| 642 | (int) ((d >> 15) & 0x3), |
| 643 | (int) ((d >> 13) & 0x3), |
| 644 | (int) ((d >> 11) & 0x3), |
| 645 | (int) ((d >> 9) & 0x3), |
| 646 | (int) ((d >> 8) & 0x1), |
| 647 | (int) ((d >> 7) & 0x1), |
| 648 | (int) ((d >> 6) & 0x1), |
| 649 | (int) ((d >> 5) & 0x1), |
| 650 | (int) ((d >> 4) & 0x1), |
| 651 | (int) ((d >> 3) & 0x1), |
| 652 | (int) ((d >> 2) & 0x1), |
| 653 | (int) ((d >> 1) & 0x1), |
| 654 | (int) ((d >> 0) & 0x1)); |
| 655 | } |
| 656 | else if (regnum == RISCV_CSR_MISA_REGNUM) |
| 657 | { |
| 658 | int base; |
| 659 | unsigned xlen, i; |
| 660 | LONGEST d; |
| 661 | |
| 662 | d = value_as_long (val); |
| 663 | base = d >> 30; |
| 664 | xlen = 16; |
| 665 | |
| 666 | for (; base > 0; base--) |
| 667 | xlen *= 2; |
| 668 | fprintf_filtered (file, "\tRV%d", xlen); |
| 669 | |
| 670 | for (i = 0; i < 26; i++) |
| 671 | { |
| 672 | if (d & (1 << i)) |
| 673 | fprintf_filtered (file, "%c", 'A' + i); |
| 674 | } |
| 675 | } |
| 676 | else if (regnum == RISCV_CSR_FCSR_REGNUM |
| 677 | || regnum == RISCV_CSR_FFLAGS_REGNUM |
| 678 | || regnum == RISCV_CSR_FRM_REGNUM) |
| 679 | { |
| 680 | LONGEST d; |
| 681 | |
| 682 | d = value_as_long (val); |
| 683 | |
| 684 | fprintf_filtered (file, "\t"); |
| 685 | if (regnum != RISCV_CSR_FRM_REGNUM) |
| 686 | fprintf_filtered (file, |
| 687 | "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d", |
| 688 | (int) ((d >> 5) & 0x7), |
| 689 | (int) ((d >> 4) & 0x1), |
| 690 | (int) ((d >> 3) & 0x1), |
| 691 | (int) ((d >> 2) & 0x1), |
| 692 | (int) ((d >> 1) & 0x1), |
| 693 | (int) ((d >> 0) & 0x1)); |
| 694 | |
| 695 | if (regnum != RISCV_CSR_FFLAGS_REGNUM) |
| 696 | { |
| 697 | static const char * const sfrm[] = |
| 698 | { |
| 699 | "RNE (round to nearest; ties to even)", |
| 700 | "RTZ (Round towards zero)", |
| 701 | "RDN (Round down towards -INF)", |
| 702 | "RUP (Round up towards +INF)", |
| 703 | "RMM (Round to nearest; ties to max magnitude)", |
| 704 | "INVALID[5]", |
| 705 | "INVALID[6]", |
| 706 | "dynamic rounding mode", |
| 707 | }; |
| 708 | int frm = ((regnum == RISCV_CSR_FCSR_REGNUM) |
| 709 | ? (d >> 5) : d) & 0x3; |
| 710 | |
| 711 | fprintf_filtered (file, "%sFRM:%i [%s]", |
| 712 | (regnum == RISCV_CSR_FCSR_REGNUM |
| 713 | ? " " : ""), |
| 714 | frm, sfrm[frm]); |
| 715 | } |
| 716 | } |
| 717 | else if (regnum == RISCV_PRIV_REGNUM) |
| 718 | { |
| 719 | LONGEST d; |
| 720 | uint8_t priv; |
| 721 | |
| 722 | d = value_as_long (val); |
| 723 | priv = d & 0xff; |
| 724 | |
| 725 | if (priv < 4) |
| 726 | { |
| 727 | static const char * const sprv[] = |
| 728 | { |
| 729 | "User/Application", |
| 730 | "Supervisor", |
| 731 | "Hypervisor", |
| 732 | "Machine" |
| 733 | }; |
| 734 | fprintf_filtered (file, "\tprv:%d [%s]", |
| 735 | priv, sprv[priv]); |
| 736 | } |
| 737 | else |
| 738 | fprintf_filtered (file, "\tprv:%d [INVALID]", priv); |
| 739 | } |
| 740 | else |
| 741 | { |
| 742 | /* If not a vector register, print it also according to its |
| 743 | natural format. */ |
| 744 | if (TYPE_VECTOR (regtype) == 0) |
| 745 | { |
| 746 | get_user_print_options (&opts); |
| 747 | opts.deref_ref = 1; |
| 748 | fprintf_filtered (file, "\t"); |
| 749 | val_print (regtype, |
| 750 | value_embedded_offset (val), 0, |
| 751 | file, 0, val, &opts, current_language); |
| 752 | } |
| 753 | } |
| 754 | } |
| 755 | } |
| 756 | fprintf_filtered (file, "\n"); |
| 757 | } |
| 758 | |
| 759 | /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member |
| 760 | of REGGROUP? */ |
| 761 | |
| 762 | static int |
| 763 | riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
| 764 | struct reggroup *reggroup) |
| 765 | { |
| 766 | int float_p; |
| 767 | int raw_p; |
| 768 | unsigned int i; |
| 769 | |
| 770 | /* Used by 'info registers' and 'info registers <groupname>'. */ |
| 771 | |
| 772 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
| 773 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') |
| 774 | return 0; |
| 775 | |
| 776 | if (reggroup == all_reggroup) |
| 777 | { |
| 778 | if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM) |
| 779 | return 1; |
| 780 | /* Only include CSRs that have aliases. */ |
| 781 | for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) |
| 782 | { |
| 783 | if (regnum == riscv_register_aliases[i].regnum) |
| 784 | return 1; |
| 785 | } |
| 786 | return 0; |
| 787 | } |
| 788 | else if (reggroup == float_reggroup) |
| 789 | return ((regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM) |
| 790 | || (regnum == RISCV_CSR_FCSR_REGNUM |
| 791 | || regnum == RISCV_CSR_FFLAGS_REGNUM |
| 792 | || regnum == RISCV_CSR_FRM_REGNUM)); |
| 793 | else if (reggroup == general_reggroup) |
| 794 | return regnum < RISCV_FIRST_FP_REGNUM; |
| 795 | else if (reggroup == restore_reggroup || reggroup == save_reggroup) |
| 796 | { |
| 797 | if (riscv_has_fp_regs (gdbarch)) |
| 798 | return regnum <= RISCV_LAST_FP_REGNUM; |
| 799 | else |
| 800 | return regnum < RISCV_FIRST_FP_REGNUM; |
| 801 | } |
| 802 | else if (reggroup == system_reggroup) |
| 803 | { |
| 804 | if (regnum == RISCV_PRIV_REGNUM) |
| 805 | return 1; |
| 806 | if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM) |
| 807 | return 0; |
| 808 | /* Only include CSRs that have aliases. */ |
| 809 | for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) |
| 810 | { |
| 811 | if (regnum == riscv_register_aliases[i].regnum) |
| 812 | return 1; |
| 813 | } |
| 814 | return 0; |
| 815 | } |
| 816 | else if (reggroup == vector_reggroup) |
| 817 | return 0; |
| 818 | else |
| 819 | return 0; |
| 820 | } |
| 821 | |
| 822 | /* Implement the print_registers_info gdbarch method. This is used by |
| 823 | 'info registers' and 'info all-registers'. */ |
| 824 | |
| 825 | static void |
| 826 | riscv_print_registers_info (struct gdbarch *gdbarch, |
| 827 | struct ui_file *file, |
| 828 | struct frame_info *frame, |
| 829 | int regnum, int print_all) |
| 830 | { |
| 831 | if (regnum != -1) |
| 832 | { |
| 833 | /* Print one specified register. */ |
| 834 | gdb_assert (regnum <= RISCV_LAST_REGNUM); |
| 835 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
| 836 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') |
| 837 | error (_("Not a valid register for the current processor type")); |
| 838 | riscv_print_one_register_info (gdbarch, file, frame, regnum); |
| 839 | } |
| 840 | else |
| 841 | { |
| 842 | struct reggroup *reggroup; |
| 843 | |
| 844 | if (print_all) |
| 845 | reggroup = all_reggroup; |
| 846 | else |
| 847 | reggroup = general_reggroup; |
| 848 | |
| 849 | for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum) |
| 850 | { |
| 851 | /* Zero never changes, so might as well hide by default. */ |
| 852 | if (regnum == RISCV_ZERO_REGNUM && !print_all) |
| 853 | continue; |
| 854 | |
| 855 | /* Registers with no name are not valid on this ISA. */ |
| 856 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
| 857 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') |
| 858 | continue; |
| 859 | |
| 860 | /* Is the register in the group we're interested in? */ |
| 861 | if (!riscv_register_reggroup_p (gdbarch, regnum, reggroup)) |
| 862 | continue; |
| 863 | |
| 864 | riscv_print_one_register_info (gdbarch, file, frame, regnum); |
| 865 | } |
| 866 | } |
| 867 | } |
| 868 | |
| 869 | /* Class that handles one decoded RiscV instruction. */ |
| 870 | |
| 871 | class riscv_insn |
| 872 | { |
| 873 | public: |
| 874 | |
| 875 | /* Enum of all the opcodes that GDB cares about during the prologue scan. */ |
| 876 | enum opcode |
| 877 | { |
| 878 | /* Unknown value is used at initialisation time. */ |
| 879 | UNKNOWN = 0, |
| 880 | |
| 881 | /* These instructions are all the ones we are interested in during the |
| 882 | prologue scan. */ |
| 883 | ADD, |
| 884 | ADDI, |
| 885 | ADDIW, |
| 886 | ADDW, |
| 887 | AUIPC, |
| 888 | LUI, |
| 889 | SD, |
| 890 | SW, |
| 891 | |
| 892 | /* Other instructions are not interesting during the prologue scan, and |
| 893 | are ignored. */ |
| 894 | OTHER |
| 895 | }; |
| 896 | |
| 897 | riscv_insn () |
| 898 | : m_length (0), |
| 899 | m_opcode (OTHER), |
| 900 | m_rd (0), |
| 901 | m_rs1 (0), |
| 902 | m_rs2 (0) |
| 903 | { |
| 904 | /* Nothing. */ |
| 905 | } |
| 906 | |
| 907 | void decode (struct gdbarch *gdbarch, CORE_ADDR pc); |
| 908 | |
| 909 | /* Get the length of the instruction in bytes. */ |
| 910 | int length () const |
| 911 | { return m_length; } |
| 912 | |
| 913 | /* Get the opcode for this instruction. */ |
| 914 | enum opcode opcode () const |
| 915 | { return m_opcode; } |
| 916 | |
| 917 | /* Get destination register field for this instruction. This is only |
| 918 | valid if the OPCODE implies there is such a field for this |
| 919 | instruction. */ |
| 920 | int rd () const |
| 921 | { return m_rd; } |
| 922 | |
| 923 | /* Get the RS1 register field for this instruction. This is only valid |
| 924 | if the OPCODE implies there is such a field for this instruction. */ |
| 925 | int rs1 () const |
| 926 | { return m_rs1; } |
| 927 | |
| 928 | /* Get the RS2 register field for this instruction. This is only valid |
| 929 | if the OPCODE implies there is such a field for this instruction. */ |
| 930 | int rs2 () const |
| 931 | { return m_rs2; } |
| 932 | |
| 933 | /* Get the immediate for this instruction in signed form. This is only |
| 934 | valid if the OPCODE implies there is such a field for this |
| 935 | instruction. */ |
| 936 | int imm_signed () const |
| 937 | { return m_imm.s; } |
| 938 | |
| 939 | private: |
| 940 | |
| 941 | /* Extract 5 bit register field at OFFSET from instruction OPCODE. */ |
| 942 | int decode_register_index (unsigned long opcode, int offset) |
| 943 | { |
| 944 | return (opcode >> offset) & 0x1F; |
| 945 | } |
| 946 | |
| 947 | /* Helper for DECODE, decode 32-bit R-type instruction. */ |
| 948 | void decode_r_type_insn (enum opcode opcode, ULONGEST ival) |
| 949 | { |
| 950 | m_opcode = opcode; |
| 951 | m_rd = decode_register_index (ival, OP_SH_RD); |
| 952 | m_rs1 = decode_register_index (ival, OP_SH_RS1); |
| 953 | m_rs2 = decode_register_index (ival, OP_SH_RS2); |
| 954 | } |
| 955 | |
| 956 | /* Helper for DECODE, decode 16-bit compressed R-type instruction. */ |
| 957 | void decode_cr_type_insn (enum opcode opcode, ULONGEST ival) |
| 958 | { |
| 959 | m_opcode = opcode; |
| 960 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S); |
| 961 | m_rs2 = decode_register_index (ival, OP_SH_CRS2); |
| 962 | } |
| 963 | |
| 964 | /* Helper for DECODE, decode 32-bit I-type instruction. */ |
| 965 | void decode_i_type_insn (enum opcode opcode, ULONGEST ival) |
| 966 | { |
| 967 | m_opcode = opcode; |
| 968 | m_rd = decode_register_index (ival, OP_SH_RD); |
| 969 | m_rs1 = decode_register_index (ival, OP_SH_RS1); |
| 970 | m_imm.s = EXTRACT_ITYPE_IMM (ival); |
| 971 | } |
| 972 | |
| 973 | /* Helper for DECODE, decode 16-bit compressed I-type instruction. */ |
| 974 | void decode_ci_type_insn (enum opcode opcode, ULONGEST ival) |
| 975 | { |
| 976 | m_opcode = opcode; |
| 977 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S); |
| 978 | m_imm.s = EXTRACT_RVC_IMM (ival); |
| 979 | } |
| 980 | |
| 981 | /* Helper for DECODE, decode 32-bit S-type instruction. */ |
| 982 | void decode_s_type_insn (enum opcode opcode, ULONGEST ival) |
| 983 | { |
| 984 | m_opcode = opcode; |
| 985 | m_rs1 = decode_register_index (ival, OP_SH_RS1); |
| 986 | m_rs2 = decode_register_index (ival, OP_SH_RS2); |
| 987 | m_imm.s = EXTRACT_STYPE_IMM (ival); |
| 988 | } |
| 989 | |
| 990 | /* Helper for DECODE, decode 32-bit U-type instruction. */ |
| 991 | void decode_u_type_insn (enum opcode opcode, ULONGEST ival) |
| 992 | { |
| 993 | m_opcode = opcode; |
| 994 | m_rd = decode_register_index (ival, OP_SH_RD); |
| 995 | m_imm.s = EXTRACT_UTYPE_IMM (ival); |
| 996 | } |
| 997 | |
| 998 | /* Fetch instruction from target memory at ADDR, return the content of |
| 999 | the instruction, and update LEN with the instruction length. */ |
| 1000 | static ULONGEST fetch_instruction (struct gdbarch *gdbarch, |
| 1001 | CORE_ADDR addr, int *len); |
| 1002 | |
| 1003 | /* The length of the instruction in bytes. Should be 2 or 4. */ |
| 1004 | int m_length; |
| 1005 | |
| 1006 | /* The instruction opcode. */ |
| 1007 | enum opcode m_opcode; |
| 1008 | |
| 1009 | /* The three possible registers an instruction might reference. Not |
| 1010 | every instruction fills in all of these registers. Which fields are |
| 1011 | valid depends on the opcode. The naming of these fields matches the |
| 1012 | naming in the riscv isa manual. */ |
| 1013 | int m_rd; |
| 1014 | int m_rs1; |
| 1015 | int m_rs2; |
| 1016 | |
| 1017 | /* Possible instruction immediate. This is only valid if the instruction |
| 1018 | format contains an immediate, not all instruction, whether this is |
| 1019 | valid depends on the opcode. Despite only having one format for now |
| 1020 | the immediate is packed into a union, later instructions might require |
| 1021 | an unsigned formatted immediate, having the union in place now will |
| 1022 | reduce the need for code churn later. */ |
| 1023 | union riscv_insn_immediate |
| 1024 | { |
| 1025 | riscv_insn_immediate () |
| 1026 | : s (0) |
| 1027 | { |
| 1028 | /* Nothing. */ |
| 1029 | } |
| 1030 | |
| 1031 | int s; |
| 1032 | } m_imm; |
| 1033 | }; |
| 1034 | |
| 1035 | /* Fetch instruction from target memory at ADDR, return the content of the |
| 1036 | instruction, and update LEN with the instruction length. */ |
| 1037 | |
| 1038 | ULONGEST |
| 1039 | riscv_insn::fetch_instruction (struct gdbarch *gdbarch, |
| 1040 | CORE_ADDR addr, int *len) |
| 1041 | { |
| 1042 | enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch); |
| 1043 | gdb_byte buf[8]; |
| 1044 | int instlen, status; |
| 1045 | |
| 1046 | /* All insns are at least 16 bits. */ |
| 1047 | status = target_read_memory (addr, buf, 2); |
| 1048 | if (status) |
| 1049 | memory_error (TARGET_XFER_E_IO, addr); |
| 1050 | |
| 1051 | /* If we need more, grab it now. */ |
| 1052 | instlen = riscv_insn_length (buf[0]); |
| 1053 | gdb_assert (instlen <= sizeof (buf)); |
| 1054 | *len = instlen; |
| 1055 | |
| 1056 | if (instlen > 2) |
| 1057 | { |
| 1058 | status = target_read_memory (addr + 2, buf + 2, instlen - 2); |
| 1059 | if (status) |
| 1060 | memory_error (TARGET_XFER_E_IO, addr + 2); |
| 1061 | } |
| 1062 | |
| 1063 | return extract_unsigned_integer (buf, instlen, byte_order); |
| 1064 | } |
| 1065 | |
| 1066 | /* Fetch from target memory an instruction at PC and decode it. */ |
| 1067 | |
| 1068 | void |
| 1069 | riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 1070 | { |
| 1071 | ULONGEST ival; |
| 1072 | |
| 1073 | /* Fetch the instruction, and the instructions length. */ |
| 1074 | ival = fetch_instruction (gdbarch, pc, &m_length); |
| 1075 | |
| 1076 | if (m_length == 4) |
| 1077 | { |
| 1078 | if (is_add_insn (ival)) |
| 1079 | decode_r_type_insn (ADD, ival); |
| 1080 | else if (is_addw_insn (ival)) |
| 1081 | decode_r_type_insn (ADDW, ival); |
| 1082 | else if (is_addi_insn (ival)) |
| 1083 | decode_i_type_insn (ADDI, ival); |
| 1084 | else if (is_addiw_insn (ival)) |
| 1085 | decode_i_type_insn (ADDIW, ival); |
| 1086 | else if (is_auipc_insn (ival)) |
| 1087 | decode_u_type_insn (AUIPC, ival); |
| 1088 | else if (is_lui_insn (ival)) |
| 1089 | decode_u_type_insn (LUI, ival); |
| 1090 | else if (is_sd_insn (ival)) |
| 1091 | decode_s_type_insn (SD, ival); |
| 1092 | else if (is_sw_insn (ival)) |
| 1093 | decode_s_type_insn (SW, ival); |
| 1094 | else |
| 1095 | /* None of the other fields are valid in this case. */ |
| 1096 | m_opcode = OTHER; |
| 1097 | } |
| 1098 | else if (m_length == 2) |
| 1099 | { |
| 1100 | if (is_c_add_insn (ival)) |
| 1101 | decode_cr_type_insn (ADD, ival); |
| 1102 | else if (is_c_addw_insn (ival)) |
| 1103 | decode_cr_type_insn (ADDW, ival); |
| 1104 | else if (is_c_addi_insn (ival)) |
| 1105 | decode_ci_type_insn (ADDI, ival); |
| 1106 | else if (is_c_addiw_insn (ival)) |
| 1107 | decode_ci_type_insn (ADDIW, ival); |
| 1108 | else if (is_c_addi16sp_insn (ival)) |
| 1109 | { |
| 1110 | m_opcode = ADDI; |
| 1111 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD); |
| 1112 | m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival); |
| 1113 | } |
| 1114 | else if (is_lui_insn (ival)) |
| 1115 | m_opcode = OTHER; |
| 1116 | else if (is_c_sd_insn (ival)) |
| 1117 | m_opcode = OTHER; |
| 1118 | else if (is_sw_insn (ival)) |
| 1119 | m_opcode = OTHER; |
| 1120 | else |
| 1121 | /* None of the other fields of INSN are valid in this case. */ |
| 1122 | m_opcode = OTHER; |
| 1123 | } |
| 1124 | else |
| 1125 | internal_error (__FILE__, __LINE__, |
| 1126 | _("unable to decode %d byte instructions in " |
| 1127 | "prologue at %s"), m_length, |
| 1128 | core_addr_to_string (pc)); |
| 1129 | } |
| 1130 | |
| 1131 | /* The prologue scanner. This is currently only used for skipping the |
| 1132 | prologue of a function when the DWARF information is not sufficient. |
| 1133 | However, it is written with filling of the frame cache in mind, which |
| 1134 | is why different groups of stack setup instructions are split apart |
| 1135 | during the core of the inner loop. In the future, the intention is to |
| 1136 | extend this function to fully support building up a frame cache that |
| 1137 | can unwind register values when there is no DWARF information. */ |
| 1138 | |
| 1139 | static CORE_ADDR |
| 1140 | riscv_scan_prologue (struct gdbarch *gdbarch, |
| 1141 | CORE_ADDR start_pc, CORE_ADDR limit_pc) |
| 1142 | { |
| 1143 | CORE_ADDR cur_pc, next_pc; |
| 1144 | long frame_offset = 0; |
| 1145 | CORE_ADDR end_prologue_addr = 0; |
| 1146 | |
| 1147 | if (limit_pc > start_pc + 200) |
| 1148 | limit_pc = start_pc + 200; |
| 1149 | |
| 1150 | for (next_pc = cur_pc = start_pc; cur_pc < limit_pc; cur_pc = next_pc) |
| 1151 | { |
| 1152 | struct riscv_insn insn; |
| 1153 | |
| 1154 | /* Decode the current instruction, and decide where the next |
| 1155 | instruction lives based on the size of this instruction. */ |
| 1156 | insn.decode (gdbarch, cur_pc); |
| 1157 | gdb_assert (insn.length () > 0); |
| 1158 | next_pc = cur_pc + insn.length (); |
| 1159 | |
| 1160 | /* Look for common stack adjustment insns. */ |
| 1161 | if ((insn.opcode () == riscv_insn::ADDI |
| 1162 | || insn.opcode () == riscv_insn::ADDIW) |
| 1163 | && insn.rd () == RISCV_SP_REGNUM |
| 1164 | && insn.rs1 () == RISCV_SP_REGNUM) |
| 1165 | { |
| 1166 | /* Handle: addi sp, sp, -i |
| 1167 | or: addiw sp, sp, -i */ |
| 1168 | if (insn.imm_signed () < 0) |
| 1169 | frame_offset += insn.imm_signed (); |
| 1170 | else |
| 1171 | break; |
| 1172 | } |
| 1173 | else if ((insn.opcode () == riscv_insn::SW |
| 1174 | || insn.opcode () == riscv_insn::SD) |
| 1175 | && (insn.rs1 () == RISCV_SP_REGNUM |
| 1176 | || insn.rs1 () == RISCV_FP_REGNUM)) |
| 1177 | { |
| 1178 | /* Handle: sw reg, offset(sp) |
| 1179 | or: sd reg, offset(sp) |
| 1180 | or: sw reg, offset(s0) |
| 1181 | or: sd reg, offset(s0) */ |
| 1182 | /* Instruction storing a register onto the stack. */ |
| 1183 | } |
| 1184 | else if (insn.opcode () == riscv_insn::ADDI |
| 1185 | && insn.rd () == RISCV_FP_REGNUM |
| 1186 | && insn.rs1 () == RISCV_SP_REGNUM) |
| 1187 | { |
| 1188 | /* Handle: addi s0, sp, size */ |
| 1189 | /* Instructions setting up the frame pointer. */ |
| 1190 | } |
| 1191 | else if ((insn.opcode () == riscv_insn::ADD |
| 1192 | || insn.opcode () == riscv_insn::ADDW) |
| 1193 | && insn.rd () == RISCV_FP_REGNUM |
| 1194 | && insn.rs1 () == RISCV_SP_REGNUM |
| 1195 | && insn.rs2 () == RISCV_ZERO_REGNUM) |
| 1196 | { |
| 1197 | /* Handle: add s0, sp, 0 |
| 1198 | or: addw s0, sp, 0 */ |
| 1199 | /* Instructions setting up the frame pointer. */ |
| 1200 | } |
| 1201 | else if ((insn.rd () == RISCV_GP_REGNUM |
| 1202 | && (insn.opcode () == riscv_insn::AUIPC |
| 1203 | || insn.opcode () == riscv_insn::LUI |
| 1204 | || (insn.opcode () == riscv_insn::ADDI |
| 1205 | && insn.rs1 () == RISCV_GP_REGNUM) |
| 1206 | || (insn.opcode () == riscv_insn::ADD |
| 1207 | && (insn.rs1 () == RISCV_GP_REGNUM |
| 1208 | || insn.rs2 () == RISCV_GP_REGNUM)))) |
| 1209 | || (insn.opcode () == riscv_insn::ADDI |
| 1210 | && insn.rd () == RISCV_ZERO_REGNUM |
| 1211 | && insn.rs1 () == RISCV_ZERO_REGNUM |
| 1212 | && insn.imm_signed () == 0)) |
| 1213 | { |
| 1214 | /* Handle: auipc gp, n |
| 1215 | or: addi gp, gp, n |
| 1216 | or: add gp, gp, reg |
| 1217 | or: add gp, reg, gp |
| 1218 | or: lui gp, n |
| 1219 | or: add x0, x0, 0 (NOP) */ |
| 1220 | /* These instructions are part of the prologue, but we don't need |
| 1221 | to do anything special to handle them. */ |
| 1222 | } |
| 1223 | else |
| 1224 | { |
| 1225 | if (end_prologue_addr == 0) |
| 1226 | end_prologue_addr = cur_pc; |
| 1227 | } |
| 1228 | } |
| 1229 | |
| 1230 | if (end_prologue_addr == 0) |
| 1231 | end_prologue_addr = cur_pc; |
| 1232 | |
| 1233 | return end_prologue_addr; |
| 1234 | } |
| 1235 | |
| 1236 | /* Implement the riscv_skip_prologue gdbarch method. */ |
| 1237 | |
| 1238 | static CORE_ADDR |
| 1239 | riscv_skip_prologue (struct gdbarch *gdbarch, |
| 1240 | CORE_ADDR pc) |
| 1241 | { |
| 1242 | CORE_ADDR limit_pc; |
| 1243 | CORE_ADDR func_addr; |
| 1244 | |
| 1245 | /* See if we can determine the end of the prologue via the symbol |
| 1246 | table. If so, then return either PC, or the PC after the |
| 1247 | prologue, whichever is greater. */ |
| 1248 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
| 1249 | { |
| 1250 | CORE_ADDR post_prologue_pc |
| 1251 | = skip_prologue_using_sal (gdbarch, func_addr); |
| 1252 | |
| 1253 | if (post_prologue_pc != 0) |
| 1254 | return std::max (pc, post_prologue_pc); |
| 1255 | } |
| 1256 | |
| 1257 | /* Can't determine prologue from the symbol table, need to examine |
| 1258 | instructions. */ |
| 1259 | |
| 1260 | /* Find an upper limit on the function prologue using the debug |
| 1261 | information. If the debug information could not be used to provide |
| 1262 | that bound, then use an arbitrary large number as the upper bound. */ |
| 1263 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
| 1264 | if (limit_pc == 0) |
| 1265 | limit_pc = pc + 100; /* MAGIC! */ |
| 1266 | |
| 1267 | return riscv_scan_prologue (gdbarch, pc, limit_pc); |
| 1268 | } |
| 1269 | |
| 1270 | /* Implement the gdbarch push dummy code callback. */ |
| 1271 | |
| 1272 | static CORE_ADDR |
| 1273 | riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, |
| 1274 | CORE_ADDR funaddr, struct value **args, int nargs, |
| 1275 | struct type *value_type, CORE_ADDR *real_pc, |
| 1276 | CORE_ADDR *bp_addr, struct regcache *regcache) |
| 1277 | { |
| 1278 | /* Allocate space for a breakpoint, and keep the stack correctly |
| 1279 | aligned. */ |
| 1280 | sp -= 16; |
| 1281 | *bp_addr = sp; |
| 1282 | *real_pc = funaddr; |
| 1283 | return sp; |
| 1284 | } |
| 1285 | |
| 1286 | /* Compute the alignment of the type T. Used while setting up the |
| 1287 | arguments for a dummy call. */ |
| 1288 | |
| 1289 | static int |
| 1290 | riscv_type_alignment (struct type *t) |
| 1291 | { |
| 1292 | t = check_typedef (t); |
| 1293 | switch (TYPE_CODE (t)) |
| 1294 | { |
| 1295 | default: |
| 1296 | error (_("Could not compute alignment of type")); |
| 1297 | |
| 1298 | case TYPE_CODE_RVALUE_REF: |
| 1299 | case TYPE_CODE_PTR: |
| 1300 | case TYPE_CODE_ENUM: |
| 1301 | case TYPE_CODE_INT: |
| 1302 | case TYPE_CODE_FLT: |
| 1303 | case TYPE_CODE_REF: |
| 1304 | case TYPE_CODE_CHAR: |
| 1305 | case TYPE_CODE_BOOL: |
| 1306 | return TYPE_LENGTH (t); |
| 1307 | |
| 1308 | case TYPE_CODE_ARRAY: |
| 1309 | case TYPE_CODE_COMPLEX: |
| 1310 | return riscv_type_alignment (TYPE_TARGET_TYPE (t)); |
| 1311 | |
| 1312 | case TYPE_CODE_STRUCT: |
| 1313 | case TYPE_CODE_UNION: |
| 1314 | { |
| 1315 | int i; |
| 1316 | int align = 1; |
| 1317 | |
| 1318 | for (i = 0; i < TYPE_NFIELDS (t); ++i) |
| 1319 | { |
| 1320 | if (TYPE_FIELD_LOC_KIND (t, i) == FIELD_LOC_KIND_BITPOS) |
| 1321 | { |
| 1322 | int a = riscv_type_alignment (TYPE_FIELD_TYPE (t, i)); |
| 1323 | if (a > align) |
| 1324 | align = a; |
| 1325 | } |
| 1326 | } |
| 1327 | return align; |
| 1328 | } |
| 1329 | } |
| 1330 | } |
| 1331 | |
| 1332 | /* Holds information about a single argument either being passed to an |
| 1333 | inferior function, or returned from an inferior function. This includes |
| 1334 | information about the size, type, etc of the argument, and also |
| 1335 | information about how the argument will be passed (or returned). */ |
| 1336 | |
| 1337 | struct riscv_arg_info |
| 1338 | { |
| 1339 | /* Contents of the argument. */ |
| 1340 | const gdb_byte *contents; |
| 1341 | |
| 1342 | /* Length of argument. */ |
| 1343 | int length; |
| 1344 | |
| 1345 | /* Alignment required for an argument of this type. */ |
| 1346 | int align; |
| 1347 | |
| 1348 | /* The type for this argument. */ |
| 1349 | struct type *type; |
| 1350 | |
| 1351 | /* Each argument can have either 1 or 2 locations assigned to it. Each |
| 1352 | location describes where part of the argument will be placed. The |
| 1353 | second location is valid based on the LOC_TYPE and C_LENGTH fields |
| 1354 | of the first location (which is always valid). */ |
| 1355 | struct location |
| 1356 | { |
| 1357 | /* What type of location this is. */ |
| 1358 | enum location_type |
| 1359 | { |
| 1360 | /* Argument passed in a register. */ |
| 1361 | in_reg, |
| 1362 | |
| 1363 | /* Argument passed as an on stack argument. */ |
| 1364 | on_stack, |
| 1365 | |
| 1366 | /* Argument passed by reference. The second location is always |
| 1367 | valid for a BY_REF argument, and describes where the address |
| 1368 | of the BY_REF argument should be placed. */ |
| 1369 | by_ref |
| 1370 | } loc_type; |
| 1371 | |
| 1372 | /* Information that depends on the location type. */ |
| 1373 | union |
| 1374 | { |
| 1375 | /* Which register number to use. */ |
| 1376 | int regno; |
| 1377 | |
| 1378 | /* The offset into the stack region. */ |
| 1379 | int offset; |
| 1380 | } loc_data; |
| 1381 | |
| 1382 | /* The length of contents covered by this location. If this is less |
| 1383 | than the total length of the argument, then the second location |
| 1384 | will be valid, and will describe where the rest of the argument |
| 1385 | will go. */ |
| 1386 | int c_length; |
| 1387 | |
| 1388 | /* The offset within CONTENTS for this part of the argument. Will |
| 1389 | always be 0 for the first part. For the second part of the |
| 1390 | argument, this might be the C_LENGTH value of the first part, |
| 1391 | however, if we are passing a structure in two registers, and there's |
| 1392 | is padding between the first and second field, then this offset |
| 1393 | might be greater than the length of the first argument part. When |
| 1394 | the second argument location is not holding part of the argument |
| 1395 | value, but is instead holding the address of a reference argument, |
| 1396 | then this offset will be set to 0. */ |
| 1397 | int c_offset; |
| 1398 | } argloc[2]; |
| 1399 | }; |
| 1400 | |
| 1401 | /* Information about a set of registers being used for passing arguments as |
| 1402 | part of a function call. The register set must be numerically |
| 1403 | sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be |
| 1404 | disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */ |
| 1405 | |
| 1406 | struct riscv_arg_reg |
| 1407 | { |
| 1408 | riscv_arg_reg (int first, int last) |
| 1409 | : next_regnum (first), |
| 1410 | last_regnum (last) |
| 1411 | { |
| 1412 | /* Nothing. */ |
| 1413 | } |
| 1414 | |
| 1415 | /* The GDB register number to use in this set. */ |
| 1416 | int next_regnum; |
| 1417 | |
| 1418 | /* The last GDB register number to use in this set. */ |
| 1419 | int last_regnum; |
| 1420 | }; |
| 1421 | |
| 1422 | /* Arguments can be passed as on stack arguments, or by reference. The |
| 1423 | on stack arguments must be in a continuous region starting from $sp, |
| 1424 | while the by reference arguments can be anywhere, but we'll put them |
| 1425 | on the stack after (at higher address) the on stack arguments. |
| 1426 | |
| 1427 | This might not be the right approach to take. The ABI is clear that |
| 1428 | an argument passed by reference can be modified by the callee, which |
| 1429 | us placing the argument (temporarily) onto the stack will not achieve |
| 1430 | (changes will be lost). There's also the possibility that very large |
| 1431 | arguments could overflow the stack. |
| 1432 | |
| 1433 | This struct is used to track offset into these two areas for where |
| 1434 | arguments are to be placed. */ |
| 1435 | struct riscv_memory_offsets |
| 1436 | { |
| 1437 | riscv_memory_offsets () |
| 1438 | : arg_offset (0), |
| 1439 | ref_offset (0) |
| 1440 | { |
| 1441 | /* Nothing. */ |
| 1442 | } |
| 1443 | |
| 1444 | /* Offset into on stack argument area. */ |
| 1445 | int arg_offset; |
| 1446 | |
| 1447 | /* Offset into the pass by reference area. */ |
| 1448 | int ref_offset; |
| 1449 | }; |
| 1450 | |
| 1451 | /* Holds information about where arguments to a call will be placed. This |
| 1452 | is updated as arguments are added onto the call, and can be used to |
| 1453 | figure out where the next argument should be placed. */ |
| 1454 | |
| 1455 | struct riscv_call_info |
| 1456 | { |
| 1457 | riscv_call_info (struct gdbarch *gdbarch) |
| 1458 | : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7), |
| 1459 | float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7) |
| 1460 | { |
| 1461 | xlen = riscv_isa_xlen (gdbarch); |
| 1462 | flen = riscv_isa_flen (gdbarch); |
| 1463 | |
| 1464 | /* Disable use of floating point registers if needed. */ |
| 1465 | if (!riscv_has_fp_abi (gdbarch)) |
| 1466 | float_regs.next_regnum = float_regs.last_regnum + 1; |
| 1467 | } |
| 1468 | |
| 1469 | /* Track the memory areas used for holding in-memory arguments to a |
| 1470 | call. */ |
| 1471 | struct riscv_memory_offsets memory; |
| 1472 | |
| 1473 | /* Holds information about the next integer register to use for passing |
| 1474 | an argument. */ |
| 1475 | struct riscv_arg_reg int_regs; |
| 1476 | |
| 1477 | /* Holds information about the next floating point register to use for |
| 1478 | passing an argument. */ |
| 1479 | struct riscv_arg_reg float_regs; |
| 1480 | |
| 1481 | /* The XLEN and FLEN are copied in to this structure for convenience, and |
| 1482 | are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */ |
| 1483 | int xlen; |
| 1484 | int flen; |
| 1485 | }; |
| 1486 | |
| 1487 | /* Return the number of registers available for use as parameters in the |
| 1488 | register set REG. Returned value can be 0 or more. */ |
| 1489 | |
| 1490 | static int |
| 1491 | riscv_arg_regs_available (struct riscv_arg_reg *reg) |
| 1492 | { |
| 1493 | if (reg->next_regnum > reg->last_regnum) |
| 1494 | return 0; |
| 1495 | |
| 1496 | return (reg->last_regnum - reg->next_regnum + 1); |
| 1497 | } |
| 1498 | |
| 1499 | /* If there is at least one register available in the register set REG then |
| 1500 | the next register from REG is assigned to LOC and the length field of |
| 1501 | LOC is updated to LENGTH. The register set REG is updated to indicate |
| 1502 | that the assigned register is no longer available and the function |
| 1503 | returns true. |
| 1504 | |
| 1505 | If there are no registers available in REG then the function returns |
| 1506 | false, and LOC and REG are unchanged. */ |
| 1507 | |
| 1508 | static bool |
| 1509 | riscv_assign_reg_location (struct riscv_arg_info::location *loc, |
| 1510 | struct riscv_arg_reg *reg, |
| 1511 | int length, int offset) |
| 1512 | { |
| 1513 | if (reg->next_regnum <= reg->last_regnum) |
| 1514 | { |
| 1515 | loc->loc_type = riscv_arg_info::location::in_reg; |
| 1516 | loc->loc_data.regno = reg->next_regnum; |
| 1517 | reg->next_regnum++; |
| 1518 | loc->c_length = length; |
| 1519 | loc->c_offset = offset; |
| 1520 | return true; |
| 1521 | } |
| 1522 | |
| 1523 | return false; |
| 1524 | } |
| 1525 | |
| 1526 | /* Assign LOC a location as the next stack parameter, and update MEMORY to |
| 1527 | record that an area of stack has been used to hold the parameter |
| 1528 | described by LOC. |
| 1529 | |
| 1530 | The length field of LOC is updated to LENGTH, the length of the |
| 1531 | parameter being stored, and ALIGN is the alignment required by the |
| 1532 | parameter, which will affect how memory is allocated out of MEMORY. */ |
| 1533 | |
| 1534 | static void |
| 1535 | riscv_assign_stack_location (struct riscv_arg_info::location *loc, |
| 1536 | struct riscv_memory_offsets *memory, |
| 1537 | int length, int align) |
| 1538 | { |
| 1539 | loc->loc_type = riscv_arg_info::location::on_stack; |
| 1540 | memory->arg_offset |
| 1541 | = align_up (memory->arg_offset, align); |
| 1542 | loc->loc_data.offset = memory->arg_offset; |
| 1543 | memory->arg_offset += length; |
| 1544 | loc->c_length = length; |
| 1545 | |
| 1546 | /* Offset is always 0, either we're the first location part, in which |
| 1547 | case we're reading content from the start of the argument, or we're |
| 1548 | passing the address of a reference argument, so 0. */ |
| 1549 | loc->c_offset = 0; |
| 1550 | } |
| 1551 | |
| 1552 | /* Update AINFO, which describes an argument that should be passed or |
| 1553 | returned using the integer ABI. The argloc fields within AINFO are |
| 1554 | updated to describe the location in which the argument will be passed to |
| 1555 | a function, or returned from a function. |
| 1556 | |
| 1557 | The CINFO structure contains the ongoing call information, the holds |
| 1558 | information such as which argument registers are remaining to be |
| 1559 | assigned to parameter, and how much memory has been used by parameters |
| 1560 | so far. |
| 1561 | |
| 1562 | By examining the state of CINFO a suitable location can be selected, |
| 1563 | and assigned to AINFO. */ |
| 1564 | |
| 1565 | static void |
| 1566 | riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo, |
| 1567 | struct riscv_call_info *cinfo) |
| 1568 | { |
| 1569 | if (ainfo->length > (2 * cinfo->xlen)) |
| 1570 | { |
| 1571 | /* Argument is going to be passed by reference. */ |
| 1572 | ainfo->argloc[0].loc_type |
| 1573 | = riscv_arg_info::location::by_ref; |
| 1574 | cinfo->memory.ref_offset |
| 1575 | = align_up (cinfo->memory.ref_offset, ainfo->align); |
| 1576 | ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset; |
| 1577 | cinfo->memory.ref_offset += ainfo->length; |
| 1578 | ainfo->argloc[0].c_length = ainfo->length; |
| 1579 | |
| 1580 | /* The second location for this argument is given over to holding the |
| 1581 | address of the by-reference data. Pass 0 for the offset as this |
| 1582 | is not part of the actual argument value. */ |
| 1583 | if (!riscv_assign_reg_location (&ainfo->argloc[1], |
| 1584 | &cinfo->int_regs, |
| 1585 | cinfo->xlen, 0)) |
| 1586 | riscv_assign_stack_location (&ainfo->argloc[1], |
| 1587 | &cinfo->memory, cinfo->xlen, |
| 1588 | cinfo->xlen); |
| 1589 | } |
| 1590 | else |
| 1591 | { |
| 1592 | int len = (ainfo->length > cinfo->xlen) ? cinfo->xlen : ainfo->length; |
| 1593 | |
| 1594 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
| 1595 | &cinfo->int_regs, len, 0)) |
| 1596 | riscv_assign_stack_location (&ainfo->argloc[0], |
| 1597 | &cinfo->memory, len, ainfo->align); |
| 1598 | |
| 1599 | if (len < ainfo->length) |
| 1600 | { |
| 1601 | len = ainfo->length - len; |
| 1602 | if (!riscv_assign_reg_location (&ainfo->argloc[1], |
| 1603 | &cinfo->int_regs, len, |
| 1604 | cinfo->xlen)) |
| 1605 | riscv_assign_stack_location (&ainfo->argloc[1], |
| 1606 | &cinfo->memory, len, cinfo->xlen); |
| 1607 | } |
| 1608 | } |
| 1609 | } |
| 1610 | |
| 1611 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO |
| 1612 | is being passed with the floating point ABI. */ |
| 1613 | |
| 1614 | static void |
| 1615 | riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo, |
| 1616 | struct riscv_call_info *cinfo) |
| 1617 | { |
| 1618 | if (ainfo->length > cinfo->flen) |
| 1619 | return riscv_call_arg_scalar_int (ainfo, cinfo); |
| 1620 | else |
| 1621 | { |
| 1622 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
| 1623 | &cinfo->float_regs, |
| 1624 | ainfo->length, 0)) |
| 1625 | return riscv_call_arg_scalar_int (ainfo, cinfo); |
| 1626 | } |
| 1627 | } |
| 1628 | |
| 1629 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO |
| 1630 | is a complex floating point argument, and is therefore handled |
| 1631 | differently to other argument types. */ |
| 1632 | |
| 1633 | static void |
| 1634 | riscv_call_arg_complex_float (struct riscv_arg_info *ainfo, |
| 1635 | struct riscv_call_info *cinfo) |
| 1636 | { |
| 1637 | if (ainfo->length <= (2 * cinfo->flen) |
| 1638 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2) |
| 1639 | { |
| 1640 | bool result; |
| 1641 | int len = ainfo->length / 2; |
| 1642 | |
| 1643 | result = riscv_assign_reg_location (&ainfo->argloc[0], |
| 1644 | &cinfo->float_regs, len, len); |
| 1645 | gdb_assert (result); |
| 1646 | |
| 1647 | result = riscv_assign_reg_location (&ainfo->argloc[1], |
| 1648 | &cinfo->float_regs, len, len); |
| 1649 | gdb_assert (result); |
| 1650 | } |
| 1651 | else |
| 1652 | return riscv_call_arg_scalar_int (ainfo, cinfo); |
| 1653 | } |
| 1654 | |
| 1655 | /* A structure used for holding information about a structure type within |
| 1656 | the inferior program. The RiscV ABI has special rules for handling some |
| 1657 | structures with a single field or with two fields. The counting of |
| 1658 | fields here is done after flattening out all nested structures. */ |
| 1659 | |
| 1660 | class riscv_struct_info |
| 1661 | { |
| 1662 | public: |
| 1663 | riscv_struct_info () |
| 1664 | : m_number_of_fields (0), |
| 1665 | m_types { nullptr, nullptr } |
| 1666 | { |
| 1667 | /* Nothing. */ |
| 1668 | } |
| 1669 | |
| 1670 | /* Analyse TYPE descending into nested structures, count the number of |
| 1671 | scalar fields and record the types of the first two fields found. */ |
| 1672 | void analyse (struct type *type); |
| 1673 | |
| 1674 | /* The number of scalar fields found in the analysed type. This is |
| 1675 | currently only accurate if the value returned is 0, 1, or 2 as the |
| 1676 | analysis stops counting when the number of fields is 3. This is |
| 1677 | because the RiscV ABI only has special cases for 1 or 2 fields, |
| 1678 | anything else we just don't care about. */ |
| 1679 | int number_of_fields () const |
| 1680 | { return m_number_of_fields; } |
| 1681 | |
| 1682 | /* Return the type for scalar field INDEX within the analysed type. Will |
| 1683 | return nullptr if there is no field at that index. Only INDEX values |
| 1684 | 0 and 1 can be requested as the RiscV ABI only has special cases for |
| 1685 | structures with 1 or 2 fields. */ |
| 1686 | struct type *field_type (int index) const |
| 1687 | { |
| 1688 | gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0]))); |
| 1689 | return m_types[index]; |
| 1690 | } |
| 1691 | |
| 1692 | private: |
| 1693 | /* The number of scalar fields found within the structure after recursing |
| 1694 | into nested structures. */ |
| 1695 | int m_number_of_fields; |
| 1696 | |
| 1697 | /* The types of the first two scalar fields found within the structure |
| 1698 | after recursing into nested structures. */ |
| 1699 | struct type *m_types[2]; |
| 1700 | }; |
| 1701 | |
| 1702 | /* Analyse TYPE descending into nested structures, count the number of |
| 1703 | scalar fields and record the types of the first two fields found. */ |
| 1704 | |
| 1705 | void |
| 1706 | riscv_struct_info::analyse (struct type *type) |
| 1707 | { |
| 1708 | unsigned int count = TYPE_NFIELDS (type); |
| 1709 | unsigned int i; |
| 1710 | |
| 1711 | for (i = 0; i < count; ++i) |
| 1712 | { |
| 1713 | if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS) |
| 1714 | continue; |
| 1715 | |
| 1716 | struct type *field_type = TYPE_FIELD_TYPE (type, i); |
| 1717 | field_type = check_typedef (field_type); |
| 1718 | |
| 1719 | switch (TYPE_CODE (field_type)) |
| 1720 | { |
| 1721 | case TYPE_CODE_STRUCT: |
| 1722 | analyse (field_type); |
| 1723 | break; |
| 1724 | |
| 1725 | default: |
| 1726 | /* RiscV only flattens out structures. Anything else does not |
| 1727 | need to be flattened, we just record the type, and when we |
| 1728 | look at the analysis results we'll realise this is not a |
| 1729 | structure we can special case, and pass the structure in |
| 1730 | memory. */ |
| 1731 | if (m_number_of_fields < 2) |
| 1732 | m_types[m_number_of_fields] = field_type; |
| 1733 | m_number_of_fields++; |
| 1734 | break; |
| 1735 | } |
| 1736 | |
| 1737 | /* RiscV only has special handling for structures with 1 or 2 scalar |
| 1738 | fields, any more than that and the structure is just passed in |
| 1739 | memory. We can safely drop out early when we find 3 or more |
| 1740 | fields then. */ |
| 1741 | |
| 1742 | if (m_number_of_fields > 2) |
| 1743 | return; |
| 1744 | } |
| 1745 | } |
| 1746 | |
| 1747 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO |
| 1748 | is a structure. Small structures on RiscV have some special case |
| 1749 | handling in order that the structure might be passed in register. |
| 1750 | Larger structures are passed in memory. After assigning location |
| 1751 | information to AINFO, CINFO will have been updated. */ |
| 1752 | |
| 1753 | static void |
| 1754 | riscv_call_arg_struct (struct riscv_arg_info *ainfo, |
| 1755 | struct riscv_call_info *cinfo) |
| 1756 | { |
| 1757 | if (riscv_arg_regs_available (&cinfo->float_regs) >= 1) |
| 1758 | { |
| 1759 | struct riscv_struct_info sinfo; |
| 1760 | |
| 1761 | sinfo.analyse (ainfo->type); |
| 1762 | if (sinfo.number_of_fields () == 1 |
| 1763 | && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX) |
| 1764 | { |
| 1765 | gdb_assert (TYPE_LENGTH (ainfo->type) |
| 1766 | == TYPE_LENGTH (sinfo.field_type (0))); |
| 1767 | return riscv_call_arg_complex_float (ainfo, cinfo); |
| 1768 | } |
| 1769 | |
| 1770 | if (sinfo.number_of_fields () == 1 |
| 1771 | && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT) |
| 1772 | { |
| 1773 | gdb_assert (TYPE_LENGTH (ainfo->type) |
| 1774 | == TYPE_LENGTH (sinfo.field_type (0))); |
| 1775 | return riscv_call_arg_scalar_float (ainfo, cinfo); |
| 1776 | } |
| 1777 | |
| 1778 | if (sinfo.number_of_fields () == 2 |
| 1779 | && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT |
| 1780 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen |
| 1781 | && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT |
| 1782 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen |
| 1783 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2) |
| 1784 | { |
| 1785 | int len0, len1, offset; |
| 1786 | |
| 1787 | gdb_assert (TYPE_LENGTH (ainfo->type) <= (2 * cinfo->flen)); |
| 1788 | |
| 1789 | len0 = TYPE_LENGTH (sinfo.field_type (0)); |
| 1790 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
| 1791 | &cinfo->float_regs, len0, 0)) |
| 1792 | error (_("failed during argument setup")); |
| 1793 | |
| 1794 | len1 = TYPE_LENGTH (sinfo.field_type (1)); |
| 1795 | offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1))); |
| 1796 | gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type) |
| 1797 | - TYPE_LENGTH (sinfo.field_type (0)))); |
| 1798 | |
| 1799 | if (!riscv_assign_reg_location (&ainfo->argloc[1], |
| 1800 | &cinfo->float_regs, |
| 1801 | len1, offset)) |
| 1802 | error (_("failed during argument setup")); |
| 1803 | return; |
| 1804 | } |
| 1805 | |
| 1806 | if (sinfo.number_of_fields () == 2 |
| 1807 | && riscv_arg_regs_available (&cinfo->int_regs) >= 1 |
| 1808 | && (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT |
| 1809 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen |
| 1810 | && is_integral_type (sinfo.field_type (1)) |
| 1811 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen)) |
| 1812 | { |
| 1813 | int len0, len1, offset; |
| 1814 | |
| 1815 | gdb_assert (TYPE_LENGTH (ainfo->type) |
| 1816 | <= (cinfo->flen + cinfo->xlen)); |
| 1817 | |
| 1818 | len0 = TYPE_LENGTH (sinfo.field_type (0)); |
| 1819 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
| 1820 | &cinfo->float_regs, len0, 0)) |
| 1821 | error (_("failed during argument setup")); |
| 1822 | |
| 1823 | len1 = TYPE_LENGTH (sinfo.field_type (1)); |
| 1824 | offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1))); |
| 1825 | gdb_assert (len1 <= cinfo->xlen); |
| 1826 | if (!riscv_assign_reg_location (&ainfo->argloc[1], |
| 1827 | &cinfo->int_regs, len1, offset)) |
| 1828 | error (_("failed during argument setup")); |
| 1829 | return; |
| 1830 | } |
| 1831 | |
| 1832 | if (sinfo.number_of_fields () == 2 |
| 1833 | && riscv_arg_regs_available (&cinfo->int_regs) >= 1 |
| 1834 | && (is_integral_type (sinfo.field_type (0)) |
| 1835 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen |
| 1836 | && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT |
| 1837 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen)) |
| 1838 | { |
| 1839 | int len0, len1, offset; |
| 1840 | |
| 1841 | gdb_assert (TYPE_LENGTH (ainfo->type) |
| 1842 | <= (cinfo->flen + cinfo->xlen)); |
| 1843 | |
| 1844 | len0 = TYPE_LENGTH (sinfo.field_type (0)); |
| 1845 | len1 = TYPE_LENGTH (sinfo.field_type (1)); |
| 1846 | offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1))); |
| 1847 | |
| 1848 | gdb_assert (len0 <= cinfo->xlen); |
| 1849 | gdb_assert (len1 <= cinfo->flen); |
| 1850 | |
| 1851 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
| 1852 | &cinfo->int_regs, len0, 0)) |
| 1853 | error (_("failed during argument setup")); |
| 1854 | |
| 1855 | if (!riscv_assign_reg_location (&ainfo->argloc[1], |
| 1856 | &cinfo->float_regs, |
| 1857 | len1, offset)) |
| 1858 | error (_("failed during argument setup")); |
| 1859 | |
| 1860 | return; |
| 1861 | } |
| 1862 | } |
| 1863 | |
| 1864 | /* Non of the structure flattening cases apply, so we just pass using |
| 1865 | the integer ABI. */ |
| 1866 | ainfo->length = align_up (ainfo->length, cinfo->xlen); |
| 1867 | riscv_call_arg_scalar_int (ainfo, cinfo); |
| 1868 | } |
| 1869 | |
| 1870 | /* Assign a location to call (or return) argument AINFO, the location is |
| 1871 | selected from CINFO which holds information about what call argument |
| 1872 | locations are available for use next. The TYPE is the type of the |
| 1873 | argument being passed, this information is recorded into AINFO (along |
| 1874 | with some additional information derived from the type). |
| 1875 | |
| 1876 | After assigning a location to AINFO, CINFO will have been updated. */ |
| 1877 | |
| 1878 | static void |
| 1879 | riscv_arg_location (struct gdbarch *gdbarch, |
| 1880 | struct riscv_arg_info *ainfo, |
| 1881 | struct riscv_call_info *cinfo, |
| 1882 | struct type *type) |
| 1883 | { |
| 1884 | ainfo->type = type; |
| 1885 | ainfo->length = TYPE_LENGTH (ainfo->type); |
| 1886 | ainfo->align = riscv_type_alignment (ainfo->type); |
| 1887 | ainfo->contents = nullptr; |
| 1888 | |
| 1889 | switch (TYPE_CODE (ainfo->type)) |
| 1890 | { |
| 1891 | case TYPE_CODE_INT: |
| 1892 | case TYPE_CODE_BOOL: |
| 1893 | case TYPE_CODE_CHAR: |
| 1894 | case TYPE_CODE_RANGE: |
| 1895 | case TYPE_CODE_ENUM: |
| 1896 | case TYPE_CODE_PTR: |
| 1897 | if (ainfo->length <= cinfo->xlen) |
| 1898 | { |
| 1899 | ainfo->type = builtin_type (gdbarch)->builtin_long; |
| 1900 | ainfo->length = cinfo->xlen; |
| 1901 | } |
| 1902 | else if (ainfo->length <= (2 * cinfo->xlen)) |
| 1903 | { |
| 1904 | ainfo->type = builtin_type (gdbarch)->builtin_long_long; |
| 1905 | ainfo->length = 2 * cinfo->xlen; |
| 1906 | } |
| 1907 | |
| 1908 | /* Recalculate the alignment requirement. */ |
| 1909 | ainfo->align = riscv_type_alignment (ainfo->type); |
| 1910 | riscv_call_arg_scalar_int (ainfo, cinfo); |
| 1911 | break; |
| 1912 | |
| 1913 | case TYPE_CODE_FLT: |
| 1914 | riscv_call_arg_scalar_float (ainfo, cinfo); |
| 1915 | break; |
| 1916 | |
| 1917 | case TYPE_CODE_COMPLEX: |
| 1918 | riscv_call_arg_complex_float (ainfo, cinfo); |
| 1919 | break; |
| 1920 | |
| 1921 | case TYPE_CODE_STRUCT: |
| 1922 | riscv_call_arg_struct (ainfo, cinfo); |
| 1923 | break; |
| 1924 | |
| 1925 | default: |
| 1926 | riscv_call_arg_scalar_int (ainfo, cinfo); |
| 1927 | break; |
| 1928 | } |
| 1929 | } |
| 1930 | |
| 1931 | /* Used for printing debug information about the call argument location in |
| 1932 | INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base |
| 1933 | addresses for the location of pass-by-reference and |
| 1934 | arguments-on-the-stack memory areas. */ |
| 1935 | |
| 1936 | static void |
| 1937 | riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch, |
| 1938 | struct riscv_arg_info *info, |
| 1939 | CORE_ADDR sp_refs, CORE_ADDR sp_args) |
| 1940 | { |
| 1941 | const char* type_name = TYPE_NAME (info->type); |
| 1942 | if (type_name == nullptr) |
| 1943 | type_name = "???"; |
| 1944 | |
| 1945 | fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x", |
| 1946 | type_name, info->length, info->align); |
| 1947 | switch (info->argloc[0].loc_type) |
| 1948 | { |
| 1949 | case riscv_arg_info::location::in_reg: |
| 1950 | fprintf_unfiltered |
| 1951 | (stream, ", register %s", |
| 1952 | gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno)); |
| 1953 | if (info->argloc[0].c_length < info->length) |
| 1954 | { |
| 1955 | switch (info->argloc[1].loc_type) |
| 1956 | { |
| 1957 | case riscv_arg_info::location::in_reg: |
| 1958 | fprintf_unfiltered |
| 1959 | (stream, ", register %s", |
| 1960 | gdbarch_register_name (gdbarch, |
| 1961 | info->argloc[1].loc_data.regno)); |
| 1962 | break; |
| 1963 | |
| 1964 | case riscv_arg_info::location::on_stack: |
| 1965 | fprintf_unfiltered (stream, ", on stack at offset 0x%x", |
| 1966 | info->argloc[1].loc_data.offset); |
| 1967 | break; |
| 1968 | |
| 1969 | case riscv_arg_info::location::by_ref: |
| 1970 | default: |
| 1971 | /* The second location should never be a reference, any |
| 1972 | argument being passed by reference just places its address |
| 1973 | in the first location and is done. */ |
| 1974 | error (_("invalid argument location")); |
| 1975 | break; |
| 1976 | } |
| 1977 | |
| 1978 | if (info->argloc[1].c_offset > info->argloc[0].c_length) |
| 1979 | fprintf_unfiltered (stream, " (offset 0x%x)", |
| 1980 | info->argloc[1].c_offset); |
| 1981 | } |
| 1982 | break; |
| 1983 | |
| 1984 | case riscv_arg_info::location::on_stack: |
| 1985 | fprintf_unfiltered (stream, ", on stack at offset 0x%x", |
| 1986 | info->argloc[0].loc_data.offset); |
| 1987 | break; |
| 1988 | |
| 1989 | case riscv_arg_info::location::by_ref: |
| 1990 | fprintf_unfiltered |
| 1991 | (stream, ", by reference, data at offset 0x%x (%s)", |
| 1992 | info->argloc[0].loc_data.offset, |
| 1993 | core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset)); |
| 1994 | if (info->argloc[1].loc_type |
| 1995 | == riscv_arg_info::location::in_reg) |
| 1996 | fprintf_unfiltered |
| 1997 | (stream, ", address in register %s", |
| 1998 | gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno)); |
| 1999 | else |
| 2000 | { |
| 2001 | gdb_assert (info->argloc[1].loc_type |
| 2002 | == riscv_arg_info::location::on_stack); |
| 2003 | fprintf_unfiltered |
| 2004 | (stream, ", address on stack at offset 0x%x (%s)", |
| 2005 | info->argloc[1].loc_data.offset, |
| 2006 | core_addr_to_string (sp_args + info->argloc[1].loc_data.offset)); |
| 2007 | } |
| 2008 | break; |
| 2009 | |
| 2010 | default: |
| 2011 | gdb_assert_not_reached (_("unknown argument location type")); |
| 2012 | } |
| 2013 | } |
| 2014 | |
| 2015 | /* Implement the push dummy call gdbarch callback. */ |
| 2016 | |
| 2017 | static CORE_ADDR |
| 2018 | riscv_push_dummy_call (struct gdbarch *gdbarch, |
| 2019 | struct value *function, |
| 2020 | struct regcache *regcache, |
| 2021 | CORE_ADDR bp_addr, |
| 2022 | int nargs, |
| 2023 | struct value **args, |
| 2024 | CORE_ADDR sp, |
| 2025 | int struct_return, |
| 2026 | CORE_ADDR struct_addr) |
| 2027 | { |
| 2028 | int i; |
| 2029 | CORE_ADDR sp_args, sp_refs; |
| 2030 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2031 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2032 | |
| 2033 | struct riscv_arg_info *arg_info = |
| 2034 | (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info)); |
| 2035 | struct riscv_arg_info *info; |
| 2036 | |
| 2037 | struct riscv_call_info call_info (gdbarch); |
| 2038 | |
| 2039 | CORE_ADDR osp = sp; |
| 2040 | |
| 2041 | /* We'll use register $a0 if we're returning a struct. */ |
| 2042 | if (struct_return) |
| 2043 | ++call_info.int_regs.next_regnum; |
| 2044 | |
| 2045 | for (i = 0, info = &arg_info[0]; |
| 2046 | i < nargs; |
| 2047 | ++i, ++info) |
| 2048 | { |
| 2049 | struct value *arg_value; |
| 2050 | struct type *arg_type; |
| 2051 | |
| 2052 | arg_value = args[i]; |
| 2053 | arg_type = check_typedef (value_type (arg_value)); |
| 2054 | |
| 2055 | riscv_arg_location (gdbarch, info, &call_info, arg_type); |
| 2056 | |
| 2057 | if (info->type != arg_type) |
| 2058 | arg_value = value_cast (info->type, arg_value); |
| 2059 | info->contents = value_contents (arg_value); |
| 2060 | } |
| 2061 | |
| 2062 | /* Adjust the stack pointer and align it. */ |
| 2063 | sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT); |
| 2064 | sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT); |
| 2065 | |
| 2066 | if (riscv_debug_infcall > 0) |
| 2067 | { |
| 2068 | fprintf_unfiltered (gdb_stdlog, "dummy call args:\n"); |
| 2069 | fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n", |
| 2070 | (riscv_has_fp_abi (gdbarch) ? "is" : "is not")); |
| 2071 | fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n", |
| 2072 | call_info.xlen, call_info.flen); |
| 2073 | if (struct_return) |
| 2074 | fprintf_unfiltered (gdb_stdlog, |
| 2075 | "[*] struct return pointer in register $A0\n"); |
| 2076 | for (i = 0; i < nargs; ++i) |
| 2077 | { |
| 2078 | struct riscv_arg_info *info = &arg_info [i]; |
| 2079 | |
| 2080 | fprintf_unfiltered (gdb_stdlog, "[%2d] ", i); |
| 2081 | riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args); |
| 2082 | fprintf_unfiltered (gdb_stdlog, "\n"); |
| 2083 | } |
| 2084 | if (call_info.memory.arg_offset > 0 |
| 2085 | || call_info.memory.ref_offset > 0) |
| 2086 | { |
| 2087 | fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n", |
| 2088 | core_addr_to_string (osp)); |
| 2089 | fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n", |
| 2090 | call_info.memory.arg_offset); |
| 2091 | fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n", |
| 2092 | call_info.memory.ref_offset); |
| 2093 | fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n", |
| 2094 | core_addr_to_string_nz (osp - sp)); |
| 2095 | } |
| 2096 | } |
| 2097 | |
| 2098 | /* Now load the argument into registers, or onto the stack. */ |
| 2099 | |
| 2100 | if (struct_return) |
| 2101 | { |
| 2102 | gdb_byte buf[sizeof (LONGEST)]; |
| 2103 | |
| 2104 | store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr); |
| 2105 | regcache_cooked_write (regcache, RISCV_A0_REGNUM, buf); |
| 2106 | } |
| 2107 | |
| 2108 | for (i = 0; i < nargs; ++i) |
| 2109 | { |
| 2110 | CORE_ADDR dst; |
| 2111 | int second_arg_length = 0; |
| 2112 | const gdb_byte *second_arg_data; |
| 2113 | struct riscv_arg_info *info = &arg_info [i]; |
| 2114 | |
| 2115 | gdb_assert (info->length > 0); |
| 2116 | |
| 2117 | switch (info->argloc[0].loc_type) |
| 2118 | { |
| 2119 | case riscv_arg_info::location::in_reg: |
| 2120 | { |
| 2121 | gdb_byte tmp [sizeof (ULONGEST)]; |
| 2122 | |
| 2123 | gdb_assert (info->argloc[0].c_length <= info->length); |
| 2124 | memset (tmp, 0, sizeof (tmp)); |
| 2125 | memcpy (tmp, info->contents, info->argloc[0].c_length); |
| 2126 | regcache_cooked_write (regcache, |
| 2127 | info->argloc[0].loc_data.regno, |
| 2128 | tmp); |
| 2129 | second_arg_length = |
| 2130 | ((info->argloc[0].c_length < info->length) |
| 2131 | ? info->argloc[1].c_length : 0); |
| 2132 | second_arg_data = info->contents + info->argloc[1].c_offset; |
| 2133 | } |
| 2134 | break; |
| 2135 | |
| 2136 | case riscv_arg_info::location::on_stack: |
| 2137 | dst = sp_args + info->argloc[0].loc_data.offset; |
| 2138 | write_memory (dst, info->contents, info->length); |
| 2139 | second_arg_length = 0; |
| 2140 | break; |
| 2141 | |
| 2142 | case riscv_arg_info::location::by_ref: |
| 2143 | dst = sp_refs + info->argloc[0].loc_data.offset; |
| 2144 | write_memory (dst, info->contents, info->length); |
| 2145 | |
| 2146 | second_arg_length = call_info.xlen; |
| 2147 | second_arg_data = (gdb_byte *) &dst; |
| 2148 | break; |
| 2149 | |
| 2150 | default: |
| 2151 | gdb_assert_not_reached (_("unknown argument location type")); |
| 2152 | } |
| 2153 | |
| 2154 | if (second_arg_length > 0) |
| 2155 | { |
| 2156 | switch (info->argloc[1].loc_type) |
| 2157 | { |
| 2158 | case riscv_arg_info::location::in_reg: |
| 2159 | { |
| 2160 | gdb_byte tmp [sizeof (ULONGEST)]; |
| 2161 | |
| 2162 | gdb_assert (second_arg_length <= call_info.xlen); |
| 2163 | memset (tmp, 0, sizeof (tmp)); |
| 2164 | memcpy (tmp, second_arg_data, second_arg_length); |
| 2165 | regcache_cooked_write (regcache, |
| 2166 | info->argloc[1].loc_data.regno, |
| 2167 | tmp); |
| 2168 | } |
| 2169 | break; |
| 2170 | |
| 2171 | case riscv_arg_info::location::on_stack: |
| 2172 | { |
| 2173 | CORE_ADDR arg_addr; |
| 2174 | |
| 2175 | arg_addr = sp_args + info->argloc[1].loc_data.offset; |
| 2176 | write_memory (arg_addr, second_arg_data, second_arg_length); |
| 2177 | break; |
| 2178 | } |
| 2179 | |
| 2180 | case riscv_arg_info::location::by_ref: |
| 2181 | default: |
| 2182 | /* The second location should never be a reference, any |
| 2183 | argument being passed by reference just places its address |
| 2184 | in the first location and is done. */ |
| 2185 | error (_("invalid argument location")); |
| 2186 | break; |
| 2187 | } |
| 2188 | } |
| 2189 | } |
| 2190 | |
| 2191 | /* Set the dummy return value to bp_addr. |
| 2192 | A dummy breakpoint will be setup to execute the call. */ |
| 2193 | |
| 2194 | if (riscv_debug_infcall > 0) |
| 2195 | fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n", |
| 2196 | core_addr_to_string (bp_addr)); |
| 2197 | regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr); |
| 2198 | |
| 2199 | /* Finally, update the stack pointer. */ |
| 2200 | |
| 2201 | if (riscv_debug_infcall > 0) |
| 2202 | fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n", |
| 2203 | core_addr_to_string (sp)); |
| 2204 | regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp); |
| 2205 | |
| 2206 | return sp; |
| 2207 | } |
| 2208 | |
| 2209 | /* Implement the return_value gdbarch method. */ |
| 2210 | |
| 2211 | static enum return_value_convention |
| 2212 | riscv_return_value (struct gdbarch *gdbarch, |
| 2213 | struct value *function, |
| 2214 | struct type *type, |
| 2215 | struct regcache *regcache, |
| 2216 | gdb_byte *readbuf, |
| 2217 | const gdb_byte *writebuf) |
| 2218 | { |
| 2219 | enum type_code rv_type = TYPE_CODE (type); |
| 2220 | unsigned int rv_size = TYPE_LENGTH (type); |
| 2221 | int fp, regnum, flen; |
| 2222 | ULONGEST tmp; |
| 2223 | struct riscv_call_info call_info (gdbarch); |
| 2224 | struct riscv_arg_info info; |
| 2225 | struct type *arg_type; |
| 2226 | |
| 2227 | arg_type = check_typedef (type); |
| 2228 | riscv_arg_location (gdbarch, &info, &call_info, arg_type); |
| 2229 | |
| 2230 | if (riscv_debug_infcall > 0) |
| 2231 | { |
| 2232 | fprintf_unfiltered (gdb_stdlog, "riscv return value:\n"); |
| 2233 | fprintf_unfiltered (gdb_stdlog, "[R] "); |
| 2234 | riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0); |
| 2235 | fprintf_unfiltered (gdb_stdlog, "\n"); |
| 2236 | } |
| 2237 | |
| 2238 | if (readbuf != nullptr || writebuf != nullptr) |
| 2239 | { |
| 2240 | int regnum; |
| 2241 | |
| 2242 | switch (info.argloc[0].loc_type) |
| 2243 | { |
| 2244 | /* Return value in register(s). */ |
| 2245 | case riscv_arg_info::location::in_reg: |
| 2246 | { |
| 2247 | regnum = info.argloc[0].loc_data.regno; |
| 2248 | |
| 2249 | if (readbuf) |
| 2250 | regcache_cooked_read (regcache, regnum, readbuf); |
| 2251 | |
| 2252 | if (writebuf) |
| 2253 | regcache_cooked_write (regcache, regnum, writebuf); |
| 2254 | |
| 2255 | /* A return value in register can have a second part in a |
| 2256 | second register. */ |
| 2257 | if (info.argloc[0].c_length < info.length) |
| 2258 | { |
| 2259 | switch (info.argloc[1].loc_type) |
| 2260 | { |
| 2261 | case riscv_arg_info::location::in_reg: |
| 2262 | regnum = info.argloc[1].loc_data.regno; |
| 2263 | |
| 2264 | if (readbuf) |
| 2265 | { |
| 2266 | readbuf += info.argloc[1].c_offset; |
| 2267 | regcache_cooked_read (regcache, regnum, readbuf); |
| 2268 | } |
| 2269 | |
| 2270 | if (writebuf) |
| 2271 | { |
| 2272 | writebuf += info.argloc[1].c_offset; |
| 2273 | regcache_cooked_write (regcache, regnum, writebuf); |
| 2274 | } |
| 2275 | break; |
| 2276 | |
| 2277 | case riscv_arg_info::location::by_ref: |
| 2278 | case riscv_arg_info::location::on_stack: |
| 2279 | default: |
| 2280 | error (_("invalid argument location")); |
| 2281 | break; |
| 2282 | } |
| 2283 | } |
| 2284 | } |
| 2285 | break; |
| 2286 | |
| 2287 | /* Return value by reference will have its address in A0. */ |
| 2288 | case riscv_arg_info::location::by_ref: |
| 2289 | { |
| 2290 | ULONGEST addr; |
| 2291 | |
| 2292 | regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM, |
| 2293 | &addr); |
| 2294 | if (readbuf != nullptr) |
| 2295 | read_memory (addr, readbuf, info.length); |
| 2296 | if (writebuf != nullptr) |
| 2297 | write_memory (addr, writebuf, info.length); |
| 2298 | } |
| 2299 | break; |
| 2300 | |
| 2301 | case riscv_arg_info::location::on_stack: |
| 2302 | default: |
| 2303 | error (_("invalid argument location")); |
| 2304 | break; |
| 2305 | } |
| 2306 | } |
| 2307 | |
| 2308 | switch (info.argloc[0].loc_type) |
| 2309 | { |
| 2310 | case riscv_arg_info::location::in_reg: |
| 2311 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 2312 | case riscv_arg_info::location::by_ref: |
| 2313 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; |
| 2314 | case riscv_arg_info::location::on_stack: |
| 2315 | default: |
| 2316 | error (_("invalid argument location")); |
| 2317 | } |
| 2318 | } |
| 2319 | |
| 2320 | /* Implement the frame_align gdbarch method. */ |
| 2321 | |
| 2322 | static CORE_ADDR |
| 2323 | riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 2324 | { |
| 2325 | return align_down (addr, 16); |
| 2326 | } |
| 2327 | |
| 2328 | /* Implement the unwind_pc gdbarch method. */ |
| 2329 | |
| 2330 | static CORE_ADDR |
| 2331 | riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 2332 | { |
| 2333 | return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM); |
| 2334 | } |
| 2335 | |
| 2336 | /* Implement the unwind_sp gdbarch method. */ |
| 2337 | |
| 2338 | static CORE_ADDR |
| 2339 | riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 2340 | { |
| 2341 | return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM); |
| 2342 | } |
| 2343 | |
| 2344 | /* Implement the dummy_id gdbarch method. */ |
| 2345 | |
| 2346 | static struct frame_id |
| 2347 | riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 2348 | { |
| 2349 | return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM), |
| 2350 | get_frame_pc (this_frame)); |
| 2351 | } |
| 2352 | |
| 2353 | /* Generate, or return the cached frame cache for the RiscV frame |
| 2354 | unwinder. */ |
| 2355 | |
| 2356 | static struct trad_frame_cache * |
| 2357 | riscv_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 2358 | { |
| 2359 | CORE_ADDR pc; |
| 2360 | CORE_ADDR start_addr; |
| 2361 | CORE_ADDR stack_addr; |
| 2362 | struct trad_frame_cache *this_trad_cache; |
| 2363 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 2364 | |
| 2365 | if ((*this_cache) != NULL) |
| 2366 | return (struct trad_frame_cache *) *this_cache; |
| 2367 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
| 2368 | (*this_cache) = this_trad_cache; |
| 2369 | |
| 2370 | trad_frame_set_reg_realreg (this_trad_cache, gdbarch_pc_regnum (gdbarch), |
| 2371 | RISCV_RA_REGNUM); |
| 2372 | |
| 2373 | pc = get_frame_pc (this_frame); |
| 2374 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
| 2375 | stack_addr = get_frame_register_signed (this_frame, RISCV_SP_REGNUM); |
| 2376 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
| 2377 | |
| 2378 | trad_frame_set_this_base (this_trad_cache, stack_addr); |
| 2379 | |
| 2380 | return this_trad_cache; |
| 2381 | } |
| 2382 | |
| 2383 | /* Implement the this_id callback for RiscV frame unwinder. */ |
| 2384 | |
| 2385 | static void |
| 2386 | riscv_frame_this_id (struct frame_info *this_frame, |
| 2387 | void **prologue_cache, |
| 2388 | struct frame_id *this_id) |
| 2389 | { |
| 2390 | struct trad_frame_cache *info; |
| 2391 | |
| 2392 | info = riscv_frame_cache (this_frame, prologue_cache); |
| 2393 | trad_frame_get_id (info, this_id); |
| 2394 | } |
| 2395 | |
| 2396 | /* Implement the prev_register callback for RiscV frame unwinder. */ |
| 2397 | |
| 2398 | static struct value * |
| 2399 | riscv_frame_prev_register (struct frame_info *this_frame, |
| 2400 | void **prologue_cache, |
| 2401 | int regnum) |
| 2402 | { |
| 2403 | struct trad_frame_cache *info; |
| 2404 | |
| 2405 | info = riscv_frame_cache (this_frame, prologue_cache); |
| 2406 | return trad_frame_get_register (info, this_frame, regnum); |
| 2407 | } |
| 2408 | |
| 2409 | /* Structure defining the RiscV normal frame unwind functions. Since we |
| 2410 | are the fallback unwinder (DWARF unwinder is used first), we use the |
| 2411 | default frame sniffer, which always accepts the frame. */ |
| 2412 | |
| 2413 | static const struct frame_unwind riscv_frame_unwind = |
| 2414 | { |
| 2415 | /*.type =*/ NORMAL_FRAME, |
| 2416 | /*.stop_reason =*/ default_frame_unwind_stop_reason, |
| 2417 | /*.this_id =*/ riscv_frame_this_id, |
| 2418 | /*.prev_register =*/ riscv_frame_prev_register, |
| 2419 | /*.unwind_data =*/ NULL, |
| 2420 | /*.sniffer =*/ default_frame_sniffer, |
| 2421 | /*.dealloc_cache =*/ NULL, |
| 2422 | /*.prev_arch =*/ NULL, |
| 2423 | }; |
| 2424 | |
| 2425 | /* Initialize the current architecture based on INFO. If possible, |
| 2426 | re-use an architecture from ARCHES, which is a list of |
| 2427 | architectures already created during this debugging session. |
| 2428 | |
| 2429 | Called e.g. at program startup, when reading a core file, and when |
| 2430 | reading a binary file. */ |
| 2431 | |
| 2432 | static struct gdbarch * |
| 2433 | riscv_gdbarch_init (struct gdbarch_info info, |
| 2434 | struct gdbarch_list *arches) |
| 2435 | { |
| 2436 | struct gdbarch *gdbarch; |
| 2437 | struct gdbarch_tdep *tdep; |
| 2438 | struct gdbarch_tdep tmp_tdep; |
| 2439 | bool has_compressed_isa = false; |
| 2440 | int i; |
| 2441 | |
| 2442 | /* Ideally, we'd like to get as much information from the target for |
| 2443 | things like register size, and whether the target has floating point |
| 2444 | hardware. However, there are some things that the target can't tell |
| 2445 | us, like, what ABI is being used. |
| 2446 | |
| 2447 | So, for now, we take as much information as possible from the ELF, |
| 2448 | including things like register size, and FP hardware support, along |
| 2449 | with information about the ABI. |
| 2450 | |
| 2451 | Information about this target is built up in TMP_TDEP, and then we |
| 2452 | look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no |
| 2453 | match is found we'll create a new gdbarch and copy TMP_TDEP over. */ |
| 2454 | memset (&tmp_tdep, 0, sizeof (tmp_tdep)); |
| 2455 | |
| 2456 | if (info.abfd != NULL |
| 2457 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) |
| 2458 | { |
| 2459 | unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS]; |
| 2460 | int e_flags = elf_elfheader (info.abfd)->e_flags; |
| 2461 | |
| 2462 | if (eclass == ELFCLASS32) |
| 2463 | tmp_tdep.abi.fields.base_len = 1; |
| 2464 | else if (eclass == ELFCLASS64) |
| 2465 | tmp_tdep.abi.fields.base_len = 2; |
| 2466 | else |
| 2467 | internal_error (__FILE__, __LINE__, |
| 2468 | _("unknown ELF header class %d"), eclass); |
| 2469 | |
| 2470 | if (e_flags & EF_RISCV_RVC) |
| 2471 | { |
| 2472 | has_compressed_isa = true; |
| 2473 | tmp_tdep.core_features |= (1 << ('C' - 'A')); |
| 2474 | } |
| 2475 | |
| 2476 | if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE) |
| 2477 | { |
| 2478 | tmp_tdep.abi.fields.float_abi = 2; |
| 2479 | tmp_tdep.core_features |= (1 << ('D' - 'A')); |
| 2480 | tmp_tdep.core_features |= (1 << ('F' - 'A')); |
| 2481 | } |
| 2482 | else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE) |
| 2483 | { |
| 2484 | tmp_tdep.abi.fields.float_abi = 1; |
| 2485 | tmp_tdep.core_features |= (1 << ('F' - 'A')); |
| 2486 | } |
| 2487 | } |
| 2488 | else |
| 2489 | { |
| 2490 | const struct bfd_arch_info *binfo = info.bfd_arch_info; |
| 2491 | |
| 2492 | if (binfo->bits_per_word == 32) |
| 2493 | tmp_tdep.abi.fields.base_len = 1; |
| 2494 | else if (binfo->bits_per_word == 64) |
| 2495 | tmp_tdep.abi.fields.base_len = 2; |
| 2496 | else |
| 2497 | internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"), |
| 2498 | binfo->bits_per_word); |
| 2499 | } |
| 2500 | |
| 2501 | /* Find a candidate among the list of pre-declared architectures. */ |
| 2502 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
| 2503 | arches != NULL; |
| 2504 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) |
| 2505 | if (gdbarch_tdep (arches->gdbarch)->abi.value == tmp_tdep.abi.value) |
| 2506 | return arches->gdbarch; |
| 2507 | |
| 2508 | /* None found, so create a new architecture from the information provided. */ |
| 2509 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof *tdep); |
| 2510 | gdbarch = gdbarch_alloc (&info, tdep); |
| 2511 | memcpy (tdep, &tmp_tdep, sizeof (tmp_tdep)); |
| 2512 | |
| 2513 | /* Target data types. */ |
| 2514 | set_gdbarch_short_bit (gdbarch, 16); |
| 2515 | set_gdbarch_int_bit (gdbarch, 32); |
| 2516 | set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); |
| 2517 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 2518 | set_gdbarch_float_bit (gdbarch, 32); |
| 2519 | set_gdbarch_double_bit (gdbarch, 64); |
| 2520 | set_gdbarch_long_double_bit (gdbarch, 128); |
| 2521 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
| 2522 | set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); |
| 2523 | set_gdbarch_char_signed (gdbarch, 0); |
| 2524 | |
| 2525 | /* Information about the target architecture. */ |
| 2526 | set_gdbarch_return_value (gdbarch, riscv_return_value); |
| 2527 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc); |
| 2528 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind); |
| 2529 | |
| 2530 | /* Register architecture. */ |
| 2531 | set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1); |
| 2532 | set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM); |
| 2533 | set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM); |
| 2534 | set_gdbarch_ps_regnum (gdbarch, RISCV_FP_REGNUM); |
| 2535 | set_gdbarch_deprecated_fp_regnum (gdbarch, RISCV_FP_REGNUM); |
| 2536 | |
| 2537 | /* Functions to supply register information. */ |
| 2538 | set_gdbarch_register_name (gdbarch, riscv_register_name); |
| 2539 | set_gdbarch_register_type (gdbarch, riscv_register_type); |
| 2540 | set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info); |
| 2541 | set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p); |
| 2542 | |
| 2543 | /* Functions to analyze frames. */ |
| 2544 | set_gdbarch_decr_pc_after_break (gdbarch, (has_compressed_isa ? 2 : 4)); |
| 2545 | set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue); |
| 2546 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 2547 | set_gdbarch_frame_align (gdbarch, riscv_frame_align); |
| 2548 | |
| 2549 | /* Functions to access frame data. */ |
| 2550 | set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc); |
| 2551 | set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp); |
| 2552 | |
| 2553 | /* Functions handling dummy frames. */ |
| 2554 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
| 2555 | set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code); |
| 2556 | set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call); |
| 2557 | set_gdbarch_dummy_id (gdbarch, riscv_dummy_id); |
| 2558 | |
| 2559 | /* Frame unwinders. Use DWARF debug info if available, otherwise use our own |
| 2560 | unwinder. */ |
| 2561 | dwarf2_append_unwinders (gdbarch); |
| 2562 | frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind); |
| 2563 | |
| 2564 | for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) |
| 2565 | user_reg_add (gdbarch, riscv_register_aliases[i].name, |
| 2566 | value_of_riscv_user_reg, &riscv_register_aliases[i].regnum); |
| 2567 | |
| 2568 | return gdbarch; |
| 2569 | } |
| 2570 | |
| 2571 | |
| 2572 | /* Allocate new riscv_inferior_data object. */ |
| 2573 | |
| 2574 | static struct riscv_inferior_data * |
| 2575 | riscv_new_inferior_data (void) |
| 2576 | { |
| 2577 | struct riscv_inferior_data *inf_data |
| 2578 | = new (struct riscv_inferior_data); |
| 2579 | inf_data->misa_read = false; |
| 2580 | return inf_data; |
| 2581 | } |
| 2582 | |
| 2583 | /* Free inferior data. */ |
| 2584 | |
| 2585 | static void |
| 2586 | riscv_inferior_data_cleanup (struct inferior *inf, void *data) |
| 2587 | { |
| 2588 | struct riscv_inferior_data *inf_data = |
| 2589 | static_cast <struct riscv_inferior_data *> (data); |
| 2590 | delete (inf_data); |
| 2591 | } |
| 2592 | |
| 2593 | /* Return riscv_inferior_data for the given INFERIOR. If not yet created, |
| 2594 | construct it. */ |
| 2595 | |
| 2596 | struct riscv_inferior_data * |
| 2597 | riscv_inferior_data (struct inferior *const inf) |
| 2598 | { |
| 2599 | struct riscv_inferior_data *inf_data; |
| 2600 | |
| 2601 | gdb_assert (inf != NULL); |
| 2602 | |
| 2603 | inf_data |
| 2604 | = (struct riscv_inferior_data *) inferior_data (inf, riscv_inferior_data_reg); |
| 2605 | if (inf_data == NULL) |
| 2606 | { |
| 2607 | inf_data = riscv_new_inferior_data (); |
| 2608 | set_inferior_data (inf, riscv_inferior_data_reg, inf_data); |
| 2609 | } |
| 2610 | |
| 2611 | return inf_data; |
| 2612 | } |
| 2613 | |
| 2614 | /* Free the inferior data when an inferior exits. */ |
| 2615 | |
| 2616 | static void |
| 2617 | riscv_invalidate_inferior_data (struct inferior *inf) |
| 2618 | { |
| 2619 | struct riscv_inferior_data *inf_data; |
| 2620 | |
| 2621 | gdb_assert (inf != NULL); |
| 2622 | |
| 2623 | /* Don't call RISCV_INFERIOR_DATA as we don't want to create the data if |
| 2624 | we've not already created it by this point. */ |
| 2625 | inf_data |
| 2626 | = (struct riscv_inferior_data *) inferior_data (inf, riscv_inferior_data_reg); |
| 2627 | if (inf_data != NULL) |
| 2628 | { |
| 2629 | delete (inf_data); |
| 2630 | set_inferior_data (inf, riscv_inferior_data_reg, NULL); |
| 2631 | } |
| 2632 | } |
| 2633 | |
| 2634 | void |
| 2635 | _initialize_riscv_tdep (void) |
| 2636 | { |
| 2637 | gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL); |
| 2638 | |
| 2639 | /* Register per-inferior data. */ |
| 2640 | riscv_inferior_data_reg |
| 2641 | = register_inferior_data_with_cleanup (NULL, riscv_inferior_data_cleanup); |
| 2642 | |
| 2643 | /* Observers used to invalidate the inferior data when needed. */ |
| 2644 | gdb::observers::inferior_exit.attach (riscv_invalidate_inferior_data); |
| 2645 | gdb::observers::inferior_appeared.attach (riscv_invalidate_inferior_data); |
| 2646 | |
| 2647 | /* Add root prefix command for all "set debug riscv" and "show debug |
| 2648 | riscv" commands. */ |
| 2649 | add_prefix_cmd ("riscv", no_class, set_debug_riscv_command, |
| 2650 | _("RISC-V specific debug commands."), |
| 2651 | &setdebugriscvcmdlist, "set debug riscv ", 0, |
| 2652 | &setdebuglist); |
| 2653 | |
| 2654 | add_prefix_cmd ("riscv", no_class, show_debug_riscv_command, |
| 2655 | _("RISC-V specific debug commands."), |
| 2656 | &showdebugriscvcmdlist, "show debug riscv ", 0, |
| 2657 | &showdebuglist); |
| 2658 | |
| 2659 | add_setshow_zuinteger_cmd ("infcall", class_maintenance, |
| 2660 | &riscv_debug_infcall, _("\ |
| 2661 | Set riscv inferior call debugging."), _("\ |
| 2662 | Show riscv inferior call debugging."), _("\ |
| 2663 | When non-zero, print debugging information for the riscv specific parts\n\ |
| 2664 | of the inferior call mechanism."), |
| 2665 | NULL, |
| 2666 | show_riscv_debug_variable, |
| 2667 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); |
| 2668 | |
| 2669 | /* Add root prefix command for all "set riscv" and "show riscv" commands. */ |
| 2670 | add_prefix_cmd ("riscv", no_class, set_riscv_command, |
| 2671 | _("RISC-V specific commands."), |
| 2672 | &setriscvcmdlist, "set riscv ", 0, &setlist); |
| 2673 | |
| 2674 | add_prefix_cmd ("riscv", no_class, show_riscv_command, |
| 2675 | _("RISC-V specific commands."), |
| 2676 | &showriscvcmdlist, "show riscv ", 0, &showlist); |
| 2677 | |
| 2678 | |
| 2679 | use_compressed_breakpoints = AUTO_BOOLEAN_AUTO; |
| 2680 | add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class, |
| 2681 | &use_compressed_breakpoints, |
| 2682 | _("\ |
| 2683 | Set debugger's use of compressed breakpoints."), _(" \ |
| 2684 | Show debugger's use of compressed breakpoints."), _("\ |
| 2685 | Debugging compressed code requires compressed breakpoints to be used. If\n \ |
| 2686 | left to 'auto' then gdb will use them if $misa indicates the C extension\n \ |
| 2687 | is supported. If that doesn't give the correct behavior, then this option\n\ |
| 2688 | can be used."), |
| 2689 | NULL, |
| 2690 | show_use_compressed_breakpoints, |
| 2691 | &setriscvcmdlist, |
| 2692 | &showriscvcmdlist); |
| 2693 | } |