| 1 | /* Target-dependent code for the RISC-V architecture, for GDB. |
| 2 | |
| 3 | Copyright (C) 2018-2020 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #include "defs.h" |
| 21 | #include "frame.h" |
| 22 | #include "inferior.h" |
| 23 | #include "symtab.h" |
| 24 | #include "value.h" |
| 25 | #include "gdbcmd.h" |
| 26 | #include "language.h" |
| 27 | #include "gdbcore.h" |
| 28 | #include "symfile.h" |
| 29 | #include "objfiles.h" |
| 30 | #include "gdbtypes.h" |
| 31 | #include "target.h" |
| 32 | #include "arch-utils.h" |
| 33 | #include "regcache.h" |
| 34 | #include "osabi.h" |
| 35 | #include "riscv-tdep.h" |
| 36 | #include "block.h" |
| 37 | #include "reggroups.h" |
| 38 | #include "opcode/riscv.h" |
| 39 | #include "elf/riscv.h" |
| 40 | #include "elf-bfd.h" |
| 41 | #include "symcat.h" |
| 42 | #include "dis-asm.h" |
| 43 | #include "frame-unwind.h" |
| 44 | #include "frame-base.h" |
| 45 | #include "trad-frame.h" |
| 46 | #include "infcall.h" |
| 47 | #include "floatformat.h" |
| 48 | #include "remote.h" |
| 49 | #include "target-descriptions.h" |
| 50 | #include "dwarf2/frame.h" |
| 51 | #include "user-regs.h" |
| 52 | #include "valprint.h" |
| 53 | #include "gdbsupport/common-defs.h" |
| 54 | #include "opcode/riscv-opc.h" |
| 55 | #include "cli/cli-decode.h" |
| 56 | #include "observable.h" |
| 57 | #include "prologue-value.h" |
| 58 | #include "arch/riscv.h" |
| 59 | #include "riscv-ravenscar-thread.h" |
| 60 | |
| 61 | /* The stack must be 16-byte aligned. */ |
| 62 | #define SP_ALIGNMENT 16 |
| 63 | |
| 64 | /* The biggest alignment that the target supports. */ |
| 65 | #define BIGGEST_ALIGNMENT 16 |
| 66 | |
| 67 | /* Define a series of is_XXX_insn functions to check if the value INSN |
| 68 | is an instance of instruction XXX. */ |
| 69 | #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \ |
| 70 | static inline bool is_ ## INSN_NAME ## _insn (long insn) \ |
| 71 | { \ |
| 72 | return (insn & INSN_MASK) == INSN_MATCH; \ |
| 73 | } |
| 74 | #include "opcode/riscv-opc.h" |
| 75 | #undef DECLARE_INSN |
| 76 | |
| 77 | /* Cached information about a frame. */ |
| 78 | |
| 79 | struct riscv_unwind_cache |
| 80 | { |
| 81 | /* The register from which we can calculate the frame base. This is |
| 82 | usually $sp or $fp. */ |
| 83 | int frame_base_reg; |
| 84 | |
| 85 | /* The offset from the current value in register FRAME_BASE_REG to the |
| 86 | actual frame base address. */ |
| 87 | int frame_base_offset; |
| 88 | |
| 89 | /* Information about previous register values. */ |
| 90 | struct trad_frame_saved_reg *regs; |
| 91 | |
| 92 | /* The id for this frame. */ |
| 93 | struct frame_id this_id; |
| 94 | |
| 95 | /* The base (stack) address for this frame. This is the stack pointer |
| 96 | value on entry to this frame before any adjustments are made. */ |
| 97 | CORE_ADDR frame_base; |
| 98 | }; |
| 99 | |
| 100 | /* RISC-V specific register group for CSRs. */ |
| 101 | |
| 102 | static reggroup *csr_reggroup = NULL; |
| 103 | |
| 104 | /* Callback function for user_reg_add. */ |
| 105 | |
| 106 | static struct value * |
| 107 | value_of_riscv_user_reg (struct frame_info *frame, const void *baton) |
| 108 | { |
| 109 | const int *reg_p = (const int *) baton; |
| 110 | return value_of_register (*reg_p, frame); |
| 111 | } |
| 112 | |
| 113 | /* Information about a register alias that needs to be set up for this |
| 114 | target. These are collected when the target's XML description is |
| 115 | analysed, and then processed later, once the gdbarch has been created. */ |
| 116 | |
| 117 | class riscv_pending_register_alias |
| 118 | { |
| 119 | public: |
| 120 | /* Constructor. */ |
| 121 | |
| 122 | riscv_pending_register_alias (const char *name, const void *baton) |
| 123 | : m_name (name), |
| 124 | m_baton (baton) |
| 125 | { /* Nothing. */ } |
| 126 | |
| 127 | /* Convert this into a user register for GDBARCH. */ |
| 128 | |
| 129 | void create (struct gdbarch *gdbarch) const |
| 130 | { |
| 131 | user_reg_add (gdbarch, m_name, value_of_riscv_user_reg, m_baton); |
| 132 | } |
| 133 | |
| 134 | private: |
| 135 | /* The name for this alias. */ |
| 136 | const char *m_name; |
| 137 | |
| 138 | /* The baton value for passing to user_reg_add. This must point to some |
| 139 | data that will live for at least as long as the gdbarch object to |
| 140 | which the user register is attached. */ |
| 141 | const void *m_baton; |
| 142 | }; |
| 143 | |
| 144 | /* Registers in the RISCV_REGISTER_FEATURE lists below are either optional, |
| 145 | or required. For example the $pc register is always going to be a |
| 146 | required register, you can't do much debugging without that. In |
| 147 | contrast, most of the CSRs are optional, GDB doesn't require them in |
| 148 | order to have a useful debug session. This enum models the difference |
| 149 | between these register types. */ |
| 150 | |
| 151 | enum riscv_register_required_status |
| 152 | { |
| 153 | /* This register is optional within this feature. */ |
| 154 | RISCV_REG_OPTIONAL, |
| 155 | |
| 156 | /* This register is required within this feature. */ |
| 157 | RISCV_REG_REQUIRED, |
| 158 | |
| 159 | /* This register is required, the register must either be in this |
| 160 | feature, or it could appear within the CSR feature. */ |
| 161 | RISCV_REG_REQUIRED_MAYBE_CSR |
| 162 | }; |
| 163 | |
| 164 | /* A set of registers that we expect to find in a tdesc_feature. These |
| 165 | are use in RISCV_GDBARCH_INIT when processing the target description. */ |
| 166 | |
| 167 | struct riscv_register_feature |
| 168 | { |
| 169 | /* Information for a single register. */ |
| 170 | struct register_info |
| 171 | { |
| 172 | /* The GDB register number for this register. */ |
| 173 | int regnum; |
| 174 | |
| 175 | /* List of names for this register. The first name in this list is the |
| 176 | preferred name, the name GDB should use when describing this |
| 177 | register. */ |
| 178 | std::vector<const char *> names; |
| 179 | |
| 180 | /* Is this register required within this feature? In some cases the |
| 181 | register could be required, but might also be in the CSR feature. */ |
| 182 | riscv_register_required_status required; |
| 183 | |
| 184 | /* Look in FEATURE for a register with a name from this classes names |
| 185 | list. If the register is found then register its number with |
| 186 | TDESC_DATA and add all its aliases to the ALIASES list. REG_SET is |
| 187 | used to help create the aliases. */ |
| 188 | bool check (struct tdesc_arch_data *tdesc_data, |
| 189 | const struct tdesc_feature *feature, |
| 190 | const struct riscv_register_feature *reg_set, |
| 191 | std::vector<riscv_pending_register_alias> *aliases) const; |
| 192 | }; |
| 193 | |
| 194 | /* The name for this feature. This is the name used to find this feature |
| 195 | within the target description. */ |
| 196 | const char *name; |
| 197 | |
| 198 | /* For x-regs and f-regs we always force GDB to use the first name from |
| 199 | the REGISTERS.NAMES vector, it is therefore important that we create |
| 200 | user-register aliases for all of the remaining names at indexes 1+ in |
| 201 | the names vector. |
| 202 | |
| 203 | For CSRs we take a different approach, we prefer whatever name the |
| 204 | target description uses, in this case we want to create user-register |
| 205 | aliases for any other names that aren't the target description |
| 206 | provided name. |
| 207 | |
| 208 | When this flag is true we are dealing with the first case, and when |
| 209 | this is false we are dealing with the latter. */ |
| 210 | bool prefer_first_name; |
| 211 | |
| 212 | /* List of all the registers that we expect that we might find in this |
| 213 | register set. */ |
| 214 | std::vector<struct register_info> registers; |
| 215 | }; |
| 216 | |
| 217 | /* See description in the class declaration above. */ |
| 218 | |
| 219 | bool |
| 220 | riscv_register_feature::register_info::check |
| 221 | (struct tdesc_arch_data *tdesc_data, |
| 222 | const struct tdesc_feature *feature, |
| 223 | const struct riscv_register_feature *reg_set, |
| 224 | std::vector<riscv_pending_register_alias> *aliases) const |
| 225 | { |
| 226 | for (const char *name : this->names) |
| 227 | { |
| 228 | bool found = tdesc_numbered_register (feature, tdesc_data, |
| 229 | this->regnum, name); |
| 230 | if (found) |
| 231 | { |
| 232 | /* We know that the target description mentions this |
| 233 | register. In RISCV_REGISTER_NAME we ensure that GDB |
| 234 | always uses the first name for each register, so here we |
| 235 | add aliases for all of the remaining names. */ |
| 236 | bool prefer_first_name = reg_set->prefer_first_name; |
| 237 | int start_index = prefer_first_name ? 1 : 0; |
| 238 | for (int i = start_index; i < this->names.size (); ++i) |
| 239 | { |
| 240 | const char *alias = this->names[i]; |
| 241 | if (alias == name && !prefer_first_name) |
| 242 | continue; |
| 243 | aliases->emplace_back (alias, (void *) &this->regnum); |
| 244 | } |
| 245 | return true; |
| 246 | } |
| 247 | } |
| 248 | return false; |
| 249 | } |
| 250 | |
| 251 | /* The general x-registers feature set. */ |
| 252 | |
| 253 | static const struct riscv_register_feature riscv_xreg_feature = |
| 254 | { |
| 255 | "org.gnu.gdb.riscv.cpu", true, |
| 256 | { |
| 257 | { RISCV_ZERO_REGNUM + 0, { "zero", "x0" }, RISCV_REG_REQUIRED }, |
| 258 | { RISCV_ZERO_REGNUM + 1, { "ra", "x1" }, RISCV_REG_REQUIRED }, |
| 259 | { RISCV_ZERO_REGNUM + 2, { "sp", "x2" }, RISCV_REG_REQUIRED }, |
| 260 | { RISCV_ZERO_REGNUM + 3, { "gp", "x3" }, RISCV_REG_REQUIRED }, |
| 261 | { RISCV_ZERO_REGNUM + 4, { "tp", "x4" }, RISCV_REG_REQUIRED }, |
| 262 | { RISCV_ZERO_REGNUM + 5, { "t0", "x5" }, RISCV_REG_REQUIRED }, |
| 263 | { RISCV_ZERO_REGNUM + 6, { "t1", "x6" }, RISCV_REG_REQUIRED }, |
| 264 | { RISCV_ZERO_REGNUM + 7, { "t2", "x7" }, RISCV_REG_REQUIRED }, |
| 265 | { RISCV_ZERO_REGNUM + 8, { "fp", "x8", "s0" }, RISCV_REG_REQUIRED }, |
| 266 | { RISCV_ZERO_REGNUM + 9, { "s1", "x9" }, RISCV_REG_REQUIRED }, |
| 267 | { RISCV_ZERO_REGNUM + 10, { "a0", "x10" }, RISCV_REG_REQUIRED }, |
| 268 | { RISCV_ZERO_REGNUM + 11, { "a1", "x11" }, RISCV_REG_REQUIRED }, |
| 269 | { RISCV_ZERO_REGNUM + 12, { "a2", "x12" }, RISCV_REG_REQUIRED }, |
| 270 | { RISCV_ZERO_REGNUM + 13, { "a3", "x13" }, RISCV_REG_REQUIRED }, |
| 271 | { RISCV_ZERO_REGNUM + 14, { "a4", "x14" }, RISCV_REG_REQUIRED }, |
| 272 | { RISCV_ZERO_REGNUM + 15, { "a5", "x15" }, RISCV_REG_REQUIRED }, |
| 273 | { RISCV_ZERO_REGNUM + 16, { "a6", "x16" }, RISCV_REG_REQUIRED }, |
| 274 | { RISCV_ZERO_REGNUM + 17, { "a7", "x17" }, RISCV_REG_REQUIRED }, |
| 275 | { RISCV_ZERO_REGNUM + 18, { "s2", "x18" }, RISCV_REG_REQUIRED }, |
| 276 | { RISCV_ZERO_REGNUM + 19, { "s3", "x19" }, RISCV_REG_REQUIRED }, |
| 277 | { RISCV_ZERO_REGNUM + 20, { "s4", "x20" }, RISCV_REG_REQUIRED }, |
| 278 | { RISCV_ZERO_REGNUM + 21, { "s5", "x21" }, RISCV_REG_REQUIRED }, |
| 279 | { RISCV_ZERO_REGNUM + 22, { "s6", "x22" }, RISCV_REG_REQUIRED }, |
| 280 | { RISCV_ZERO_REGNUM + 23, { "s7", "x23" }, RISCV_REG_REQUIRED }, |
| 281 | { RISCV_ZERO_REGNUM + 24, { "s8", "x24" }, RISCV_REG_REQUIRED }, |
| 282 | { RISCV_ZERO_REGNUM + 25, { "s9", "x25" }, RISCV_REG_REQUIRED }, |
| 283 | { RISCV_ZERO_REGNUM + 26, { "s10", "x26" }, RISCV_REG_REQUIRED }, |
| 284 | { RISCV_ZERO_REGNUM + 27, { "s11", "x27" }, RISCV_REG_REQUIRED }, |
| 285 | { RISCV_ZERO_REGNUM + 28, { "t3", "x28" }, RISCV_REG_REQUIRED }, |
| 286 | { RISCV_ZERO_REGNUM + 29, { "t4", "x29" }, RISCV_REG_REQUIRED }, |
| 287 | { RISCV_ZERO_REGNUM + 30, { "t5", "x30" }, RISCV_REG_REQUIRED }, |
| 288 | { RISCV_ZERO_REGNUM + 31, { "t6", "x31" }, RISCV_REG_REQUIRED }, |
| 289 | { RISCV_ZERO_REGNUM + 32, { "pc" }, RISCV_REG_REQUIRED } |
| 290 | } |
| 291 | }; |
| 292 | |
| 293 | /* The f-registers feature set. */ |
| 294 | |
| 295 | static const struct riscv_register_feature riscv_freg_feature = |
| 296 | { |
| 297 | "org.gnu.gdb.riscv.fpu", true, |
| 298 | { |
| 299 | { RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" }, RISCV_REG_REQUIRED }, |
| 300 | { RISCV_FIRST_FP_REGNUM + 1, { "ft1", "f1" }, RISCV_REG_REQUIRED }, |
| 301 | { RISCV_FIRST_FP_REGNUM + 2, { "ft2", "f2" }, RISCV_REG_REQUIRED }, |
| 302 | { RISCV_FIRST_FP_REGNUM + 3, { "ft3", "f3" }, RISCV_REG_REQUIRED }, |
| 303 | { RISCV_FIRST_FP_REGNUM + 4, { "ft4", "f4" }, RISCV_REG_REQUIRED }, |
| 304 | { RISCV_FIRST_FP_REGNUM + 5, { "ft5", "f5" }, RISCV_REG_REQUIRED }, |
| 305 | { RISCV_FIRST_FP_REGNUM + 6, { "ft6", "f6" }, RISCV_REG_REQUIRED }, |
| 306 | { RISCV_FIRST_FP_REGNUM + 7, { "ft7", "f7" }, RISCV_REG_REQUIRED }, |
| 307 | { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8" }, RISCV_REG_REQUIRED }, |
| 308 | { RISCV_FIRST_FP_REGNUM + 9, { "fs1", "f9" }, RISCV_REG_REQUIRED }, |
| 309 | { RISCV_FIRST_FP_REGNUM + 10, { "fa0", "f10" }, RISCV_REG_REQUIRED }, |
| 310 | { RISCV_FIRST_FP_REGNUM + 11, { "fa1", "f11" }, RISCV_REG_REQUIRED }, |
| 311 | { RISCV_FIRST_FP_REGNUM + 12, { "fa2", "f12" }, RISCV_REG_REQUIRED }, |
| 312 | { RISCV_FIRST_FP_REGNUM + 13, { "fa3", "f13" }, RISCV_REG_REQUIRED }, |
| 313 | { RISCV_FIRST_FP_REGNUM + 14, { "fa4", "f14" }, RISCV_REG_REQUIRED }, |
| 314 | { RISCV_FIRST_FP_REGNUM + 15, { "fa5", "f15" }, RISCV_REG_REQUIRED }, |
| 315 | { RISCV_FIRST_FP_REGNUM + 16, { "fa6", "f16" }, RISCV_REG_REQUIRED }, |
| 316 | { RISCV_FIRST_FP_REGNUM + 17, { "fa7", "f17" }, RISCV_REG_REQUIRED }, |
| 317 | { RISCV_FIRST_FP_REGNUM + 18, { "fs2", "f18" }, RISCV_REG_REQUIRED }, |
| 318 | { RISCV_FIRST_FP_REGNUM + 19, { "fs3", "f19" }, RISCV_REG_REQUIRED }, |
| 319 | { RISCV_FIRST_FP_REGNUM + 20, { "fs4", "f20" }, RISCV_REG_REQUIRED }, |
| 320 | { RISCV_FIRST_FP_REGNUM + 21, { "fs5", "f21" }, RISCV_REG_REQUIRED }, |
| 321 | { RISCV_FIRST_FP_REGNUM + 22, { "fs6", "f22" }, RISCV_REG_REQUIRED }, |
| 322 | { RISCV_FIRST_FP_REGNUM + 23, { "fs7", "f23" }, RISCV_REG_REQUIRED }, |
| 323 | { RISCV_FIRST_FP_REGNUM + 24, { "fs8", "f24" }, RISCV_REG_REQUIRED }, |
| 324 | { RISCV_FIRST_FP_REGNUM + 25, { "fs9", "f25" }, RISCV_REG_REQUIRED }, |
| 325 | { RISCV_FIRST_FP_REGNUM + 26, { "fs10", "f26" }, RISCV_REG_REQUIRED }, |
| 326 | { RISCV_FIRST_FP_REGNUM + 27, { "fs11", "f27" }, RISCV_REG_REQUIRED }, |
| 327 | { RISCV_FIRST_FP_REGNUM + 28, { "ft8", "f28" }, RISCV_REG_REQUIRED }, |
| 328 | { RISCV_FIRST_FP_REGNUM + 29, { "ft9", "f29" }, RISCV_REG_REQUIRED }, |
| 329 | { RISCV_FIRST_FP_REGNUM + 30, { "ft10", "f30" }, RISCV_REG_REQUIRED }, |
| 330 | { RISCV_FIRST_FP_REGNUM + 31, { "ft11", "f31" }, RISCV_REG_REQUIRED }, |
| 331 | |
| 332 | { RISCV_CSR_FFLAGS_REGNUM, { "fflags", "csr1" }, RISCV_REG_REQUIRED_MAYBE_CSR }, |
| 333 | { RISCV_CSR_FRM_REGNUM, { "frm", "csr2" }, RISCV_REG_REQUIRED_MAYBE_CSR }, |
| 334 | { RISCV_CSR_FCSR_REGNUM, { "fcsr", "csr3" }, RISCV_REG_REQUIRED_MAYBE_CSR }, |
| 335 | |
| 336 | } |
| 337 | }; |
| 338 | |
| 339 | /* Set of virtual registers. These are not physical registers on the |
| 340 | hardware, but might be available from the target. These are not pseudo |
| 341 | registers, reading these really does result in a register read from the |
| 342 | target, it is just that there might not be a physical register backing |
| 343 | the result. */ |
| 344 | |
| 345 | static const struct riscv_register_feature riscv_virtual_feature = |
| 346 | { |
| 347 | "org.gnu.gdb.riscv.virtual", false, |
| 348 | { |
| 349 | { RISCV_PRIV_REGNUM, { "priv" }, RISCV_REG_OPTIONAL } |
| 350 | } |
| 351 | }; |
| 352 | |
| 353 | /* Feature set for CSRs. This set is NOT constant as the register names |
| 354 | list for each register is not complete. The aliases are computed |
| 355 | during RISCV_CREATE_CSR_ALIASES. */ |
| 356 | |
| 357 | static struct riscv_register_feature riscv_csr_feature = |
| 358 | { |
| 359 | "org.gnu.gdb.riscv.csr", false, |
| 360 | { |
| 361 | #define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \ |
| 362 | { RISCV_ ## VALUE ## _REGNUM, { # NAME }, RISCV_REG_OPTIONAL }, |
| 363 | #include "opcode/riscv-opc.h" |
| 364 | #undef DECLARE_CSR |
| 365 | } |
| 366 | }; |
| 367 | |
| 368 | /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them |
| 369 | to the name list for each register. */ |
| 370 | |
| 371 | static void |
| 372 | riscv_create_csr_aliases () |
| 373 | { |
| 374 | for (auto ® : riscv_csr_feature.registers) |
| 375 | { |
| 376 | int csr_num = reg.regnum - RISCV_FIRST_CSR_REGNUM; |
| 377 | const char *alias = xstrprintf ("csr%d", csr_num); |
| 378 | reg.names.push_back (alias); |
| 379 | |
| 380 | /* Setup the other csr aliases. We don't use a switch table here in |
| 381 | case there are multiple aliases with the same value. Also filter |
| 382 | based on ABRT_VER in order to avoid a very old alias for misa that |
| 383 | duplicates the name "misa" but at a different CSR address. */ |
| 384 | #define DECLARE_CSR_ALIAS(NAME,VALUE,CLASS,DEF_VER,ABRT_VER) \ |
| 385 | if (csr_num == VALUE && ABRT_VER >= PRIV_SPEC_CLASS_1P11) \ |
| 386 | reg.names.push_back ( # NAME ); |
| 387 | #include "opcode/riscv-opc.h" |
| 388 | #undef DECLARE_CSR_ALIAS |
| 389 | } |
| 390 | } |
| 391 | |
| 392 | /* Controls whether we place compressed breakpoints or not. When in auto |
| 393 | mode GDB tries to determine if the target supports compressed |
| 394 | breakpoints, and uses them if it does. */ |
| 395 | |
| 396 | static enum auto_boolean use_compressed_breakpoints; |
| 397 | |
| 398 | /* The show callback for 'show riscv use-compressed-breakpoints'. */ |
| 399 | |
| 400 | static void |
| 401 | show_use_compressed_breakpoints (struct ui_file *file, int from_tty, |
| 402 | struct cmd_list_element *c, |
| 403 | const char *value) |
| 404 | { |
| 405 | fprintf_filtered (file, |
| 406 | _("Debugger's use of compressed breakpoints is set " |
| 407 | "to %s.\n"), value); |
| 408 | } |
| 409 | |
| 410 | /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */ |
| 411 | |
| 412 | static struct cmd_list_element *setriscvcmdlist = NULL; |
| 413 | static struct cmd_list_element *showriscvcmdlist = NULL; |
| 414 | |
| 415 | /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */ |
| 416 | |
| 417 | static struct cmd_list_element *setdebugriscvcmdlist = NULL; |
| 418 | static struct cmd_list_element *showdebugriscvcmdlist = NULL; |
| 419 | |
| 420 | /* The show callback for all 'show debug riscv VARNAME' variables. */ |
| 421 | |
| 422 | static void |
| 423 | show_riscv_debug_variable (struct ui_file *file, int from_tty, |
| 424 | struct cmd_list_element *c, |
| 425 | const char *value) |
| 426 | { |
| 427 | fprintf_filtered (file, |
| 428 | _("RiscV debug variable `%s' is set to: %s\n"), |
| 429 | c->name, value); |
| 430 | } |
| 431 | |
| 432 | /* When this is set to non-zero debugging information about breakpoint |
| 433 | kinds will be printed. */ |
| 434 | |
| 435 | static unsigned int riscv_debug_breakpoints = 0; |
| 436 | |
| 437 | /* When this is set to non-zero debugging information about inferior calls |
| 438 | will be printed. */ |
| 439 | |
| 440 | static unsigned int riscv_debug_infcall = 0; |
| 441 | |
| 442 | /* When this is set to non-zero debugging information about stack unwinding |
| 443 | will be printed. */ |
| 444 | |
| 445 | static unsigned int riscv_debug_unwinder = 0; |
| 446 | |
| 447 | /* When this is set to non-zero debugging information about gdbarch |
| 448 | initialisation will be printed. */ |
| 449 | |
| 450 | static unsigned int riscv_debug_gdbarch = 0; |
| 451 | |
| 452 | /* See riscv-tdep.h. */ |
| 453 | |
| 454 | int |
| 455 | riscv_isa_xlen (struct gdbarch *gdbarch) |
| 456 | { |
| 457 | return gdbarch_tdep (gdbarch)->isa_features.xlen; |
| 458 | } |
| 459 | |
| 460 | /* See riscv-tdep.h. */ |
| 461 | |
| 462 | int |
| 463 | riscv_abi_xlen (struct gdbarch *gdbarch) |
| 464 | { |
| 465 | return gdbarch_tdep (gdbarch)->abi_features.xlen; |
| 466 | } |
| 467 | |
| 468 | /* See riscv-tdep.h. */ |
| 469 | |
| 470 | int |
| 471 | riscv_isa_flen (struct gdbarch *gdbarch) |
| 472 | { |
| 473 | return gdbarch_tdep (gdbarch)->isa_features.flen; |
| 474 | } |
| 475 | |
| 476 | /* See riscv-tdep.h. */ |
| 477 | |
| 478 | int |
| 479 | riscv_abi_flen (struct gdbarch *gdbarch) |
| 480 | { |
| 481 | return gdbarch_tdep (gdbarch)->abi_features.flen; |
| 482 | } |
| 483 | |
| 484 | /* Return true if the target for GDBARCH has floating point hardware. */ |
| 485 | |
| 486 | static bool |
| 487 | riscv_has_fp_regs (struct gdbarch *gdbarch) |
| 488 | { |
| 489 | return (riscv_isa_flen (gdbarch) > 0); |
| 490 | } |
| 491 | |
| 492 | /* Return true if GDBARCH is using any of the floating point hardware ABIs. */ |
| 493 | |
| 494 | static bool |
| 495 | riscv_has_fp_abi (struct gdbarch *gdbarch) |
| 496 | { |
| 497 | return gdbarch_tdep (gdbarch)->abi_features.flen > 0; |
| 498 | } |
| 499 | |
| 500 | /* Return true if REGNO is a floating pointer register. */ |
| 501 | |
| 502 | static bool |
| 503 | riscv_is_fp_regno_p (int regno) |
| 504 | { |
| 505 | return (regno >= RISCV_FIRST_FP_REGNUM |
| 506 | && regno <= RISCV_LAST_FP_REGNUM); |
| 507 | } |
| 508 | |
| 509 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
| 510 | |
| 511 | static int |
| 512 | riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) |
| 513 | { |
| 514 | if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO) |
| 515 | { |
| 516 | bool unaligned_p = false; |
| 517 | gdb_byte buf[1]; |
| 518 | |
| 519 | /* Some targets don't support unaligned reads. The address can only |
| 520 | be unaligned if the C extension is supported. So it is safe to |
| 521 | use a compressed breakpoint in this case. */ |
| 522 | if (*pcptr & 0x2) |
| 523 | unaligned_p = true; |
| 524 | else |
| 525 | { |
| 526 | /* Read the opcode byte to determine the instruction length. If |
| 527 | the read fails this may be because we tried to set the |
| 528 | breakpoint at an invalid address, in this case we provide a |
| 529 | fake result which will give a breakpoint length of 4. |
| 530 | Hopefully when we try to actually insert the breakpoint we |
| 531 | will see a failure then too which will be reported to the |
| 532 | user. */ |
| 533 | if (target_read_code (*pcptr, buf, 1) == -1) |
| 534 | buf[0] = 0; |
| 535 | read_code (*pcptr, buf, 1); |
| 536 | } |
| 537 | |
| 538 | if (riscv_debug_breakpoints) |
| 539 | { |
| 540 | const char *bp = (unaligned_p || riscv_insn_length (buf[0]) == 2 |
| 541 | ? "C.EBREAK" : "EBREAK"); |
| 542 | |
| 543 | fprintf_unfiltered (gdb_stdlog, "Using %s for breakpoint at %s ", |
| 544 | bp, paddress (gdbarch, *pcptr)); |
| 545 | if (unaligned_p) |
| 546 | fprintf_unfiltered (gdb_stdlog, "(unaligned address)\n"); |
| 547 | else |
| 548 | fprintf_unfiltered (gdb_stdlog, "(instruction length %d)\n", |
| 549 | riscv_insn_length (buf[0])); |
| 550 | } |
| 551 | if (unaligned_p || riscv_insn_length (buf[0]) == 2) |
| 552 | return 2; |
| 553 | else |
| 554 | return 4; |
| 555 | } |
| 556 | else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE) |
| 557 | return 2; |
| 558 | else |
| 559 | return 4; |
| 560 | } |
| 561 | |
| 562 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
| 563 | |
| 564 | static const gdb_byte * |
| 565 | riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) |
| 566 | { |
| 567 | static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, }; |
| 568 | static const gdb_byte c_ebreak[] = { 0x02, 0x90 }; |
| 569 | |
| 570 | *size = kind; |
| 571 | switch (kind) |
| 572 | { |
| 573 | case 2: |
| 574 | return c_ebreak; |
| 575 | case 4: |
| 576 | return ebreak; |
| 577 | default: |
| 578 | gdb_assert_not_reached (_("unhandled breakpoint kind")); |
| 579 | } |
| 580 | } |
| 581 | |
| 582 | /* Implement the register_name gdbarch method. This is used instead of |
| 583 | the function supplied by calling TDESC_USE_REGISTERS so that we can |
| 584 | ensure the preferred names are offered for x-regs and f-regs. */ |
| 585 | |
| 586 | static const char * |
| 587 | riscv_register_name (struct gdbarch *gdbarch, int regnum) |
| 588 | { |
| 589 | /* Lookup the name through the target description. If we get back NULL |
| 590 | then this is an unknown register. If we do get a name back then we |
| 591 | look up the registers preferred name below. */ |
| 592 | const char *name = tdesc_register_name (gdbarch, regnum); |
| 593 | if (name == NULL || name[0] == '\0') |
| 594 | return NULL; |
| 595 | |
| 596 | /* We want GDB to use the ABI names for registers even if the target |
| 597 | gives us a target description with the architectural name. For |
| 598 | example we want to see 'ra' instead of 'x1' whatever the target |
| 599 | description called it. */ |
| 600 | if (regnum >= RISCV_ZERO_REGNUM && regnum < RISCV_FIRST_FP_REGNUM) |
| 601 | { |
| 602 | gdb_assert (regnum < riscv_xreg_feature.registers.size ()); |
| 603 | return riscv_xreg_feature.registers[regnum].names[0]; |
| 604 | } |
| 605 | |
| 606 | /* Like with the x-regs we prefer the abi names for the floating point |
| 607 | registers. */ |
| 608 | if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM) |
| 609 | { |
| 610 | if (riscv_has_fp_regs (gdbarch)) |
| 611 | { |
| 612 | regnum -= RISCV_FIRST_FP_REGNUM; |
| 613 | gdb_assert (regnum < riscv_freg_feature.registers.size ()); |
| 614 | return riscv_freg_feature.registers[regnum].names[0]; |
| 615 | } |
| 616 | else |
| 617 | return NULL; |
| 618 | } |
| 619 | |
| 620 | /* Some targets (QEMU) are reporting these three registers twice, once |
| 621 | in the FPU feature, and once in the CSR feature. Both of these read |
| 622 | the same underlying state inside the target, but naming the register |
| 623 | twice in the target description results in GDB having two registers |
| 624 | with the same name, only one of which can ever be accessed, but both |
| 625 | will show up in 'info register all'. Unless, we identify the |
| 626 | duplicate copies of these registers (in riscv_tdesc_unknown_reg) and |
| 627 | then hide the registers here by giving them no name. */ |
| 628 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 629 | if (tdep->duplicate_fflags_regnum == regnum) |
| 630 | return NULL; |
| 631 | if (tdep->duplicate_frm_regnum == regnum) |
| 632 | return NULL; |
| 633 | if (tdep->duplicate_fcsr_regnum == regnum) |
| 634 | return NULL; |
| 635 | |
| 636 | /* The remaining registers are different. For all other registers on the |
| 637 | machine we prefer to see the names that the target description |
| 638 | provides. This is particularly important for CSRs which might be |
| 639 | renamed over time. If GDB keeps track of the "latest" name, but a |
| 640 | particular target provides an older name then we don't want to force |
| 641 | users to see the newer name in register output. |
| 642 | |
| 643 | The other case that reaches here are any registers that the target |
| 644 | provided that GDB is completely unaware of. For these we have no |
| 645 | choice but to accept the target description name. |
| 646 | |
| 647 | Just accept whatever name TDESC_REGISTER_NAME returned. */ |
| 648 | return name; |
| 649 | } |
| 650 | |
| 651 | /* Construct a type for 64-bit FP registers. */ |
| 652 | |
| 653 | static struct type * |
| 654 | riscv_fpreg_d_type (struct gdbarch *gdbarch) |
| 655 | { |
| 656 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 657 | |
| 658 | if (tdep->riscv_fpreg_d_type == nullptr) |
| 659 | { |
| 660 | const struct builtin_type *bt = builtin_type (gdbarch); |
| 661 | |
| 662 | /* The type we're building is this: */ |
| 663 | #if 0 |
| 664 | union __gdb_builtin_type_fpreg_d |
| 665 | { |
| 666 | float f; |
| 667 | double d; |
| 668 | }; |
| 669 | #endif |
| 670 | |
| 671 | struct type *t; |
| 672 | |
| 673 | t = arch_composite_type (gdbarch, |
| 674 | "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION); |
| 675 | append_composite_type_field (t, "float", bt->builtin_float); |
| 676 | append_composite_type_field (t, "double", bt->builtin_double); |
| 677 | t->set_is_vector (true); |
| 678 | t->set_name ("builtin_type_fpreg_d"); |
| 679 | tdep->riscv_fpreg_d_type = t; |
| 680 | } |
| 681 | |
| 682 | return tdep->riscv_fpreg_d_type; |
| 683 | } |
| 684 | |
| 685 | /* Implement the register_type gdbarch method. This is installed as an |
| 686 | for the override setup by TDESC_USE_REGISTERS, for most registers we |
| 687 | delegate the type choice to the target description, but for a few |
| 688 | registers we try to improve the types if the target description has |
| 689 | taken a simplistic approach. */ |
| 690 | |
| 691 | static struct type * |
| 692 | riscv_register_type (struct gdbarch *gdbarch, int regnum) |
| 693 | { |
| 694 | struct type *type = tdesc_register_type (gdbarch, regnum); |
| 695 | int xlen = riscv_isa_xlen (gdbarch); |
| 696 | |
| 697 | /* We want to perform some specific type "fixes" in cases where we feel |
| 698 | that we really can do better than the target description. For all |
| 699 | other cases we just return what the target description says. */ |
| 700 | if (riscv_is_fp_regno_p (regnum)) |
| 701 | { |
| 702 | /* This spots the case for RV64 where the double is defined as |
| 703 | either 'ieee_double' or 'float' (which is the generic name that |
| 704 | converts to 'double' on 64-bit). In these cases its better to |
| 705 | present the registers using a union type. */ |
| 706 | int flen = riscv_isa_flen (gdbarch); |
| 707 | if (flen == 8 |
| 708 | && type->code () == TYPE_CODE_FLT |
| 709 | && TYPE_LENGTH (type) == flen |
| 710 | && (strcmp (type->name (), "builtin_type_ieee_double") == 0 |
| 711 | || strcmp (type->name (), "double") == 0)) |
| 712 | type = riscv_fpreg_d_type (gdbarch); |
| 713 | } |
| 714 | |
| 715 | if ((regnum == gdbarch_pc_regnum (gdbarch) |
| 716 | || regnum == RISCV_RA_REGNUM |
| 717 | || regnum == RISCV_FP_REGNUM |
| 718 | || regnum == RISCV_SP_REGNUM |
| 719 | || regnum == RISCV_GP_REGNUM |
| 720 | || regnum == RISCV_TP_REGNUM) |
| 721 | && type->code () == TYPE_CODE_INT |
| 722 | && TYPE_LENGTH (type) == xlen) |
| 723 | { |
| 724 | /* This spots the case where some interesting registers are defined |
| 725 | as simple integers of the expected size, we force these registers |
| 726 | to be pointers as we believe that is more useful. */ |
| 727 | if (regnum == gdbarch_pc_regnum (gdbarch) |
| 728 | || regnum == RISCV_RA_REGNUM) |
| 729 | type = builtin_type (gdbarch)->builtin_func_ptr; |
| 730 | else if (regnum == RISCV_FP_REGNUM |
| 731 | || regnum == RISCV_SP_REGNUM |
| 732 | || regnum == RISCV_GP_REGNUM |
| 733 | || regnum == RISCV_TP_REGNUM) |
| 734 | type = builtin_type (gdbarch)->builtin_data_ptr; |
| 735 | } |
| 736 | |
| 737 | return type; |
| 738 | } |
| 739 | |
| 740 | /* Helper for riscv_print_registers_info, prints info for a single register |
| 741 | REGNUM. */ |
| 742 | |
| 743 | static void |
| 744 | riscv_print_one_register_info (struct gdbarch *gdbarch, |
| 745 | struct ui_file *file, |
| 746 | struct frame_info *frame, |
| 747 | int regnum) |
| 748 | { |
| 749 | const char *name = gdbarch_register_name (gdbarch, regnum); |
| 750 | struct value *val; |
| 751 | struct type *regtype; |
| 752 | int print_raw_format; |
| 753 | enum tab_stops { value_column_1 = 15 }; |
| 754 | |
| 755 | fputs_filtered (name, file); |
| 756 | print_spaces_filtered (value_column_1 - strlen (name), file); |
| 757 | |
| 758 | try |
| 759 | { |
| 760 | val = value_of_register (regnum, frame); |
| 761 | regtype = value_type (val); |
| 762 | } |
| 763 | catch (const gdb_exception_error &ex) |
| 764 | { |
| 765 | /* Handle failure to read a register without interrupting the entire |
| 766 | 'info registers' flow. */ |
| 767 | fprintf_filtered (file, "%s\n", ex.what ()); |
| 768 | return; |
| 769 | } |
| 770 | |
| 771 | print_raw_format = (value_entirely_available (val) |
| 772 | && !value_optimized_out (val)); |
| 773 | |
| 774 | if (regtype->code () == TYPE_CODE_FLT |
| 775 | || (regtype->code () == TYPE_CODE_UNION |
| 776 | && regtype->num_fields () == 2 |
| 777 | && regtype->field (0).type ()->code () == TYPE_CODE_FLT |
| 778 | && regtype->field (1).type ()->code () == TYPE_CODE_FLT) |
| 779 | || (regtype->code () == TYPE_CODE_UNION |
| 780 | && regtype->num_fields () == 3 |
| 781 | && regtype->field (0).type ()->code () == TYPE_CODE_FLT |
| 782 | && regtype->field (1).type ()->code () == TYPE_CODE_FLT |
| 783 | && regtype->field (2).type ()->code () == TYPE_CODE_FLT)) |
| 784 | { |
| 785 | struct value_print_options opts; |
| 786 | const gdb_byte *valaddr = value_contents_for_printing (val); |
| 787 | enum bfd_endian byte_order = type_byte_order (regtype); |
| 788 | |
| 789 | get_user_print_options (&opts); |
| 790 | opts.deref_ref = 1; |
| 791 | |
| 792 | common_val_print (val, file, 0, &opts, current_language); |
| 793 | |
| 794 | if (print_raw_format) |
| 795 | { |
| 796 | fprintf_filtered (file, "\t(raw "); |
| 797 | print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order, |
| 798 | true); |
| 799 | fprintf_filtered (file, ")"); |
| 800 | } |
| 801 | } |
| 802 | else |
| 803 | { |
| 804 | struct value_print_options opts; |
| 805 | |
| 806 | /* Print the register in hex. */ |
| 807 | get_formatted_print_options (&opts, 'x'); |
| 808 | opts.deref_ref = 1; |
| 809 | common_val_print (val, file, 0, &opts, current_language); |
| 810 | |
| 811 | if (print_raw_format) |
| 812 | { |
| 813 | if (regnum == RISCV_CSR_MSTATUS_REGNUM) |
| 814 | { |
| 815 | LONGEST d; |
| 816 | int size = register_size (gdbarch, regnum); |
| 817 | unsigned xlen; |
| 818 | |
| 819 | /* The SD field is always in the upper bit of MSTATUS, regardless |
| 820 | of the number of bits in MSTATUS. */ |
| 821 | d = value_as_long (val); |
| 822 | xlen = size * 8; |
| 823 | fprintf_filtered (file, |
| 824 | "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X " |
| 825 | "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X " |
| 826 | "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X", |
| 827 | (int) ((d >> (xlen - 1)) & 0x1), |
| 828 | (int) ((d >> 24) & 0x1f), |
| 829 | (int) ((d >> 19) & 0x1), |
| 830 | (int) ((d >> 18) & 0x1), |
| 831 | (int) ((d >> 17) & 0x1), |
| 832 | (int) ((d >> 15) & 0x3), |
| 833 | (int) ((d >> 13) & 0x3), |
| 834 | (int) ((d >> 11) & 0x3), |
| 835 | (int) ((d >> 9) & 0x3), |
| 836 | (int) ((d >> 8) & 0x1), |
| 837 | (int) ((d >> 7) & 0x1), |
| 838 | (int) ((d >> 6) & 0x1), |
| 839 | (int) ((d >> 5) & 0x1), |
| 840 | (int) ((d >> 4) & 0x1), |
| 841 | (int) ((d >> 3) & 0x1), |
| 842 | (int) ((d >> 2) & 0x1), |
| 843 | (int) ((d >> 1) & 0x1), |
| 844 | (int) ((d >> 0) & 0x1)); |
| 845 | } |
| 846 | else if (regnum == RISCV_CSR_MISA_REGNUM) |
| 847 | { |
| 848 | int base; |
| 849 | unsigned xlen, i; |
| 850 | LONGEST d; |
| 851 | int size = register_size (gdbarch, regnum); |
| 852 | |
| 853 | /* The MXL field is always in the upper two bits of MISA, |
| 854 | regardless of the number of bits in MISA. Mask out other |
| 855 | bits to ensure we have a positive value. */ |
| 856 | d = value_as_long (val); |
| 857 | base = (d >> ((size * 8) - 2)) & 0x3; |
| 858 | xlen = 16; |
| 859 | |
| 860 | for (; base > 0; base--) |
| 861 | xlen *= 2; |
| 862 | fprintf_filtered (file, "\tRV%d", xlen); |
| 863 | |
| 864 | for (i = 0; i < 26; i++) |
| 865 | { |
| 866 | if (d & (1 << i)) |
| 867 | fprintf_filtered (file, "%c", 'A' + i); |
| 868 | } |
| 869 | } |
| 870 | else if (regnum == RISCV_CSR_FCSR_REGNUM |
| 871 | || regnum == RISCV_CSR_FFLAGS_REGNUM |
| 872 | || regnum == RISCV_CSR_FRM_REGNUM) |
| 873 | { |
| 874 | LONGEST d; |
| 875 | |
| 876 | d = value_as_long (val); |
| 877 | |
| 878 | fprintf_filtered (file, "\t"); |
| 879 | if (regnum != RISCV_CSR_FRM_REGNUM) |
| 880 | fprintf_filtered (file, |
| 881 | "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d", |
| 882 | (int) ((d >> 5) & 0x7), |
| 883 | (int) ((d >> 4) & 0x1), |
| 884 | (int) ((d >> 3) & 0x1), |
| 885 | (int) ((d >> 2) & 0x1), |
| 886 | (int) ((d >> 1) & 0x1), |
| 887 | (int) ((d >> 0) & 0x1)); |
| 888 | |
| 889 | if (regnum != RISCV_CSR_FFLAGS_REGNUM) |
| 890 | { |
| 891 | static const char * const sfrm[] = |
| 892 | { |
| 893 | "RNE (round to nearest; ties to even)", |
| 894 | "RTZ (Round towards zero)", |
| 895 | "RDN (Round down towards -INF)", |
| 896 | "RUP (Round up towards +INF)", |
| 897 | "RMM (Round to nearest; ties to max magnitude)", |
| 898 | "INVALID[5]", |
| 899 | "INVALID[6]", |
| 900 | "dynamic rounding mode", |
| 901 | }; |
| 902 | int frm = ((regnum == RISCV_CSR_FCSR_REGNUM) |
| 903 | ? (d >> 5) : d) & 0x3; |
| 904 | |
| 905 | fprintf_filtered (file, "%sFRM:%i [%s]", |
| 906 | (regnum == RISCV_CSR_FCSR_REGNUM |
| 907 | ? " " : ""), |
| 908 | frm, sfrm[frm]); |
| 909 | } |
| 910 | } |
| 911 | else if (regnum == RISCV_PRIV_REGNUM) |
| 912 | { |
| 913 | LONGEST d; |
| 914 | uint8_t priv; |
| 915 | |
| 916 | d = value_as_long (val); |
| 917 | priv = d & 0xff; |
| 918 | |
| 919 | if (priv < 4) |
| 920 | { |
| 921 | static const char * const sprv[] = |
| 922 | { |
| 923 | "User/Application", |
| 924 | "Supervisor", |
| 925 | "Hypervisor", |
| 926 | "Machine" |
| 927 | }; |
| 928 | fprintf_filtered (file, "\tprv:%d [%s]", |
| 929 | priv, sprv[priv]); |
| 930 | } |
| 931 | else |
| 932 | fprintf_filtered (file, "\tprv:%d [INVALID]", priv); |
| 933 | } |
| 934 | else |
| 935 | { |
| 936 | /* If not a vector register, print it also according to its |
| 937 | natural format. */ |
| 938 | if (regtype->is_vector () == 0) |
| 939 | { |
| 940 | get_user_print_options (&opts); |
| 941 | opts.deref_ref = 1; |
| 942 | fprintf_filtered (file, "\t"); |
| 943 | common_val_print (val, file, 0, &opts, current_language); |
| 944 | } |
| 945 | } |
| 946 | } |
| 947 | } |
| 948 | fprintf_filtered (file, "\n"); |
| 949 | } |
| 950 | |
| 951 | /* Return true if REGNUM is a valid CSR register. The CSR register space |
| 952 | is sparsely populated, so not every number is a named CSR. */ |
| 953 | |
| 954 | static bool |
| 955 | riscv_is_regnum_a_named_csr (int regnum) |
| 956 | { |
| 957 | gdb_assert (regnum >= RISCV_FIRST_CSR_REGNUM |
| 958 | && regnum <= RISCV_LAST_CSR_REGNUM); |
| 959 | |
| 960 | switch (regnum) |
| 961 | { |
| 962 | #define DECLARE_CSR(name, num, class, define_ver, abort_ver) case RISCV_ ## num ## _REGNUM: |
| 963 | #include "opcode/riscv-opc.h" |
| 964 | #undef DECLARE_CSR |
| 965 | return true; |
| 966 | |
| 967 | default: |
| 968 | return false; |
| 969 | } |
| 970 | } |
| 971 | |
| 972 | /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member |
| 973 | of REGGROUP? */ |
| 974 | |
| 975 | static int |
| 976 | riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
| 977 | struct reggroup *reggroup) |
| 978 | { |
| 979 | /* Used by 'info registers' and 'info registers <groupname>'. */ |
| 980 | |
| 981 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
| 982 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') |
| 983 | return 0; |
| 984 | |
| 985 | if (regnum > RISCV_LAST_REGNUM) |
| 986 | { |
| 987 | /* Any extra registers from the CSR tdesc_feature (identified in |
| 988 | riscv_tdesc_unknown_reg) are removed from the save/restore groups |
| 989 | as some targets (QEMU) report CSRs which then can't be read. */ |
| 990 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 991 | if ((reggroup == restore_reggroup || reggroup == save_reggroup) |
| 992 | && regnum >= tdep->unknown_csrs_first_regnum |
| 993 | && regnum < (tdep->unknown_csrs_first_regnum |
| 994 | + tdep->unknown_csrs_count)) |
| 995 | return 0; |
| 996 | |
| 997 | /* This is some other unknown register from the target description. |
| 998 | In this case we trust whatever the target description says about |
| 999 | which groups this register should be in. */ |
| 1000 | int ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup); |
| 1001 | if (ret != -1) |
| 1002 | return ret; |
| 1003 | |
| 1004 | return default_register_reggroup_p (gdbarch, regnum, reggroup); |
| 1005 | } |
| 1006 | |
| 1007 | if (reggroup == all_reggroup) |
| 1008 | { |
| 1009 | if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM) |
| 1010 | return 1; |
| 1011 | if (riscv_is_regnum_a_named_csr (regnum)) |
| 1012 | return 1; |
| 1013 | return 0; |
| 1014 | } |
| 1015 | else if (reggroup == float_reggroup) |
| 1016 | return (riscv_is_fp_regno_p (regnum) |
| 1017 | || regnum == RISCV_CSR_FCSR_REGNUM |
| 1018 | || regnum == RISCV_CSR_FFLAGS_REGNUM |
| 1019 | || regnum == RISCV_CSR_FRM_REGNUM); |
| 1020 | else if (reggroup == general_reggroup) |
| 1021 | return regnum < RISCV_FIRST_FP_REGNUM; |
| 1022 | else if (reggroup == restore_reggroup || reggroup == save_reggroup) |
| 1023 | { |
| 1024 | if (riscv_has_fp_regs (gdbarch)) |
| 1025 | return (regnum <= RISCV_LAST_FP_REGNUM |
| 1026 | || regnum == RISCV_CSR_FCSR_REGNUM |
| 1027 | || regnum == RISCV_CSR_FFLAGS_REGNUM |
| 1028 | || regnum == RISCV_CSR_FRM_REGNUM); |
| 1029 | else |
| 1030 | return regnum < RISCV_FIRST_FP_REGNUM; |
| 1031 | } |
| 1032 | else if (reggroup == system_reggroup || reggroup == csr_reggroup) |
| 1033 | { |
| 1034 | if (regnum == RISCV_PRIV_REGNUM) |
| 1035 | return 1; |
| 1036 | if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM) |
| 1037 | return 0; |
| 1038 | if (riscv_is_regnum_a_named_csr (regnum)) |
| 1039 | return 1; |
| 1040 | return 0; |
| 1041 | } |
| 1042 | else if (reggroup == vector_reggroup) |
| 1043 | return 0; |
| 1044 | else |
| 1045 | return 0; |
| 1046 | } |
| 1047 | |
| 1048 | /* Implement the print_registers_info gdbarch method. This is used by |
| 1049 | 'info registers' and 'info all-registers'. */ |
| 1050 | |
| 1051 | static void |
| 1052 | riscv_print_registers_info (struct gdbarch *gdbarch, |
| 1053 | struct ui_file *file, |
| 1054 | struct frame_info *frame, |
| 1055 | int regnum, int print_all) |
| 1056 | { |
| 1057 | if (regnum != -1) |
| 1058 | { |
| 1059 | /* Print one specified register. */ |
| 1060 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
| 1061 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') |
| 1062 | error (_("Not a valid register for the current processor type")); |
| 1063 | riscv_print_one_register_info (gdbarch, file, frame, regnum); |
| 1064 | } |
| 1065 | else |
| 1066 | { |
| 1067 | struct reggroup *reggroup; |
| 1068 | |
| 1069 | if (print_all) |
| 1070 | reggroup = all_reggroup; |
| 1071 | else |
| 1072 | reggroup = general_reggroup; |
| 1073 | |
| 1074 | for (regnum = 0; regnum < gdbarch_num_cooked_regs (gdbarch); ++regnum) |
| 1075 | { |
| 1076 | /* Zero never changes, so might as well hide by default. */ |
| 1077 | if (regnum == RISCV_ZERO_REGNUM && !print_all) |
| 1078 | continue; |
| 1079 | |
| 1080 | /* Registers with no name are not valid on this ISA. */ |
| 1081 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
| 1082 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') |
| 1083 | continue; |
| 1084 | |
| 1085 | /* Is the register in the group we're interested in? */ |
| 1086 | if (!gdbarch_register_reggroup_p (gdbarch, regnum, reggroup)) |
| 1087 | continue; |
| 1088 | |
| 1089 | riscv_print_one_register_info (gdbarch, file, frame, regnum); |
| 1090 | } |
| 1091 | } |
| 1092 | } |
| 1093 | |
| 1094 | /* Class that handles one decoded RiscV instruction. */ |
| 1095 | |
| 1096 | class riscv_insn |
| 1097 | { |
| 1098 | public: |
| 1099 | |
| 1100 | /* Enum of all the opcodes that GDB cares about during the prologue scan. */ |
| 1101 | enum opcode |
| 1102 | { |
| 1103 | /* Unknown value is used at initialisation time. */ |
| 1104 | UNKNOWN = 0, |
| 1105 | |
| 1106 | /* These instructions are all the ones we are interested in during the |
| 1107 | prologue scan. */ |
| 1108 | ADD, |
| 1109 | ADDI, |
| 1110 | ADDIW, |
| 1111 | ADDW, |
| 1112 | AUIPC, |
| 1113 | LUI, |
| 1114 | SD, |
| 1115 | SW, |
| 1116 | /* These are needed for software breakpoint support. */ |
| 1117 | JAL, |
| 1118 | JALR, |
| 1119 | BEQ, |
| 1120 | BNE, |
| 1121 | BLT, |
| 1122 | BGE, |
| 1123 | BLTU, |
| 1124 | BGEU, |
| 1125 | /* These are needed for stepping over atomic sequences. */ |
| 1126 | LR, |
| 1127 | SC, |
| 1128 | |
| 1129 | /* Other instructions are not interesting during the prologue scan, and |
| 1130 | are ignored. */ |
| 1131 | OTHER |
| 1132 | }; |
| 1133 | |
| 1134 | riscv_insn () |
| 1135 | : m_length (0), |
| 1136 | m_opcode (OTHER), |
| 1137 | m_rd (0), |
| 1138 | m_rs1 (0), |
| 1139 | m_rs2 (0) |
| 1140 | { |
| 1141 | /* Nothing. */ |
| 1142 | } |
| 1143 | |
| 1144 | void decode (struct gdbarch *gdbarch, CORE_ADDR pc); |
| 1145 | |
| 1146 | /* Get the length of the instruction in bytes. */ |
| 1147 | int length () const |
| 1148 | { return m_length; } |
| 1149 | |
| 1150 | /* Get the opcode for this instruction. */ |
| 1151 | enum opcode opcode () const |
| 1152 | { return m_opcode; } |
| 1153 | |
| 1154 | /* Get destination register field for this instruction. This is only |
| 1155 | valid if the OPCODE implies there is such a field for this |
| 1156 | instruction. */ |
| 1157 | int rd () const |
| 1158 | { return m_rd; } |
| 1159 | |
| 1160 | /* Get the RS1 register field for this instruction. This is only valid |
| 1161 | if the OPCODE implies there is such a field for this instruction. */ |
| 1162 | int rs1 () const |
| 1163 | { return m_rs1; } |
| 1164 | |
| 1165 | /* Get the RS2 register field for this instruction. This is only valid |
| 1166 | if the OPCODE implies there is such a field for this instruction. */ |
| 1167 | int rs2 () const |
| 1168 | { return m_rs2; } |
| 1169 | |
| 1170 | /* Get the immediate for this instruction in signed form. This is only |
| 1171 | valid if the OPCODE implies there is such a field for this |
| 1172 | instruction. */ |
| 1173 | int imm_signed () const |
| 1174 | { return m_imm.s; } |
| 1175 | |
| 1176 | private: |
| 1177 | |
| 1178 | /* Extract 5 bit register field at OFFSET from instruction OPCODE. */ |
| 1179 | int decode_register_index (unsigned long opcode, int offset) |
| 1180 | { |
| 1181 | return (opcode >> offset) & 0x1F; |
| 1182 | } |
| 1183 | |
| 1184 | /* Extract 5 bit register field at OFFSET from instruction OPCODE. */ |
| 1185 | int decode_register_index_short (unsigned long opcode, int offset) |
| 1186 | { |
| 1187 | return ((opcode >> offset) & 0x7) + 8; |
| 1188 | } |
| 1189 | |
| 1190 | /* Helper for DECODE, decode 32-bit R-type instruction. */ |
| 1191 | void decode_r_type_insn (enum opcode opcode, ULONGEST ival) |
| 1192 | { |
| 1193 | m_opcode = opcode; |
| 1194 | m_rd = decode_register_index (ival, OP_SH_RD); |
| 1195 | m_rs1 = decode_register_index (ival, OP_SH_RS1); |
| 1196 | m_rs2 = decode_register_index (ival, OP_SH_RS2); |
| 1197 | } |
| 1198 | |
| 1199 | /* Helper for DECODE, decode 16-bit compressed R-type instruction. */ |
| 1200 | void decode_cr_type_insn (enum opcode opcode, ULONGEST ival) |
| 1201 | { |
| 1202 | m_opcode = opcode; |
| 1203 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S); |
| 1204 | m_rs2 = decode_register_index (ival, OP_SH_CRS2); |
| 1205 | } |
| 1206 | |
| 1207 | /* Helper for DECODE, decode 32-bit I-type instruction. */ |
| 1208 | void decode_i_type_insn (enum opcode opcode, ULONGEST ival) |
| 1209 | { |
| 1210 | m_opcode = opcode; |
| 1211 | m_rd = decode_register_index (ival, OP_SH_RD); |
| 1212 | m_rs1 = decode_register_index (ival, OP_SH_RS1); |
| 1213 | m_imm.s = EXTRACT_ITYPE_IMM (ival); |
| 1214 | } |
| 1215 | |
| 1216 | /* Helper for DECODE, decode 16-bit compressed I-type instruction. */ |
| 1217 | void decode_ci_type_insn (enum opcode opcode, ULONGEST ival) |
| 1218 | { |
| 1219 | m_opcode = opcode; |
| 1220 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S); |
| 1221 | m_imm.s = EXTRACT_RVC_IMM (ival); |
| 1222 | } |
| 1223 | |
| 1224 | /* Helper for DECODE, decode 32-bit S-type instruction. */ |
| 1225 | void decode_s_type_insn (enum opcode opcode, ULONGEST ival) |
| 1226 | { |
| 1227 | m_opcode = opcode; |
| 1228 | m_rs1 = decode_register_index (ival, OP_SH_RS1); |
| 1229 | m_rs2 = decode_register_index (ival, OP_SH_RS2); |
| 1230 | m_imm.s = EXTRACT_STYPE_IMM (ival); |
| 1231 | } |
| 1232 | |
| 1233 | /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate |
| 1234 | encoding is different for each CS format instruction, so extracting |
| 1235 | the immediate is left up to the caller, who should pass the extracted |
| 1236 | immediate value through in IMM. */ |
| 1237 | void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm) |
| 1238 | { |
| 1239 | m_opcode = opcode; |
| 1240 | m_imm.s = imm; |
| 1241 | m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S); |
| 1242 | m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S); |
| 1243 | } |
| 1244 | |
| 1245 | /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate |
| 1246 | encoding is different for each CSS format instruction, so extracting |
| 1247 | the immediate is left up to the caller, who should pass the extracted |
| 1248 | immediate value through in IMM. */ |
| 1249 | void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm) |
| 1250 | { |
| 1251 | m_opcode = opcode; |
| 1252 | m_imm.s = imm; |
| 1253 | m_rs1 = RISCV_SP_REGNUM; |
| 1254 | /* Not a compressed register number in this case. */ |
| 1255 | m_rs2 = decode_register_index (ival, OP_SH_CRS2); |
| 1256 | } |
| 1257 | |
| 1258 | /* Helper for DECODE, decode 32-bit U-type instruction. */ |
| 1259 | void decode_u_type_insn (enum opcode opcode, ULONGEST ival) |
| 1260 | { |
| 1261 | m_opcode = opcode; |
| 1262 | m_rd = decode_register_index (ival, OP_SH_RD); |
| 1263 | m_imm.s = EXTRACT_UTYPE_IMM (ival); |
| 1264 | } |
| 1265 | |
| 1266 | /* Helper for DECODE, decode 32-bit J-type instruction. */ |
| 1267 | void decode_j_type_insn (enum opcode opcode, ULONGEST ival) |
| 1268 | { |
| 1269 | m_opcode = opcode; |
| 1270 | m_rd = decode_register_index (ival, OP_SH_RD); |
| 1271 | m_imm.s = EXTRACT_UJTYPE_IMM (ival); |
| 1272 | } |
| 1273 | |
| 1274 | /* Helper for DECODE, decode 32-bit J-type instruction. */ |
| 1275 | void decode_cj_type_insn (enum opcode opcode, ULONGEST ival) |
| 1276 | { |
| 1277 | m_opcode = opcode; |
| 1278 | m_imm.s = EXTRACT_RVC_J_IMM (ival); |
| 1279 | } |
| 1280 | |
| 1281 | void decode_b_type_insn (enum opcode opcode, ULONGEST ival) |
| 1282 | { |
| 1283 | m_opcode = opcode; |
| 1284 | m_rs1 = decode_register_index (ival, OP_SH_RS1); |
| 1285 | m_rs2 = decode_register_index (ival, OP_SH_RS2); |
| 1286 | m_imm.s = EXTRACT_SBTYPE_IMM (ival); |
| 1287 | } |
| 1288 | |
| 1289 | void decode_cb_type_insn (enum opcode opcode, ULONGEST ival) |
| 1290 | { |
| 1291 | m_opcode = opcode; |
| 1292 | m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S); |
| 1293 | m_imm.s = EXTRACT_RVC_B_IMM (ival); |
| 1294 | } |
| 1295 | |
| 1296 | /* Fetch instruction from target memory at ADDR, return the content of |
| 1297 | the instruction, and update LEN with the instruction length. */ |
| 1298 | static ULONGEST fetch_instruction (struct gdbarch *gdbarch, |
| 1299 | CORE_ADDR addr, int *len); |
| 1300 | |
| 1301 | /* The length of the instruction in bytes. Should be 2 or 4. */ |
| 1302 | int m_length; |
| 1303 | |
| 1304 | /* The instruction opcode. */ |
| 1305 | enum opcode m_opcode; |
| 1306 | |
| 1307 | /* The three possible registers an instruction might reference. Not |
| 1308 | every instruction fills in all of these registers. Which fields are |
| 1309 | valid depends on the opcode. The naming of these fields matches the |
| 1310 | naming in the riscv isa manual. */ |
| 1311 | int m_rd; |
| 1312 | int m_rs1; |
| 1313 | int m_rs2; |
| 1314 | |
| 1315 | /* Possible instruction immediate. This is only valid if the instruction |
| 1316 | format contains an immediate, not all instruction, whether this is |
| 1317 | valid depends on the opcode. Despite only having one format for now |
| 1318 | the immediate is packed into a union, later instructions might require |
| 1319 | an unsigned formatted immediate, having the union in place now will |
| 1320 | reduce the need for code churn later. */ |
| 1321 | union riscv_insn_immediate |
| 1322 | { |
| 1323 | riscv_insn_immediate () |
| 1324 | : s (0) |
| 1325 | { |
| 1326 | /* Nothing. */ |
| 1327 | } |
| 1328 | |
| 1329 | int s; |
| 1330 | } m_imm; |
| 1331 | }; |
| 1332 | |
| 1333 | /* Fetch instruction from target memory at ADDR, return the content of the |
| 1334 | instruction, and update LEN with the instruction length. */ |
| 1335 | |
| 1336 | ULONGEST |
| 1337 | riscv_insn::fetch_instruction (struct gdbarch *gdbarch, |
| 1338 | CORE_ADDR addr, int *len) |
| 1339 | { |
| 1340 | enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch); |
| 1341 | gdb_byte buf[8]; |
| 1342 | int instlen, status; |
| 1343 | |
| 1344 | /* All insns are at least 16 bits. */ |
| 1345 | status = target_read_memory (addr, buf, 2); |
| 1346 | if (status) |
| 1347 | memory_error (TARGET_XFER_E_IO, addr); |
| 1348 | |
| 1349 | /* If we need more, grab it now. */ |
| 1350 | instlen = riscv_insn_length (buf[0]); |
| 1351 | gdb_assert (instlen <= sizeof (buf)); |
| 1352 | *len = instlen; |
| 1353 | |
| 1354 | if (instlen > 2) |
| 1355 | { |
| 1356 | status = target_read_memory (addr + 2, buf + 2, instlen - 2); |
| 1357 | if (status) |
| 1358 | memory_error (TARGET_XFER_E_IO, addr + 2); |
| 1359 | } |
| 1360 | |
| 1361 | return extract_unsigned_integer (buf, instlen, byte_order); |
| 1362 | } |
| 1363 | |
| 1364 | /* Fetch from target memory an instruction at PC and decode it. This can |
| 1365 | throw an error if the memory access fails, callers are responsible for |
| 1366 | handling this error if that is appropriate. */ |
| 1367 | |
| 1368 | void |
| 1369 | riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 1370 | { |
| 1371 | ULONGEST ival; |
| 1372 | |
| 1373 | /* Fetch the instruction, and the instructions length. */ |
| 1374 | ival = fetch_instruction (gdbarch, pc, &m_length); |
| 1375 | |
| 1376 | if (m_length == 4) |
| 1377 | { |
| 1378 | if (is_add_insn (ival)) |
| 1379 | decode_r_type_insn (ADD, ival); |
| 1380 | else if (is_addw_insn (ival)) |
| 1381 | decode_r_type_insn (ADDW, ival); |
| 1382 | else if (is_addi_insn (ival)) |
| 1383 | decode_i_type_insn (ADDI, ival); |
| 1384 | else if (is_addiw_insn (ival)) |
| 1385 | decode_i_type_insn (ADDIW, ival); |
| 1386 | else if (is_auipc_insn (ival)) |
| 1387 | decode_u_type_insn (AUIPC, ival); |
| 1388 | else if (is_lui_insn (ival)) |
| 1389 | decode_u_type_insn (LUI, ival); |
| 1390 | else if (is_sd_insn (ival)) |
| 1391 | decode_s_type_insn (SD, ival); |
| 1392 | else if (is_sw_insn (ival)) |
| 1393 | decode_s_type_insn (SW, ival); |
| 1394 | else if (is_jal_insn (ival)) |
| 1395 | decode_j_type_insn (JAL, ival); |
| 1396 | else if (is_jalr_insn (ival)) |
| 1397 | decode_i_type_insn (JALR, ival); |
| 1398 | else if (is_beq_insn (ival)) |
| 1399 | decode_b_type_insn (BEQ, ival); |
| 1400 | else if (is_bne_insn (ival)) |
| 1401 | decode_b_type_insn (BNE, ival); |
| 1402 | else if (is_blt_insn (ival)) |
| 1403 | decode_b_type_insn (BLT, ival); |
| 1404 | else if (is_bge_insn (ival)) |
| 1405 | decode_b_type_insn (BGE, ival); |
| 1406 | else if (is_bltu_insn (ival)) |
| 1407 | decode_b_type_insn (BLTU, ival); |
| 1408 | else if (is_bgeu_insn (ival)) |
| 1409 | decode_b_type_insn (BGEU, ival); |
| 1410 | else if (is_lr_w_insn (ival)) |
| 1411 | decode_r_type_insn (LR, ival); |
| 1412 | else if (is_lr_d_insn (ival)) |
| 1413 | decode_r_type_insn (LR, ival); |
| 1414 | else if (is_sc_w_insn (ival)) |
| 1415 | decode_r_type_insn (SC, ival); |
| 1416 | else if (is_sc_d_insn (ival)) |
| 1417 | decode_r_type_insn (SC, ival); |
| 1418 | else |
| 1419 | /* None of the other fields are valid in this case. */ |
| 1420 | m_opcode = OTHER; |
| 1421 | } |
| 1422 | else if (m_length == 2) |
| 1423 | { |
| 1424 | int xlen = riscv_isa_xlen (gdbarch); |
| 1425 | |
| 1426 | /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a |
| 1427 | C_JALR. So must try to match C_JALR first as it has more bits in |
| 1428 | mask. */ |
| 1429 | if (is_c_jalr_insn (ival)) |
| 1430 | decode_cr_type_insn (JALR, ival); |
| 1431 | else if (is_c_add_insn (ival)) |
| 1432 | decode_cr_type_insn (ADD, ival); |
| 1433 | /* C_ADDW is RV64 and RV128 only. */ |
| 1434 | else if (xlen != 4 && is_c_addw_insn (ival)) |
| 1435 | decode_cr_type_insn (ADDW, ival); |
| 1436 | else if (is_c_addi_insn (ival)) |
| 1437 | decode_ci_type_insn (ADDI, ival); |
| 1438 | /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128 |
| 1439 | only and C_JAL is RV32 only. */ |
| 1440 | else if (xlen != 4 && is_c_addiw_insn (ival)) |
| 1441 | decode_ci_type_insn (ADDIW, ival); |
| 1442 | else if (xlen == 4 && is_c_jal_insn (ival)) |
| 1443 | decode_cj_type_insn (JAL, ival); |
| 1444 | /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a |
| 1445 | C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits |
| 1446 | in mask. */ |
| 1447 | else if (is_c_addi16sp_insn (ival)) |
| 1448 | { |
| 1449 | m_opcode = ADDI; |
| 1450 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD); |
| 1451 | m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival); |
| 1452 | } |
| 1453 | else if (is_c_addi4spn_insn (ival)) |
| 1454 | { |
| 1455 | m_opcode = ADDI; |
| 1456 | m_rd = decode_register_index_short (ival, OP_SH_CRS2S); |
| 1457 | m_rs1 = RISCV_SP_REGNUM; |
| 1458 | m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival); |
| 1459 | } |
| 1460 | else if (is_c_lui_insn (ival)) |
| 1461 | { |
| 1462 | m_opcode = LUI; |
| 1463 | m_rd = decode_register_index (ival, OP_SH_CRS1S); |
| 1464 | m_imm.s = EXTRACT_RVC_LUI_IMM (ival); |
| 1465 | } |
| 1466 | /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only, |
| 1467 | and C_FSW is RV32 only. */ |
| 1468 | else if (xlen != 4 && is_c_sd_insn (ival)) |
| 1469 | decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival)); |
| 1470 | else if (is_c_sw_insn (ival)) |
| 1471 | decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival)); |
| 1472 | else if (is_c_swsp_insn (ival)) |
| 1473 | decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival)); |
| 1474 | else if (xlen != 4 && is_c_sdsp_insn (ival)) |
| 1475 | decode_css_type_insn (SD, ival, EXTRACT_RVC_SDSP_IMM (ival)); |
| 1476 | /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR. |
| 1477 | So must try to match C_JR first as it ahs more bits in mask. */ |
| 1478 | else if (is_c_jr_insn (ival)) |
| 1479 | decode_cr_type_insn (JALR, ival); |
| 1480 | else if (is_c_j_insn (ival)) |
| 1481 | decode_cj_type_insn (JAL, ival); |
| 1482 | else if (is_c_beqz_insn (ival)) |
| 1483 | decode_cb_type_insn (BEQ, ival); |
| 1484 | else if (is_c_bnez_insn (ival)) |
| 1485 | decode_cb_type_insn (BNE, ival); |
| 1486 | else |
| 1487 | /* None of the other fields of INSN are valid in this case. */ |
| 1488 | m_opcode = OTHER; |
| 1489 | } |
| 1490 | else |
| 1491 | { |
| 1492 | /* This must be a 6 or 8 byte instruction, we don't currently decode |
| 1493 | any of these, so just ignore it. */ |
| 1494 | gdb_assert (m_length == 6 || m_length == 8); |
| 1495 | m_opcode = OTHER; |
| 1496 | } |
| 1497 | } |
| 1498 | |
| 1499 | /* The prologue scanner. This is currently only used for skipping the |
| 1500 | prologue of a function when the DWARF information is not sufficient. |
| 1501 | However, it is written with filling of the frame cache in mind, which |
| 1502 | is why different groups of stack setup instructions are split apart |
| 1503 | during the core of the inner loop. In the future, the intention is to |
| 1504 | extend this function to fully support building up a frame cache that |
| 1505 | can unwind register values when there is no DWARF information. */ |
| 1506 | |
| 1507 | static CORE_ADDR |
| 1508 | riscv_scan_prologue (struct gdbarch *gdbarch, |
| 1509 | CORE_ADDR start_pc, CORE_ADDR end_pc, |
| 1510 | struct riscv_unwind_cache *cache) |
| 1511 | { |
| 1512 | CORE_ADDR cur_pc, next_pc, after_prologue_pc; |
| 1513 | CORE_ADDR end_prologue_addr = 0; |
| 1514 | |
| 1515 | /* Find an upper limit on the function prologue using the debug |
| 1516 | information. If the debug information could not be used to provide |
| 1517 | that bound, then use an arbitrary large number as the upper bound. */ |
| 1518 | after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc); |
| 1519 | if (after_prologue_pc == 0) |
| 1520 | after_prologue_pc = start_pc + 100; /* Arbitrary large number. */ |
| 1521 | if (after_prologue_pc < end_pc) |
| 1522 | end_pc = after_prologue_pc; |
| 1523 | |
| 1524 | pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */ |
| 1525 | for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++) |
| 1526 | regs[regno] = pv_register (regno, 0); |
| 1527 | pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
| 1528 | |
| 1529 | if (riscv_debug_unwinder) |
| 1530 | fprintf_unfiltered |
| 1531 | (gdb_stdlog, |
| 1532 | "Prologue scan for function starting at %s (limit %s)\n", |
| 1533 | core_addr_to_string (start_pc), |
| 1534 | core_addr_to_string (end_pc)); |
| 1535 | |
| 1536 | for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc) |
| 1537 | { |
| 1538 | struct riscv_insn insn; |
| 1539 | |
| 1540 | /* Decode the current instruction, and decide where the next |
| 1541 | instruction lives based on the size of this instruction. */ |
| 1542 | insn.decode (gdbarch, cur_pc); |
| 1543 | gdb_assert (insn.length () > 0); |
| 1544 | next_pc = cur_pc + insn.length (); |
| 1545 | |
| 1546 | /* Look for common stack adjustment insns. */ |
| 1547 | if ((insn.opcode () == riscv_insn::ADDI |
| 1548 | || insn.opcode () == riscv_insn::ADDIW) |
| 1549 | && insn.rd () == RISCV_SP_REGNUM |
| 1550 | && insn.rs1 () == RISCV_SP_REGNUM) |
| 1551 | { |
| 1552 | /* Handle: addi sp, sp, -i |
| 1553 | or: addiw sp, sp, -i */ |
| 1554 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
| 1555 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); |
| 1556 | regs[insn.rd ()] |
| 1557 | = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()); |
| 1558 | } |
| 1559 | else if ((insn.opcode () == riscv_insn::SW |
| 1560 | || insn.opcode () == riscv_insn::SD) |
| 1561 | && (insn.rs1 () == RISCV_SP_REGNUM |
| 1562 | || insn.rs1 () == RISCV_FP_REGNUM)) |
| 1563 | { |
| 1564 | /* Handle: sw reg, offset(sp) |
| 1565 | or: sd reg, offset(sp) |
| 1566 | or: sw reg, offset(s0) |
| 1567 | or: sd reg, offset(s0) */ |
| 1568 | /* Instruction storing a register onto the stack. */ |
| 1569 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); |
| 1570 | gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS); |
| 1571 | stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()), |
| 1572 | (insn.opcode () == riscv_insn::SW ? 4 : 8), |
| 1573 | regs[insn.rs2 ()]); |
| 1574 | } |
| 1575 | else if (insn.opcode () == riscv_insn::ADDI |
| 1576 | && insn.rd () == RISCV_FP_REGNUM |
| 1577 | && insn.rs1 () == RISCV_SP_REGNUM) |
| 1578 | { |
| 1579 | /* Handle: addi s0, sp, size */ |
| 1580 | /* Instructions setting up the frame pointer. */ |
| 1581 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
| 1582 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); |
| 1583 | regs[insn.rd ()] |
| 1584 | = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()); |
| 1585 | } |
| 1586 | else if ((insn.opcode () == riscv_insn::ADD |
| 1587 | || insn.opcode () == riscv_insn::ADDW) |
| 1588 | && insn.rd () == RISCV_FP_REGNUM |
| 1589 | && insn.rs1 () == RISCV_SP_REGNUM |
| 1590 | && insn.rs2 () == RISCV_ZERO_REGNUM) |
| 1591 | { |
| 1592 | /* Handle: add s0, sp, 0 |
| 1593 | or: addw s0, sp, 0 */ |
| 1594 | /* Instructions setting up the frame pointer. */ |
| 1595 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
| 1596 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); |
| 1597 | regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0); |
| 1598 | } |
| 1599 | else if ((insn.opcode () == riscv_insn::ADDI |
| 1600 | && insn.rd () == RISCV_ZERO_REGNUM |
| 1601 | && insn.rs1 () == RISCV_ZERO_REGNUM |
| 1602 | && insn.imm_signed () == 0)) |
| 1603 | { |
| 1604 | /* Handle: add x0, x0, 0 (NOP) */ |
| 1605 | } |
| 1606 | else if (insn.opcode () == riscv_insn::AUIPC) |
| 1607 | { |
| 1608 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
| 1609 | regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ()); |
| 1610 | } |
| 1611 | else if (insn.opcode () == riscv_insn::LUI) |
| 1612 | { |
| 1613 | /* Handle: lui REG, n |
| 1614 | Where REG is not gp register. */ |
| 1615 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
| 1616 | regs[insn.rd ()] = pv_constant (insn.imm_signed ()); |
| 1617 | } |
| 1618 | else if (insn.opcode () == riscv_insn::ADDI) |
| 1619 | { |
| 1620 | /* Handle: addi REG1, REG2, IMM */ |
| 1621 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
| 1622 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); |
| 1623 | regs[insn.rd ()] |
| 1624 | = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()); |
| 1625 | } |
| 1626 | else if (insn.opcode () == riscv_insn::ADD) |
| 1627 | { |
| 1628 | /* Handle: addi REG1, REG2, IMM */ |
| 1629 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
| 1630 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); |
| 1631 | gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS); |
| 1632 | regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]); |
| 1633 | } |
| 1634 | else |
| 1635 | { |
| 1636 | end_prologue_addr = cur_pc; |
| 1637 | break; |
| 1638 | } |
| 1639 | } |
| 1640 | |
| 1641 | if (end_prologue_addr == 0) |
| 1642 | end_prologue_addr = cur_pc; |
| 1643 | |
| 1644 | if (riscv_debug_unwinder) |
| 1645 | fprintf_unfiltered (gdb_stdlog, "End of prologue at %s\n", |
| 1646 | core_addr_to_string (end_prologue_addr)); |
| 1647 | |
| 1648 | if (cache != NULL) |
| 1649 | { |
| 1650 | /* Figure out if it is a frame pointer or just a stack pointer. Also |
| 1651 | the offset held in the pv_t is from the original register value to |
| 1652 | the current value, which for a grows down stack means a negative |
| 1653 | value. The FRAME_BASE_OFFSET is the negation of this, how to get |
| 1654 | from the current value to the original value. */ |
| 1655 | if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM)) |
| 1656 | { |
| 1657 | cache->frame_base_reg = RISCV_FP_REGNUM; |
| 1658 | cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k; |
| 1659 | } |
| 1660 | else |
| 1661 | { |
| 1662 | cache->frame_base_reg = RISCV_SP_REGNUM; |
| 1663 | cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k; |
| 1664 | } |
| 1665 | |
| 1666 | /* Assign offset from old SP to all saved registers. As we don't |
| 1667 | have the previous value for the frame base register at this |
| 1668 | point, we store the offset as the address in the trad_frame, and |
| 1669 | then convert this to an actual address later. */ |
| 1670 | for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++) |
| 1671 | { |
| 1672 | CORE_ADDR offset; |
| 1673 | if (stack.find_reg (gdbarch, i, &offset)) |
| 1674 | { |
| 1675 | if (riscv_debug_unwinder) |
| 1676 | { |
| 1677 | /* Display OFFSET as a signed value, the offsets are from |
| 1678 | the frame base address to the registers location on |
| 1679 | the stack, with a descending stack this means the |
| 1680 | offsets are always negative. */ |
| 1681 | fprintf_unfiltered (gdb_stdlog, |
| 1682 | "Register $%s at stack offset %s\n", |
| 1683 | gdbarch_register_name (gdbarch, i), |
| 1684 | plongest ((LONGEST) offset)); |
| 1685 | } |
| 1686 | trad_frame_set_addr (cache->regs, i, offset); |
| 1687 | } |
| 1688 | } |
| 1689 | } |
| 1690 | |
| 1691 | return end_prologue_addr; |
| 1692 | } |
| 1693 | |
| 1694 | /* Implement the riscv_skip_prologue gdbarch method. */ |
| 1695 | |
| 1696 | static CORE_ADDR |
| 1697 | riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 1698 | { |
| 1699 | CORE_ADDR func_addr; |
| 1700 | |
| 1701 | /* See if we can determine the end of the prologue via the symbol |
| 1702 | table. If so, then return either PC, or the PC after the |
| 1703 | prologue, whichever is greater. */ |
| 1704 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
| 1705 | { |
| 1706 | CORE_ADDR post_prologue_pc |
| 1707 | = skip_prologue_using_sal (gdbarch, func_addr); |
| 1708 | |
| 1709 | if (post_prologue_pc != 0) |
| 1710 | return std::max (pc, post_prologue_pc); |
| 1711 | } |
| 1712 | |
| 1713 | /* Can't determine prologue from the symbol table, need to examine |
| 1714 | instructions. Pass -1 for the end address to indicate the prologue |
| 1715 | scanner can scan as far as it needs to find the end of the prologue. */ |
| 1716 | return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL); |
| 1717 | } |
| 1718 | |
| 1719 | /* Implement the gdbarch push dummy code callback. */ |
| 1720 | |
| 1721 | static CORE_ADDR |
| 1722 | riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, |
| 1723 | CORE_ADDR funaddr, struct value **args, int nargs, |
| 1724 | struct type *value_type, CORE_ADDR *real_pc, |
| 1725 | CORE_ADDR *bp_addr, struct regcache *regcache) |
| 1726 | { |
| 1727 | /* A nop instruction is 'add x0, x0, 0'. */ |
| 1728 | static const gdb_byte nop_insn[] = { 0x13, 0x00, 0x00, 0x00 }; |
| 1729 | |
| 1730 | /* Allocate space for a breakpoint, and keep the stack correctly |
| 1731 | aligned. The space allocated here must be at least big enough to |
| 1732 | accommodate the NOP_INSN defined above. */ |
| 1733 | sp -= 16; |
| 1734 | *bp_addr = sp; |
| 1735 | *real_pc = funaddr; |
| 1736 | |
| 1737 | /* When we insert a breakpoint we select whether to use a compressed |
| 1738 | breakpoint or not based on the existing contents of the memory. |
| 1739 | |
| 1740 | If the breakpoint is being placed onto the stack as part of setting up |
| 1741 | for an inferior call from GDB, then the existing stack contents may |
| 1742 | randomly appear to be a compressed instruction, causing GDB to insert |
| 1743 | a compressed breakpoint. If this happens on a target that does not |
| 1744 | support compressed instructions then this could cause problems. |
| 1745 | |
| 1746 | To prevent this issue we write an uncompressed nop onto the stack at |
| 1747 | the location where the breakpoint will be inserted. In this way we |
| 1748 | ensure that we always use an uncompressed breakpoint, which should |
| 1749 | work on all targets. |
| 1750 | |
| 1751 | We call TARGET_WRITE_MEMORY here so that if the write fails we don't |
| 1752 | throw an exception. Instead we ignore the error and move on. The |
| 1753 | assumption is that either GDB will error later when actually trying to |
| 1754 | insert a software breakpoint, or GDB will use hardware breakpoints and |
| 1755 | there will be no need to write to memory later. */ |
| 1756 | int status = target_write_memory (*bp_addr, nop_insn, sizeof (nop_insn)); |
| 1757 | |
| 1758 | if (riscv_debug_breakpoints || riscv_debug_infcall) |
| 1759 | fprintf_unfiltered (gdb_stdlog, |
| 1760 | "Writing %s-byte nop instruction to %s: %s\n", |
| 1761 | plongest (sizeof (nop_insn)), |
| 1762 | paddress (gdbarch, *bp_addr), |
| 1763 | (status == 0 ? "success" : "failed")); |
| 1764 | |
| 1765 | return sp; |
| 1766 | } |
| 1767 | |
| 1768 | /* Implement the gdbarch type alignment method, overrides the generic |
| 1769 | alignment algorithm for anything that is RISC-V specific. */ |
| 1770 | |
| 1771 | static ULONGEST |
| 1772 | riscv_type_align (gdbarch *gdbarch, type *type) |
| 1773 | { |
| 1774 | type = check_typedef (type); |
| 1775 | if (type->code () == TYPE_CODE_ARRAY && type->is_vector ()) |
| 1776 | return std::min (TYPE_LENGTH (type), (ULONGEST) BIGGEST_ALIGNMENT); |
| 1777 | |
| 1778 | /* Anything else will be aligned by the generic code. */ |
| 1779 | return 0; |
| 1780 | } |
| 1781 | |
| 1782 | /* Holds information about a single argument either being passed to an |
| 1783 | inferior function, or returned from an inferior function. This includes |
| 1784 | information about the size, type, etc of the argument, and also |
| 1785 | information about how the argument will be passed (or returned). */ |
| 1786 | |
| 1787 | struct riscv_arg_info |
| 1788 | { |
| 1789 | /* Contents of the argument. */ |
| 1790 | const gdb_byte *contents; |
| 1791 | |
| 1792 | /* Length of argument. */ |
| 1793 | int length; |
| 1794 | |
| 1795 | /* Alignment required for an argument of this type. */ |
| 1796 | int align; |
| 1797 | |
| 1798 | /* The type for this argument. */ |
| 1799 | struct type *type; |
| 1800 | |
| 1801 | /* Each argument can have either 1 or 2 locations assigned to it. Each |
| 1802 | location describes where part of the argument will be placed. The |
| 1803 | second location is valid based on the LOC_TYPE and C_LENGTH fields |
| 1804 | of the first location (which is always valid). */ |
| 1805 | struct location |
| 1806 | { |
| 1807 | /* What type of location this is. */ |
| 1808 | enum location_type |
| 1809 | { |
| 1810 | /* Argument passed in a register. */ |
| 1811 | in_reg, |
| 1812 | |
| 1813 | /* Argument passed as an on stack argument. */ |
| 1814 | on_stack, |
| 1815 | |
| 1816 | /* Argument passed by reference. The second location is always |
| 1817 | valid for a BY_REF argument, and describes where the address |
| 1818 | of the BY_REF argument should be placed. */ |
| 1819 | by_ref |
| 1820 | } loc_type; |
| 1821 | |
| 1822 | /* Information that depends on the location type. */ |
| 1823 | union |
| 1824 | { |
| 1825 | /* Which register number to use. */ |
| 1826 | int regno; |
| 1827 | |
| 1828 | /* The offset into the stack region. */ |
| 1829 | int offset; |
| 1830 | } loc_data; |
| 1831 | |
| 1832 | /* The length of contents covered by this location. If this is less |
| 1833 | than the total length of the argument, then the second location |
| 1834 | will be valid, and will describe where the rest of the argument |
| 1835 | will go. */ |
| 1836 | int c_length; |
| 1837 | |
| 1838 | /* The offset within CONTENTS for this part of the argument. This can |
| 1839 | be non-zero even for the first part (the first field of a struct can |
| 1840 | have a non-zero offset due to padding). For the second part of the |
| 1841 | argument, this might be the C_LENGTH value of the first part, |
| 1842 | however, if we are passing a structure in two registers, and there's |
| 1843 | is padding between the first and second field, then this offset |
| 1844 | might be greater than the length of the first argument part. When |
| 1845 | the second argument location is not holding part of the argument |
| 1846 | value, but is instead holding the address of a reference argument, |
| 1847 | then this offset will be set to 0. */ |
| 1848 | int c_offset; |
| 1849 | } argloc[2]; |
| 1850 | |
| 1851 | /* TRUE if this is an unnamed argument. */ |
| 1852 | bool is_unnamed; |
| 1853 | }; |
| 1854 | |
| 1855 | /* Information about a set of registers being used for passing arguments as |
| 1856 | part of a function call. The register set must be numerically |
| 1857 | sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be |
| 1858 | disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */ |
| 1859 | |
| 1860 | struct riscv_arg_reg |
| 1861 | { |
| 1862 | riscv_arg_reg (int first, int last) |
| 1863 | : next_regnum (first), |
| 1864 | last_regnum (last) |
| 1865 | { |
| 1866 | /* Nothing. */ |
| 1867 | } |
| 1868 | |
| 1869 | /* The GDB register number to use in this set. */ |
| 1870 | int next_regnum; |
| 1871 | |
| 1872 | /* The last GDB register number to use in this set. */ |
| 1873 | int last_regnum; |
| 1874 | }; |
| 1875 | |
| 1876 | /* Arguments can be passed as on stack arguments, or by reference. The |
| 1877 | on stack arguments must be in a continuous region starting from $sp, |
| 1878 | while the by reference arguments can be anywhere, but we'll put them |
| 1879 | on the stack after (at higher address) the on stack arguments. |
| 1880 | |
| 1881 | This might not be the right approach to take. The ABI is clear that |
| 1882 | an argument passed by reference can be modified by the callee, which |
| 1883 | us placing the argument (temporarily) onto the stack will not achieve |
| 1884 | (changes will be lost). There's also the possibility that very large |
| 1885 | arguments could overflow the stack. |
| 1886 | |
| 1887 | This struct is used to track offset into these two areas for where |
| 1888 | arguments are to be placed. */ |
| 1889 | struct riscv_memory_offsets |
| 1890 | { |
| 1891 | riscv_memory_offsets () |
| 1892 | : arg_offset (0), |
| 1893 | ref_offset (0) |
| 1894 | { |
| 1895 | /* Nothing. */ |
| 1896 | } |
| 1897 | |
| 1898 | /* Offset into on stack argument area. */ |
| 1899 | int arg_offset; |
| 1900 | |
| 1901 | /* Offset into the pass by reference area. */ |
| 1902 | int ref_offset; |
| 1903 | }; |
| 1904 | |
| 1905 | /* Holds information about where arguments to a call will be placed. This |
| 1906 | is updated as arguments are added onto the call, and can be used to |
| 1907 | figure out where the next argument should be placed. */ |
| 1908 | |
| 1909 | struct riscv_call_info |
| 1910 | { |
| 1911 | riscv_call_info (struct gdbarch *gdbarch) |
| 1912 | : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7), |
| 1913 | float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7) |
| 1914 | { |
| 1915 | xlen = riscv_abi_xlen (gdbarch); |
| 1916 | flen = riscv_abi_flen (gdbarch); |
| 1917 | |
| 1918 | /* Disable use of floating point registers if needed. */ |
| 1919 | if (!riscv_has_fp_abi (gdbarch)) |
| 1920 | float_regs.next_regnum = float_regs.last_regnum + 1; |
| 1921 | } |
| 1922 | |
| 1923 | /* Track the memory areas used for holding in-memory arguments to a |
| 1924 | call. */ |
| 1925 | struct riscv_memory_offsets memory; |
| 1926 | |
| 1927 | /* Holds information about the next integer register to use for passing |
| 1928 | an argument. */ |
| 1929 | struct riscv_arg_reg int_regs; |
| 1930 | |
| 1931 | /* Holds information about the next floating point register to use for |
| 1932 | passing an argument. */ |
| 1933 | struct riscv_arg_reg float_regs; |
| 1934 | |
| 1935 | /* The XLEN and FLEN are copied in to this structure for convenience, and |
| 1936 | are just the results of calling RISCV_ABI_XLEN and RISCV_ABI_FLEN. */ |
| 1937 | int xlen; |
| 1938 | int flen; |
| 1939 | }; |
| 1940 | |
| 1941 | /* Return the number of registers available for use as parameters in the |
| 1942 | register set REG. Returned value can be 0 or more. */ |
| 1943 | |
| 1944 | static int |
| 1945 | riscv_arg_regs_available (struct riscv_arg_reg *reg) |
| 1946 | { |
| 1947 | if (reg->next_regnum > reg->last_regnum) |
| 1948 | return 0; |
| 1949 | |
| 1950 | return (reg->last_regnum - reg->next_regnum + 1); |
| 1951 | } |
| 1952 | |
| 1953 | /* If there is at least one register available in the register set REG then |
| 1954 | the next register from REG is assigned to LOC and the length field of |
| 1955 | LOC is updated to LENGTH. The register set REG is updated to indicate |
| 1956 | that the assigned register is no longer available and the function |
| 1957 | returns true. |
| 1958 | |
| 1959 | If there are no registers available in REG then the function returns |
| 1960 | false, and LOC and REG are unchanged. */ |
| 1961 | |
| 1962 | static bool |
| 1963 | riscv_assign_reg_location (struct riscv_arg_info::location *loc, |
| 1964 | struct riscv_arg_reg *reg, |
| 1965 | int length, int offset) |
| 1966 | { |
| 1967 | if (reg->next_regnum <= reg->last_regnum) |
| 1968 | { |
| 1969 | loc->loc_type = riscv_arg_info::location::in_reg; |
| 1970 | loc->loc_data.regno = reg->next_regnum; |
| 1971 | reg->next_regnum++; |
| 1972 | loc->c_length = length; |
| 1973 | loc->c_offset = offset; |
| 1974 | return true; |
| 1975 | } |
| 1976 | |
| 1977 | return false; |
| 1978 | } |
| 1979 | |
| 1980 | /* Assign LOC a location as the next stack parameter, and update MEMORY to |
| 1981 | record that an area of stack has been used to hold the parameter |
| 1982 | described by LOC. |
| 1983 | |
| 1984 | The length field of LOC is updated to LENGTH, the length of the |
| 1985 | parameter being stored, and ALIGN is the alignment required by the |
| 1986 | parameter, which will affect how memory is allocated out of MEMORY. */ |
| 1987 | |
| 1988 | static void |
| 1989 | riscv_assign_stack_location (struct riscv_arg_info::location *loc, |
| 1990 | struct riscv_memory_offsets *memory, |
| 1991 | int length, int align) |
| 1992 | { |
| 1993 | loc->loc_type = riscv_arg_info::location::on_stack; |
| 1994 | memory->arg_offset |
| 1995 | = align_up (memory->arg_offset, align); |
| 1996 | loc->loc_data.offset = memory->arg_offset; |
| 1997 | memory->arg_offset += length; |
| 1998 | loc->c_length = length; |
| 1999 | |
| 2000 | /* Offset is always 0, either we're the first location part, in which |
| 2001 | case we're reading content from the start of the argument, or we're |
| 2002 | passing the address of a reference argument, so 0. */ |
| 2003 | loc->c_offset = 0; |
| 2004 | } |
| 2005 | |
| 2006 | /* Update AINFO, which describes an argument that should be passed or |
| 2007 | returned using the integer ABI. The argloc fields within AINFO are |
| 2008 | updated to describe the location in which the argument will be passed to |
| 2009 | a function, or returned from a function. |
| 2010 | |
| 2011 | The CINFO structure contains the ongoing call information, the holds |
| 2012 | information such as which argument registers are remaining to be |
| 2013 | assigned to parameter, and how much memory has been used by parameters |
| 2014 | so far. |
| 2015 | |
| 2016 | By examining the state of CINFO a suitable location can be selected, |
| 2017 | and assigned to AINFO. */ |
| 2018 | |
| 2019 | static void |
| 2020 | riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo, |
| 2021 | struct riscv_call_info *cinfo) |
| 2022 | { |
| 2023 | if (ainfo->length > (2 * cinfo->xlen)) |
| 2024 | { |
| 2025 | /* Argument is going to be passed by reference. */ |
| 2026 | ainfo->argloc[0].loc_type |
| 2027 | = riscv_arg_info::location::by_ref; |
| 2028 | cinfo->memory.ref_offset |
| 2029 | = align_up (cinfo->memory.ref_offset, ainfo->align); |
| 2030 | ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset; |
| 2031 | cinfo->memory.ref_offset += ainfo->length; |
| 2032 | ainfo->argloc[0].c_length = ainfo->length; |
| 2033 | |
| 2034 | /* The second location for this argument is given over to holding the |
| 2035 | address of the by-reference data. Pass 0 for the offset as this |
| 2036 | is not part of the actual argument value. */ |
| 2037 | if (!riscv_assign_reg_location (&ainfo->argloc[1], |
| 2038 | &cinfo->int_regs, |
| 2039 | cinfo->xlen, 0)) |
| 2040 | riscv_assign_stack_location (&ainfo->argloc[1], |
| 2041 | &cinfo->memory, cinfo->xlen, |
| 2042 | cinfo->xlen); |
| 2043 | } |
| 2044 | else |
| 2045 | { |
| 2046 | int len = std::min (ainfo->length, cinfo->xlen); |
| 2047 | int align = std::max (ainfo->align, cinfo->xlen); |
| 2048 | |
| 2049 | /* Unnamed arguments in registers that require 2*XLEN alignment are |
| 2050 | passed in an aligned register pair. */ |
| 2051 | if (ainfo->is_unnamed && (align == cinfo->xlen * 2) |
| 2052 | && cinfo->int_regs.next_regnum & 1) |
| 2053 | cinfo->int_regs.next_regnum++; |
| 2054 | |
| 2055 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
| 2056 | &cinfo->int_regs, len, 0)) |
| 2057 | riscv_assign_stack_location (&ainfo->argloc[0], |
| 2058 | &cinfo->memory, len, align); |
| 2059 | |
| 2060 | if (len < ainfo->length) |
| 2061 | { |
| 2062 | len = ainfo->length - len; |
| 2063 | if (!riscv_assign_reg_location (&ainfo->argloc[1], |
| 2064 | &cinfo->int_regs, len, |
| 2065 | cinfo->xlen)) |
| 2066 | riscv_assign_stack_location (&ainfo->argloc[1], |
| 2067 | &cinfo->memory, len, cinfo->xlen); |
| 2068 | } |
| 2069 | } |
| 2070 | } |
| 2071 | |
| 2072 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO |
| 2073 | is being passed with the floating point ABI. */ |
| 2074 | |
| 2075 | static void |
| 2076 | riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo, |
| 2077 | struct riscv_call_info *cinfo) |
| 2078 | { |
| 2079 | if (ainfo->length > cinfo->flen || ainfo->is_unnamed) |
| 2080 | return riscv_call_arg_scalar_int (ainfo, cinfo); |
| 2081 | else |
| 2082 | { |
| 2083 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
| 2084 | &cinfo->float_regs, |
| 2085 | ainfo->length, 0)) |
| 2086 | return riscv_call_arg_scalar_int (ainfo, cinfo); |
| 2087 | } |
| 2088 | } |
| 2089 | |
| 2090 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO |
| 2091 | is a complex floating point argument, and is therefore handled |
| 2092 | differently to other argument types. */ |
| 2093 | |
| 2094 | static void |
| 2095 | riscv_call_arg_complex_float (struct riscv_arg_info *ainfo, |
| 2096 | struct riscv_call_info *cinfo) |
| 2097 | { |
| 2098 | if (ainfo->length <= (2 * cinfo->flen) |
| 2099 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2 |
| 2100 | && !ainfo->is_unnamed) |
| 2101 | { |
| 2102 | bool result; |
| 2103 | int len = ainfo->length / 2; |
| 2104 | |
| 2105 | result = riscv_assign_reg_location (&ainfo->argloc[0], |
| 2106 | &cinfo->float_regs, len, 0); |
| 2107 | gdb_assert (result); |
| 2108 | |
| 2109 | result = riscv_assign_reg_location (&ainfo->argloc[1], |
| 2110 | &cinfo->float_regs, len, len); |
| 2111 | gdb_assert (result); |
| 2112 | } |
| 2113 | else |
| 2114 | return riscv_call_arg_scalar_int (ainfo, cinfo); |
| 2115 | } |
| 2116 | |
| 2117 | /* A structure used for holding information about a structure type within |
| 2118 | the inferior program. The RiscV ABI has special rules for handling some |
| 2119 | structures with a single field or with two fields. The counting of |
| 2120 | fields here is done after flattening out all nested structures. */ |
| 2121 | |
| 2122 | class riscv_struct_info |
| 2123 | { |
| 2124 | public: |
| 2125 | riscv_struct_info () |
| 2126 | : m_number_of_fields (0), |
| 2127 | m_types { nullptr, nullptr }, |
| 2128 | m_offsets { 0, 0 } |
| 2129 | { |
| 2130 | /* Nothing. */ |
| 2131 | } |
| 2132 | |
| 2133 | /* Analyse TYPE descending into nested structures, count the number of |
| 2134 | scalar fields and record the types of the first two fields found. */ |
| 2135 | void analyse (struct type *type) |
| 2136 | { |
| 2137 | analyse_inner (type, 0); |
| 2138 | } |
| 2139 | |
| 2140 | /* The number of scalar fields found in the analysed type. This is |
| 2141 | currently only accurate if the value returned is 0, 1, or 2 as the |
| 2142 | analysis stops counting when the number of fields is 3. This is |
| 2143 | because the RiscV ABI only has special cases for 1 or 2 fields, |
| 2144 | anything else we just don't care about. */ |
| 2145 | int number_of_fields () const |
| 2146 | { return m_number_of_fields; } |
| 2147 | |
| 2148 | /* Return the type for scalar field INDEX within the analysed type. Will |
| 2149 | return nullptr if there is no field at that index. Only INDEX values |
| 2150 | 0 and 1 can be requested as the RiscV ABI only has special cases for |
| 2151 | structures with 1 or 2 fields. */ |
| 2152 | struct type *field_type (int index) const |
| 2153 | { |
| 2154 | gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0]))); |
| 2155 | return m_types[index]; |
| 2156 | } |
| 2157 | |
| 2158 | /* Return the offset of scalar field INDEX within the analysed type. Will |
| 2159 | return 0 if there is no field at that index. Only INDEX values 0 and |
| 2160 | 1 can be requested as the RiscV ABI only has special cases for |
| 2161 | structures with 1 or 2 fields. */ |
| 2162 | int field_offset (int index) const |
| 2163 | { |
| 2164 | gdb_assert (index < (sizeof (m_offsets) / sizeof (m_offsets[0]))); |
| 2165 | return m_offsets[index]; |
| 2166 | } |
| 2167 | |
| 2168 | private: |
| 2169 | /* The number of scalar fields found within the structure after recursing |
| 2170 | into nested structures. */ |
| 2171 | int m_number_of_fields; |
| 2172 | |
| 2173 | /* The types of the first two scalar fields found within the structure |
| 2174 | after recursing into nested structures. */ |
| 2175 | struct type *m_types[2]; |
| 2176 | |
| 2177 | /* The offsets of the first two scalar fields found within the structure |
| 2178 | after recursing into nested structures. */ |
| 2179 | int m_offsets[2]; |
| 2180 | |
| 2181 | /* Recursive core for ANALYSE, the OFFSET parameter tracks the byte |
| 2182 | offset from the start of the top level structure being analysed. */ |
| 2183 | void analyse_inner (struct type *type, int offset); |
| 2184 | }; |
| 2185 | |
| 2186 | /* See description in class declaration. */ |
| 2187 | |
| 2188 | void |
| 2189 | riscv_struct_info::analyse_inner (struct type *type, int offset) |
| 2190 | { |
| 2191 | unsigned int count = type->num_fields (); |
| 2192 | unsigned int i; |
| 2193 | |
| 2194 | for (i = 0; i < count; ++i) |
| 2195 | { |
| 2196 | if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS) |
| 2197 | continue; |
| 2198 | |
| 2199 | struct type *field_type = type->field (i).type (); |
| 2200 | field_type = check_typedef (field_type); |
| 2201 | int field_offset |
| 2202 | = offset + TYPE_FIELD_BITPOS (type, i) / TARGET_CHAR_BIT; |
| 2203 | |
| 2204 | switch (field_type->code ()) |
| 2205 | { |
| 2206 | case TYPE_CODE_STRUCT: |
| 2207 | analyse_inner (field_type, field_offset); |
| 2208 | break; |
| 2209 | |
| 2210 | default: |
| 2211 | /* RiscV only flattens out structures. Anything else does not |
| 2212 | need to be flattened, we just record the type, and when we |
| 2213 | look at the analysis results we'll realise this is not a |
| 2214 | structure we can special case, and pass the structure in |
| 2215 | memory. */ |
| 2216 | if (m_number_of_fields < 2) |
| 2217 | { |
| 2218 | m_types[m_number_of_fields] = field_type; |
| 2219 | m_offsets[m_number_of_fields] = field_offset; |
| 2220 | } |
| 2221 | m_number_of_fields++; |
| 2222 | break; |
| 2223 | } |
| 2224 | |
| 2225 | /* RiscV only has special handling for structures with 1 or 2 scalar |
| 2226 | fields, any more than that and the structure is just passed in |
| 2227 | memory. We can safely drop out early when we find 3 or more |
| 2228 | fields then. */ |
| 2229 | |
| 2230 | if (m_number_of_fields > 2) |
| 2231 | return; |
| 2232 | } |
| 2233 | } |
| 2234 | |
| 2235 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO |
| 2236 | is a structure. Small structures on RiscV have some special case |
| 2237 | handling in order that the structure might be passed in register. |
| 2238 | Larger structures are passed in memory. After assigning location |
| 2239 | information to AINFO, CINFO will have been updated. */ |
| 2240 | |
| 2241 | static void |
| 2242 | riscv_call_arg_struct (struct riscv_arg_info *ainfo, |
| 2243 | struct riscv_call_info *cinfo) |
| 2244 | { |
| 2245 | if (riscv_arg_regs_available (&cinfo->float_regs) >= 1) |
| 2246 | { |
| 2247 | struct riscv_struct_info sinfo; |
| 2248 | |
| 2249 | sinfo.analyse (ainfo->type); |
| 2250 | if (sinfo.number_of_fields () == 1 |
| 2251 | && sinfo.field_type(0)->code () == TYPE_CODE_COMPLEX) |
| 2252 | { |
| 2253 | /* The following is similar to RISCV_CALL_ARG_COMPLEX_FLOAT, |
| 2254 | except we use the type of the complex field instead of the |
| 2255 | type from AINFO, and the first location might be at a non-zero |
| 2256 | offset. */ |
| 2257 | if (TYPE_LENGTH (sinfo.field_type (0)) <= (2 * cinfo->flen) |
| 2258 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2 |
| 2259 | && !ainfo->is_unnamed) |
| 2260 | { |
| 2261 | bool result; |
| 2262 | int len = TYPE_LENGTH (sinfo.field_type (0)) / 2; |
| 2263 | int offset = sinfo.field_offset (0); |
| 2264 | |
| 2265 | result = riscv_assign_reg_location (&ainfo->argloc[0], |
| 2266 | &cinfo->float_regs, len, |
| 2267 | offset); |
| 2268 | gdb_assert (result); |
| 2269 | |
| 2270 | result = riscv_assign_reg_location (&ainfo->argloc[1], |
| 2271 | &cinfo->float_regs, len, |
| 2272 | (offset + len)); |
| 2273 | gdb_assert (result); |
| 2274 | } |
| 2275 | else |
| 2276 | riscv_call_arg_scalar_int (ainfo, cinfo); |
| 2277 | return; |
| 2278 | } |
| 2279 | |
| 2280 | if (sinfo.number_of_fields () == 1 |
| 2281 | && sinfo.field_type(0)->code () == TYPE_CODE_FLT) |
| 2282 | { |
| 2283 | /* The following is similar to RISCV_CALL_ARG_SCALAR_FLOAT, |
| 2284 | except we use the type of the first scalar field instead of |
| 2285 | the type from AINFO. Also the location might be at a non-zero |
| 2286 | offset. */ |
| 2287 | if (TYPE_LENGTH (sinfo.field_type (0)) > cinfo->flen |
| 2288 | || ainfo->is_unnamed) |
| 2289 | riscv_call_arg_scalar_int (ainfo, cinfo); |
| 2290 | else |
| 2291 | { |
| 2292 | int offset = sinfo.field_offset (0); |
| 2293 | int len = TYPE_LENGTH (sinfo.field_type (0)); |
| 2294 | |
| 2295 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
| 2296 | &cinfo->float_regs, |
| 2297 | len, offset)) |
| 2298 | riscv_call_arg_scalar_int (ainfo, cinfo); |
| 2299 | } |
| 2300 | return; |
| 2301 | } |
| 2302 | |
| 2303 | if (sinfo.number_of_fields () == 2 |
| 2304 | && sinfo.field_type(0)->code () == TYPE_CODE_FLT |
| 2305 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen |
| 2306 | && sinfo.field_type(1)->code () == TYPE_CODE_FLT |
| 2307 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen |
| 2308 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2) |
| 2309 | { |
| 2310 | int len0 = TYPE_LENGTH (sinfo.field_type (0)); |
| 2311 | int offset = sinfo.field_offset (0); |
| 2312 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
| 2313 | &cinfo->float_regs, len0, offset)) |
| 2314 | error (_("failed during argument setup")); |
| 2315 | |
| 2316 | int len1 = TYPE_LENGTH (sinfo.field_type (1)); |
| 2317 | offset = sinfo.field_offset (1); |
| 2318 | gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type) |
| 2319 | - TYPE_LENGTH (sinfo.field_type (0)))); |
| 2320 | |
| 2321 | if (!riscv_assign_reg_location (&ainfo->argloc[1], |
| 2322 | &cinfo->float_regs, |
| 2323 | len1, offset)) |
| 2324 | error (_("failed during argument setup")); |
| 2325 | return; |
| 2326 | } |
| 2327 | |
| 2328 | if (sinfo.number_of_fields () == 2 |
| 2329 | && riscv_arg_regs_available (&cinfo->int_regs) >= 1 |
| 2330 | && (sinfo.field_type(0)->code () == TYPE_CODE_FLT |
| 2331 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen |
| 2332 | && is_integral_type (sinfo.field_type (1)) |
| 2333 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen)) |
| 2334 | { |
| 2335 | int len0 = TYPE_LENGTH (sinfo.field_type (0)); |
| 2336 | int offset = sinfo.field_offset (0); |
| 2337 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
| 2338 | &cinfo->float_regs, len0, offset)) |
| 2339 | error (_("failed during argument setup")); |
| 2340 | |
| 2341 | int len1 = TYPE_LENGTH (sinfo.field_type (1)); |
| 2342 | offset = sinfo.field_offset (1); |
| 2343 | gdb_assert (len1 <= cinfo->xlen); |
| 2344 | if (!riscv_assign_reg_location (&ainfo->argloc[1], |
| 2345 | &cinfo->int_regs, len1, offset)) |
| 2346 | error (_("failed during argument setup")); |
| 2347 | return; |
| 2348 | } |
| 2349 | |
| 2350 | if (sinfo.number_of_fields () == 2 |
| 2351 | && riscv_arg_regs_available (&cinfo->int_regs) >= 1 |
| 2352 | && (is_integral_type (sinfo.field_type (0)) |
| 2353 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen |
| 2354 | && sinfo.field_type(1)->code () == TYPE_CODE_FLT |
| 2355 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen)) |
| 2356 | { |
| 2357 | int len0 = TYPE_LENGTH (sinfo.field_type (0)); |
| 2358 | int len1 = TYPE_LENGTH (sinfo.field_type (1)); |
| 2359 | |
| 2360 | gdb_assert (len0 <= cinfo->xlen); |
| 2361 | gdb_assert (len1 <= cinfo->flen); |
| 2362 | |
| 2363 | int offset = sinfo.field_offset (0); |
| 2364 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
| 2365 | &cinfo->int_regs, len0, offset)) |
| 2366 | error (_("failed during argument setup")); |
| 2367 | |
| 2368 | offset = sinfo.field_offset (1); |
| 2369 | if (!riscv_assign_reg_location (&ainfo->argloc[1], |
| 2370 | &cinfo->float_regs, |
| 2371 | len1, offset)) |
| 2372 | error (_("failed during argument setup")); |
| 2373 | |
| 2374 | return; |
| 2375 | } |
| 2376 | } |
| 2377 | |
| 2378 | /* Non of the structure flattening cases apply, so we just pass using |
| 2379 | the integer ABI. */ |
| 2380 | riscv_call_arg_scalar_int (ainfo, cinfo); |
| 2381 | } |
| 2382 | |
| 2383 | /* Assign a location to call (or return) argument AINFO, the location is |
| 2384 | selected from CINFO which holds information about what call argument |
| 2385 | locations are available for use next. The TYPE is the type of the |
| 2386 | argument being passed, this information is recorded into AINFO (along |
| 2387 | with some additional information derived from the type). IS_UNNAMED |
| 2388 | is true if this is an unnamed (stdarg) argument, this info is also |
| 2389 | recorded into AINFO. |
| 2390 | |
| 2391 | After assigning a location to AINFO, CINFO will have been updated. */ |
| 2392 | |
| 2393 | static void |
| 2394 | riscv_arg_location (struct gdbarch *gdbarch, |
| 2395 | struct riscv_arg_info *ainfo, |
| 2396 | struct riscv_call_info *cinfo, |
| 2397 | struct type *type, bool is_unnamed) |
| 2398 | { |
| 2399 | ainfo->type = type; |
| 2400 | ainfo->length = TYPE_LENGTH (ainfo->type); |
| 2401 | ainfo->align = type_align (ainfo->type); |
| 2402 | ainfo->is_unnamed = is_unnamed; |
| 2403 | ainfo->contents = nullptr; |
| 2404 | ainfo->argloc[0].c_length = 0; |
| 2405 | ainfo->argloc[1].c_length = 0; |
| 2406 | |
| 2407 | switch (ainfo->type->code ()) |
| 2408 | { |
| 2409 | case TYPE_CODE_INT: |
| 2410 | case TYPE_CODE_BOOL: |
| 2411 | case TYPE_CODE_CHAR: |
| 2412 | case TYPE_CODE_RANGE: |
| 2413 | case TYPE_CODE_ENUM: |
| 2414 | case TYPE_CODE_PTR: |
| 2415 | if (ainfo->length <= cinfo->xlen) |
| 2416 | { |
| 2417 | ainfo->type = builtin_type (gdbarch)->builtin_long; |
| 2418 | ainfo->length = cinfo->xlen; |
| 2419 | } |
| 2420 | else if (ainfo->length <= (2 * cinfo->xlen)) |
| 2421 | { |
| 2422 | ainfo->type = builtin_type (gdbarch)->builtin_long_long; |
| 2423 | ainfo->length = 2 * cinfo->xlen; |
| 2424 | } |
| 2425 | |
| 2426 | /* Recalculate the alignment requirement. */ |
| 2427 | ainfo->align = type_align (ainfo->type); |
| 2428 | riscv_call_arg_scalar_int (ainfo, cinfo); |
| 2429 | break; |
| 2430 | |
| 2431 | case TYPE_CODE_FLT: |
| 2432 | riscv_call_arg_scalar_float (ainfo, cinfo); |
| 2433 | break; |
| 2434 | |
| 2435 | case TYPE_CODE_COMPLEX: |
| 2436 | riscv_call_arg_complex_float (ainfo, cinfo); |
| 2437 | break; |
| 2438 | |
| 2439 | case TYPE_CODE_STRUCT: |
| 2440 | riscv_call_arg_struct (ainfo, cinfo); |
| 2441 | break; |
| 2442 | |
| 2443 | default: |
| 2444 | riscv_call_arg_scalar_int (ainfo, cinfo); |
| 2445 | break; |
| 2446 | } |
| 2447 | } |
| 2448 | |
| 2449 | /* Used for printing debug information about the call argument location in |
| 2450 | INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base |
| 2451 | addresses for the location of pass-by-reference and |
| 2452 | arguments-on-the-stack memory areas. */ |
| 2453 | |
| 2454 | static void |
| 2455 | riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch, |
| 2456 | struct riscv_arg_info *info, |
| 2457 | CORE_ADDR sp_refs, CORE_ADDR sp_args) |
| 2458 | { |
| 2459 | fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x", |
| 2460 | TYPE_SAFE_NAME (info->type), info->length, info->align); |
| 2461 | switch (info->argloc[0].loc_type) |
| 2462 | { |
| 2463 | case riscv_arg_info::location::in_reg: |
| 2464 | fprintf_unfiltered |
| 2465 | (stream, ", register %s", |
| 2466 | gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno)); |
| 2467 | if (info->argloc[0].c_length < info->length) |
| 2468 | { |
| 2469 | switch (info->argloc[1].loc_type) |
| 2470 | { |
| 2471 | case riscv_arg_info::location::in_reg: |
| 2472 | fprintf_unfiltered |
| 2473 | (stream, ", register %s", |
| 2474 | gdbarch_register_name (gdbarch, |
| 2475 | info->argloc[1].loc_data.regno)); |
| 2476 | break; |
| 2477 | |
| 2478 | case riscv_arg_info::location::on_stack: |
| 2479 | fprintf_unfiltered (stream, ", on stack at offset 0x%x", |
| 2480 | info->argloc[1].loc_data.offset); |
| 2481 | break; |
| 2482 | |
| 2483 | case riscv_arg_info::location::by_ref: |
| 2484 | default: |
| 2485 | /* The second location should never be a reference, any |
| 2486 | argument being passed by reference just places its address |
| 2487 | in the first location and is done. */ |
| 2488 | error (_("invalid argument location")); |
| 2489 | break; |
| 2490 | } |
| 2491 | |
| 2492 | if (info->argloc[1].c_offset > info->argloc[0].c_length) |
| 2493 | fprintf_unfiltered (stream, " (offset 0x%x)", |
| 2494 | info->argloc[1].c_offset); |
| 2495 | } |
| 2496 | break; |
| 2497 | |
| 2498 | case riscv_arg_info::location::on_stack: |
| 2499 | fprintf_unfiltered (stream, ", on stack at offset 0x%x", |
| 2500 | info->argloc[0].loc_data.offset); |
| 2501 | break; |
| 2502 | |
| 2503 | case riscv_arg_info::location::by_ref: |
| 2504 | fprintf_unfiltered |
| 2505 | (stream, ", by reference, data at offset 0x%x (%s)", |
| 2506 | info->argloc[0].loc_data.offset, |
| 2507 | core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset)); |
| 2508 | if (info->argloc[1].loc_type |
| 2509 | == riscv_arg_info::location::in_reg) |
| 2510 | fprintf_unfiltered |
| 2511 | (stream, ", address in register %s", |
| 2512 | gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno)); |
| 2513 | else |
| 2514 | { |
| 2515 | gdb_assert (info->argloc[1].loc_type |
| 2516 | == riscv_arg_info::location::on_stack); |
| 2517 | fprintf_unfiltered |
| 2518 | (stream, ", address on stack at offset 0x%x (%s)", |
| 2519 | info->argloc[1].loc_data.offset, |
| 2520 | core_addr_to_string (sp_args + info->argloc[1].loc_data.offset)); |
| 2521 | } |
| 2522 | break; |
| 2523 | |
| 2524 | default: |
| 2525 | gdb_assert_not_reached (_("unknown argument location type")); |
| 2526 | } |
| 2527 | } |
| 2528 | |
| 2529 | /* Wrapper around REGCACHE->cooked_write. Places the LEN bytes of DATA |
| 2530 | into a buffer that is at least as big as the register REGNUM, padding |
| 2531 | out the DATA with either 0x00, or 0xff. For floating point registers |
| 2532 | 0xff is used, for everyone else 0x00 is used. */ |
| 2533 | |
| 2534 | static void |
| 2535 | riscv_regcache_cooked_write (int regnum, const gdb_byte *data, int len, |
| 2536 | struct regcache *regcache, int flen) |
| 2537 | { |
| 2538 | gdb_byte tmp [sizeof (ULONGEST)]; |
| 2539 | |
| 2540 | /* FP values in FP registers must be NaN-boxed. */ |
| 2541 | if (riscv_is_fp_regno_p (regnum) && len < flen) |
| 2542 | memset (tmp, -1, sizeof (tmp)); |
| 2543 | else |
| 2544 | memset (tmp, 0, sizeof (tmp)); |
| 2545 | memcpy (tmp, data, len); |
| 2546 | regcache->cooked_write (regnum, tmp); |
| 2547 | } |
| 2548 | |
| 2549 | /* Implement the push dummy call gdbarch callback. */ |
| 2550 | |
| 2551 | static CORE_ADDR |
| 2552 | riscv_push_dummy_call (struct gdbarch *gdbarch, |
| 2553 | struct value *function, |
| 2554 | struct regcache *regcache, |
| 2555 | CORE_ADDR bp_addr, |
| 2556 | int nargs, |
| 2557 | struct value **args, |
| 2558 | CORE_ADDR sp, |
| 2559 | function_call_return_method return_method, |
| 2560 | CORE_ADDR struct_addr) |
| 2561 | { |
| 2562 | int i; |
| 2563 | CORE_ADDR sp_args, sp_refs; |
| 2564 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2565 | |
| 2566 | struct riscv_arg_info *arg_info = |
| 2567 | (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info)); |
| 2568 | |
| 2569 | struct riscv_call_info call_info (gdbarch); |
| 2570 | |
| 2571 | CORE_ADDR osp = sp; |
| 2572 | |
| 2573 | struct type *ftype = check_typedef (value_type (function)); |
| 2574 | |
| 2575 | if (ftype->code () == TYPE_CODE_PTR) |
| 2576 | ftype = check_typedef (TYPE_TARGET_TYPE (ftype)); |
| 2577 | |
| 2578 | /* We'll use register $a0 if we're returning a struct. */ |
| 2579 | if (return_method == return_method_struct) |
| 2580 | ++call_info.int_regs.next_regnum; |
| 2581 | |
| 2582 | for (i = 0; i < nargs; ++i) |
| 2583 | { |
| 2584 | struct value *arg_value; |
| 2585 | struct type *arg_type; |
| 2586 | struct riscv_arg_info *info = &arg_info[i]; |
| 2587 | |
| 2588 | arg_value = args[i]; |
| 2589 | arg_type = check_typedef (value_type (arg_value)); |
| 2590 | |
| 2591 | riscv_arg_location (gdbarch, info, &call_info, arg_type, |
| 2592 | ftype->has_varargs () && i >= ftype->num_fields ()); |
| 2593 | |
| 2594 | if (info->type != arg_type) |
| 2595 | arg_value = value_cast (info->type, arg_value); |
| 2596 | info->contents = value_contents (arg_value); |
| 2597 | } |
| 2598 | |
| 2599 | /* Adjust the stack pointer and align it. */ |
| 2600 | sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT); |
| 2601 | sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT); |
| 2602 | |
| 2603 | if (riscv_debug_infcall > 0) |
| 2604 | { |
| 2605 | fprintf_unfiltered (gdb_stdlog, "dummy call args:\n"); |
| 2606 | fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n", |
| 2607 | (riscv_has_fp_abi (gdbarch) ? "is" : "is not")); |
| 2608 | fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n", |
| 2609 | call_info.xlen, call_info.flen); |
| 2610 | if (return_method == return_method_struct) |
| 2611 | fprintf_unfiltered (gdb_stdlog, |
| 2612 | "[*] struct return pointer in register $A0\n"); |
| 2613 | for (i = 0; i < nargs; ++i) |
| 2614 | { |
| 2615 | struct riscv_arg_info *info = &arg_info [i]; |
| 2616 | |
| 2617 | fprintf_unfiltered (gdb_stdlog, "[%2d] ", i); |
| 2618 | riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args); |
| 2619 | fprintf_unfiltered (gdb_stdlog, "\n"); |
| 2620 | } |
| 2621 | if (call_info.memory.arg_offset > 0 |
| 2622 | || call_info.memory.ref_offset > 0) |
| 2623 | { |
| 2624 | fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n", |
| 2625 | core_addr_to_string (osp)); |
| 2626 | fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n", |
| 2627 | call_info.memory.arg_offset); |
| 2628 | fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n", |
| 2629 | call_info.memory.ref_offset); |
| 2630 | fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n", |
| 2631 | core_addr_to_string_nz (osp - sp)); |
| 2632 | } |
| 2633 | } |
| 2634 | |
| 2635 | /* Now load the argument into registers, or onto the stack. */ |
| 2636 | |
| 2637 | if (return_method == return_method_struct) |
| 2638 | { |
| 2639 | gdb_byte buf[sizeof (LONGEST)]; |
| 2640 | |
| 2641 | store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr); |
| 2642 | regcache->cooked_write (RISCV_A0_REGNUM, buf); |
| 2643 | } |
| 2644 | |
| 2645 | for (i = 0; i < nargs; ++i) |
| 2646 | { |
| 2647 | CORE_ADDR dst; |
| 2648 | int second_arg_length = 0; |
| 2649 | const gdb_byte *second_arg_data; |
| 2650 | struct riscv_arg_info *info = &arg_info [i]; |
| 2651 | |
| 2652 | gdb_assert (info->length > 0); |
| 2653 | |
| 2654 | switch (info->argloc[0].loc_type) |
| 2655 | { |
| 2656 | case riscv_arg_info::location::in_reg: |
| 2657 | { |
| 2658 | gdb_assert (info->argloc[0].c_length <= info->length); |
| 2659 | |
| 2660 | riscv_regcache_cooked_write (info->argloc[0].loc_data.regno, |
| 2661 | (info->contents |
| 2662 | + info->argloc[0].c_offset), |
| 2663 | info->argloc[0].c_length, |
| 2664 | regcache, call_info.flen); |
| 2665 | second_arg_length = |
| 2666 | (((info->argloc[0].c_length + info->argloc[0].c_offset) < info->length) |
| 2667 | ? info->argloc[1].c_length : 0); |
| 2668 | second_arg_data = info->contents + info->argloc[1].c_offset; |
| 2669 | } |
| 2670 | break; |
| 2671 | |
| 2672 | case riscv_arg_info::location::on_stack: |
| 2673 | dst = sp_args + info->argloc[0].loc_data.offset; |
| 2674 | write_memory (dst, info->contents, info->length); |
| 2675 | second_arg_length = 0; |
| 2676 | break; |
| 2677 | |
| 2678 | case riscv_arg_info::location::by_ref: |
| 2679 | dst = sp_refs + info->argloc[0].loc_data.offset; |
| 2680 | write_memory (dst, info->contents, info->length); |
| 2681 | |
| 2682 | second_arg_length = call_info.xlen; |
| 2683 | second_arg_data = (gdb_byte *) &dst; |
| 2684 | break; |
| 2685 | |
| 2686 | default: |
| 2687 | gdb_assert_not_reached (_("unknown argument location type")); |
| 2688 | } |
| 2689 | |
| 2690 | if (second_arg_length > 0) |
| 2691 | { |
| 2692 | switch (info->argloc[1].loc_type) |
| 2693 | { |
| 2694 | case riscv_arg_info::location::in_reg: |
| 2695 | { |
| 2696 | gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno) |
| 2697 | && second_arg_length <= call_info.flen) |
| 2698 | || second_arg_length <= call_info.xlen); |
| 2699 | riscv_regcache_cooked_write (info->argloc[1].loc_data.regno, |
| 2700 | second_arg_data, |
| 2701 | second_arg_length, |
| 2702 | regcache, call_info.flen); |
| 2703 | } |
| 2704 | break; |
| 2705 | |
| 2706 | case riscv_arg_info::location::on_stack: |
| 2707 | { |
| 2708 | CORE_ADDR arg_addr; |
| 2709 | |
| 2710 | arg_addr = sp_args + info->argloc[1].loc_data.offset; |
| 2711 | write_memory (arg_addr, second_arg_data, second_arg_length); |
| 2712 | break; |
| 2713 | } |
| 2714 | |
| 2715 | case riscv_arg_info::location::by_ref: |
| 2716 | default: |
| 2717 | /* The second location should never be a reference, any |
| 2718 | argument being passed by reference just places its address |
| 2719 | in the first location and is done. */ |
| 2720 | error (_("invalid argument location")); |
| 2721 | break; |
| 2722 | } |
| 2723 | } |
| 2724 | } |
| 2725 | |
| 2726 | /* Set the dummy return value to bp_addr. |
| 2727 | A dummy breakpoint will be setup to execute the call. */ |
| 2728 | |
| 2729 | if (riscv_debug_infcall > 0) |
| 2730 | fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n", |
| 2731 | core_addr_to_string (bp_addr)); |
| 2732 | regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr); |
| 2733 | |
| 2734 | /* Finally, update the stack pointer. */ |
| 2735 | |
| 2736 | if (riscv_debug_infcall > 0) |
| 2737 | fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n", |
| 2738 | core_addr_to_string (sp)); |
| 2739 | regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp); |
| 2740 | |
| 2741 | return sp; |
| 2742 | } |
| 2743 | |
| 2744 | /* Implement the return_value gdbarch method. */ |
| 2745 | |
| 2746 | static enum return_value_convention |
| 2747 | riscv_return_value (struct gdbarch *gdbarch, |
| 2748 | struct value *function, |
| 2749 | struct type *type, |
| 2750 | struct regcache *regcache, |
| 2751 | gdb_byte *readbuf, |
| 2752 | const gdb_byte *writebuf) |
| 2753 | { |
| 2754 | struct riscv_call_info call_info (gdbarch); |
| 2755 | struct riscv_arg_info info; |
| 2756 | struct type *arg_type; |
| 2757 | |
| 2758 | arg_type = check_typedef (type); |
| 2759 | riscv_arg_location (gdbarch, &info, &call_info, arg_type, false); |
| 2760 | |
| 2761 | if (riscv_debug_infcall > 0) |
| 2762 | { |
| 2763 | fprintf_unfiltered (gdb_stdlog, "riscv return value:\n"); |
| 2764 | fprintf_unfiltered (gdb_stdlog, "[R] "); |
| 2765 | riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0); |
| 2766 | fprintf_unfiltered (gdb_stdlog, "\n"); |
| 2767 | } |
| 2768 | |
| 2769 | if (readbuf != nullptr || writebuf != nullptr) |
| 2770 | { |
| 2771 | unsigned int arg_len; |
| 2772 | struct value *abi_val; |
| 2773 | gdb_byte *old_readbuf = nullptr; |
| 2774 | int regnum; |
| 2775 | |
| 2776 | /* We only do one thing at a time. */ |
| 2777 | gdb_assert (readbuf == nullptr || writebuf == nullptr); |
| 2778 | |
| 2779 | /* In some cases the argument is not returned as the declared type, |
| 2780 | and we need to cast to or from the ABI type in order to |
| 2781 | correctly access the argument. When writing to the machine we |
| 2782 | do the cast here, when reading from the machine the cast occurs |
| 2783 | later, after extracting the value. As the ABI type can be |
| 2784 | larger than the declared type, then the read or write buffers |
| 2785 | passed in might be too small. Here we ensure that we are using |
| 2786 | buffers of sufficient size. */ |
| 2787 | if (writebuf != nullptr) |
| 2788 | { |
| 2789 | struct value *arg_val = value_from_contents (arg_type, writebuf); |
| 2790 | abi_val = value_cast (info.type, arg_val); |
| 2791 | writebuf = value_contents_raw (abi_val); |
| 2792 | } |
| 2793 | else |
| 2794 | { |
| 2795 | abi_val = allocate_value (info.type); |
| 2796 | old_readbuf = readbuf; |
| 2797 | readbuf = value_contents_raw (abi_val); |
| 2798 | } |
| 2799 | arg_len = TYPE_LENGTH (info.type); |
| 2800 | |
| 2801 | switch (info.argloc[0].loc_type) |
| 2802 | { |
| 2803 | /* Return value in register(s). */ |
| 2804 | case riscv_arg_info::location::in_reg: |
| 2805 | { |
| 2806 | regnum = info.argloc[0].loc_data.regno; |
| 2807 | gdb_assert (info.argloc[0].c_length <= arg_len); |
| 2808 | gdb_assert (info.argloc[0].c_length |
| 2809 | <= register_size (gdbarch, regnum)); |
| 2810 | |
| 2811 | if (readbuf) |
| 2812 | { |
| 2813 | gdb_byte *ptr = readbuf + info.argloc[0].c_offset; |
| 2814 | regcache->cooked_read_part (regnum, 0, |
| 2815 | info.argloc[0].c_length, |
| 2816 | ptr); |
| 2817 | } |
| 2818 | |
| 2819 | if (writebuf) |
| 2820 | { |
| 2821 | const gdb_byte *ptr = writebuf + info.argloc[0].c_offset; |
| 2822 | riscv_regcache_cooked_write (regnum, ptr, |
| 2823 | info.argloc[0].c_length, |
| 2824 | regcache, call_info.flen); |
| 2825 | } |
| 2826 | |
| 2827 | /* A return value in register can have a second part in a |
| 2828 | second register. */ |
| 2829 | if (info.argloc[1].c_length > 0) |
| 2830 | { |
| 2831 | switch (info.argloc[1].loc_type) |
| 2832 | { |
| 2833 | case riscv_arg_info::location::in_reg: |
| 2834 | regnum = info.argloc[1].loc_data.regno; |
| 2835 | |
| 2836 | gdb_assert ((info.argloc[0].c_length |
| 2837 | + info.argloc[1].c_length) <= arg_len); |
| 2838 | gdb_assert (info.argloc[1].c_length |
| 2839 | <= register_size (gdbarch, regnum)); |
| 2840 | |
| 2841 | if (readbuf) |
| 2842 | { |
| 2843 | readbuf += info.argloc[1].c_offset; |
| 2844 | regcache->cooked_read_part (regnum, 0, |
| 2845 | info.argloc[1].c_length, |
| 2846 | readbuf); |
| 2847 | } |
| 2848 | |
| 2849 | if (writebuf) |
| 2850 | { |
| 2851 | const gdb_byte *ptr |
| 2852 | = writebuf + info.argloc[1].c_offset; |
| 2853 | riscv_regcache_cooked_write |
| 2854 | (regnum, ptr, info.argloc[1].c_length, |
| 2855 | regcache, call_info.flen); |
| 2856 | } |
| 2857 | break; |
| 2858 | |
| 2859 | case riscv_arg_info::location::by_ref: |
| 2860 | case riscv_arg_info::location::on_stack: |
| 2861 | default: |
| 2862 | error (_("invalid argument location")); |
| 2863 | break; |
| 2864 | } |
| 2865 | } |
| 2866 | } |
| 2867 | break; |
| 2868 | |
| 2869 | /* Return value by reference will have its address in A0. */ |
| 2870 | case riscv_arg_info::location::by_ref: |
| 2871 | { |
| 2872 | ULONGEST addr; |
| 2873 | |
| 2874 | regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM, |
| 2875 | &addr); |
| 2876 | if (readbuf != nullptr) |
| 2877 | read_memory (addr, readbuf, info.length); |
| 2878 | if (writebuf != nullptr) |
| 2879 | write_memory (addr, writebuf, info.length); |
| 2880 | } |
| 2881 | break; |
| 2882 | |
| 2883 | case riscv_arg_info::location::on_stack: |
| 2884 | default: |
| 2885 | error (_("invalid argument location")); |
| 2886 | break; |
| 2887 | } |
| 2888 | |
| 2889 | /* This completes the cast from abi type back to the declared type |
| 2890 | in the case that we are reading from the machine. See the |
| 2891 | comment at the head of this block for more details. */ |
| 2892 | if (readbuf != nullptr) |
| 2893 | { |
| 2894 | struct value *arg_val = value_cast (arg_type, abi_val); |
| 2895 | memcpy (old_readbuf, value_contents_raw (arg_val), |
| 2896 | TYPE_LENGTH (arg_type)); |
| 2897 | } |
| 2898 | } |
| 2899 | |
| 2900 | switch (info.argloc[0].loc_type) |
| 2901 | { |
| 2902 | case riscv_arg_info::location::in_reg: |
| 2903 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 2904 | case riscv_arg_info::location::by_ref: |
| 2905 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; |
| 2906 | case riscv_arg_info::location::on_stack: |
| 2907 | default: |
| 2908 | error (_("invalid argument location")); |
| 2909 | } |
| 2910 | } |
| 2911 | |
| 2912 | /* Implement the frame_align gdbarch method. */ |
| 2913 | |
| 2914 | static CORE_ADDR |
| 2915 | riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 2916 | { |
| 2917 | return align_down (addr, 16); |
| 2918 | } |
| 2919 | |
| 2920 | /* Generate, or return the cached frame cache for the RiscV frame |
| 2921 | unwinder. */ |
| 2922 | |
| 2923 | static struct riscv_unwind_cache * |
| 2924 | riscv_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 2925 | { |
| 2926 | CORE_ADDR pc, start_addr; |
| 2927 | struct riscv_unwind_cache *cache; |
| 2928 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 2929 | int numregs, regno; |
| 2930 | |
| 2931 | if ((*this_cache) != NULL) |
| 2932 | return (struct riscv_unwind_cache *) *this_cache; |
| 2933 | |
| 2934 | cache = FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache); |
| 2935 | cache->regs = trad_frame_alloc_saved_regs (this_frame); |
| 2936 | (*this_cache) = cache; |
| 2937 | |
| 2938 | /* Scan the prologue, filling in the cache. */ |
| 2939 | start_addr = get_frame_func (this_frame); |
| 2940 | pc = get_frame_pc (this_frame); |
| 2941 | riscv_scan_prologue (gdbarch, start_addr, pc, cache); |
| 2942 | |
| 2943 | /* We can now calculate the frame base address. */ |
| 2944 | cache->frame_base |
| 2945 | = (get_frame_register_signed (this_frame, cache->frame_base_reg) |
| 2946 | + cache->frame_base_offset); |
| 2947 | if (riscv_debug_unwinder) |
| 2948 | fprintf_unfiltered (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n", |
| 2949 | core_addr_to_string (cache->frame_base), |
| 2950 | gdbarch_register_name (gdbarch, |
| 2951 | cache->frame_base_reg), |
| 2952 | cache->frame_base_offset); |
| 2953 | |
| 2954 | /* The prologue scanner sets the address of registers stored to the stack |
| 2955 | as the offset of that register from the frame base. The prologue |
| 2956 | scanner doesn't know the actual frame base value, and so is unable to |
| 2957 | compute the exact address. We do now know the frame base value, so |
| 2958 | update the address of registers stored to the stack. */ |
| 2959 | numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
| 2960 | for (regno = 0; regno < numregs; ++regno) |
| 2961 | { |
| 2962 | if (trad_frame_addr_p (cache->regs, regno)) |
| 2963 | cache->regs[regno].addr += cache->frame_base; |
| 2964 | } |
| 2965 | |
| 2966 | /* The previous $pc can be found wherever the $ra value can be found. |
| 2967 | The previous $ra value is gone, this would have been stored be the |
| 2968 | previous frame if required. */ |
| 2969 | cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM]; |
| 2970 | trad_frame_set_unknown (cache->regs, RISCV_RA_REGNUM); |
| 2971 | |
| 2972 | /* Build the frame id. */ |
| 2973 | cache->this_id = frame_id_build (cache->frame_base, start_addr); |
| 2974 | |
| 2975 | /* The previous $sp value is the frame base value. */ |
| 2976 | trad_frame_set_value (cache->regs, gdbarch_sp_regnum (gdbarch), |
| 2977 | cache->frame_base); |
| 2978 | |
| 2979 | return cache; |
| 2980 | } |
| 2981 | |
| 2982 | /* Implement the this_id callback for RiscV frame unwinder. */ |
| 2983 | |
| 2984 | static void |
| 2985 | riscv_frame_this_id (struct frame_info *this_frame, |
| 2986 | void **prologue_cache, |
| 2987 | struct frame_id *this_id) |
| 2988 | { |
| 2989 | struct riscv_unwind_cache *cache; |
| 2990 | |
| 2991 | try |
| 2992 | { |
| 2993 | cache = riscv_frame_cache (this_frame, prologue_cache); |
| 2994 | *this_id = cache->this_id; |
| 2995 | } |
| 2996 | catch (const gdb_exception_error &ex) |
| 2997 | { |
| 2998 | /* Ignore errors, this leaves the frame id as the predefined outer |
| 2999 | frame id which terminates the backtrace at this point. */ |
| 3000 | } |
| 3001 | } |
| 3002 | |
| 3003 | /* Implement the prev_register callback for RiscV frame unwinder. */ |
| 3004 | |
| 3005 | static struct value * |
| 3006 | riscv_frame_prev_register (struct frame_info *this_frame, |
| 3007 | void **prologue_cache, |
| 3008 | int regnum) |
| 3009 | { |
| 3010 | struct riscv_unwind_cache *cache; |
| 3011 | |
| 3012 | cache = riscv_frame_cache (this_frame, prologue_cache); |
| 3013 | return trad_frame_get_prev_register (this_frame, cache->regs, regnum); |
| 3014 | } |
| 3015 | |
| 3016 | /* Structure defining the RiscV normal frame unwind functions. Since we |
| 3017 | are the fallback unwinder (DWARF unwinder is used first), we use the |
| 3018 | default frame sniffer, which always accepts the frame. */ |
| 3019 | |
| 3020 | static const struct frame_unwind riscv_frame_unwind = |
| 3021 | { |
| 3022 | /*.type =*/ NORMAL_FRAME, |
| 3023 | /*.stop_reason =*/ default_frame_unwind_stop_reason, |
| 3024 | /*.this_id =*/ riscv_frame_this_id, |
| 3025 | /*.prev_register =*/ riscv_frame_prev_register, |
| 3026 | /*.unwind_data =*/ NULL, |
| 3027 | /*.sniffer =*/ default_frame_sniffer, |
| 3028 | /*.dealloc_cache =*/ NULL, |
| 3029 | /*.prev_arch =*/ NULL, |
| 3030 | }; |
| 3031 | |
| 3032 | /* Extract a set of required target features out of INFO, specifically the |
| 3033 | bfd being executed is examined to see what target features it requires. |
| 3034 | IF there is no current bfd, or the bfd doesn't indicate any useful |
| 3035 | features then a RISCV_GDBARCH_FEATURES is returned in its default state. */ |
| 3036 | |
| 3037 | static struct riscv_gdbarch_features |
| 3038 | riscv_features_from_gdbarch_info (const struct gdbarch_info info) |
| 3039 | { |
| 3040 | struct riscv_gdbarch_features features; |
| 3041 | |
| 3042 | /* Now try to improve on the defaults by looking at the binary we are |
| 3043 | going to execute. We assume the user knows what they are doing and |
| 3044 | that the target will match the binary. Remember, this code path is |
| 3045 | only used at all if the target hasn't given us a description, so this |
| 3046 | is really a last ditched effort to do something sane before giving |
| 3047 | up. */ |
| 3048 | if (info.abfd != NULL |
| 3049 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) |
| 3050 | { |
| 3051 | unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS]; |
| 3052 | int e_flags = elf_elfheader (info.abfd)->e_flags; |
| 3053 | |
| 3054 | if (eclass == ELFCLASS32) |
| 3055 | features.xlen = 4; |
| 3056 | else if (eclass == ELFCLASS64) |
| 3057 | features.xlen = 8; |
| 3058 | else |
| 3059 | internal_error (__FILE__, __LINE__, |
| 3060 | _("unknown ELF header class %d"), eclass); |
| 3061 | |
| 3062 | if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE) |
| 3063 | features.flen = 8; |
| 3064 | else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE) |
| 3065 | features.flen = 4; |
| 3066 | } |
| 3067 | |
| 3068 | return features; |
| 3069 | } |
| 3070 | |
| 3071 | /* Find a suitable default target description. Use the contents of INFO, |
| 3072 | specifically the bfd object being executed, to guide the selection of a |
| 3073 | suitable default target description. */ |
| 3074 | |
| 3075 | static const struct target_desc * |
| 3076 | riscv_find_default_target_description (const struct gdbarch_info info) |
| 3077 | { |
| 3078 | /* Extract desired feature set from INFO. */ |
| 3079 | struct riscv_gdbarch_features features |
| 3080 | = riscv_features_from_gdbarch_info (info); |
| 3081 | |
| 3082 | /* If the XLEN field is still 0 then we got nothing useful from INFO. In |
| 3083 | this case we fall back to a minimal useful target, 8-byte x-registers, |
| 3084 | with no floating point. */ |
| 3085 | if (features.xlen == 0) |
| 3086 | features.xlen = 8; |
| 3087 | |
| 3088 | /* Now build a target description based on the feature set. */ |
| 3089 | return riscv_lookup_target_description (features); |
| 3090 | } |
| 3091 | |
| 3092 | /* All of the registers in REG_SET are checked for in FEATURE, TDESC_DATA |
| 3093 | is updated with the register numbers for each register as listed in |
| 3094 | REG_SET. If any register marked as required in REG_SET is not found in |
| 3095 | FEATURE then this function returns false, otherwise, it returns true. */ |
| 3096 | |
| 3097 | static bool |
| 3098 | riscv_check_tdesc_feature (struct tdesc_arch_data *tdesc_data, |
| 3099 | const struct tdesc_feature *main_feature, |
| 3100 | const struct tdesc_feature *csr_feature, |
| 3101 | const struct riscv_register_feature *reg_set, |
| 3102 | std::vector<riscv_pending_register_alias> *aliases) |
| 3103 | { |
| 3104 | for (const auto ® : reg_set->registers) |
| 3105 | { |
| 3106 | bool found = reg.check (tdesc_data, main_feature, reg_set, aliases); |
| 3107 | |
| 3108 | if (!found && reg.required != RISCV_REG_OPTIONAL) |
| 3109 | { |
| 3110 | if (reg.required == RISCV_REG_REQUIRED_MAYBE_CSR |
| 3111 | && csr_feature != nullptr) |
| 3112 | { |
| 3113 | gdb_assert (main_feature != csr_feature); |
| 3114 | found = reg.check (tdesc_data, csr_feature, reg_set, aliases); |
| 3115 | } |
| 3116 | if (!found) |
| 3117 | return false; |
| 3118 | } |
| 3119 | } |
| 3120 | |
| 3121 | return true; |
| 3122 | } |
| 3123 | |
| 3124 | /* Add all the expected register sets into GDBARCH. */ |
| 3125 | |
| 3126 | static void |
| 3127 | riscv_add_reggroups (struct gdbarch *gdbarch) |
| 3128 | { |
| 3129 | /* Add predefined register groups. */ |
| 3130 | reggroup_add (gdbarch, all_reggroup); |
| 3131 | reggroup_add (gdbarch, save_reggroup); |
| 3132 | reggroup_add (gdbarch, restore_reggroup); |
| 3133 | reggroup_add (gdbarch, system_reggroup); |
| 3134 | reggroup_add (gdbarch, vector_reggroup); |
| 3135 | reggroup_add (gdbarch, general_reggroup); |
| 3136 | reggroup_add (gdbarch, float_reggroup); |
| 3137 | |
| 3138 | /* Add RISC-V specific register groups. */ |
| 3139 | reggroup_add (gdbarch, csr_reggroup); |
| 3140 | } |
| 3141 | |
| 3142 | /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */ |
| 3143 | |
| 3144 | static int |
| 3145 | riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
| 3146 | { |
| 3147 | if (reg < RISCV_DWARF_REGNUM_X31) |
| 3148 | return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0); |
| 3149 | |
| 3150 | else if (reg < RISCV_DWARF_REGNUM_F31) |
| 3151 | return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0); |
| 3152 | |
| 3153 | return -1; |
| 3154 | } |
| 3155 | |
| 3156 | /* Implement the gcc_target_options method. We have to select the arch and abi |
| 3157 | from the feature info. We have enough feature info to select the abi, but |
| 3158 | not enough info for the arch given all of the possible architecture |
| 3159 | extensions. So choose reasonable defaults for now. */ |
| 3160 | |
| 3161 | static std::string |
| 3162 | riscv_gcc_target_options (struct gdbarch *gdbarch) |
| 3163 | { |
| 3164 | int isa_xlen = riscv_isa_xlen (gdbarch); |
| 3165 | int isa_flen = riscv_isa_flen (gdbarch); |
| 3166 | int abi_xlen = riscv_abi_xlen (gdbarch); |
| 3167 | int abi_flen = riscv_abi_flen (gdbarch); |
| 3168 | std::string target_options; |
| 3169 | |
| 3170 | target_options = "-march=rv"; |
| 3171 | if (isa_xlen == 8) |
| 3172 | target_options += "64"; |
| 3173 | else |
| 3174 | target_options += "32"; |
| 3175 | if (isa_flen == 8) |
| 3176 | target_options += "gc"; |
| 3177 | else if (isa_flen == 4) |
| 3178 | target_options += "imafc"; |
| 3179 | else |
| 3180 | target_options += "imac"; |
| 3181 | |
| 3182 | target_options += " -mabi="; |
| 3183 | if (abi_xlen == 8) |
| 3184 | target_options += "lp64"; |
| 3185 | else |
| 3186 | target_options += "ilp32"; |
| 3187 | if (abi_flen == 8) |
| 3188 | target_options += "d"; |
| 3189 | else if (abi_flen == 4) |
| 3190 | target_options += "f"; |
| 3191 | |
| 3192 | /* The gdb loader doesn't handle link-time relaxation relocations. */ |
| 3193 | target_options += " -mno-relax"; |
| 3194 | |
| 3195 | return target_options; |
| 3196 | } |
| 3197 | |
| 3198 | /* Call back from tdesc_use_registers, called for each unknown register |
| 3199 | found in the target description. |
| 3200 | |
| 3201 | See target-description.h (typedef tdesc_unknown_register_ftype) for a |
| 3202 | discussion of the arguments and return values. */ |
| 3203 | |
| 3204 | static int |
| 3205 | riscv_tdesc_unknown_reg (struct gdbarch *gdbarch, tdesc_feature *feature, |
| 3206 | const char *reg_name, int possible_regnum) |
| 3207 | { |
| 3208 | /* At one point in time GDB had an incorrect default target description |
| 3209 | that duplicated the fflags, frm, and fcsr registers in both the FPU |
| 3210 | and CSR register sets. |
| 3211 | |
| 3212 | Some targets (QEMU) copied these target descriptions into their source |
| 3213 | tree, and so we're currently stuck working with some targets that |
| 3214 | declare the same registers twice. |
| 3215 | |
| 3216 | There's not much we can do about this any more. Assuming the target |
| 3217 | will direct a request for either register number to the correct |
| 3218 | underlying hardware register then it doesn't matter which one GDB |
| 3219 | uses, so long as we (GDB) are consistent (so that we don't end up with |
| 3220 | invalid cache misses). |
| 3221 | |
| 3222 | As we always scan the FPU registers first, then the CSRs, if the |
| 3223 | target has included the offending registers in both sets then we will |
| 3224 | always see the FPU copies here, as the CSR versions will replace them |
| 3225 | in the register list. |
| 3226 | |
| 3227 | To prevent these duplicates showing up in any of the register list, |
| 3228 | record their register numbers here. */ |
| 3229 | if (strcmp (tdesc_feature_name (feature), riscv_freg_feature.name) == 0) |
| 3230 | { |
| 3231 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3232 | int *regnum_ptr = nullptr; |
| 3233 | |
| 3234 | if (strcmp (reg_name, "fflags") == 0) |
| 3235 | regnum_ptr = &tdep->duplicate_fflags_regnum; |
| 3236 | else if (strcmp (reg_name, "frm") == 0) |
| 3237 | regnum_ptr = &tdep->duplicate_frm_regnum; |
| 3238 | else if (strcmp (reg_name, "fcsr") == 0) |
| 3239 | regnum_ptr = &tdep->duplicate_fcsr_regnum; |
| 3240 | |
| 3241 | if (regnum_ptr != nullptr) |
| 3242 | { |
| 3243 | /* This means the register appears more than twice in the target |
| 3244 | description. Just let GDB add this as another register. |
| 3245 | We'll have duplicates in the register name list, but there's |
| 3246 | not much more we can do. */ |
| 3247 | if (*regnum_ptr != -1) |
| 3248 | return -1; |
| 3249 | |
| 3250 | /* Record the number assigned to this register, then return the |
| 3251 | number (so it actually gets assigned to this register). */ |
| 3252 | *regnum_ptr = possible_regnum; |
| 3253 | return possible_regnum; |
| 3254 | } |
| 3255 | } |
| 3256 | |
| 3257 | /* Any unknown registers in the CSR feature are recorded within a single |
| 3258 | block so we can easily identify these registers when making choices |
| 3259 | about register groups in riscv_register_reggroup_p. */ |
| 3260 | if (strcmp (tdesc_feature_name (feature), riscv_csr_feature.name) == 0) |
| 3261 | { |
| 3262 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3263 | if (tdep->unknown_csrs_first_regnum == -1) |
| 3264 | tdep->unknown_csrs_first_regnum = possible_regnum; |
| 3265 | gdb_assert (tdep->unknown_csrs_first_regnum |
| 3266 | + tdep->unknown_csrs_count == possible_regnum); |
| 3267 | tdep->unknown_csrs_count++; |
| 3268 | return possible_regnum; |
| 3269 | } |
| 3270 | |
| 3271 | /* Some other unknown register. Don't assign this a number now, it will |
| 3272 | be assigned a number automatically later by the target description |
| 3273 | handling code. */ |
| 3274 | return -1; |
| 3275 | } |
| 3276 | |
| 3277 | /* Implement the gnu_triplet_regexp method. A single compiler supports both |
| 3278 | 32-bit and 64-bit code, and may be named riscv32 or riscv64 or (not |
| 3279 | recommended) riscv. */ |
| 3280 | |
| 3281 | static const char * |
| 3282 | riscv_gnu_triplet_regexp (struct gdbarch *gdbarch) |
| 3283 | { |
| 3284 | return "riscv(32|64)?"; |
| 3285 | } |
| 3286 | |
| 3287 | /* Initialize the current architecture based on INFO. If possible, |
| 3288 | re-use an architecture from ARCHES, which is a list of |
| 3289 | architectures already created during this debugging session. |
| 3290 | |
| 3291 | Called e.g. at program startup, when reading a core file, and when |
| 3292 | reading a binary file. */ |
| 3293 | |
| 3294 | static struct gdbarch * |
| 3295 | riscv_gdbarch_init (struct gdbarch_info info, |
| 3296 | struct gdbarch_list *arches) |
| 3297 | { |
| 3298 | struct gdbarch *gdbarch; |
| 3299 | struct gdbarch_tdep *tdep; |
| 3300 | struct riscv_gdbarch_features features; |
| 3301 | const struct target_desc *tdesc = info.target_desc; |
| 3302 | |
| 3303 | /* Ensure we always have a target description. */ |
| 3304 | if (!tdesc_has_registers (tdesc)) |
| 3305 | tdesc = riscv_find_default_target_description (info); |
| 3306 | gdb_assert (tdesc); |
| 3307 | |
| 3308 | if (riscv_debug_gdbarch) |
| 3309 | fprintf_unfiltered (gdb_stdlog, "Have got a target description\n"); |
| 3310 | |
| 3311 | const struct tdesc_feature *feature_cpu |
| 3312 | = tdesc_find_feature (tdesc, riscv_xreg_feature.name); |
| 3313 | const struct tdesc_feature *feature_fpu |
| 3314 | = tdesc_find_feature (tdesc, riscv_freg_feature.name); |
| 3315 | const struct tdesc_feature *feature_virtual |
| 3316 | = tdesc_find_feature (tdesc, riscv_virtual_feature.name); |
| 3317 | const struct tdesc_feature *feature_csr |
| 3318 | = tdesc_find_feature (tdesc, riscv_csr_feature.name); |
| 3319 | |
| 3320 | if (feature_cpu == NULL) |
| 3321 | return NULL; |
| 3322 | |
| 3323 | struct tdesc_arch_data *tdesc_data = tdesc_data_alloc (); |
| 3324 | std::vector<riscv_pending_register_alias> pending_aliases; |
| 3325 | |
| 3326 | bool valid_p = riscv_check_tdesc_feature (tdesc_data, |
| 3327 | feature_cpu, feature_csr, |
| 3328 | &riscv_xreg_feature, |
| 3329 | &pending_aliases); |
| 3330 | if (valid_p) |
| 3331 | { |
| 3332 | /* Check that all of the core cpu registers have the same bitsize. */ |
| 3333 | int xlen_bitsize = tdesc_register_bitsize (feature_cpu, "pc"); |
| 3334 | |
| 3335 | for (auto &tdesc_reg : feature_cpu->registers) |
| 3336 | valid_p &= (tdesc_reg->bitsize == xlen_bitsize); |
| 3337 | |
| 3338 | if (riscv_debug_gdbarch) |
| 3339 | fprintf_filtered |
| 3340 | (gdb_stdlog, |
| 3341 | "From target-description, xlen = %d\n", xlen_bitsize); |
| 3342 | |
| 3343 | features.xlen = (xlen_bitsize / 8); |
| 3344 | } |
| 3345 | |
| 3346 | if (feature_fpu != NULL) |
| 3347 | { |
| 3348 | valid_p &= riscv_check_tdesc_feature (tdesc_data, feature_fpu, |
| 3349 | feature_csr, |
| 3350 | &riscv_freg_feature, |
| 3351 | &pending_aliases); |
| 3352 | |
| 3353 | /* Search for the first floating point register (by any alias), to |
| 3354 | determine the bitsize. */ |
| 3355 | int bitsize = -1; |
| 3356 | const auto &fp0 = riscv_freg_feature.registers[0]; |
| 3357 | |
| 3358 | for (const char *name : fp0.names) |
| 3359 | { |
| 3360 | if (tdesc_unnumbered_register (feature_fpu, name)) |
| 3361 | { |
| 3362 | bitsize = tdesc_register_bitsize (feature_fpu, name); |
| 3363 | break; |
| 3364 | } |
| 3365 | } |
| 3366 | |
| 3367 | gdb_assert (bitsize != -1); |
| 3368 | features.flen = (bitsize / 8); |
| 3369 | |
| 3370 | if (riscv_debug_gdbarch) |
| 3371 | fprintf_filtered |
| 3372 | (gdb_stdlog, |
| 3373 | "From target-description, flen = %d\n", bitsize); |
| 3374 | } |
| 3375 | else |
| 3376 | { |
| 3377 | features.flen = 0; |
| 3378 | |
| 3379 | if (riscv_debug_gdbarch) |
| 3380 | fprintf_filtered |
| 3381 | (gdb_stdlog, |
| 3382 | "No FPU in target-description, assume soft-float ABI\n"); |
| 3383 | } |
| 3384 | |
| 3385 | if (feature_virtual) |
| 3386 | riscv_check_tdesc_feature (tdesc_data, feature_virtual, feature_csr, |
| 3387 | &riscv_virtual_feature, |
| 3388 | &pending_aliases); |
| 3389 | |
| 3390 | if (feature_csr) |
| 3391 | riscv_check_tdesc_feature (tdesc_data, feature_csr, nullptr, |
| 3392 | &riscv_csr_feature, |
| 3393 | &pending_aliases); |
| 3394 | |
| 3395 | if (!valid_p) |
| 3396 | { |
| 3397 | if (riscv_debug_gdbarch) |
| 3398 | fprintf_unfiltered (gdb_stdlog, "Target description is not valid\n"); |
| 3399 | tdesc_data_cleanup (tdesc_data); |
| 3400 | return NULL; |
| 3401 | } |
| 3402 | |
| 3403 | /* Have a look at what the supplied (if any) bfd object requires of the |
| 3404 | target, then check that this matches with what the target is |
| 3405 | providing. */ |
| 3406 | struct riscv_gdbarch_features abi_features |
| 3407 | = riscv_features_from_gdbarch_info (info); |
| 3408 | /* In theory a binary compiled for RV32 could run on an RV64 target, |
| 3409 | however, this has not been tested in GDB yet, so for now we require |
| 3410 | that the requested xlen match the targets xlen. */ |
| 3411 | if (abi_features.xlen != 0 && abi_features.xlen != features.xlen) |
| 3412 | error (_("bfd requires xlen %d, but target has xlen %d"), |
| 3413 | abi_features.xlen, features.xlen); |
| 3414 | /* We do support running binaries compiled for 32-bit float on targets |
| 3415 | with 64-bit float, so we only complain if the binary requires more |
| 3416 | than the target has available. */ |
| 3417 | if (abi_features.flen > features.flen) |
| 3418 | error (_("bfd requires flen %d, but target has flen %d"), |
| 3419 | abi_features.flen, features.flen); |
| 3420 | |
| 3421 | /* If the ABI_FEATURES xlen is 0 then this indicates we got no useful abi |
| 3422 | features from the INFO object. In this case we assume that the xlen |
| 3423 | abi matches the hardware. */ |
| 3424 | if (abi_features.xlen == 0) |
| 3425 | abi_features.xlen = features.xlen; |
| 3426 | |
| 3427 | /* Find a candidate among the list of pre-declared architectures. */ |
| 3428 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
| 3429 | arches != NULL; |
| 3430 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) |
| 3431 | { |
| 3432 | /* Check that the feature set of the ARCHES matches the feature set |
| 3433 | we are looking for. If it doesn't then we can't reuse this |
| 3434 | gdbarch. */ |
| 3435 | struct gdbarch_tdep *other_tdep = gdbarch_tdep (arches->gdbarch); |
| 3436 | |
| 3437 | if (other_tdep->isa_features != features |
| 3438 | || other_tdep->abi_features != abi_features) |
| 3439 | continue; |
| 3440 | |
| 3441 | break; |
| 3442 | } |
| 3443 | |
| 3444 | if (arches != NULL) |
| 3445 | { |
| 3446 | tdesc_data_cleanup (tdesc_data); |
| 3447 | return arches->gdbarch; |
| 3448 | } |
| 3449 | |
| 3450 | /* None found, so create a new architecture from the information provided. */ |
| 3451 | tdep = new (struct gdbarch_tdep); |
| 3452 | gdbarch = gdbarch_alloc (&info, tdep); |
| 3453 | tdep->isa_features = features; |
| 3454 | tdep->abi_features = abi_features; |
| 3455 | |
| 3456 | /* Target data types. */ |
| 3457 | set_gdbarch_short_bit (gdbarch, 16); |
| 3458 | set_gdbarch_int_bit (gdbarch, 32); |
| 3459 | set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); |
| 3460 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 3461 | set_gdbarch_float_bit (gdbarch, 32); |
| 3462 | set_gdbarch_double_bit (gdbarch, 64); |
| 3463 | set_gdbarch_long_double_bit (gdbarch, 128); |
| 3464 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
| 3465 | set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); |
| 3466 | set_gdbarch_char_signed (gdbarch, 0); |
| 3467 | set_gdbarch_type_align (gdbarch, riscv_type_align); |
| 3468 | |
| 3469 | /* Information about the target architecture. */ |
| 3470 | set_gdbarch_return_value (gdbarch, riscv_return_value); |
| 3471 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc); |
| 3472 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind); |
| 3473 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
| 3474 | |
| 3475 | /* Functions to analyze frames. */ |
| 3476 | set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue); |
| 3477 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 3478 | set_gdbarch_frame_align (gdbarch, riscv_frame_align); |
| 3479 | |
| 3480 | /* Functions handling dummy frames. */ |
| 3481 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
| 3482 | set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code); |
| 3483 | set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call); |
| 3484 | |
| 3485 | /* Frame unwinders. Use DWARF debug info if available, otherwise use our own |
| 3486 | unwinder. */ |
| 3487 | dwarf2_append_unwinders (gdbarch); |
| 3488 | frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind); |
| 3489 | |
| 3490 | /* Register architecture. */ |
| 3491 | riscv_add_reggroups (gdbarch); |
| 3492 | |
| 3493 | /* Internal <-> external register number maps. */ |
| 3494 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, riscv_dwarf_reg_to_regnum); |
| 3495 | |
| 3496 | /* We reserve all possible register numbers for the known registers. |
| 3497 | This means the target description mechanism will add any target |
| 3498 | specific registers after this number. This helps make debugging GDB |
| 3499 | just a little easier. */ |
| 3500 | set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1); |
| 3501 | |
| 3502 | /* We don't have to provide the count of 0 here (its the default) but |
| 3503 | include this line to make it explicit that, right now, we don't have |
| 3504 | any pseudo registers on RISC-V. */ |
| 3505 | set_gdbarch_num_pseudo_regs (gdbarch, 0); |
| 3506 | |
| 3507 | /* Some specific register numbers GDB likes to know about. */ |
| 3508 | set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM); |
| 3509 | set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM); |
| 3510 | |
| 3511 | set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info); |
| 3512 | |
| 3513 | /* Finalise the target description registers. */ |
| 3514 | tdesc_use_registers (gdbarch, tdesc, tdesc_data, riscv_tdesc_unknown_reg); |
| 3515 | |
| 3516 | /* Override the register type callback setup by the target description |
| 3517 | mechanism. This allows us to provide special type for floating point |
| 3518 | registers. */ |
| 3519 | set_gdbarch_register_type (gdbarch, riscv_register_type); |
| 3520 | |
| 3521 | /* Override the register name callback setup by the target description |
| 3522 | mechanism. This allows us to force our preferred names for the |
| 3523 | registers, no matter what the target description called them. */ |
| 3524 | set_gdbarch_register_name (gdbarch, riscv_register_name); |
| 3525 | |
| 3526 | /* Override the register group callback setup by the target description |
| 3527 | mechanism. This allows us to force registers into the groups we |
| 3528 | want, ignoring what the target tells us. */ |
| 3529 | set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p); |
| 3530 | |
| 3531 | /* Create register aliases for alternative register names. We only |
| 3532 | create aliases for registers which were mentioned in the target |
| 3533 | description. */ |
| 3534 | for (const auto &alias : pending_aliases) |
| 3535 | alias.create (gdbarch); |
| 3536 | |
| 3537 | /* Compile command hooks. */ |
| 3538 | set_gdbarch_gcc_target_options (gdbarch, riscv_gcc_target_options); |
| 3539 | set_gdbarch_gnu_triplet_regexp (gdbarch, riscv_gnu_triplet_regexp); |
| 3540 | |
| 3541 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
| 3542 | gdbarch_init_osabi (info, gdbarch); |
| 3543 | |
| 3544 | register_riscv_ravenscar_ops (gdbarch); |
| 3545 | |
| 3546 | return gdbarch; |
| 3547 | } |
| 3548 | |
| 3549 | /* This decodes the current instruction and determines the address of the |
| 3550 | next instruction. */ |
| 3551 | |
| 3552 | static CORE_ADDR |
| 3553 | riscv_next_pc (struct regcache *regcache, CORE_ADDR pc) |
| 3554 | { |
| 3555 | struct gdbarch *gdbarch = regcache->arch (); |
| 3556 | struct riscv_insn insn; |
| 3557 | CORE_ADDR next_pc; |
| 3558 | |
| 3559 | insn.decode (gdbarch, pc); |
| 3560 | next_pc = pc + insn.length (); |
| 3561 | |
| 3562 | if (insn.opcode () == riscv_insn::JAL) |
| 3563 | next_pc = pc + insn.imm_signed (); |
| 3564 | else if (insn.opcode () == riscv_insn::JALR) |
| 3565 | { |
| 3566 | LONGEST source; |
| 3567 | regcache->cooked_read (insn.rs1 (), &source); |
| 3568 | next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1; |
| 3569 | } |
| 3570 | else if (insn.opcode () == riscv_insn::BEQ) |
| 3571 | { |
| 3572 | LONGEST src1, src2; |
| 3573 | regcache->cooked_read (insn.rs1 (), &src1); |
| 3574 | regcache->cooked_read (insn.rs2 (), &src2); |
| 3575 | if (src1 == src2) |
| 3576 | next_pc = pc + insn.imm_signed (); |
| 3577 | } |
| 3578 | else if (insn.opcode () == riscv_insn::BNE) |
| 3579 | { |
| 3580 | LONGEST src1, src2; |
| 3581 | regcache->cooked_read (insn.rs1 (), &src1); |
| 3582 | regcache->cooked_read (insn.rs2 (), &src2); |
| 3583 | if (src1 != src2) |
| 3584 | next_pc = pc + insn.imm_signed (); |
| 3585 | } |
| 3586 | else if (insn.opcode () == riscv_insn::BLT) |
| 3587 | { |
| 3588 | LONGEST src1, src2; |
| 3589 | regcache->cooked_read (insn.rs1 (), &src1); |
| 3590 | regcache->cooked_read (insn.rs2 (), &src2); |
| 3591 | if (src1 < src2) |
| 3592 | next_pc = pc + insn.imm_signed (); |
| 3593 | } |
| 3594 | else if (insn.opcode () == riscv_insn::BGE) |
| 3595 | { |
| 3596 | LONGEST src1, src2; |
| 3597 | regcache->cooked_read (insn.rs1 (), &src1); |
| 3598 | regcache->cooked_read (insn.rs2 (), &src2); |
| 3599 | if (src1 >= src2) |
| 3600 | next_pc = pc + insn.imm_signed (); |
| 3601 | } |
| 3602 | else if (insn.opcode () == riscv_insn::BLTU) |
| 3603 | { |
| 3604 | ULONGEST src1, src2; |
| 3605 | regcache->cooked_read (insn.rs1 (), &src1); |
| 3606 | regcache->cooked_read (insn.rs2 (), &src2); |
| 3607 | if (src1 < src2) |
| 3608 | next_pc = pc + insn.imm_signed (); |
| 3609 | } |
| 3610 | else if (insn.opcode () == riscv_insn::BGEU) |
| 3611 | { |
| 3612 | ULONGEST src1, src2; |
| 3613 | regcache->cooked_read (insn.rs1 (), &src1); |
| 3614 | regcache->cooked_read (insn.rs2 (), &src2); |
| 3615 | if (src1 >= src2) |
| 3616 | next_pc = pc + insn.imm_signed (); |
| 3617 | } |
| 3618 | |
| 3619 | return next_pc; |
| 3620 | } |
| 3621 | |
| 3622 | /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look |
| 3623 | for the end of the sequence and put the breakpoint there. */ |
| 3624 | |
| 3625 | static bool |
| 3626 | riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc, |
| 3627 | CORE_ADDR *next_pc) |
| 3628 | { |
| 3629 | struct gdbarch *gdbarch = regcache->arch (); |
| 3630 | struct riscv_insn insn; |
| 3631 | CORE_ADDR cur_step_pc = pc; |
| 3632 | CORE_ADDR last_addr = 0; |
| 3633 | |
| 3634 | /* First instruction has to be a load reserved. */ |
| 3635 | insn.decode (gdbarch, cur_step_pc); |
| 3636 | if (insn.opcode () != riscv_insn::LR) |
| 3637 | return false; |
| 3638 | cur_step_pc = cur_step_pc + insn.length (); |
| 3639 | |
| 3640 | /* Next instruction should be branch to exit. */ |
| 3641 | insn.decode (gdbarch, cur_step_pc); |
| 3642 | if (insn.opcode () != riscv_insn::BNE) |
| 3643 | return false; |
| 3644 | last_addr = cur_step_pc + insn.imm_signed (); |
| 3645 | cur_step_pc = cur_step_pc + insn.length (); |
| 3646 | |
| 3647 | /* Next instruction should be store conditional. */ |
| 3648 | insn.decode (gdbarch, cur_step_pc); |
| 3649 | if (insn.opcode () != riscv_insn::SC) |
| 3650 | return false; |
| 3651 | cur_step_pc = cur_step_pc + insn.length (); |
| 3652 | |
| 3653 | /* Next instruction should be branch to start. */ |
| 3654 | insn.decode (gdbarch, cur_step_pc); |
| 3655 | if (insn.opcode () != riscv_insn::BNE) |
| 3656 | return false; |
| 3657 | if (pc != (cur_step_pc + insn.imm_signed ())) |
| 3658 | return false; |
| 3659 | cur_step_pc = cur_step_pc + insn.length (); |
| 3660 | |
| 3661 | /* We should now be at the end of the sequence. */ |
| 3662 | if (cur_step_pc != last_addr) |
| 3663 | return false; |
| 3664 | |
| 3665 | *next_pc = cur_step_pc; |
| 3666 | return true; |
| 3667 | } |
| 3668 | |
| 3669 | /* This is called just before we want to resume the inferior, if we want to |
| 3670 | single-step it but there is no hardware or kernel single-step support. We |
| 3671 | find the target of the coming instruction and breakpoint it. */ |
| 3672 | |
| 3673 | std::vector<CORE_ADDR> |
| 3674 | riscv_software_single_step (struct regcache *regcache) |
| 3675 | { |
| 3676 | CORE_ADDR pc, next_pc; |
| 3677 | |
| 3678 | pc = regcache_read_pc (regcache); |
| 3679 | |
| 3680 | if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc)) |
| 3681 | return {next_pc}; |
| 3682 | |
| 3683 | next_pc = riscv_next_pc (regcache, pc); |
| 3684 | |
| 3685 | return {next_pc}; |
| 3686 | } |
| 3687 | |
| 3688 | /* Create RISC-V specific reggroups. */ |
| 3689 | |
| 3690 | static void |
| 3691 | riscv_init_reggroups () |
| 3692 | { |
| 3693 | csr_reggroup = reggroup_new ("csr", USER_REGGROUP); |
| 3694 | } |
| 3695 | |
| 3696 | void _initialize_riscv_tdep (); |
| 3697 | void |
| 3698 | _initialize_riscv_tdep () |
| 3699 | { |
| 3700 | riscv_create_csr_aliases (); |
| 3701 | riscv_init_reggroups (); |
| 3702 | |
| 3703 | gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL); |
| 3704 | |
| 3705 | /* Add root prefix command for all "set debug riscv" and "show debug |
| 3706 | riscv" commands. */ |
| 3707 | add_basic_prefix_cmd ("riscv", no_class, |
| 3708 | _("RISC-V specific debug commands."), |
| 3709 | &setdebugriscvcmdlist, "set debug riscv ", 0, |
| 3710 | &setdebuglist); |
| 3711 | |
| 3712 | add_show_prefix_cmd ("riscv", no_class, |
| 3713 | _("RISC-V specific debug commands."), |
| 3714 | &showdebugriscvcmdlist, "show debug riscv ", 0, |
| 3715 | &showdebuglist); |
| 3716 | |
| 3717 | add_setshow_zuinteger_cmd ("breakpoints", class_maintenance, |
| 3718 | &riscv_debug_breakpoints, _("\ |
| 3719 | Set riscv breakpoint debugging."), _("\ |
| 3720 | Show riscv breakpoint debugging."), _("\ |
| 3721 | When non-zero, print debugging information for the riscv specific parts\n\ |
| 3722 | of the breakpoint mechanism."), |
| 3723 | NULL, |
| 3724 | show_riscv_debug_variable, |
| 3725 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); |
| 3726 | |
| 3727 | add_setshow_zuinteger_cmd ("infcall", class_maintenance, |
| 3728 | &riscv_debug_infcall, _("\ |
| 3729 | Set riscv inferior call debugging."), _("\ |
| 3730 | Show riscv inferior call debugging."), _("\ |
| 3731 | When non-zero, print debugging information for the riscv specific parts\n\ |
| 3732 | of the inferior call mechanism."), |
| 3733 | NULL, |
| 3734 | show_riscv_debug_variable, |
| 3735 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); |
| 3736 | |
| 3737 | add_setshow_zuinteger_cmd ("unwinder", class_maintenance, |
| 3738 | &riscv_debug_unwinder, _("\ |
| 3739 | Set riscv stack unwinding debugging."), _("\ |
| 3740 | Show riscv stack unwinding debugging."), _("\ |
| 3741 | When non-zero, print debugging information for the riscv specific parts\n\ |
| 3742 | of the stack unwinding mechanism."), |
| 3743 | NULL, |
| 3744 | show_riscv_debug_variable, |
| 3745 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); |
| 3746 | |
| 3747 | add_setshow_zuinteger_cmd ("gdbarch", class_maintenance, |
| 3748 | &riscv_debug_gdbarch, _("\ |
| 3749 | Set riscv gdbarch initialisation debugging."), _("\ |
| 3750 | Show riscv gdbarch initialisation debugging."), _("\ |
| 3751 | When non-zero, print debugging information for the riscv gdbarch\n\ |
| 3752 | initialisation process."), |
| 3753 | NULL, |
| 3754 | show_riscv_debug_variable, |
| 3755 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); |
| 3756 | |
| 3757 | /* Add root prefix command for all "set riscv" and "show riscv" commands. */ |
| 3758 | add_basic_prefix_cmd ("riscv", no_class, |
| 3759 | _("RISC-V specific commands."), |
| 3760 | &setriscvcmdlist, "set riscv ", 0, &setlist); |
| 3761 | |
| 3762 | add_show_prefix_cmd ("riscv", no_class, |
| 3763 | _("RISC-V specific commands."), |
| 3764 | &showriscvcmdlist, "show riscv ", 0, &showlist); |
| 3765 | |
| 3766 | |
| 3767 | use_compressed_breakpoints = AUTO_BOOLEAN_AUTO; |
| 3768 | add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class, |
| 3769 | &use_compressed_breakpoints, |
| 3770 | _("\ |
| 3771 | Set debugger's use of compressed breakpoints."), _(" \ |
| 3772 | Show debugger's use of compressed breakpoints."), _("\ |
| 3773 | Debugging compressed code requires compressed breakpoints to be used. If\n\ |
| 3774 | left to 'auto' then gdb will use them if the existing instruction is a\n\ |
| 3775 | compressed instruction. If that doesn't give the correct behavior, then\n\ |
| 3776 | this option can be used."), |
| 3777 | NULL, |
| 3778 | show_use_compressed_breakpoints, |
| 3779 | &setriscvcmdlist, |
| 3780 | &showriscvcmdlist); |
| 3781 | } |