| 1 | /* Target-dependent code for the Renesas RL78 for GDB, the GNU debugger. |
| 2 | |
| 3 | Copyright (C) 2011-2019 Free Software Foundation, Inc. |
| 4 | |
| 5 | Contributed by Red Hat, Inc. |
| 6 | |
| 7 | This file is part of GDB. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3 of the License, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 21 | |
| 22 | #include "defs.h" |
| 23 | #include "arch-utils.h" |
| 24 | #include "prologue-value.h" |
| 25 | #include "target.h" |
| 26 | #include "regcache.h" |
| 27 | #include "opcode/rl78.h" |
| 28 | #include "dis-asm.h" |
| 29 | #include "gdbtypes.h" |
| 30 | #include "frame.h" |
| 31 | #include "frame-unwind.h" |
| 32 | #include "frame-base.h" |
| 33 | #include "value.h" |
| 34 | #include "gdbcore.h" |
| 35 | #include "dwarf2-frame.h" |
| 36 | #include "reggroups.h" |
| 37 | |
| 38 | #include "elf/rl78.h" |
| 39 | #include "elf-bfd.h" |
| 40 | |
| 41 | /* Register Banks. */ |
| 42 | |
| 43 | enum |
| 44 | { |
| 45 | RL78_BANK0 = 0, |
| 46 | RL78_BANK1 = 1, |
| 47 | RL78_BANK2 = 2, |
| 48 | RL78_BANK3 = 3, |
| 49 | RL78_NUMBANKS = 4, |
| 50 | RL78_REGS_PER_BANK = 8 |
| 51 | }; |
| 52 | |
| 53 | /* Register Numbers. */ |
| 54 | |
| 55 | enum |
| 56 | { |
| 57 | /* All general purpose registers are 8 bits wide. */ |
| 58 | RL78_RAW_BANK0_R0_REGNUM = 0, |
| 59 | RL78_RAW_BANK0_R1_REGNUM, |
| 60 | RL78_RAW_BANK0_R2_REGNUM, |
| 61 | RL78_RAW_BANK0_R3_REGNUM, |
| 62 | RL78_RAW_BANK0_R4_REGNUM, |
| 63 | RL78_RAW_BANK0_R5_REGNUM, |
| 64 | RL78_RAW_BANK0_R6_REGNUM, |
| 65 | RL78_RAW_BANK0_R7_REGNUM, |
| 66 | |
| 67 | RL78_RAW_BANK1_R0_REGNUM, |
| 68 | RL78_RAW_BANK1_R1_REGNUM, |
| 69 | RL78_RAW_BANK1_R2_REGNUM, |
| 70 | RL78_RAW_BANK1_R3_REGNUM, |
| 71 | RL78_RAW_BANK1_R4_REGNUM, |
| 72 | RL78_RAW_BANK1_R5_REGNUM, |
| 73 | RL78_RAW_BANK1_R6_REGNUM, |
| 74 | RL78_RAW_BANK1_R7_REGNUM, |
| 75 | |
| 76 | RL78_RAW_BANK2_R0_REGNUM, |
| 77 | RL78_RAW_BANK2_R1_REGNUM, |
| 78 | RL78_RAW_BANK2_R2_REGNUM, |
| 79 | RL78_RAW_BANK2_R3_REGNUM, |
| 80 | RL78_RAW_BANK2_R4_REGNUM, |
| 81 | RL78_RAW_BANK2_R5_REGNUM, |
| 82 | RL78_RAW_BANK2_R6_REGNUM, |
| 83 | RL78_RAW_BANK2_R7_REGNUM, |
| 84 | |
| 85 | RL78_RAW_BANK3_R0_REGNUM, |
| 86 | RL78_RAW_BANK3_R1_REGNUM, |
| 87 | RL78_RAW_BANK3_R2_REGNUM, |
| 88 | RL78_RAW_BANK3_R3_REGNUM, |
| 89 | RL78_RAW_BANK3_R4_REGNUM, |
| 90 | RL78_RAW_BANK3_R5_REGNUM, |
| 91 | RL78_RAW_BANK3_R6_REGNUM, |
| 92 | RL78_RAW_BANK3_R7_REGNUM, |
| 93 | |
| 94 | RL78_PSW_REGNUM, /* 8 bits */ |
| 95 | RL78_ES_REGNUM, /* 8 bits */ |
| 96 | RL78_CS_REGNUM, /* 8 bits */ |
| 97 | RL78_RAW_PC_REGNUM, /* 20 bits; we'll use 32 bits for it. */ |
| 98 | |
| 99 | /* Fixed address SFRs (some of those above are SFRs too.) */ |
| 100 | RL78_SPL_REGNUM, /* 8 bits; lower half of SP */ |
| 101 | RL78_SPH_REGNUM, /* 8 bits; upper half of SP */ |
| 102 | RL78_PMC_REGNUM, /* 8 bits */ |
| 103 | RL78_MEM_REGNUM, /* 8 bits ?? */ |
| 104 | |
| 105 | RL78_NUM_REGS, |
| 106 | |
| 107 | /* Pseudo registers. */ |
| 108 | RL78_PC_REGNUM = RL78_NUM_REGS, |
| 109 | RL78_SP_REGNUM, |
| 110 | |
| 111 | RL78_X_REGNUM, |
| 112 | RL78_A_REGNUM, |
| 113 | RL78_C_REGNUM, |
| 114 | RL78_B_REGNUM, |
| 115 | RL78_E_REGNUM, |
| 116 | RL78_D_REGNUM, |
| 117 | RL78_L_REGNUM, |
| 118 | RL78_H_REGNUM, |
| 119 | |
| 120 | RL78_AX_REGNUM, |
| 121 | RL78_BC_REGNUM, |
| 122 | RL78_DE_REGNUM, |
| 123 | RL78_HL_REGNUM, |
| 124 | |
| 125 | RL78_BANK0_R0_REGNUM, |
| 126 | RL78_BANK0_R1_REGNUM, |
| 127 | RL78_BANK0_R2_REGNUM, |
| 128 | RL78_BANK0_R3_REGNUM, |
| 129 | RL78_BANK0_R4_REGNUM, |
| 130 | RL78_BANK0_R5_REGNUM, |
| 131 | RL78_BANK0_R6_REGNUM, |
| 132 | RL78_BANK0_R7_REGNUM, |
| 133 | |
| 134 | RL78_BANK1_R0_REGNUM, |
| 135 | RL78_BANK1_R1_REGNUM, |
| 136 | RL78_BANK1_R2_REGNUM, |
| 137 | RL78_BANK1_R3_REGNUM, |
| 138 | RL78_BANK1_R4_REGNUM, |
| 139 | RL78_BANK1_R5_REGNUM, |
| 140 | RL78_BANK1_R6_REGNUM, |
| 141 | RL78_BANK1_R7_REGNUM, |
| 142 | |
| 143 | RL78_BANK2_R0_REGNUM, |
| 144 | RL78_BANK2_R1_REGNUM, |
| 145 | RL78_BANK2_R2_REGNUM, |
| 146 | RL78_BANK2_R3_REGNUM, |
| 147 | RL78_BANK2_R4_REGNUM, |
| 148 | RL78_BANK2_R5_REGNUM, |
| 149 | RL78_BANK2_R6_REGNUM, |
| 150 | RL78_BANK2_R7_REGNUM, |
| 151 | |
| 152 | RL78_BANK3_R0_REGNUM, |
| 153 | RL78_BANK3_R1_REGNUM, |
| 154 | RL78_BANK3_R2_REGNUM, |
| 155 | RL78_BANK3_R3_REGNUM, |
| 156 | RL78_BANK3_R4_REGNUM, |
| 157 | RL78_BANK3_R5_REGNUM, |
| 158 | RL78_BANK3_R6_REGNUM, |
| 159 | RL78_BANK3_R7_REGNUM, |
| 160 | |
| 161 | RL78_BANK0_RP0_REGNUM, |
| 162 | RL78_BANK0_RP1_REGNUM, |
| 163 | RL78_BANK0_RP2_REGNUM, |
| 164 | RL78_BANK0_RP3_REGNUM, |
| 165 | |
| 166 | RL78_BANK1_RP0_REGNUM, |
| 167 | RL78_BANK1_RP1_REGNUM, |
| 168 | RL78_BANK1_RP2_REGNUM, |
| 169 | RL78_BANK1_RP3_REGNUM, |
| 170 | |
| 171 | RL78_BANK2_RP0_REGNUM, |
| 172 | RL78_BANK2_RP1_REGNUM, |
| 173 | RL78_BANK2_RP2_REGNUM, |
| 174 | RL78_BANK2_RP3_REGNUM, |
| 175 | |
| 176 | RL78_BANK3_RP0_REGNUM, |
| 177 | RL78_BANK3_RP1_REGNUM, |
| 178 | RL78_BANK3_RP2_REGNUM, |
| 179 | RL78_BANK3_RP3_REGNUM, |
| 180 | |
| 181 | /* These are the same as the above 16 registers, but have |
| 182 | a pointer type for use as base registers in expression |
| 183 | evaluation. These are not user visible registers. */ |
| 184 | RL78_BANK0_RP0_PTR_REGNUM, |
| 185 | RL78_BANK0_RP1_PTR_REGNUM, |
| 186 | RL78_BANK0_RP2_PTR_REGNUM, |
| 187 | RL78_BANK0_RP3_PTR_REGNUM, |
| 188 | |
| 189 | RL78_BANK1_RP0_PTR_REGNUM, |
| 190 | RL78_BANK1_RP1_PTR_REGNUM, |
| 191 | RL78_BANK1_RP2_PTR_REGNUM, |
| 192 | RL78_BANK1_RP3_PTR_REGNUM, |
| 193 | |
| 194 | RL78_BANK2_RP0_PTR_REGNUM, |
| 195 | RL78_BANK2_RP1_PTR_REGNUM, |
| 196 | RL78_BANK2_RP2_PTR_REGNUM, |
| 197 | RL78_BANK2_RP3_PTR_REGNUM, |
| 198 | |
| 199 | RL78_BANK3_RP0_PTR_REGNUM, |
| 200 | RL78_BANK3_RP1_PTR_REGNUM, |
| 201 | RL78_BANK3_RP2_PTR_REGNUM, |
| 202 | RL78_BANK3_RP3_PTR_REGNUM, |
| 203 | |
| 204 | RL78_NUM_TOTAL_REGS, |
| 205 | RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS |
| 206 | }; |
| 207 | |
| 208 | #define RL78_SP_ADDR 0xffff8 |
| 209 | |
| 210 | /* Architecture specific data. */ |
| 211 | |
| 212 | struct gdbarch_tdep |
| 213 | { |
| 214 | /* The ELF header flags specify the multilib used. */ |
| 215 | int elf_flags; |
| 216 | |
| 217 | struct type *rl78_void, |
| 218 | *rl78_uint8, |
| 219 | *rl78_int8, |
| 220 | *rl78_uint16, |
| 221 | *rl78_int16, |
| 222 | *rl78_uint32, |
| 223 | *rl78_int32, |
| 224 | *rl78_data_pointer, |
| 225 | *rl78_code_pointer, |
| 226 | *rl78_psw_type; |
| 227 | }; |
| 228 | |
| 229 | /* This structure holds the results of a prologue analysis. */ |
| 230 | |
| 231 | struct rl78_prologue |
| 232 | { |
| 233 | /* The offset from the frame base to the stack pointer --- always |
| 234 | zero or negative. |
| 235 | |
| 236 | Calling this a "size" is a bit misleading, but given that the |
| 237 | stack grows downwards, using offsets for everything keeps one |
| 238 | from going completely sign-crazy: you never change anything's |
| 239 | sign for an ADD instruction; always change the second operand's |
| 240 | sign for a SUB instruction; and everything takes care of |
| 241 | itself. */ |
| 242 | int frame_size; |
| 243 | |
| 244 | /* Non-zero if this function has initialized the frame pointer from |
| 245 | the stack pointer, zero otherwise. */ |
| 246 | int has_frame_ptr; |
| 247 | |
| 248 | /* If has_frame_ptr is non-zero, this is the offset from the frame |
| 249 | base to where the frame pointer points. This is always zero or |
| 250 | negative. */ |
| 251 | int frame_ptr_offset; |
| 252 | |
| 253 | /* The address of the first instruction at which the frame has been |
| 254 | set up and the arguments are where the debug info says they are |
| 255 | --- as best as we can tell. */ |
| 256 | CORE_ADDR prologue_end; |
| 257 | |
| 258 | /* reg_offset[R] is the offset from the CFA at which register R is |
| 259 | saved, or 1 if register R has not been saved. (Real values are |
| 260 | always zero or negative.) */ |
| 261 | int reg_offset[RL78_NUM_TOTAL_REGS]; |
| 262 | }; |
| 263 | |
| 264 | /* Construct type for PSW register. */ |
| 265 | |
| 266 | static struct type * |
| 267 | rl78_psw_type (struct gdbarch *gdbarch) |
| 268 | { |
| 269 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 270 | |
| 271 | if (tdep->rl78_psw_type == NULL) |
| 272 | { |
| 273 | tdep->rl78_psw_type = arch_flags_type (gdbarch, |
| 274 | "builtin_type_rl78_psw", 8); |
| 275 | append_flags_type_flag (tdep->rl78_psw_type, 0, "CY"); |
| 276 | append_flags_type_flag (tdep->rl78_psw_type, 1, "ISP0"); |
| 277 | append_flags_type_flag (tdep->rl78_psw_type, 2, "ISP1"); |
| 278 | append_flags_type_flag (tdep->rl78_psw_type, 3, "RBS0"); |
| 279 | append_flags_type_flag (tdep->rl78_psw_type, 4, "AC"); |
| 280 | append_flags_type_flag (tdep->rl78_psw_type, 5, "RBS1"); |
| 281 | append_flags_type_flag (tdep->rl78_psw_type, 6, "Z"); |
| 282 | append_flags_type_flag (tdep->rl78_psw_type, 7, "IE"); |
| 283 | } |
| 284 | |
| 285 | return tdep->rl78_psw_type; |
| 286 | } |
| 287 | |
| 288 | /* Implement the "register_type" gdbarch method. */ |
| 289 | |
| 290 | static struct type * |
| 291 | rl78_register_type (struct gdbarch *gdbarch, int reg_nr) |
| 292 | { |
| 293 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 294 | |
| 295 | if (reg_nr == RL78_PC_REGNUM) |
| 296 | return tdep->rl78_code_pointer; |
| 297 | else if (reg_nr == RL78_RAW_PC_REGNUM) |
| 298 | return tdep->rl78_uint32; |
| 299 | else if (reg_nr == RL78_PSW_REGNUM) |
| 300 | return rl78_psw_type (gdbarch); |
| 301 | else if (reg_nr <= RL78_MEM_REGNUM |
| 302 | || (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM) |
| 303 | || (RL78_BANK0_R0_REGNUM <= reg_nr |
| 304 | && reg_nr <= RL78_BANK3_R7_REGNUM)) |
| 305 | return tdep->rl78_int8; |
| 306 | else if (reg_nr == RL78_SP_REGNUM |
| 307 | || (RL78_BANK0_RP0_PTR_REGNUM <= reg_nr |
| 308 | && reg_nr <= RL78_BANK3_RP3_PTR_REGNUM)) |
| 309 | return tdep->rl78_data_pointer; |
| 310 | else |
| 311 | return tdep->rl78_int16; |
| 312 | } |
| 313 | |
| 314 | /* Implement the "register_name" gdbarch method. */ |
| 315 | |
| 316 | static const char * |
| 317 | rl78_register_name (struct gdbarch *gdbarch, int regnr) |
| 318 | { |
| 319 | static const char *const reg_names[] = |
| 320 | { |
| 321 | "", /* bank0_r0 */ |
| 322 | "", /* bank0_r1 */ |
| 323 | "", /* bank0_r2 */ |
| 324 | "", /* bank0_r3 */ |
| 325 | "", /* bank0_r4 */ |
| 326 | "", /* bank0_r5 */ |
| 327 | "", /* bank0_r6 */ |
| 328 | "", /* bank0_r7 */ |
| 329 | |
| 330 | "", /* bank1_r0 */ |
| 331 | "", /* bank1_r1 */ |
| 332 | "", /* bank1_r2 */ |
| 333 | "", /* bank1_r3 */ |
| 334 | "", /* bank1_r4 */ |
| 335 | "", /* bank1_r5 */ |
| 336 | "", /* bank1_r6 */ |
| 337 | "", /* bank1_r7 */ |
| 338 | |
| 339 | "", /* bank2_r0 */ |
| 340 | "", /* bank2_r1 */ |
| 341 | "", /* bank2_r2 */ |
| 342 | "", /* bank2_r3 */ |
| 343 | "", /* bank2_r4 */ |
| 344 | "", /* bank2_r5 */ |
| 345 | "", /* bank2_r6 */ |
| 346 | "", /* bank2_r7 */ |
| 347 | |
| 348 | "", /* bank3_r0 */ |
| 349 | "", /* bank3_r1 */ |
| 350 | "", /* bank3_r2 */ |
| 351 | "", /* bank3_r3 */ |
| 352 | "", /* bank3_r4 */ |
| 353 | "", /* bank3_r5 */ |
| 354 | "", /* bank3_r6 */ |
| 355 | "", /* bank3_r7 */ |
| 356 | |
| 357 | "psw", |
| 358 | "es", |
| 359 | "cs", |
| 360 | "", |
| 361 | |
| 362 | "", /* spl */ |
| 363 | "", /* sph */ |
| 364 | "pmc", |
| 365 | "mem", |
| 366 | |
| 367 | "pc", |
| 368 | "sp", |
| 369 | |
| 370 | "x", |
| 371 | "a", |
| 372 | "c", |
| 373 | "b", |
| 374 | "e", |
| 375 | "d", |
| 376 | "l", |
| 377 | "h", |
| 378 | |
| 379 | "ax", |
| 380 | "bc", |
| 381 | "de", |
| 382 | "hl", |
| 383 | |
| 384 | "bank0_r0", |
| 385 | "bank0_r1", |
| 386 | "bank0_r2", |
| 387 | "bank0_r3", |
| 388 | "bank0_r4", |
| 389 | "bank0_r5", |
| 390 | "bank0_r6", |
| 391 | "bank0_r7", |
| 392 | |
| 393 | "bank1_r0", |
| 394 | "bank1_r1", |
| 395 | "bank1_r2", |
| 396 | "bank1_r3", |
| 397 | "bank1_r4", |
| 398 | "bank1_r5", |
| 399 | "bank1_r6", |
| 400 | "bank1_r7", |
| 401 | |
| 402 | "bank2_r0", |
| 403 | "bank2_r1", |
| 404 | "bank2_r2", |
| 405 | "bank2_r3", |
| 406 | "bank2_r4", |
| 407 | "bank2_r5", |
| 408 | "bank2_r6", |
| 409 | "bank2_r7", |
| 410 | |
| 411 | "bank3_r0", |
| 412 | "bank3_r1", |
| 413 | "bank3_r2", |
| 414 | "bank3_r3", |
| 415 | "bank3_r4", |
| 416 | "bank3_r5", |
| 417 | "bank3_r6", |
| 418 | "bank3_r7", |
| 419 | |
| 420 | "bank0_rp0", |
| 421 | "bank0_rp1", |
| 422 | "bank0_rp2", |
| 423 | "bank0_rp3", |
| 424 | |
| 425 | "bank1_rp0", |
| 426 | "bank1_rp1", |
| 427 | "bank1_rp2", |
| 428 | "bank1_rp3", |
| 429 | |
| 430 | "bank2_rp0", |
| 431 | "bank2_rp1", |
| 432 | "bank2_rp2", |
| 433 | "bank2_rp3", |
| 434 | |
| 435 | "bank3_rp0", |
| 436 | "bank3_rp1", |
| 437 | "bank3_rp2", |
| 438 | "bank3_rp3", |
| 439 | |
| 440 | /* The 16 register slots would be named |
| 441 | bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't |
| 442 | want these to be user visible registers. */ |
| 443 | "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "" |
| 444 | }; |
| 445 | |
| 446 | return reg_names[regnr]; |
| 447 | } |
| 448 | |
| 449 | /* Implement the "register_name" gdbarch method for the g10 variant. */ |
| 450 | |
| 451 | static const char * |
| 452 | rl78_g10_register_name (struct gdbarch *gdbarch, int regnr) |
| 453 | { |
| 454 | static const char *const reg_names[] = |
| 455 | { |
| 456 | "", /* bank0_r0 */ |
| 457 | "", /* bank0_r1 */ |
| 458 | "", /* bank0_r2 */ |
| 459 | "", /* bank0_r3 */ |
| 460 | "", /* bank0_r4 */ |
| 461 | "", /* bank0_r5 */ |
| 462 | "", /* bank0_r6 */ |
| 463 | "", /* bank0_r7 */ |
| 464 | |
| 465 | "", /* bank1_r0 */ |
| 466 | "", /* bank1_r1 */ |
| 467 | "", /* bank1_r2 */ |
| 468 | "", /* bank1_r3 */ |
| 469 | "", /* bank1_r4 */ |
| 470 | "", /* bank1_r5 */ |
| 471 | "", /* bank1_r6 */ |
| 472 | "", /* bank1_r7 */ |
| 473 | |
| 474 | "", /* bank2_r0 */ |
| 475 | "", /* bank2_r1 */ |
| 476 | "", /* bank2_r2 */ |
| 477 | "", /* bank2_r3 */ |
| 478 | "", /* bank2_r4 */ |
| 479 | "", /* bank2_r5 */ |
| 480 | "", /* bank2_r6 */ |
| 481 | "", /* bank2_r7 */ |
| 482 | |
| 483 | "", /* bank3_r0 */ |
| 484 | "", /* bank3_r1 */ |
| 485 | "", /* bank3_r2 */ |
| 486 | "", /* bank3_r3 */ |
| 487 | "", /* bank3_r4 */ |
| 488 | "", /* bank3_r5 */ |
| 489 | "", /* bank3_r6 */ |
| 490 | "", /* bank3_r7 */ |
| 491 | |
| 492 | "psw", |
| 493 | "es", |
| 494 | "cs", |
| 495 | "", |
| 496 | |
| 497 | "", /* spl */ |
| 498 | "", /* sph */ |
| 499 | "pmc", |
| 500 | "mem", |
| 501 | |
| 502 | "pc", |
| 503 | "sp", |
| 504 | |
| 505 | "x", |
| 506 | "a", |
| 507 | "c", |
| 508 | "b", |
| 509 | "e", |
| 510 | "d", |
| 511 | "l", |
| 512 | "h", |
| 513 | |
| 514 | "ax", |
| 515 | "bc", |
| 516 | "de", |
| 517 | "hl", |
| 518 | |
| 519 | "bank0_r0", |
| 520 | "bank0_r1", |
| 521 | "bank0_r2", |
| 522 | "bank0_r3", |
| 523 | "bank0_r4", |
| 524 | "bank0_r5", |
| 525 | "bank0_r6", |
| 526 | "bank0_r7", |
| 527 | |
| 528 | "", |
| 529 | "", |
| 530 | "", |
| 531 | "", |
| 532 | "", |
| 533 | "", |
| 534 | "", |
| 535 | "", |
| 536 | |
| 537 | "", |
| 538 | "", |
| 539 | "", |
| 540 | "", |
| 541 | "", |
| 542 | "", |
| 543 | "", |
| 544 | "", |
| 545 | |
| 546 | "", |
| 547 | "", |
| 548 | "", |
| 549 | "", |
| 550 | "", |
| 551 | "", |
| 552 | "", |
| 553 | "", |
| 554 | |
| 555 | "bank0_rp0", |
| 556 | "bank0_rp1", |
| 557 | "bank0_rp2", |
| 558 | "bank0_rp3", |
| 559 | |
| 560 | "", |
| 561 | "", |
| 562 | "", |
| 563 | "", |
| 564 | |
| 565 | "", |
| 566 | "", |
| 567 | "", |
| 568 | "", |
| 569 | |
| 570 | "", |
| 571 | "", |
| 572 | "", |
| 573 | "", |
| 574 | |
| 575 | /* The 16 register slots would be named |
| 576 | bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't |
| 577 | want these to be user visible registers. */ |
| 578 | "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "" |
| 579 | }; |
| 580 | |
| 581 | return reg_names[regnr]; |
| 582 | } |
| 583 | |
| 584 | /* Implement the "register_reggroup_p" gdbarch method. */ |
| 585 | |
| 586 | static int |
| 587 | rl78_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
| 588 | struct reggroup *group) |
| 589 | { |
| 590 | if (group == all_reggroup) |
| 591 | return 1; |
| 592 | |
| 593 | /* All other registers are saved and restored. */ |
| 594 | if (group == save_reggroup || group == restore_reggroup) |
| 595 | { |
| 596 | if ((regnum < RL78_NUM_REGS |
| 597 | && regnum != RL78_SPL_REGNUM |
| 598 | && regnum != RL78_SPH_REGNUM |
| 599 | && regnum != RL78_RAW_PC_REGNUM) |
| 600 | || regnum == RL78_SP_REGNUM |
| 601 | || regnum == RL78_PC_REGNUM) |
| 602 | return 1; |
| 603 | else |
| 604 | return 0; |
| 605 | } |
| 606 | |
| 607 | if ((RL78_BANK0_R0_REGNUM <= regnum && regnum <= RL78_BANK3_R7_REGNUM) |
| 608 | || regnum == RL78_ES_REGNUM |
| 609 | || regnum == RL78_CS_REGNUM |
| 610 | || regnum == RL78_SPL_REGNUM |
| 611 | || regnum == RL78_SPH_REGNUM |
| 612 | || regnum == RL78_PMC_REGNUM |
| 613 | || regnum == RL78_MEM_REGNUM |
| 614 | || regnum == RL78_RAW_PC_REGNUM |
| 615 | || (RL78_BANK0_RP0_REGNUM <= regnum && regnum <= RL78_BANK3_RP3_REGNUM)) |
| 616 | return group == system_reggroup; |
| 617 | |
| 618 | return group == general_reggroup; |
| 619 | } |
| 620 | |
| 621 | /* Strip bits to form an instruction address. (When fetching a |
| 622 | 32-bit address from the stack, the high eight bits are garbage. |
| 623 | This function strips off those unused bits.) */ |
| 624 | |
| 625 | static CORE_ADDR |
| 626 | rl78_make_instruction_address (CORE_ADDR addr) |
| 627 | { |
| 628 | return addr & 0xffffff; |
| 629 | } |
| 630 | |
| 631 | /* Set / clear bits necessary to make a data address. */ |
| 632 | |
| 633 | static CORE_ADDR |
| 634 | rl78_make_data_address (CORE_ADDR addr) |
| 635 | { |
| 636 | return (addr & 0xffff) | 0xf0000; |
| 637 | } |
| 638 | |
| 639 | /* Implement the "pseudo_register_read" gdbarch method. */ |
| 640 | |
| 641 | static enum register_status |
| 642 | rl78_pseudo_register_read (struct gdbarch *gdbarch, |
| 643 | readable_regcache *regcache, |
| 644 | int reg, gdb_byte *buffer) |
| 645 | { |
| 646 | enum register_status status; |
| 647 | |
| 648 | if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM) |
| 649 | { |
| 650 | int raw_regnum = RL78_RAW_BANK0_R0_REGNUM |
| 651 | + (reg - RL78_BANK0_R0_REGNUM); |
| 652 | |
| 653 | status = regcache->raw_read (raw_regnum, buffer); |
| 654 | } |
| 655 | else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM) |
| 656 | { |
| 657 | int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM) |
| 658 | + RL78_RAW_BANK0_R0_REGNUM; |
| 659 | |
| 660 | status = regcache->raw_read (raw_regnum, buffer); |
| 661 | if (status == REG_VALID) |
| 662 | status = regcache->raw_read (raw_regnum + 1, buffer + 1); |
| 663 | } |
| 664 | else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM) |
| 665 | { |
| 666 | int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM) |
| 667 | + RL78_RAW_BANK0_R0_REGNUM; |
| 668 | |
| 669 | status = regcache->raw_read (raw_regnum, buffer); |
| 670 | if (status == REG_VALID) |
| 671 | status = regcache->raw_read (raw_regnum + 1, buffer + 1); |
| 672 | } |
| 673 | else if (reg == RL78_SP_REGNUM) |
| 674 | { |
| 675 | status = regcache->raw_read (RL78_SPL_REGNUM, buffer); |
| 676 | if (status == REG_VALID) |
| 677 | status = regcache->raw_read (RL78_SPH_REGNUM, buffer + 1); |
| 678 | } |
| 679 | else if (reg == RL78_PC_REGNUM) |
| 680 | { |
| 681 | gdb_byte rawbuf[4]; |
| 682 | |
| 683 | status = regcache->raw_read (RL78_RAW_PC_REGNUM, rawbuf); |
| 684 | memcpy (buffer, rawbuf, 3); |
| 685 | } |
| 686 | else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM) |
| 687 | { |
| 688 | ULONGEST psw; |
| 689 | |
| 690 | status = regcache->raw_read (RL78_PSW_REGNUM, &psw); |
| 691 | if (status == REG_VALID) |
| 692 | { |
| 693 | /* RSB0 is at bit 3; RSBS1 is at bit 5. */ |
| 694 | int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1); |
| 695 | int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK |
| 696 | + (reg - RL78_X_REGNUM); |
| 697 | status = regcache->raw_read (raw_regnum, buffer); |
| 698 | } |
| 699 | } |
| 700 | else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM) |
| 701 | { |
| 702 | ULONGEST psw; |
| 703 | |
| 704 | status = regcache->raw_read (RL78_PSW_REGNUM, &psw); |
| 705 | if (status == REG_VALID) |
| 706 | { |
| 707 | /* RSB0 is at bit 3; RSBS1 is at bit 5. */ |
| 708 | int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1); |
| 709 | int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK |
| 710 | + 2 * (reg - RL78_AX_REGNUM); |
| 711 | status = regcache->raw_read (raw_regnum, buffer); |
| 712 | if (status == REG_VALID) |
| 713 | status = regcache->raw_read (raw_regnum + 1, buffer + 1); |
| 714 | } |
| 715 | } |
| 716 | else |
| 717 | gdb_assert_not_reached ("invalid pseudo register number"); |
| 718 | return status; |
| 719 | } |
| 720 | |
| 721 | /* Implement the "pseudo_register_write" gdbarch method. */ |
| 722 | |
| 723 | static void |
| 724 | rl78_pseudo_register_write (struct gdbarch *gdbarch, |
| 725 | struct regcache *regcache, |
| 726 | int reg, const gdb_byte *buffer) |
| 727 | { |
| 728 | if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM) |
| 729 | { |
| 730 | int raw_regnum = RL78_RAW_BANK0_R0_REGNUM |
| 731 | + (reg - RL78_BANK0_R0_REGNUM); |
| 732 | |
| 733 | regcache->raw_write (raw_regnum, buffer); |
| 734 | } |
| 735 | else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM) |
| 736 | { |
| 737 | int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM) |
| 738 | + RL78_RAW_BANK0_R0_REGNUM; |
| 739 | |
| 740 | regcache->raw_write (raw_regnum, buffer); |
| 741 | regcache->raw_write (raw_regnum + 1, buffer + 1); |
| 742 | } |
| 743 | else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM) |
| 744 | { |
| 745 | int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM) |
| 746 | + RL78_RAW_BANK0_R0_REGNUM; |
| 747 | |
| 748 | regcache->raw_write (raw_regnum, buffer); |
| 749 | regcache->raw_write (raw_regnum + 1, buffer + 1); |
| 750 | } |
| 751 | else if (reg == RL78_SP_REGNUM) |
| 752 | { |
| 753 | regcache->raw_write (RL78_SPL_REGNUM, buffer); |
| 754 | regcache->raw_write (RL78_SPH_REGNUM, buffer + 1); |
| 755 | } |
| 756 | else if (reg == RL78_PC_REGNUM) |
| 757 | { |
| 758 | gdb_byte rawbuf[4]; |
| 759 | |
| 760 | memcpy (rawbuf, buffer, 3); |
| 761 | rawbuf[3] = 0; |
| 762 | regcache->raw_write (RL78_RAW_PC_REGNUM, rawbuf); |
| 763 | } |
| 764 | else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM) |
| 765 | { |
| 766 | ULONGEST psw; |
| 767 | int bank; |
| 768 | int raw_regnum; |
| 769 | |
| 770 | regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw); |
| 771 | bank = ((psw >> 3) & 1) | ((psw >> 4) & 1); |
| 772 | /* RSB0 is at bit 3; RSBS1 is at bit 5. */ |
| 773 | raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK |
| 774 | + (reg - RL78_X_REGNUM); |
| 775 | regcache->raw_write (raw_regnum, buffer); |
| 776 | } |
| 777 | else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM) |
| 778 | { |
| 779 | ULONGEST psw; |
| 780 | int bank, raw_regnum; |
| 781 | |
| 782 | regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw); |
| 783 | bank = ((psw >> 3) & 1) | ((psw >> 4) & 1); |
| 784 | /* RSB0 is at bit 3; RSBS1 is at bit 5. */ |
| 785 | raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK |
| 786 | + 2 * (reg - RL78_AX_REGNUM); |
| 787 | regcache->raw_write (raw_regnum, buffer); |
| 788 | regcache->raw_write (raw_regnum + 1, buffer + 1); |
| 789 | } |
| 790 | else |
| 791 | gdb_assert_not_reached ("invalid pseudo register number"); |
| 792 | } |
| 793 | |
| 794 | /* The documented BRK instruction is actually a two byte sequence, |
| 795 | {0x61, 0xcc}, but instructions may be as short as one byte. |
| 796 | Correspondence with Renesas revealed that the one byte sequence |
| 797 | 0xff is used when a one byte breakpoint instruction is required. */ |
| 798 | constexpr gdb_byte rl78_break_insn[] = { 0xff }; |
| 799 | |
| 800 | typedef BP_MANIPULATION (rl78_break_insn) rl78_breakpoint; |
| 801 | |
| 802 | /* Define a "handle" struct for fetching the next opcode. */ |
| 803 | |
| 804 | struct rl78_get_opcode_byte_handle |
| 805 | { |
| 806 | CORE_ADDR pc; |
| 807 | }; |
| 808 | |
| 809 | static int |
| 810 | opc_reg_to_gdb_regnum (int opcreg) |
| 811 | { |
| 812 | switch (opcreg) |
| 813 | { |
| 814 | case RL78_Reg_X: |
| 815 | return RL78_X_REGNUM; |
| 816 | case RL78_Reg_A: |
| 817 | return RL78_A_REGNUM; |
| 818 | case RL78_Reg_C: |
| 819 | return RL78_C_REGNUM; |
| 820 | case RL78_Reg_B: |
| 821 | return RL78_B_REGNUM; |
| 822 | case RL78_Reg_E: |
| 823 | return RL78_E_REGNUM; |
| 824 | case RL78_Reg_D: |
| 825 | return RL78_D_REGNUM; |
| 826 | case RL78_Reg_L: |
| 827 | return RL78_L_REGNUM; |
| 828 | case RL78_Reg_H: |
| 829 | return RL78_H_REGNUM; |
| 830 | case RL78_Reg_AX: |
| 831 | return RL78_AX_REGNUM; |
| 832 | case RL78_Reg_BC: |
| 833 | return RL78_BC_REGNUM; |
| 834 | case RL78_Reg_DE: |
| 835 | return RL78_DE_REGNUM; |
| 836 | case RL78_Reg_HL: |
| 837 | return RL78_HL_REGNUM; |
| 838 | case RL78_Reg_SP: |
| 839 | return RL78_SP_REGNUM; |
| 840 | case RL78_Reg_PSW: |
| 841 | return RL78_PSW_REGNUM; |
| 842 | case RL78_Reg_CS: |
| 843 | return RL78_CS_REGNUM; |
| 844 | case RL78_Reg_ES: |
| 845 | return RL78_ES_REGNUM; |
| 846 | case RL78_Reg_PMC: |
| 847 | return RL78_PMC_REGNUM; |
| 848 | case RL78_Reg_MEM: |
| 849 | return RL78_MEM_REGNUM; |
| 850 | default: |
| 851 | internal_error (__FILE__, __LINE__, |
| 852 | _("Undefined mapping for opc reg %d"), |
| 853 | opcreg); |
| 854 | } |
| 855 | |
| 856 | /* Not reached. */ |
| 857 | return 0; |
| 858 | } |
| 859 | |
| 860 | /* Fetch a byte on behalf of the opcode decoder. HANDLE contains |
| 861 | the memory address of the next byte to fetch. If successful, |
| 862 | the address in the handle is updated and the byte fetched is |
| 863 | returned as the value of the function. If not successful, -1 |
| 864 | is returned. */ |
| 865 | |
| 866 | static int |
| 867 | rl78_get_opcode_byte (void *handle) |
| 868 | { |
| 869 | struct rl78_get_opcode_byte_handle *opcdata |
| 870 | = (struct rl78_get_opcode_byte_handle *) handle; |
| 871 | int status; |
| 872 | gdb_byte byte; |
| 873 | |
| 874 | status = target_read_memory (opcdata->pc, &byte, 1); |
| 875 | if (status == 0) |
| 876 | { |
| 877 | opcdata->pc += 1; |
| 878 | return byte; |
| 879 | } |
| 880 | else |
| 881 | return -1; |
| 882 | } |
| 883 | |
| 884 | /* Function for finding saved registers in a 'struct pv_area'; this |
| 885 | function is passed to pv_area::scan. |
| 886 | |
| 887 | If VALUE is a saved register, ADDR says it was saved at a constant |
| 888 | offset from the frame base, and SIZE indicates that the whole |
| 889 | register was saved, record its offset. */ |
| 890 | |
| 891 | static void |
| 892 | check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size, |
| 893 | pv_t value) |
| 894 | { |
| 895 | struct rl78_prologue *result = (struct rl78_prologue *) result_untyped; |
| 896 | |
| 897 | if (value.kind == pvk_register |
| 898 | && value.k == 0 |
| 899 | && pv_is_register (addr, RL78_SP_REGNUM) |
| 900 | && size == register_size (target_gdbarch (), value.reg)) |
| 901 | result->reg_offset[value.reg] = addr.k; |
| 902 | } |
| 903 | |
| 904 | /* Analyze a prologue starting at START_PC, going no further than |
| 905 | LIMIT_PC. Fill in RESULT as appropriate. */ |
| 906 | |
| 907 | static void |
| 908 | rl78_analyze_prologue (CORE_ADDR start_pc, |
| 909 | CORE_ADDR limit_pc, struct rl78_prologue *result) |
| 910 | { |
| 911 | CORE_ADDR pc, next_pc; |
| 912 | int rn; |
| 913 | pv_t reg[RL78_NUM_TOTAL_REGS]; |
| 914 | CORE_ADDR after_last_frame_setup_insn = start_pc; |
| 915 | int bank = 0; |
| 916 | |
| 917 | memset (result, 0, sizeof (*result)); |
| 918 | |
| 919 | for (rn = 0; rn < RL78_NUM_TOTAL_REGS; rn++) |
| 920 | { |
| 921 | reg[rn] = pv_register (rn, 0); |
| 922 | result->reg_offset[rn] = 1; |
| 923 | } |
| 924 | |
| 925 | pv_area stack (RL78_SP_REGNUM, gdbarch_addr_bit (target_gdbarch ())); |
| 926 | |
| 927 | /* The call instruction has saved the return address on the stack. */ |
| 928 | reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -4); |
| 929 | stack.store (reg[RL78_SP_REGNUM], 4, reg[RL78_PC_REGNUM]); |
| 930 | |
| 931 | pc = start_pc; |
| 932 | while (pc < limit_pc) |
| 933 | { |
| 934 | int bytes_read; |
| 935 | struct rl78_get_opcode_byte_handle opcode_handle; |
| 936 | RL78_Opcode_Decoded opc; |
| 937 | |
| 938 | opcode_handle.pc = pc; |
| 939 | bytes_read = rl78_decode_opcode (pc, &opc, rl78_get_opcode_byte, |
| 940 | &opcode_handle, RL78_ISA_DEFAULT); |
| 941 | next_pc = pc + bytes_read; |
| 942 | |
| 943 | if (opc.id == RLO_sel) |
| 944 | { |
| 945 | bank = opc.op[1].addend; |
| 946 | } |
| 947 | else if (opc.id == RLO_mov |
| 948 | && opc.op[0].type == RL78_Operand_PreDec |
| 949 | && opc.op[0].reg == RL78_Reg_SP |
| 950 | && opc.op[1].type == RL78_Operand_Register) |
| 951 | { |
| 952 | int rsrc = (bank * RL78_REGS_PER_BANK) |
| 953 | + 2 * (opc.op[1].reg - RL78_Reg_AX); |
| 954 | |
| 955 | reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1); |
| 956 | stack.store (reg[RL78_SP_REGNUM], 1, reg[rsrc]); |
| 957 | reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1); |
| 958 | stack.store (reg[RL78_SP_REGNUM], 1, reg[rsrc + 1]); |
| 959 | after_last_frame_setup_insn = next_pc; |
| 960 | } |
| 961 | else if (opc.id == RLO_sub |
| 962 | && opc.op[0].type == RL78_Operand_Register |
| 963 | && opc.op[0].reg == RL78_Reg_SP |
| 964 | && opc.op[1].type == RL78_Operand_Immediate) |
| 965 | { |
| 966 | int addend = opc.op[1].addend; |
| 967 | |
| 968 | reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], |
| 969 | -addend); |
| 970 | after_last_frame_setup_insn = next_pc; |
| 971 | } |
| 972 | else if (opc.id == RLO_mov |
| 973 | && opc.size == RL78_Word |
| 974 | && opc.op[0].type == RL78_Operand_Register |
| 975 | && opc.op[1].type == RL78_Operand_Indirect |
| 976 | && opc.op[1].addend == RL78_SP_ADDR) |
| 977 | { |
| 978 | reg[opc_reg_to_gdb_regnum (opc.op[0].reg)] |
| 979 | = reg[RL78_SP_REGNUM]; |
| 980 | } |
| 981 | else if (opc.id == RLO_sub |
| 982 | && opc.size == RL78_Word |
| 983 | && opc.op[0].type == RL78_Operand_Register |
| 984 | && opc.op[1].type == RL78_Operand_Immediate) |
| 985 | { |
| 986 | int addend = opc.op[1].addend; |
| 987 | int regnum = opc_reg_to_gdb_regnum (opc.op[0].reg); |
| 988 | |
| 989 | reg[regnum] = pv_add_constant (reg[regnum], -addend); |
| 990 | } |
| 991 | else if (opc.id == RLO_mov |
| 992 | && opc.size == RL78_Word |
| 993 | && opc.op[0].type == RL78_Operand_Indirect |
| 994 | && opc.op[0].addend == RL78_SP_ADDR |
| 995 | && opc.op[1].type == RL78_Operand_Register) |
| 996 | { |
| 997 | reg[RL78_SP_REGNUM] |
| 998 | = reg[opc_reg_to_gdb_regnum (opc.op[1].reg)]; |
| 999 | after_last_frame_setup_insn = next_pc; |
| 1000 | } |
| 1001 | else |
| 1002 | { |
| 1003 | /* Terminate the prologue scan. */ |
| 1004 | break; |
| 1005 | } |
| 1006 | |
| 1007 | pc = next_pc; |
| 1008 | } |
| 1009 | |
| 1010 | /* Is the frame size (offset, really) a known constant? */ |
| 1011 | if (pv_is_register (reg[RL78_SP_REGNUM], RL78_SP_REGNUM)) |
| 1012 | result->frame_size = reg[RL78_SP_REGNUM].k; |
| 1013 | |
| 1014 | /* Record where all the registers were saved. */ |
| 1015 | stack.scan (check_for_saved, (void *) result); |
| 1016 | |
| 1017 | result->prologue_end = after_last_frame_setup_insn; |
| 1018 | } |
| 1019 | |
| 1020 | /* Implement the "addr_bits_remove" gdbarch method. */ |
| 1021 | |
| 1022 | static CORE_ADDR |
| 1023 | rl78_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 1024 | { |
| 1025 | return addr & 0xffffff; |
| 1026 | } |
| 1027 | |
| 1028 | /* Implement the "address_to_pointer" gdbarch method. */ |
| 1029 | |
| 1030 | static void |
| 1031 | rl78_address_to_pointer (struct gdbarch *gdbarch, |
| 1032 | struct type *type, gdb_byte *buf, CORE_ADDR addr) |
| 1033 | { |
| 1034 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1035 | |
| 1036 | store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, |
| 1037 | addr & 0xffffff); |
| 1038 | } |
| 1039 | |
| 1040 | /* Implement the "pointer_to_address" gdbarch method. */ |
| 1041 | |
| 1042 | static CORE_ADDR |
| 1043 | rl78_pointer_to_address (struct gdbarch *gdbarch, |
| 1044 | struct type *type, const gdb_byte *buf) |
| 1045 | { |
| 1046 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1047 | CORE_ADDR addr |
| 1048 | = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order); |
| 1049 | |
| 1050 | /* Is it a code address? */ |
| 1051 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC |
| 1052 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD |
| 1053 | || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type)) |
| 1054 | || TYPE_LENGTH (type) == 4) |
| 1055 | return rl78_make_instruction_address (addr); |
| 1056 | else |
| 1057 | return rl78_make_data_address (addr); |
| 1058 | } |
| 1059 | |
| 1060 | /* Implement the "skip_prologue" gdbarch method. */ |
| 1061 | |
| 1062 | static CORE_ADDR |
| 1063 | rl78_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 1064 | { |
| 1065 | const char *name; |
| 1066 | CORE_ADDR func_addr, func_end; |
| 1067 | struct rl78_prologue p; |
| 1068 | |
| 1069 | /* Try to find the extent of the function that contains PC. */ |
| 1070 | if (!find_pc_partial_function (pc, &name, &func_addr, &func_end)) |
| 1071 | return pc; |
| 1072 | |
| 1073 | rl78_analyze_prologue (pc, func_end, &p); |
| 1074 | return p.prologue_end; |
| 1075 | } |
| 1076 | |
| 1077 | /* Implement the "unwind_pc" gdbarch method. */ |
| 1078 | |
| 1079 | static CORE_ADDR |
| 1080 | rl78_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame) |
| 1081 | { |
| 1082 | return rl78_addr_bits_remove |
| 1083 | (arch, frame_unwind_register_unsigned (next_frame, |
| 1084 | RL78_PC_REGNUM)); |
| 1085 | } |
| 1086 | |
| 1087 | /* Given a frame described by THIS_FRAME, decode the prologue of its |
| 1088 | associated function if there is not cache entry as specified by |
| 1089 | THIS_PROLOGUE_CACHE. Save the decoded prologue in the cache and |
| 1090 | return that struct as the value of this function. */ |
| 1091 | |
| 1092 | static struct rl78_prologue * |
| 1093 | rl78_analyze_frame_prologue (struct frame_info *this_frame, |
| 1094 | void **this_prologue_cache) |
| 1095 | { |
| 1096 | if (!*this_prologue_cache) |
| 1097 | { |
| 1098 | CORE_ADDR func_start, stop_addr; |
| 1099 | |
| 1100 | *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct rl78_prologue); |
| 1101 | |
| 1102 | func_start = get_frame_func (this_frame); |
| 1103 | stop_addr = get_frame_pc (this_frame); |
| 1104 | |
| 1105 | /* If we couldn't find any function containing the PC, then |
| 1106 | just initialize the prologue cache, but don't do anything. */ |
| 1107 | if (!func_start) |
| 1108 | stop_addr = func_start; |
| 1109 | |
| 1110 | rl78_analyze_prologue (func_start, stop_addr, |
| 1111 | (struct rl78_prologue *) *this_prologue_cache); |
| 1112 | } |
| 1113 | |
| 1114 | return (struct rl78_prologue *) *this_prologue_cache; |
| 1115 | } |
| 1116 | |
| 1117 | /* Given a frame and a prologue cache, return this frame's base. */ |
| 1118 | |
| 1119 | static CORE_ADDR |
| 1120 | rl78_frame_base (struct frame_info *this_frame, void **this_prologue_cache) |
| 1121 | { |
| 1122 | struct rl78_prologue *p |
| 1123 | = rl78_analyze_frame_prologue (this_frame, this_prologue_cache); |
| 1124 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, RL78_SP_REGNUM); |
| 1125 | |
| 1126 | return rl78_make_data_address (sp - p->frame_size); |
| 1127 | } |
| 1128 | |
| 1129 | /* Implement the "frame_this_id" method for unwinding frames. */ |
| 1130 | |
| 1131 | static void |
| 1132 | rl78_this_id (struct frame_info *this_frame, |
| 1133 | void **this_prologue_cache, struct frame_id *this_id) |
| 1134 | { |
| 1135 | *this_id = frame_id_build (rl78_frame_base (this_frame, |
| 1136 | this_prologue_cache), |
| 1137 | get_frame_func (this_frame)); |
| 1138 | } |
| 1139 | |
| 1140 | /* Implement the "frame_prev_register" method for unwinding frames. */ |
| 1141 | |
| 1142 | static struct value * |
| 1143 | rl78_prev_register (struct frame_info *this_frame, |
| 1144 | void **this_prologue_cache, int regnum) |
| 1145 | { |
| 1146 | struct rl78_prologue *p |
| 1147 | = rl78_analyze_frame_prologue (this_frame, this_prologue_cache); |
| 1148 | CORE_ADDR frame_base = rl78_frame_base (this_frame, this_prologue_cache); |
| 1149 | |
| 1150 | if (regnum == RL78_SP_REGNUM) |
| 1151 | return frame_unwind_got_constant (this_frame, regnum, frame_base); |
| 1152 | |
| 1153 | else if (regnum == RL78_SPL_REGNUM) |
| 1154 | return frame_unwind_got_constant (this_frame, regnum, |
| 1155 | (frame_base & 0xff)); |
| 1156 | |
| 1157 | else if (regnum == RL78_SPH_REGNUM) |
| 1158 | return frame_unwind_got_constant (this_frame, regnum, |
| 1159 | ((frame_base >> 8) & 0xff)); |
| 1160 | |
| 1161 | /* If prologue analysis says we saved this register somewhere, |
| 1162 | return a description of the stack slot holding it. */ |
| 1163 | else if (p->reg_offset[regnum] != 1) |
| 1164 | { |
| 1165 | struct value *rv = |
| 1166 | frame_unwind_got_memory (this_frame, regnum, |
| 1167 | frame_base + p->reg_offset[regnum]); |
| 1168 | |
| 1169 | if (regnum == RL78_PC_REGNUM) |
| 1170 | { |
| 1171 | ULONGEST pc = rl78_make_instruction_address (value_as_long (rv)); |
| 1172 | |
| 1173 | return frame_unwind_got_constant (this_frame, regnum, pc); |
| 1174 | } |
| 1175 | return rv; |
| 1176 | } |
| 1177 | |
| 1178 | /* Otherwise, presume we haven't changed the value of this |
| 1179 | register, and get it from the next frame. */ |
| 1180 | else |
| 1181 | return frame_unwind_got_register (this_frame, regnum, regnum); |
| 1182 | } |
| 1183 | |
| 1184 | static const struct frame_unwind rl78_unwind = |
| 1185 | { |
| 1186 | NORMAL_FRAME, |
| 1187 | default_frame_unwind_stop_reason, |
| 1188 | rl78_this_id, |
| 1189 | rl78_prev_register, |
| 1190 | NULL, |
| 1191 | default_frame_sniffer |
| 1192 | }; |
| 1193 | |
| 1194 | /* Implement the "dwarf_reg_to_regnum" gdbarch method. */ |
| 1195 | |
| 1196 | static int |
| 1197 | rl78_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
| 1198 | { |
| 1199 | if (0 <= reg && reg <= 31) |
| 1200 | { |
| 1201 | if ((reg & 1) == 0) |
| 1202 | /* Map even registers to their 16-bit counterparts which have a |
| 1203 | pointer type. This is usually what is required from the DWARF |
| 1204 | info. */ |
| 1205 | return (reg >> 1) + RL78_BANK0_RP0_PTR_REGNUM; |
| 1206 | else |
| 1207 | return reg; |
| 1208 | } |
| 1209 | else if (reg == 32) |
| 1210 | return RL78_SP_REGNUM; |
| 1211 | else if (reg == 33) |
| 1212 | return -1; /* ap */ |
| 1213 | else if (reg == 34) |
| 1214 | return RL78_PSW_REGNUM; |
| 1215 | else if (reg == 35) |
| 1216 | return RL78_ES_REGNUM; |
| 1217 | else if (reg == 36) |
| 1218 | return RL78_CS_REGNUM; |
| 1219 | else if (reg == 37) |
| 1220 | return RL78_PC_REGNUM; |
| 1221 | else |
| 1222 | return -1; |
| 1223 | } |
| 1224 | |
| 1225 | /* Implement the `register_sim_regno' gdbarch method. */ |
| 1226 | |
| 1227 | static int |
| 1228 | rl78_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
| 1229 | { |
| 1230 | gdb_assert (regnum < RL78_NUM_REGS); |
| 1231 | |
| 1232 | /* So long as regnum is in [0, RL78_NUM_REGS), it's valid. We |
| 1233 | just want to override the default here which disallows register |
| 1234 | numbers which have no names. */ |
| 1235 | return regnum; |
| 1236 | } |
| 1237 | |
| 1238 | /* Implement the "return_value" gdbarch method. */ |
| 1239 | |
| 1240 | static enum return_value_convention |
| 1241 | rl78_return_value (struct gdbarch *gdbarch, |
| 1242 | struct value *function, |
| 1243 | struct type *valtype, |
| 1244 | struct regcache *regcache, |
| 1245 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 1246 | { |
| 1247 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1248 | ULONGEST valtype_len = TYPE_LENGTH (valtype); |
| 1249 | int is_g10 = gdbarch_tdep (gdbarch)->elf_flags & E_FLAG_RL78_G10; |
| 1250 | |
| 1251 | if (valtype_len > 8) |
| 1252 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 1253 | |
| 1254 | if (readbuf) |
| 1255 | { |
| 1256 | ULONGEST u; |
| 1257 | int argreg = RL78_RAW_BANK1_R0_REGNUM; |
| 1258 | CORE_ADDR g10_raddr = 0xffec8; |
| 1259 | int offset = 0; |
| 1260 | |
| 1261 | while (valtype_len > 0) |
| 1262 | { |
| 1263 | if (is_g10) |
| 1264 | u = read_memory_integer (g10_raddr, 1, |
| 1265 | gdbarch_byte_order (gdbarch)); |
| 1266 | else |
| 1267 | regcache_cooked_read_unsigned (regcache, argreg, &u); |
| 1268 | store_unsigned_integer (readbuf + offset, 1, byte_order, u); |
| 1269 | valtype_len -= 1; |
| 1270 | offset += 1; |
| 1271 | argreg++; |
| 1272 | g10_raddr++; |
| 1273 | } |
| 1274 | } |
| 1275 | |
| 1276 | if (writebuf) |
| 1277 | { |
| 1278 | ULONGEST u; |
| 1279 | int argreg = RL78_RAW_BANK1_R0_REGNUM; |
| 1280 | CORE_ADDR g10_raddr = 0xffec8; |
| 1281 | int offset = 0; |
| 1282 | |
| 1283 | while (valtype_len > 0) |
| 1284 | { |
| 1285 | u = extract_unsigned_integer (writebuf + offset, 1, byte_order); |
| 1286 | if (is_g10) { |
| 1287 | gdb_byte b = u & 0xff; |
| 1288 | write_memory (g10_raddr, &b, 1); |
| 1289 | } |
| 1290 | else |
| 1291 | regcache_cooked_write_unsigned (regcache, argreg, u); |
| 1292 | valtype_len -= 1; |
| 1293 | offset += 1; |
| 1294 | argreg++; |
| 1295 | g10_raddr++; |
| 1296 | } |
| 1297 | } |
| 1298 | |
| 1299 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 1300 | } |
| 1301 | |
| 1302 | |
| 1303 | /* Implement the "frame_align" gdbarch method. */ |
| 1304 | |
| 1305 | static CORE_ADDR |
| 1306 | rl78_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
| 1307 | { |
| 1308 | return rl78_make_data_address (align_down (sp, 2)); |
| 1309 | } |
| 1310 | |
| 1311 | |
| 1312 | /* Implement the "dummy_id" gdbarch method. */ |
| 1313 | |
| 1314 | static struct frame_id |
| 1315 | rl78_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1316 | { |
| 1317 | return |
| 1318 | frame_id_build (rl78_make_data_address |
| 1319 | (get_frame_register_unsigned |
| 1320 | (this_frame, RL78_SP_REGNUM)), |
| 1321 | get_frame_pc (this_frame)); |
| 1322 | } |
| 1323 | |
| 1324 | |
| 1325 | /* Implement the "push_dummy_call" gdbarch method. */ |
| 1326 | |
| 1327 | static CORE_ADDR |
| 1328 | rl78_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 1329 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 1330 | int nargs, struct value **args, CORE_ADDR sp, |
| 1331 | function_call_return_method return_method, |
| 1332 | CORE_ADDR struct_addr) |
| 1333 | { |
| 1334 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1335 | gdb_byte buf[4]; |
| 1336 | int i; |
| 1337 | |
| 1338 | /* Push arguments in reverse order. */ |
| 1339 | for (i = nargs - 1; i >= 0; i--) |
| 1340 | { |
| 1341 | struct type *value_type = value_enclosing_type (args[i]); |
| 1342 | int len = TYPE_LENGTH (value_type); |
| 1343 | int container_len = (len + 1) & ~1; |
| 1344 | |
| 1345 | sp -= container_len; |
| 1346 | write_memory (rl78_make_data_address (sp), |
| 1347 | value_contents_all (args[i]), len); |
| 1348 | } |
| 1349 | |
| 1350 | /* Store struct value address. */ |
| 1351 | if (return_method == return_method_struct) |
| 1352 | { |
| 1353 | store_unsigned_integer (buf, 2, byte_order, struct_addr); |
| 1354 | sp -= 2; |
| 1355 | write_memory (rl78_make_data_address (sp), buf, 2); |
| 1356 | } |
| 1357 | |
| 1358 | /* Store return address. */ |
| 1359 | sp -= 4; |
| 1360 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
| 1361 | write_memory (rl78_make_data_address (sp), buf, 4); |
| 1362 | |
| 1363 | /* Finally, update the stack pointer... */ |
| 1364 | regcache_cooked_write_unsigned (regcache, RL78_SP_REGNUM, sp); |
| 1365 | |
| 1366 | /* DWARF2/GCC uses the stack address *before* the function call as a |
| 1367 | frame's CFA. */ |
| 1368 | return rl78_make_data_address (sp + 4); |
| 1369 | } |
| 1370 | |
| 1371 | /* Allocate and initialize a gdbarch object. */ |
| 1372 | |
| 1373 | static struct gdbarch * |
| 1374 | rl78_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 1375 | { |
| 1376 | struct gdbarch *gdbarch; |
| 1377 | struct gdbarch_tdep *tdep; |
| 1378 | int elf_flags; |
| 1379 | |
| 1380 | /* Extract the elf_flags if available. */ |
| 1381 | if (info.abfd != NULL |
| 1382 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) |
| 1383 | elf_flags = elf_elfheader (info.abfd)->e_flags; |
| 1384 | else |
| 1385 | elf_flags = 0; |
| 1386 | |
| 1387 | |
| 1388 | /* Try to find the architecture in the list of already defined |
| 1389 | architectures. */ |
| 1390 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
| 1391 | arches != NULL; |
| 1392 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) |
| 1393 | { |
| 1394 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
| 1395 | continue; |
| 1396 | |
| 1397 | return arches->gdbarch; |
| 1398 | } |
| 1399 | |
| 1400 | /* None found, create a new architecture from the information |
| 1401 | provided. */ |
| 1402 | tdep = XCNEW (struct gdbarch_tdep); |
| 1403 | gdbarch = gdbarch_alloc (&info, tdep); |
| 1404 | tdep->elf_flags = elf_flags; |
| 1405 | |
| 1406 | /* Initialize types. */ |
| 1407 | tdep->rl78_void = arch_type (gdbarch, TYPE_CODE_VOID, TARGET_CHAR_BIT, |
| 1408 | "void"); |
| 1409 | tdep->rl78_uint8 = arch_integer_type (gdbarch, 8, 1, "uint8_t"); |
| 1410 | tdep->rl78_int8 = arch_integer_type (gdbarch, 8, 0, "int8_t"); |
| 1411 | tdep->rl78_uint16 = arch_integer_type (gdbarch, 16, 1, "uint16_t"); |
| 1412 | tdep->rl78_int16 = arch_integer_type (gdbarch, 16, 0, "int16_t"); |
| 1413 | tdep->rl78_uint32 = arch_integer_type (gdbarch, 32, 1, "uint32_t"); |
| 1414 | tdep->rl78_int32 = arch_integer_type (gdbarch, 32, 0, "int32_t"); |
| 1415 | |
| 1416 | tdep->rl78_data_pointer |
| 1417 | = arch_pointer_type (gdbarch, 16, "rl78_data_addr_t", tdep->rl78_void); |
| 1418 | tdep->rl78_code_pointer |
| 1419 | = arch_pointer_type (gdbarch, 32, "rl78_code_addr_t", tdep->rl78_void); |
| 1420 | |
| 1421 | /* Registers. */ |
| 1422 | set_gdbarch_num_regs (gdbarch, RL78_NUM_REGS); |
| 1423 | set_gdbarch_num_pseudo_regs (gdbarch, RL78_NUM_PSEUDO_REGS); |
| 1424 | if (tdep->elf_flags & E_FLAG_RL78_G10) |
| 1425 | set_gdbarch_register_name (gdbarch, rl78_g10_register_name); |
| 1426 | else |
| 1427 | set_gdbarch_register_name (gdbarch, rl78_register_name); |
| 1428 | set_gdbarch_register_type (gdbarch, rl78_register_type); |
| 1429 | set_gdbarch_pc_regnum (gdbarch, RL78_PC_REGNUM); |
| 1430 | set_gdbarch_sp_regnum (gdbarch, RL78_SP_REGNUM); |
| 1431 | set_gdbarch_pseudo_register_read (gdbarch, rl78_pseudo_register_read); |
| 1432 | set_gdbarch_pseudo_register_write (gdbarch, rl78_pseudo_register_write); |
| 1433 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rl78_dwarf_reg_to_regnum); |
| 1434 | set_gdbarch_register_reggroup_p (gdbarch, rl78_register_reggroup_p); |
| 1435 | set_gdbarch_register_sim_regno (gdbarch, rl78_register_sim_regno); |
| 1436 | |
| 1437 | /* Data types. */ |
| 1438 | set_gdbarch_char_signed (gdbarch, 0); |
| 1439 | set_gdbarch_short_bit (gdbarch, 16); |
| 1440 | set_gdbarch_int_bit (gdbarch, 16); |
| 1441 | set_gdbarch_long_bit (gdbarch, 32); |
| 1442 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 1443 | set_gdbarch_ptr_bit (gdbarch, 16); |
| 1444 | set_gdbarch_addr_bit (gdbarch, 32); |
| 1445 | set_gdbarch_dwarf2_addr_size (gdbarch, 4); |
| 1446 | set_gdbarch_float_bit (gdbarch, 32); |
| 1447 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
| 1448 | set_gdbarch_double_bit (gdbarch, 32); |
| 1449 | set_gdbarch_long_double_bit (gdbarch, 64); |
| 1450 | set_gdbarch_double_format (gdbarch, floatformats_ieee_single); |
| 1451 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); |
| 1452 | set_gdbarch_pointer_to_address (gdbarch, rl78_pointer_to_address); |
| 1453 | set_gdbarch_address_to_pointer (gdbarch, rl78_address_to_pointer); |
| 1454 | set_gdbarch_addr_bits_remove (gdbarch, rl78_addr_bits_remove); |
| 1455 | |
| 1456 | /* Breakpoints. */ |
| 1457 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, rl78_breakpoint::kind_from_pc); |
| 1458 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, rl78_breakpoint::bp_from_kind); |
| 1459 | set_gdbarch_decr_pc_after_break (gdbarch, 1); |
| 1460 | |
| 1461 | /* Frames, prologues, etc. */ |
| 1462 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 1463 | set_gdbarch_skip_prologue (gdbarch, rl78_skip_prologue); |
| 1464 | set_gdbarch_unwind_pc (gdbarch, rl78_unwind_pc); |
| 1465 | set_gdbarch_frame_align (gdbarch, rl78_frame_align); |
| 1466 | |
| 1467 | dwarf2_append_unwinders (gdbarch); |
| 1468 | frame_unwind_append_unwinder (gdbarch, &rl78_unwind); |
| 1469 | |
| 1470 | /* Dummy frames, return values. */ |
| 1471 | set_gdbarch_dummy_id (gdbarch, rl78_dummy_id); |
| 1472 | set_gdbarch_push_dummy_call (gdbarch, rl78_push_dummy_call); |
| 1473 | set_gdbarch_return_value (gdbarch, rl78_return_value); |
| 1474 | |
| 1475 | /* Virtual tables. */ |
| 1476 | set_gdbarch_vbit_in_delta (gdbarch, 1); |
| 1477 | |
| 1478 | return gdbarch; |
| 1479 | } |
| 1480 | |
| 1481 | /* Register the above initialization routine. */ |
| 1482 | |
| 1483 | void |
| 1484 | _initialize_rl78_tdep (void) |
| 1485 | { |
| 1486 | register_gdbarch_init (bfd_arch_rl78, rl78_gdbarch_init); |
| 1487 | } |