| 1 | /* Target-dependent code for GDB, the GNU debugger. |
| 2 | |
| 3 | Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
| 4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
| 5 | Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of GDB. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 2 of the License, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program; if not, write to the Free Software |
| 21 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
| 22 | Boston, MA 02110-1301, USA. */ |
| 23 | |
| 24 | #include "defs.h" |
| 25 | #include "frame.h" |
| 26 | #include "inferior.h" |
| 27 | #include "symtab.h" |
| 28 | #include "target.h" |
| 29 | #include "gdbcore.h" |
| 30 | #include "gdbcmd.h" |
| 31 | #include "objfiles.h" |
| 32 | #include "arch-utils.h" |
| 33 | #include "regcache.h" |
| 34 | #include "regset.h" |
| 35 | #include "doublest.h" |
| 36 | #include "value.h" |
| 37 | #include "parser-defs.h" |
| 38 | #include "osabi.h" |
| 39 | #include "infcall.h" |
| 40 | #include "sim-regno.h" |
| 41 | #include "gdb/sim-ppc.h" |
| 42 | #include "reggroups.h" |
| 43 | #include "dwarf2-frame.h" |
| 44 | |
| 45 | #include "libbfd.h" /* for bfd_default_set_arch_mach */ |
| 46 | #include "coff/internal.h" /* for libcoff.h */ |
| 47 | #include "libcoff.h" /* for xcoff_data */ |
| 48 | #include "coff/xcoff.h" |
| 49 | #include "libxcoff.h" |
| 50 | |
| 51 | #include "elf-bfd.h" |
| 52 | |
| 53 | #include "solib-svr4.h" |
| 54 | #include "ppc-tdep.h" |
| 55 | |
| 56 | #include "gdb_assert.h" |
| 57 | #include "dis-asm.h" |
| 58 | |
| 59 | #include "trad-frame.h" |
| 60 | #include "frame-unwind.h" |
| 61 | #include "frame-base.h" |
| 62 | |
| 63 | #include "rs6000-tdep.h" |
| 64 | |
| 65 | /* If the kernel has to deliver a signal, it pushes a sigcontext |
| 66 | structure on the stack and then calls the signal handler, passing |
| 67 | the address of the sigcontext in an argument register. Usually |
| 68 | the signal handler doesn't save this register, so we have to |
| 69 | access the sigcontext structure via an offset from the signal handler |
| 70 | frame. |
| 71 | The following constants were determined by experimentation on AIX 3.2. */ |
| 72 | #define SIG_FRAME_PC_OFFSET 96 |
| 73 | #define SIG_FRAME_LR_OFFSET 108 |
| 74 | #define SIG_FRAME_FP_OFFSET 284 |
| 75 | |
| 76 | /* To be used by skip_prologue. */ |
| 77 | |
| 78 | struct rs6000_framedata |
| 79 | { |
| 80 | int offset; /* total size of frame --- the distance |
| 81 | by which we decrement sp to allocate |
| 82 | the frame */ |
| 83 | int saved_gpr; /* smallest # of saved gpr */ |
| 84 | int saved_fpr; /* smallest # of saved fpr */ |
| 85 | int saved_vr; /* smallest # of saved vr */ |
| 86 | int saved_ev; /* smallest # of saved ev */ |
| 87 | int alloca_reg; /* alloca register number (frame ptr) */ |
| 88 | char frameless; /* true if frameless functions. */ |
| 89 | char nosavedpc; /* true if pc not saved. */ |
| 90 | int gpr_offset; /* offset of saved gprs from prev sp */ |
| 91 | int fpr_offset; /* offset of saved fprs from prev sp */ |
| 92 | int vr_offset; /* offset of saved vrs from prev sp */ |
| 93 | int ev_offset; /* offset of saved evs from prev sp */ |
| 94 | int lr_offset; /* offset of saved lr */ |
| 95 | int cr_offset; /* offset of saved cr */ |
| 96 | int vrsave_offset; /* offset of saved vrsave register */ |
| 97 | }; |
| 98 | |
| 99 | /* Description of a single register. */ |
| 100 | |
| 101 | struct reg |
| 102 | { |
| 103 | char *name; /* name of register */ |
| 104 | unsigned char sz32; /* size on 32-bit arch, 0 if nonexistent */ |
| 105 | unsigned char sz64; /* size on 64-bit arch, 0 if nonexistent */ |
| 106 | unsigned char fpr; /* whether register is floating-point */ |
| 107 | unsigned char pseudo; /* whether register is pseudo */ |
| 108 | int spr_num; /* PowerPC SPR number, or -1 if not an SPR. |
| 109 | This is an ISA SPR number, not a GDB |
| 110 | register number. */ |
| 111 | }; |
| 112 | |
| 113 | /* Hook for determining the TOC address when calling functions in the |
| 114 | inferior under AIX. The initialization code in rs6000-nat.c sets |
| 115 | this hook to point to find_toc_address. */ |
| 116 | |
| 117 | CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL; |
| 118 | |
| 119 | /* Static function prototypes */ |
| 120 | |
| 121 | static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc, |
| 122 | CORE_ADDR safety); |
| 123 | static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR, |
| 124 | struct rs6000_framedata *); |
| 125 | |
| 126 | /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ |
| 127 | int |
| 128 | altivec_register_p (int regno) |
| 129 | { |
| 130 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 131 | if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) |
| 132 | return 0; |
| 133 | else |
| 134 | return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); |
| 135 | } |
| 136 | |
| 137 | |
| 138 | /* Return true if REGNO is an SPE register, false otherwise. */ |
| 139 | int |
| 140 | spe_register_p (int regno) |
| 141 | { |
| 142 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 143 | |
| 144 | /* Is it a reference to EV0 -- EV31, and do we have those? */ |
| 145 | if (tdep->ppc_ev0_regnum >= 0 |
| 146 | && tdep->ppc_ev31_regnum >= 0 |
| 147 | && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum) |
| 148 | return 1; |
| 149 | |
| 150 | /* Is it a reference to one of the raw upper GPR halves? */ |
| 151 | if (tdep->ppc_ev0_upper_regnum >= 0 |
| 152 | && tdep->ppc_ev0_upper_regnum <= regno |
| 153 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) |
| 154 | return 1; |
| 155 | |
| 156 | /* Is it a reference to the 64-bit accumulator, and do we have that? */ |
| 157 | if (tdep->ppc_acc_regnum >= 0 |
| 158 | && tdep->ppc_acc_regnum == regno) |
| 159 | return 1; |
| 160 | |
| 161 | /* Is it a reference to the SPE floating-point status and control register, |
| 162 | and do we have that? */ |
| 163 | if (tdep->ppc_spefscr_regnum >= 0 |
| 164 | && tdep->ppc_spefscr_regnum == regno) |
| 165 | return 1; |
| 166 | |
| 167 | return 0; |
| 168 | } |
| 169 | |
| 170 | |
| 171 | /* Return non-zero if the architecture described by GDBARCH has |
| 172 | floating-point registers (f0 --- f31 and fpscr). */ |
| 173 | int |
| 174 | ppc_floating_point_unit_p (struct gdbarch *gdbarch) |
| 175 | { |
| 176 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 177 | |
| 178 | return (tdep->ppc_fp0_regnum >= 0 |
| 179 | && tdep->ppc_fpscr_regnum >= 0); |
| 180 | } |
| 181 | |
| 182 | |
| 183 | /* Check that TABLE[GDB_REGNO] is not already initialized, and then |
| 184 | set it to SIM_REGNO. |
| 185 | |
| 186 | This is a helper function for init_sim_regno_table, constructing |
| 187 | the table mapping GDB register numbers to sim register numbers; we |
| 188 | initialize every element in that table to -1 before we start |
| 189 | filling it in. */ |
| 190 | static void |
| 191 | set_sim_regno (int *table, int gdb_regno, int sim_regno) |
| 192 | { |
| 193 | /* Make sure we don't try to assign any given GDB register a sim |
| 194 | register number more than once. */ |
| 195 | gdb_assert (table[gdb_regno] == -1); |
| 196 | table[gdb_regno] = sim_regno; |
| 197 | } |
| 198 | |
| 199 | |
| 200 | /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register |
| 201 | numbers to simulator register numbers, based on the values placed |
| 202 | in the ARCH->tdep->ppc_foo_regnum members. */ |
| 203 | static void |
| 204 | init_sim_regno_table (struct gdbarch *arch) |
| 205 | { |
| 206 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
| 207 | int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch); |
| 208 | const struct reg *regs = tdep->regs; |
| 209 | int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int); |
| 210 | int i; |
| 211 | |
| 212 | /* Presume that all registers not explicitly mentioned below are |
| 213 | unavailable from the sim. */ |
| 214 | for (i = 0; i < total_regs; i++) |
| 215 | sim_regno[i] = -1; |
| 216 | |
| 217 | /* General-purpose registers. */ |
| 218 | for (i = 0; i < ppc_num_gprs; i++) |
| 219 | set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i); |
| 220 | |
| 221 | /* Floating-point registers. */ |
| 222 | if (tdep->ppc_fp0_regnum >= 0) |
| 223 | for (i = 0; i < ppc_num_fprs; i++) |
| 224 | set_sim_regno (sim_regno, |
| 225 | tdep->ppc_fp0_regnum + i, |
| 226 | sim_ppc_f0_regnum + i); |
| 227 | if (tdep->ppc_fpscr_regnum >= 0) |
| 228 | set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum); |
| 229 | |
| 230 | set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum); |
| 231 | set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum); |
| 232 | set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum); |
| 233 | |
| 234 | /* Segment registers. */ |
| 235 | if (tdep->ppc_sr0_regnum >= 0) |
| 236 | for (i = 0; i < ppc_num_srs; i++) |
| 237 | set_sim_regno (sim_regno, |
| 238 | tdep->ppc_sr0_regnum + i, |
| 239 | sim_ppc_sr0_regnum + i); |
| 240 | |
| 241 | /* Altivec registers. */ |
| 242 | if (tdep->ppc_vr0_regnum >= 0) |
| 243 | { |
| 244 | for (i = 0; i < ppc_num_vrs; i++) |
| 245 | set_sim_regno (sim_regno, |
| 246 | tdep->ppc_vr0_regnum + i, |
| 247 | sim_ppc_vr0_regnum + i); |
| 248 | |
| 249 | /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum, |
| 250 | we can treat this more like the other cases. */ |
| 251 | set_sim_regno (sim_regno, |
| 252 | tdep->ppc_vr0_regnum + ppc_num_vrs, |
| 253 | sim_ppc_vscr_regnum); |
| 254 | } |
| 255 | /* vsave is a special-purpose register, so the code below handles it. */ |
| 256 | |
| 257 | /* SPE APU (E500) registers. */ |
| 258 | if (tdep->ppc_ev0_regnum >= 0) |
| 259 | for (i = 0; i < ppc_num_gprs; i++) |
| 260 | set_sim_regno (sim_regno, |
| 261 | tdep->ppc_ev0_regnum + i, |
| 262 | sim_ppc_ev0_regnum + i); |
| 263 | if (tdep->ppc_ev0_upper_regnum >= 0) |
| 264 | for (i = 0; i < ppc_num_gprs; i++) |
| 265 | set_sim_regno (sim_regno, |
| 266 | tdep->ppc_ev0_upper_regnum + i, |
| 267 | sim_ppc_rh0_regnum + i); |
| 268 | if (tdep->ppc_acc_regnum >= 0) |
| 269 | set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum); |
| 270 | /* spefscr is a special-purpose register, so the code below handles it. */ |
| 271 | |
| 272 | /* Now handle all special-purpose registers. Verify that they |
| 273 | haven't mistakenly been assigned numbers by any of the above |
| 274 | code). */ |
| 275 | for (i = 0; i < total_regs; i++) |
| 276 | if (regs[i].spr_num >= 0) |
| 277 | set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum); |
| 278 | |
| 279 | /* Drop the initialized array into place. */ |
| 280 | tdep->sim_regno = sim_regno; |
| 281 | } |
| 282 | |
| 283 | |
| 284 | /* Given a GDB register number REG, return the corresponding SIM |
| 285 | register number. */ |
| 286 | static int |
| 287 | rs6000_register_sim_regno (int reg) |
| 288 | { |
| 289 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 290 | int sim_regno; |
| 291 | |
| 292 | gdb_assert (0 <= reg && reg <= NUM_REGS + NUM_PSEUDO_REGS); |
| 293 | sim_regno = tdep->sim_regno[reg]; |
| 294 | |
| 295 | if (sim_regno >= 0) |
| 296 | return sim_regno; |
| 297 | else |
| 298 | return LEGACY_SIM_REGNO_IGNORE; |
| 299 | } |
| 300 | |
| 301 | \f |
| 302 | |
| 303 | /* Register set support functions. */ |
| 304 | |
| 305 | static void |
| 306 | ppc_supply_reg (struct regcache *regcache, int regnum, |
| 307 | const gdb_byte *regs, size_t offset) |
| 308 | { |
| 309 | if (regnum != -1 && offset != -1) |
| 310 | regcache_raw_supply (regcache, regnum, regs + offset); |
| 311 | } |
| 312 | |
| 313 | static void |
| 314 | ppc_collect_reg (const struct regcache *regcache, int regnum, |
| 315 | gdb_byte *regs, size_t offset) |
| 316 | { |
| 317 | if (regnum != -1 && offset != -1) |
| 318 | regcache_raw_collect (regcache, regnum, regs + offset); |
| 319 | } |
| 320 | |
| 321 | /* Supply register REGNUM in the general-purpose register set REGSET |
| 322 | from the buffer specified by GREGS and LEN to register cache |
| 323 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ |
| 324 | |
| 325 | void |
| 326 | ppc_supply_gregset (const struct regset *regset, struct regcache *regcache, |
| 327 | int regnum, const void *gregs, size_t len) |
| 328 | { |
| 329 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 330 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 331 | const struct ppc_reg_offsets *offsets = regset->descr; |
| 332 | size_t offset; |
| 333 | int i; |
| 334 | |
| 335 | for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; |
| 336 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; |
| 337 | i++, offset += 4) |
| 338 | { |
| 339 | if (regnum == -1 || regnum == i) |
| 340 | ppc_supply_reg (regcache, i, gregs, offset); |
| 341 | } |
| 342 | |
| 343 | if (regnum == -1 || regnum == PC_REGNUM) |
| 344 | ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset); |
| 345 | if (regnum == -1 || regnum == tdep->ppc_ps_regnum) |
| 346 | ppc_supply_reg (regcache, tdep->ppc_ps_regnum, |
| 347 | gregs, offsets->ps_offset); |
| 348 | if (regnum == -1 || regnum == tdep->ppc_cr_regnum) |
| 349 | ppc_supply_reg (regcache, tdep->ppc_cr_regnum, |
| 350 | gregs, offsets->cr_offset); |
| 351 | if (regnum == -1 || regnum == tdep->ppc_lr_regnum) |
| 352 | ppc_supply_reg (regcache, tdep->ppc_lr_regnum, |
| 353 | gregs, offsets->lr_offset); |
| 354 | if (regnum == -1 || regnum == tdep->ppc_ctr_regnum) |
| 355 | ppc_supply_reg (regcache, tdep->ppc_ctr_regnum, |
| 356 | gregs, offsets->ctr_offset); |
| 357 | if (regnum == -1 || regnum == tdep->ppc_xer_regnum) |
| 358 | ppc_supply_reg (regcache, tdep->ppc_xer_regnum, |
| 359 | gregs, offsets->cr_offset); |
| 360 | if (regnum == -1 || regnum == tdep->ppc_mq_regnum) |
| 361 | ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset); |
| 362 | } |
| 363 | |
| 364 | /* Supply register REGNUM in the floating-point register set REGSET |
| 365 | from the buffer specified by FPREGS and LEN to register cache |
| 366 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ |
| 367 | |
| 368 | void |
| 369 | ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache, |
| 370 | int regnum, const void *fpregs, size_t len) |
| 371 | { |
| 372 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 373 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 374 | const struct ppc_reg_offsets *offsets = regset->descr; |
| 375 | size_t offset; |
| 376 | int i; |
| 377 | |
| 378 | gdb_assert (ppc_floating_point_unit_p (gdbarch)); |
| 379 | |
| 380 | offset = offsets->f0_offset; |
| 381 | for (i = tdep->ppc_fp0_regnum; |
| 382 | i < tdep->ppc_fp0_regnum + ppc_num_fprs; |
| 383 | i++, offset += 8) |
| 384 | { |
| 385 | if (regnum == -1 || regnum == i) |
| 386 | ppc_supply_reg (regcache, i, fpregs, offset); |
| 387 | } |
| 388 | |
| 389 | if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum) |
| 390 | ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum, |
| 391 | fpregs, offsets->fpscr_offset); |
| 392 | } |
| 393 | |
| 394 | /* Collect register REGNUM in the general-purpose register set |
| 395 | REGSET. from register cache REGCACHE into the buffer specified by |
| 396 | GREGS and LEN. If REGNUM is -1, do this for all registers in |
| 397 | REGSET. */ |
| 398 | |
| 399 | void |
| 400 | ppc_collect_gregset (const struct regset *regset, |
| 401 | const struct regcache *regcache, |
| 402 | int regnum, void *gregs, size_t len) |
| 403 | { |
| 404 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 405 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 406 | const struct ppc_reg_offsets *offsets = regset->descr; |
| 407 | size_t offset; |
| 408 | int i; |
| 409 | |
| 410 | offset = offsets->r0_offset; |
| 411 | for (i = tdep->ppc_gp0_regnum; |
| 412 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; |
| 413 | i++, offset += 4) |
| 414 | { |
| 415 | if (regnum == -1 || regnum == i) |
| 416 | ppc_collect_reg (regcache, i, gregs, offset); |
| 417 | } |
| 418 | |
| 419 | if (regnum == -1 || regnum == PC_REGNUM) |
| 420 | ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset); |
| 421 | if (regnum == -1 || regnum == tdep->ppc_ps_regnum) |
| 422 | ppc_collect_reg (regcache, tdep->ppc_ps_regnum, |
| 423 | gregs, offsets->ps_offset); |
| 424 | if (regnum == -1 || regnum == tdep->ppc_cr_regnum) |
| 425 | ppc_collect_reg (regcache, tdep->ppc_cr_regnum, |
| 426 | gregs, offsets->cr_offset); |
| 427 | if (regnum == -1 || regnum == tdep->ppc_lr_regnum) |
| 428 | ppc_collect_reg (regcache, tdep->ppc_lr_regnum, |
| 429 | gregs, offsets->lr_offset); |
| 430 | if (regnum == -1 || regnum == tdep->ppc_ctr_regnum) |
| 431 | ppc_collect_reg (regcache, tdep->ppc_ctr_regnum, |
| 432 | gregs, offsets->ctr_offset); |
| 433 | if (regnum == -1 || regnum == tdep->ppc_xer_regnum) |
| 434 | ppc_collect_reg (regcache, tdep->ppc_xer_regnum, |
| 435 | gregs, offsets->xer_offset); |
| 436 | if (regnum == -1 || regnum == tdep->ppc_mq_regnum) |
| 437 | ppc_collect_reg (regcache, tdep->ppc_mq_regnum, |
| 438 | gregs, offsets->mq_offset); |
| 439 | } |
| 440 | |
| 441 | /* Collect register REGNUM in the floating-point register set |
| 442 | REGSET. from register cache REGCACHE into the buffer specified by |
| 443 | FPREGS and LEN. If REGNUM is -1, do this for all registers in |
| 444 | REGSET. */ |
| 445 | |
| 446 | void |
| 447 | ppc_collect_fpregset (const struct regset *regset, |
| 448 | const struct regcache *regcache, |
| 449 | int regnum, void *fpregs, size_t len) |
| 450 | { |
| 451 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 452 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 453 | const struct ppc_reg_offsets *offsets = regset->descr; |
| 454 | size_t offset; |
| 455 | int i; |
| 456 | |
| 457 | gdb_assert (ppc_floating_point_unit_p (gdbarch)); |
| 458 | |
| 459 | offset = offsets->f0_offset; |
| 460 | for (i = tdep->ppc_fp0_regnum; |
| 461 | i <= tdep->ppc_fp0_regnum + ppc_num_fprs; |
| 462 | i++, offset += 8) |
| 463 | { |
| 464 | if (regnum == -1 || regnum == i) |
| 465 | ppc_collect_reg (regcache, i, fpregs, offset); |
| 466 | } |
| 467 | |
| 468 | if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum) |
| 469 | ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum, |
| 470 | fpregs, offsets->fpscr_offset); |
| 471 | } |
| 472 | \f |
| 473 | |
| 474 | /* Read a LEN-byte address from debugged memory address MEMADDR. */ |
| 475 | |
| 476 | static CORE_ADDR |
| 477 | read_memory_addr (CORE_ADDR memaddr, int len) |
| 478 | { |
| 479 | return read_memory_unsigned_integer (memaddr, len); |
| 480 | } |
| 481 | |
| 482 | static CORE_ADDR |
| 483 | rs6000_skip_prologue (CORE_ADDR pc) |
| 484 | { |
| 485 | struct rs6000_framedata frame; |
| 486 | CORE_ADDR limit_pc, func_addr; |
| 487 | |
| 488 | /* See if we can determine the end of the prologue via the symbol table. |
| 489 | If so, then return either PC, or the PC after the prologue, whichever |
| 490 | is greater. */ |
| 491 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
| 492 | { |
| 493 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); |
| 494 | if (post_prologue_pc != 0) |
| 495 | return max (pc, post_prologue_pc); |
| 496 | } |
| 497 | |
| 498 | /* Can't determine prologue from the symbol table, need to examine |
| 499 | instructions. */ |
| 500 | |
| 501 | /* Find an upper limit on the function prologue using the debug |
| 502 | information. If the debug information could not be used to provide |
| 503 | that bound, then use an arbitrary large number as the upper bound. */ |
| 504 | limit_pc = skip_prologue_using_sal (pc); |
| 505 | if (limit_pc == 0) |
| 506 | limit_pc = pc + 100; /* Magic. */ |
| 507 | |
| 508 | pc = skip_prologue (pc, limit_pc, &frame); |
| 509 | return pc; |
| 510 | } |
| 511 | |
| 512 | static int |
| 513 | insn_changes_sp_or_jumps (unsigned long insn) |
| 514 | { |
| 515 | int opcode = (insn >> 26) & 0x03f; |
| 516 | int sd = (insn >> 21) & 0x01f; |
| 517 | int a = (insn >> 16) & 0x01f; |
| 518 | int subcode = (insn >> 1) & 0x3ff; |
| 519 | |
| 520 | /* Changes the stack pointer. */ |
| 521 | |
| 522 | /* NOTE: There are many ways to change the value of a given register. |
| 523 | The ways below are those used when the register is R1, the SP, |
| 524 | in a funtion's epilogue. */ |
| 525 | |
| 526 | if (opcode == 31 && subcode == 444 && a == 1) |
| 527 | return 1; /* mr R1,Rn */ |
| 528 | if (opcode == 14 && sd == 1) |
| 529 | return 1; /* addi R1,Rn,simm */ |
| 530 | if (opcode == 58 && sd == 1) |
| 531 | return 1; /* ld R1,ds(Rn) */ |
| 532 | |
| 533 | /* Transfers control. */ |
| 534 | |
| 535 | if (opcode == 18) |
| 536 | return 1; /* b */ |
| 537 | if (opcode == 16) |
| 538 | return 1; /* bc */ |
| 539 | if (opcode == 19 && subcode == 16) |
| 540 | return 1; /* bclr */ |
| 541 | if (opcode == 19 && subcode == 528) |
| 542 | return 1; /* bcctr */ |
| 543 | |
| 544 | return 0; |
| 545 | } |
| 546 | |
| 547 | /* Return true if we are in the function's epilogue, i.e. after the |
| 548 | instruction that destroyed the function's stack frame. |
| 549 | |
| 550 | 1) scan forward from the point of execution: |
| 551 | a) If you find an instruction that modifies the stack pointer |
| 552 | or transfers control (except a return), execution is not in |
| 553 | an epilogue, return. |
| 554 | b) Stop scanning if you find a return instruction or reach the |
| 555 | end of the function or reach the hard limit for the size of |
| 556 | an epilogue. |
| 557 | 2) scan backward from the point of execution: |
| 558 | a) If you find an instruction that modifies the stack pointer, |
| 559 | execution *is* in an epilogue, return. |
| 560 | b) Stop scanning if you reach an instruction that transfers |
| 561 | control or the beginning of the function or reach the hard |
| 562 | limit for the size of an epilogue. */ |
| 563 | |
| 564 | static int |
| 565 | rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 566 | { |
| 567 | bfd_byte insn_buf[PPC_INSN_SIZE]; |
| 568 | CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end; |
| 569 | unsigned long insn; |
| 570 | struct frame_info *curfrm; |
| 571 | |
| 572 | /* Find the search limits based on function boundaries and hard limit. */ |
| 573 | |
| 574 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) |
| 575 | return 0; |
| 576 | |
| 577 | epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; |
| 578 | if (epilogue_start < func_start) epilogue_start = func_start; |
| 579 | |
| 580 | epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; |
| 581 | if (epilogue_end > func_end) epilogue_end = func_end; |
| 582 | |
| 583 | curfrm = get_current_frame (); |
| 584 | |
| 585 | /* Scan forward until next 'blr'. */ |
| 586 | |
| 587 | for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE) |
| 588 | { |
| 589 | if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) |
| 590 | return 0; |
| 591 | insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE); |
| 592 | if (insn == 0x4e800020) |
| 593 | break; |
| 594 | if (insn_changes_sp_or_jumps (insn)) |
| 595 | return 0; |
| 596 | } |
| 597 | |
| 598 | /* Scan backward until adjustment to stack pointer (R1). */ |
| 599 | |
| 600 | for (scan_pc = pc - PPC_INSN_SIZE; |
| 601 | scan_pc >= epilogue_start; |
| 602 | scan_pc -= PPC_INSN_SIZE) |
| 603 | { |
| 604 | if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) |
| 605 | return 0; |
| 606 | insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE); |
| 607 | if (insn_changes_sp_or_jumps (insn)) |
| 608 | return 1; |
| 609 | } |
| 610 | |
| 611 | return 0; |
| 612 | } |
| 613 | |
| 614 | /* Get the ith function argument for the current function. */ |
| 615 | static CORE_ADDR |
| 616 | rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, |
| 617 | struct type *type) |
| 618 | { |
| 619 | return get_frame_register_unsigned (frame, 3 + argi); |
| 620 | } |
| 621 | |
| 622 | /* Calculate the destination of a branch/jump. Return -1 if not a branch. */ |
| 623 | |
| 624 | static CORE_ADDR |
| 625 | branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety) |
| 626 | { |
| 627 | CORE_ADDR dest; |
| 628 | int immediate; |
| 629 | int absolute; |
| 630 | int ext_op; |
| 631 | |
| 632 | absolute = (int) ((instr >> 1) & 1); |
| 633 | |
| 634 | switch (opcode) |
| 635 | { |
| 636 | case 18: |
| 637 | immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */ |
| 638 | if (absolute) |
| 639 | dest = immediate; |
| 640 | else |
| 641 | dest = pc + immediate; |
| 642 | break; |
| 643 | |
| 644 | case 16: |
| 645 | immediate = ((instr & ~3) << 16) >> 16; /* br conditional */ |
| 646 | if (absolute) |
| 647 | dest = immediate; |
| 648 | else |
| 649 | dest = pc + immediate; |
| 650 | break; |
| 651 | |
| 652 | case 19: |
| 653 | ext_op = (instr >> 1) & 0x3ff; |
| 654 | |
| 655 | if (ext_op == 16) /* br conditional register */ |
| 656 | { |
| 657 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
| 658 | |
| 659 | /* If we are about to return from a signal handler, dest is |
| 660 | something like 0x3c90. The current frame is a signal handler |
| 661 | caller frame, upon completion of the sigreturn system call |
| 662 | execution will return to the saved PC in the frame. */ |
| 663 | if (dest < gdbarch_tdep (current_gdbarch)->text_segment_base) |
| 664 | { |
| 665 | struct frame_info *fi; |
| 666 | |
| 667 | fi = get_current_frame (); |
| 668 | if (fi != NULL) |
| 669 | dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET, |
| 670 | gdbarch_tdep (current_gdbarch)->wordsize); |
| 671 | } |
| 672 | } |
| 673 | |
| 674 | else if (ext_op == 528) /* br cond to count reg */ |
| 675 | { |
| 676 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3; |
| 677 | |
| 678 | /* If we are about to execute a system call, dest is something |
| 679 | like 0x22fc or 0x3b00. Upon completion the system call |
| 680 | will return to the address in the link register. */ |
| 681 | if (dest < gdbarch_tdep (current_gdbarch)->text_segment_base) |
| 682 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
| 683 | } |
| 684 | else |
| 685 | return -1; |
| 686 | break; |
| 687 | |
| 688 | default: |
| 689 | return -1; |
| 690 | } |
| 691 | return (dest < gdbarch_tdep (current_gdbarch)->text_segment_base) ? safety : dest; |
| 692 | } |
| 693 | |
| 694 | |
| 695 | /* Sequence of bytes for breakpoint instruction. */ |
| 696 | |
| 697 | const static unsigned char * |
| 698 | rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) |
| 699 | { |
| 700 | static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; |
| 701 | static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; |
| 702 | *bp_size = 4; |
| 703 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 704 | return big_breakpoint; |
| 705 | else |
| 706 | return little_breakpoint; |
| 707 | } |
| 708 | |
| 709 | |
| 710 | /* Instruction masks used during single-stepping of atomic sequences. */ |
| 711 | #define LWARX_MASK 0xfc0007fe |
| 712 | #define LWARX_INSTRUCTION 0x7c000028 |
| 713 | #define LDARX_INSTRUCTION 0x7c0000A8 |
| 714 | #define STWCX_MASK 0xfc0007ff |
| 715 | #define STWCX_INSTRUCTION 0x7c00012d |
| 716 | #define STDCX_INSTRUCTION 0x7c0001ad |
| 717 | #define BC_MASK 0xfc000000 |
| 718 | #define BC_INSTRUCTION 0x40000000 |
| 719 | |
| 720 | /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX |
| 721 | instruction and ending with a STWCX/STDCX instruction. If such a sequence |
| 722 | is found, attempt to step through it. A breakpoint is placed at the end of |
| 723 | the sequence. */ |
| 724 | |
| 725 | static int |
| 726 | deal_with_atomic_sequence (struct regcache *regcache) |
| 727 | { |
| 728 | CORE_ADDR pc = read_pc (); |
| 729 | CORE_ADDR breaks[2] = {-1, -1}; |
| 730 | CORE_ADDR loc = pc; |
| 731 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ |
| 732 | CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */ |
| 733 | int insn = read_memory_integer (loc, PPC_INSN_SIZE); |
| 734 | int insn_count; |
| 735 | int index; |
| 736 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ |
| 737 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ |
| 738 | int opcode; /* Branch instruction's OPcode. */ |
| 739 | int bc_insn_count = 0; /* Conditional branch instruction count. */ |
| 740 | |
| 741 | /* Assume all atomic sequences start with a lwarx/ldarx instruction. */ |
| 742 | if ((insn & LWARX_MASK) != LWARX_INSTRUCTION |
| 743 | && (insn & LWARX_MASK) != LDARX_INSTRUCTION) |
| 744 | return 0; |
| 745 | |
| 746 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" |
| 747 | instructions. */ |
| 748 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) |
| 749 | { |
| 750 | loc += PPC_INSN_SIZE; |
| 751 | insn = read_memory_integer (loc, PPC_INSN_SIZE); |
| 752 | |
| 753 | /* Assume that there is at most one conditional branch in the atomic |
| 754 | sequence. If a conditional branch is found, put a breakpoint in |
| 755 | its destination address. */ |
| 756 | if ((insn & BC_MASK) == BC_INSTRUCTION) |
| 757 | { |
| 758 | if (bc_insn_count >= 1) |
| 759 | return 0; /* More than one conditional branch found, fallback |
| 760 | to the standard single-step code. */ |
| 761 | |
| 762 | opcode = insn >> 26; |
| 763 | branch_bp = branch_dest (opcode, insn, pc, breaks[0]); |
| 764 | |
| 765 | if (branch_bp != -1) |
| 766 | { |
| 767 | breaks[1] = branch_bp; |
| 768 | bc_insn_count++; |
| 769 | last_breakpoint++; |
| 770 | } |
| 771 | } |
| 772 | |
| 773 | if ((insn & STWCX_MASK) == STWCX_INSTRUCTION |
| 774 | || (insn & STWCX_MASK) == STDCX_INSTRUCTION) |
| 775 | break; |
| 776 | } |
| 777 | |
| 778 | /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */ |
| 779 | if ((insn & STWCX_MASK) != STWCX_INSTRUCTION |
| 780 | && (insn & STWCX_MASK) != STDCX_INSTRUCTION) |
| 781 | return 0; |
| 782 | |
| 783 | closing_insn = loc; |
| 784 | loc += PPC_INSN_SIZE; |
| 785 | insn = read_memory_integer (loc, PPC_INSN_SIZE); |
| 786 | |
| 787 | /* Insert a breakpoint right after the end of the atomic sequence. */ |
| 788 | breaks[0] = loc; |
| 789 | |
| 790 | /* Check for duplicated breakpoints. Check also for a breakpoint |
| 791 | placed (branch instruction's destination) at the stwcx/stdcx |
| 792 | instruction, this resets the reservation and take us back to the |
| 793 | lwarx/ldarx instruction at the beginning of the atomic sequence. */ |
| 794 | if (last_breakpoint && ((breaks[1] == breaks[0]) |
| 795 | || (breaks[1] == closing_insn))) |
| 796 | last_breakpoint = 0; |
| 797 | |
| 798 | /* Effectively inserts the breakpoints. */ |
| 799 | for (index = 0; index <= last_breakpoint; index++) |
| 800 | insert_single_step_breakpoint (breaks[index]); |
| 801 | |
| 802 | return 1; |
| 803 | } |
| 804 | |
| 805 | /* AIX does not support PT_STEP. Simulate it. */ |
| 806 | |
| 807 | int |
| 808 | rs6000_software_single_step (struct regcache *regcache) |
| 809 | { |
| 810 | CORE_ADDR dummy; |
| 811 | int breakp_sz; |
| 812 | const gdb_byte *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz); |
| 813 | int ii, insn; |
| 814 | CORE_ADDR loc; |
| 815 | CORE_ADDR breaks[2]; |
| 816 | int opcode; |
| 817 | |
| 818 | loc = read_pc (); |
| 819 | |
| 820 | insn = read_memory_integer (loc, 4); |
| 821 | |
| 822 | if (deal_with_atomic_sequence (regcache)) |
| 823 | return 1; |
| 824 | |
| 825 | breaks[0] = loc + breakp_sz; |
| 826 | opcode = insn >> 26; |
| 827 | breaks[1] = branch_dest (opcode, insn, loc, breaks[0]); |
| 828 | |
| 829 | /* Don't put two breakpoints on the same address. */ |
| 830 | if (breaks[1] == breaks[0]) |
| 831 | breaks[1] = -1; |
| 832 | |
| 833 | for (ii = 0; ii < 2; ++ii) |
| 834 | { |
| 835 | /* ignore invalid breakpoint. */ |
| 836 | if (breaks[ii] == -1) |
| 837 | continue; |
| 838 | insert_single_step_breakpoint (breaks[ii]); |
| 839 | } |
| 840 | |
| 841 | errno = 0; /* FIXME, don't ignore errors! */ |
| 842 | /* What errors? {read,write}_memory call error(). */ |
| 843 | return 1; |
| 844 | } |
| 845 | |
| 846 | |
| 847 | /* return pc value after skipping a function prologue and also return |
| 848 | information about a function frame. |
| 849 | |
| 850 | in struct rs6000_framedata fdata: |
| 851 | - frameless is TRUE, if function does not have a frame. |
| 852 | - nosavedpc is TRUE, if function does not save %pc value in its frame. |
| 853 | - offset is the initial size of this stack frame --- the amount by |
| 854 | which we decrement the sp to allocate the frame. |
| 855 | - saved_gpr is the number of the first saved gpr. |
| 856 | - saved_fpr is the number of the first saved fpr. |
| 857 | - saved_vr is the number of the first saved vr. |
| 858 | - saved_ev is the number of the first saved ev. |
| 859 | - alloca_reg is the number of the register used for alloca() handling. |
| 860 | Otherwise -1. |
| 861 | - gpr_offset is the offset of the first saved gpr from the previous frame. |
| 862 | - fpr_offset is the offset of the first saved fpr from the previous frame. |
| 863 | - vr_offset is the offset of the first saved vr from the previous frame. |
| 864 | - ev_offset is the offset of the first saved ev from the previous frame. |
| 865 | - lr_offset is the offset of the saved lr |
| 866 | - cr_offset is the offset of the saved cr |
| 867 | - vrsave_offset is the offset of the saved vrsave register |
| 868 | */ |
| 869 | |
| 870 | #define SIGNED_SHORT(x) \ |
| 871 | ((sizeof (short) == 2) \ |
| 872 | ? ((int)(short)(x)) \ |
| 873 | : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) |
| 874 | |
| 875 | #define GET_SRC_REG(x) (((x) >> 21) & 0x1f) |
| 876 | |
| 877 | /* Limit the number of skipped non-prologue instructions, as the examining |
| 878 | of the prologue is expensive. */ |
| 879 | static int max_skip_non_prologue_insns = 10; |
| 880 | |
| 881 | /* Return nonzero if the given instruction OP can be part of the prologue |
| 882 | of a function and saves a parameter on the stack. FRAMEP should be |
| 883 | set if one of the previous instructions in the function has set the |
| 884 | Frame Pointer. */ |
| 885 | |
| 886 | static int |
| 887 | store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg) |
| 888 | { |
| 889 | /* Move parameters from argument registers to temporary register. */ |
| 890 | if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */ |
| 891 | { |
| 892 | /* Rx must be scratch register r0. */ |
| 893 | const int rx_regno = (op >> 16) & 31; |
| 894 | /* Ry: Only r3 - r10 are used for parameter passing. */ |
| 895 | const int ry_regno = GET_SRC_REG (op); |
| 896 | |
| 897 | if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10) |
| 898 | { |
| 899 | *r0_contains_arg = 1; |
| 900 | return 1; |
| 901 | } |
| 902 | else |
| 903 | return 0; |
| 904 | } |
| 905 | |
| 906 | /* Save a General Purpose Register on stack. */ |
| 907 | |
| 908 | if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */ |
| 909 | (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */ |
| 910 | { |
| 911 | /* Rx: Only r3 - r10 are used for parameter passing. */ |
| 912 | const int rx_regno = GET_SRC_REG (op); |
| 913 | |
| 914 | return (rx_regno >= 3 && rx_regno <= 10); |
| 915 | } |
| 916 | |
| 917 | /* Save a General Purpose Register on stack via the Frame Pointer. */ |
| 918 | |
| 919 | if (framep && |
| 920 | ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */ |
| 921 | (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */ |
| 922 | (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */ |
| 923 | { |
| 924 | /* Rx: Usually, only r3 - r10 are used for parameter passing. |
| 925 | However, the compiler sometimes uses r0 to hold an argument. */ |
| 926 | const int rx_regno = GET_SRC_REG (op); |
| 927 | |
| 928 | return ((rx_regno >= 3 && rx_regno <= 10) |
| 929 | || (rx_regno == 0 && *r0_contains_arg)); |
| 930 | } |
| 931 | |
| 932 | if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ |
| 933 | { |
| 934 | /* Only f2 - f8 are used for parameter passing. */ |
| 935 | const int src_regno = GET_SRC_REG (op); |
| 936 | |
| 937 | return (src_regno >= 2 && src_regno <= 8); |
| 938 | } |
| 939 | |
| 940 | if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */ |
| 941 | { |
| 942 | /* Only f2 - f8 are used for parameter passing. */ |
| 943 | const int src_regno = GET_SRC_REG (op); |
| 944 | |
| 945 | return (src_regno >= 2 && src_regno <= 8); |
| 946 | } |
| 947 | |
| 948 | /* Not an insn that saves a parameter on stack. */ |
| 949 | return 0; |
| 950 | } |
| 951 | |
| 952 | /* Assuming that INSN is a "bl" instruction located at PC, return |
| 953 | nonzero if the destination of the branch is a "blrl" instruction. |
| 954 | |
| 955 | This sequence is sometimes found in certain function prologues. |
| 956 | It allows the function to load the LR register with a value that |
| 957 | they can use to access PIC data using PC-relative offsets. */ |
| 958 | |
| 959 | static int |
| 960 | bl_to_blrl_insn_p (CORE_ADDR pc, int insn) |
| 961 | { |
| 962 | const int opcode = 18; |
| 963 | const CORE_ADDR dest = branch_dest (opcode, insn, pc, -1); |
| 964 | int dest_insn; |
| 965 | |
| 966 | if (dest == -1) |
| 967 | return 0; /* Should never happen, but just return zero to be safe. */ |
| 968 | |
| 969 | dest_insn = read_memory_integer (dest, 4); |
| 970 | if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */ |
| 971 | return 1; |
| 972 | |
| 973 | return 0; |
| 974 | } |
| 975 | |
| 976 | static CORE_ADDR |
| 977 | skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) |
| 978 | { |
| 979 | CORE_ADDR orig_pc = pc; |
| 980 | CORE_ADDR last_prologue_pc = pc; |
| 981 | CORE_ADDR li_found_pc = 0; |
| 982 | gdb_byte buf[4]; |
| 983 | unsigned long op; |
| 984 | long offset = 0; |
| 985 | long vr_saved_offset = 0; |
| 986 | int lr_reg = -1; |
| 987 | int cr_reg = -1; |
| 988 | int vr_reg = -1; |
| 989 | int ev_reg = -1; |
| 990 | long ev_offset = 0; |
| 991 | int vrsave_reg = -1; |
| 992 | int reg; |
| 993 | int framep = 0; |
| 994 | int minimal_toc_loaded = 0; |
| 995 | int prev_insn_was_prologue_insn = 1; |
| 996 | int num_skip_non_prologue_insns = 0; |
| 997 | int r0_contains_arg = 0; |
| 998 | const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch); |
| 999 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 1000 | |
| 1001 | memset (fdata, 0, sizeof (struct rs6000_framedata)); |
| 1002 | fdata->saved_gpr = -1; |
| 1003 | fdata->saved_fpr = -1; |
| 1004 | fdata->saved_vr = -1; |
| 1005 | fdata->saved_ev = -1; |
| 1006 | fdata->alloca_reg = -1; |
| 1007 | fdata->frameless = 1; |
| 1008 | fdata->nosavedpc = 1; |
| 1009 | |
| 1010 | for (;; pc += 4) |
| 1011 | { |
| 1012 | /* Sometimes it isn't clear if an instruction is a prologue |
| 1013 | instruction or not. When we encounter one of these ambiguous |
| 1014 | cases, we'll set prev_insn_was_prologue_insn to 0 (false). |
| 1015 | Otherwise, we'll assume that it really is a prologue instruction. */ |
| 1016 | if (prev_insn_was_prologue_insn) |
| 1017 | last_prologue_pc = pc; |
| 1018 | |
| 1019 | /* Stop scanning if we've hit the limit. */ |
| 1020 | if (pc >= lim_pc) |
| 1021 | break; |
| 1022 | |
| 1023 | prev_insn_was_prologue_insn = 1; |
| 1024 | |
| 1025 | /* Fetch the instruction and convert it to an integer. */ |
| 1026 | if (target_read_memory (pc, buf, 4)) |
| 1027 | break; |
| 1028 | op = extract_unsigned_integer (buf, 4); |
| 1029 | |
| 1030 | if ((op & 0xfc1fffff) == 0x7c0802a6) |
| 1031 | { /* mflr Rx */ |
| 1032 | /* Since shared library / PIC code, which needs to get its |
| 1033 | address at runtime, can appear to save more than one link |
| 1034 | register vis: |
| 1035 | |
| 1036 | *INDENT-OFF* |
| 1037 | stwu r1,-304(r1) |
| 1038 | mflr r3 |
| 1039 | bl 0xff570d0 (blrl) |
| 1040 | stw r30,296(r1) |
| 1041 | mflr r30 |
| 1042 | stw r31,300(r1) |
| 1043 | stw r3,308(r1); |
| 1044 | ... |
| 1045 | *INDENT-ON* |
| 1046 | |
| 1047 | remember just the first one, but skip over additional |
| 1048 | ones. */ |
| 1049 | if (lr_reg == -1) |
| 1050 | lr_reg = (op & 0x03e00000); |
| 1051 | if (lr_reg == 0) |
| 1052 | r0_contains_arg = 0; |
| 1053 | continue; |
| 1054 | } |
| 1055 | else if ((op & 0xfc1fffff) == 0x7c000026) |
| 1056 | { /* mfcr Rx */ |
| 1057 | cr_reg = (op & 0x03e00000); |
| 1058 | if (cr_reg == 0) |
| 1059 | r0_contains_arg = 0; |
| 1060 | continue; |
| 1061 | |
| 1062 | } |
| 1063 | else if ((op & 0xfc1f0000) == 0xd8010000) |
| 1064 | { /* stfd Rx,NUM(r1) */ |
| 1065 | reg = GET_SRC_REG (op); |
| 1066 | if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) |
| 1067 | { |
| 1068 | fdata->saved_fpr = reg; |
| 1069 | fdata->fpr_offset = SIGNED_SHORT (op) + offset; |
| 1070 | } |
| 1071 | continue; |
| 1072 | |
| 1073 | } |
| 1074 | else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ |
| 1075 | (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ |
| 1076 | (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ |
| 1077 | (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ |
| 1078 | { |
| 1079 | |
| 1080 | reg = GET_SRC_REG (op); |
| 1081 | if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) |
| 1082 | { |
| 1083 | fdata->saved_gpr = reg; |
| 1084 | if ((op & 0xfc1f0003) == 0xf8010000) |
| 1085 | op &= ~3UL; |
| 1086 | fdata->gpr_offset = SIGNED_SHORT (op) + offset; |
| 1087 | } |
| 1088 | continue; |
| 1089 | |
| 1090 | } |
| 1091 | else if ((op & 0xffff0000) == 0x60000000) |
| 1092 | { |
| 1093 | /* nop */ |
| 1094 | /* Allow nops in the prologue, but do not consider them to |
| 1095 | be part of the prologue unless followed by other prologue |
| 1096 | instructions. */ |
| 1097 | prev_insn_was_prologue_insn = 0; |
| 1098 | continue; |
| 1099 | |
| 1100 | } |
| 1101 | else if ((op & 0xffff0000) == 0x3c000000) |
| 1102 | { /* addis 0,0,NUM, used |
| 1103 | for >= 32k frames */ |
| 1104 | fdata->offset = (op & 0x0000ffff) << 16; |
| 1105 | fdata->frameless = 0; |
| 1106 | r0_contains_arg = 0; |
| 1107 | continue; |
| 1108 | |
| 1109 | } |
| 1110 | else if ((op & 0xffff0000) == 0x60000000) |
| 1111 | { /* ori 0,0,NUM, 2nd ha |
| 1112 | lf of >= 32k frames */ |
| 1113 | fdata->offset |= (op & 0x0000ffff); |
| 1114 | fdata->frameless = 0; |
| 1115 | r0_contains_arg = 0; |
| 1116 | continue; |
| 1117 | |
| 1118 | } |
| 1119 | else if (lr_reg >= 0 && |
| 1120 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ |
| 1121 | (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || |
| 1122 | /* stw Rx, NUM(r1) */ |
| 1123 | ((op & 0xffff0000) == (lr_reg | 0x90010000)) || |
| 1124 | /* stwu Rx, NUM(r1) */ |
| 1125 | ((op & 0xffff0000) == (lr_reg | 0x94010000)))) |
| 1126 | { /* where Rx == lr */ |
| 1127 | fdata->lr_offset = offset; |
| 1128 | fdata->nosavedpc = 0; |
| 1129 | /* Invalidate lr_reg, but don't set it to -1. |
| 1130 | That would mean that it had never been set. */ |
| 1131 | lr_reg = -2; |
| 1132 | if ((op & 0xfc000003) == 0xf8000000 || /* std */ |
| 1133 | (op & 0xfc000000) == 0x90000000) /* stw */ |
| 1134 | { |
| 1135 | /* Does not update r1, so add displacement to lr_offset. */ |
| 1136 | fdata->lr_offset += SIGNED_SHORT (op); |
| 1137 | } |
| 1138 | continue; |
| 1139 | |
| 1140 | } |
| 1141 | else if (cr_reg >= 0 && |
| 1142 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ |
| 1143 | (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || |
| 1144 | /* stw Rx, NUM(r1) */ |
| 1145 | ((op & 0xffff0000) == (cr_reg | 0x90010000)) || |
| 1146 | /* stwu Rx, NUM(r1) */ |
| 1147 | ((op & 0xffff0000) == (cr_reg | 0x94010000)))) |
| 1148 | { /* where Rx == cr */ |
| 1149 | fdata->cr_offset = offset; |
| 1150 | /* Invalidate cr_reg, but don't set it to -1. |
| 1151 | That would mean that it had never been set. */ |
| 1152 | cr_reg = -2; |
| 1153 | if ((op & 0xfc000003) == 0xf8000000 || |
| 1154 | (op & 0xfc000000) == 0x90000000) |
| 1155 | { |
| 1156 | /* Does not update r1, so add displacement to cr_offset. */ |
| 1157 | fdata->cr_offset += SIGNED_SHORT (op); |
| 1158 | } |
| 1159 | continue; |
| 1160 | |
| 1161 | } |
| 1162 | else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1) |
| 1163 | { |
| 1164 | /* bcl 20,xx,.+4 is used to get the current PC, with or without |
| 1165 | prediction bits. If the LR has already been saved, we can |
| 1166 | skip it. */ |
| 1167 | continue; |
| 1168 | } |
| 1169 | else if (op == 0x48000005) |
| 1170 | { /* bl .+4 used in |
| 1171 | -mrelocatable */ |
| 1172 | continue; |
| 1173 | |
| 1174 | } |
| 1175 | else if (op == 0x48000004) |
| 1176 | { /* b .+4 (xlc) */ |
| 1177 | break; |
| 1178 | |
| 1179 | } |
| 1180 | else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used |
| 1181 | in V.4 -mminimal-toc */ |
| 1182 | (op & 0xffff0000) == 0x3bde0000) |
| 1183 | { /* addi 30,30,foo@l */ |
| 1184 | continue; |
| 1185 | |
| 1186 | } |
| 1187 | else if ((op & 0xfc000001) == 0x48000001) |
| 1188 | { /* bl foo, |
| 1189 | to save fprs??? */ |
| 1190 | |
| 1191 | fdata->frameless = 0; |
| 1192 | |
| 1193 | /* If the return address has already been saved, we can skip |
| 1194 | calls to blrl (for PIC). */ |
| 1195 | if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op)) |
| 1196 | continue; |
| 1197 | |
| 1198 | /* Don't skip over the subroutine call if it is not within |
| 1199 | the first three instructions of the prologue and either |
| 1200 | we have no line table information or the line info tells |
| 1201 | us that the subroutine call is not part of the line |
| 1202 | associated with the prologue. */ |
| 1203 | if ((pc - orig_pc) > 8) |
| 1204 | { |
| 1205 | struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0); |
| 1206 | struct symtab_and_line this_sal = find_pc_line (pc, 0); |
| 1207 | |
| 1208 | if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line)) |
| 1209 | break; |
| 1210 | } |
| 1211 | |
| 1212 | op = read_memory_integer (pc + 4, 4); |
| 1213 | |
| 1214 | /* At this point, make sure this is not a trampoline |
| 1215 | function (a function that simply calls another functions, |
| 1216 | and nothing else). If the next is not a nop, this branch |
| 1217 | was part of the function prologue. */ |
| 1218 | |
| 1219 | if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ |
| 1220 | break; /* don't skip over |
| 1221 | this branch */ |
| 1222 | continue; |
| 1223 | |
| 1224 | } |
| 1225 | /* update stack pointer */ |
| 1226 | else if ((op & 0xfc1f0000) == 0x94010000) |
| 1227 | { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ |
| 1228 | fdata->frameless = 0; |
| 1229 | fdata->offset = SIGNED_SHORT (op); |
| 1230 | offset = fdata->offset; |
| 1231 | continue; |
| 1232 | } |
| 1233 | else if ((op & 0xfc1f016a) == 0x7c01016e) |
| 1234 | { /* stwux rX,r1,rY */ |
| 1235 | /* no way to figure out what r1 is going to be */ |
| 1236 | fdata->frameless = 0; |
| 1237 | offset = fdata->offset; |
| 1238 | continue; |
| 1239 | } |
| 1240 | else if ((op & 0xfc1f0003) == 0xf8010001) |
| 1241 | { /* stdu rX,NUM(r1) */ |
| 1242 | fdata->frameless = 0; |
| 1243 | fdata->offset = SIGNED_SHORT (op & ~3UL); |
| 1244 | offset = fdata->offset; |
| 1245 | continue; |
| 1246 | } |
| 1247 | else if ((op & 0xfc1f016a) == 0x7c01016a) |
| 1248 | { /* stdux rX,r1,rY */ |
| 1249 | /* no way to figure out what r1 is going to be */ |
| 1250 | fdata->frameless = 0; |
| 1251 | offset = fdata->offset; |
| 1252 | continue; |
| 1253 | } |
| 1254 | else if ((op & 0xffff0000) == 0x38210000) |
| 1255 | { /* addi r1,r1,SIMM */ |
| 1256 | fdata->frameless = 0; |
| 1257 | fdata->offset += SIGNED_SHORT (op); |
| 1258 | offset = fdata->offset; |
| 1259 | continue; |
| 1260 | } |
| 1261 | /* Load up minimal toc pointer. Do not treat an epilogue restore |
| 1262 | of r31 as a minimal TOC load. */ |
| 1263 | else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ |
| 1264 | (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ |
| 1265 | && !framep |
| 1266 | && !minimal_toc_loaded) |
| 1267 | { |
| 1268 | minimal_toc_loaded = 1; |
| 1269 | continue; |
| 1270 | |
| 1271 | /* move parameters from argument registers to local variable |
| 1272 | registers */ |
| 1273 | } |
| 1274 | else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ |
| 1275 | (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ |
| 1276 | (((op >> 21) & 31) <= 10) && |
| 1277 | ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */ |
| 1278 | { |
| 1279 | continue; |
| 1280 | |
| 1281 | /* store parameters in stack */ |
| 1282 | } |
| 1283 | /* Move parameters from argument registers to temporary register. */ |
| 1284 | else if (store_param_on_stack_p (op, framep, &r0_contains_arg)) |
| 1285 | { |
| 1286 | continue; |
| 1287 | |
| 1288 | /* Set up frame pointer */ |
| 1289 | } |
| 1290 | else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ |
| 1291 | || op == 0x7c3f0b78) |
| 1292 | { /* mr r31, r1 */ |
| 1293 | fdata->frameless = 0; |
| 1294 | framep = 1; |
| 1295 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); |
| 1296 | continue; |
| 1297 | |
| 1298 | /* Another way to set up the frame pointer. */ |
| 1299 | } |
| 1300 | else if ((op & 0xfc1fffff) == 0x38010000) |
| 1301 | { /* addi rX, r1, 0x0 */ |
| 1302 | fdata->frameless = 0; |
| 1303 | framep = 1; |
| 1304 | fdata->alloca_reg = (tdep->ppc_gp0_regnum |
| 1305 | + ((op & ~0x38010000) >> 21)); |
| 1306 | continue; |
| 1307 | } |
| 1308 | /* AltiVec related instructions. */ |
| 1309 | /* Store the vrsave register (spr 256) in another register for |
| 1310 | later manipulation, or load a register into the vrsave |
| 1311 | register. 2 instructions are used: mfvrsave and |
| 1312 | mtvrsave. They are shorthand notation for mfspr Rn, SPR256 |
| 1313 | and mtspr SPR256, Rn. */ |
| 1314 | /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 |
| 1315 | mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ |
| 1316 | else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ |
| 1317 | { |
| 1318 | vrsave_reg = GET_SRC_REG (op); |
| 1319 | continue; |
| 1320 | } |
| 1321 | else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ |
| 1322 | { |
| 1323 | continue; |
| 1324 | } |
| 1325 | /* Store the register where vrsave was saved to onto the stack: |
| 1326 | rS is the register where vrsave was stored in a previous |
| 1327 | instruction. */ |
| 1328 | /* 100100 sssss 00001 dddddddd dddddddd */ |
| 1329 | else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ |
| 1330 | { |
| 1331 | if (vrsave_reg == GET_SRC_REG (op)) |
| 1332 | { |
| 1333 | fdata->vrsave_offset = SIGNED_SHORT (op) + offset; |
| 1334 | vrsave_reg = -1; |
| 1335 | } |
| 1336 | continue; |
| 1337 | } |
| 1338 | /* Compute the new value of vrsave, by modifying the register |
| 1339 | where vrsave was saved to. */ |
| 1340 | else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ |
| 1341 | || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ |
| 1342 | { |
| 1343 | continue; |
| 1344 | } |
| 1345 | /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first |
| 1346 | in a pair of insns to save the vector registers on the |
| 1347 | stack. */ |
| 1348 | /* 001110 00000 00000 iiii iiii iiii iiii */ |
| 1349 | /* 001110 01110 00000 iiii iiii iiii iiii */ |
| 1350 | else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ |
| 1351 | || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ |
| 1352 | { |
| 1353 | if ((op & 0xffff0000) == 0x38000000) |
| 1354 | r0_contains_arg = 0; |
| 1355 | li_found_pc = pc; |
| 1356 | vr_saved_offset = SIGNED_SHORT (op); |
| 1357 | |
| 1358 | /* This insn by itself is not part of the prologue, unless |
| 1359 | if part of the pair of insns mentioned above. So do not |
| 1360 | record this insn as part of the prologue yet. */ |
| 1361 | prev_insn_was_prologue_insn = 0; |
| 1362 | } |
| 1363 | /* Store vector register S at (r31+r0) aligned to 16 bytes. */ |
| 1364 | /* 011111 sssss 11111 00000 00111001110 */ |
| 1365 | else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ |
| 1366 | { |
| 1367 | if (pc == (li_found_pc + 4)) |
| 1368 | { |
| 1369 | vr_reg = GET_SRC_REG (op); |
| 1370 | /* If this is the first vector reg to be saved, or if |
| 1371 | it has a lower number than others previously seen, |
| 1372 | reupdate the frame info. */ |
| 1373 | if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) |
| 1374 | { |
| 1375 | fdata->saved_vr = vr_reg; |
| 1376 | fdata->vr_offset = vr_saved_offset + offset; |
| 1377 | } |
| 1378 | vr_saved_offset = -1; |
| 1379 | vr_reg = -1; |
| 1380 | li_found_pc = 0; |
| 1381 | } |
| 1382 | } |
| 1383 | /* End AltiVec related instructions. */ |
| 1384 | |
| 1385 | /* Start BookE related instructions. */ |
| 1386 | /* Store gen register S at (r31+uimm). |
| 1387 | Any register less than r13 is volatile, so we don't care. */ |
| 1388 | /* 000100 sssss 11111 iiiii 01100100001 */ |
| 1389 | else if (arch_info->mach == bfd_mach_ppc_e500 |
| 1390 | && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ |
| 1391 | { |
| 1392 | if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ |
| 1393 | { |
| 1394 | unsigned int imm; |
| 1395 | ev_reg = GET_SRC_REG (op); |
| 1396 | imm = (op >> 11) & 0x1f; |
| 1397 | ev_offset = imm * 8; |
| 1398 | /* If this is the first vector reg to be saved, or if |
| 1399 | it has a lower number than others previously seen, |
| 1400 | reupdate the frame info. */ |
| 1401 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) |
| 1402 | { |
| 1403 | fdata->saved_ev = ev_reg; |
| 1404 | fdata->ev_offset = ev_offset + offset; |
| 1405 | } |
| 1406 | } |
| 1407 | continue; |
| 1408 | } |
| 1409 | /* Store gen register rS at (r1+rB). */ |
| 1410 | /* 000100 sssss 00001 bbbbb 01100100000 */ |
| 1411 | else if (arch_info->mach == bfd_mach_ppc_e500 |
| 1412 | && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ |
| 1413 | { |
| 1414 | if (pc == (li_found_pc + 4)) |
| 1415 | { |
| 1416 | ev_reg = GET_SRC_REG (op); |
| 1417 | /* If this is the first vector reg to be saved, or if |
| 1418 | it has a lower number than others previously seen, |
| 1419 | reupdate the frame info. */ |
| 1420 | /* We know the contents of rB from the previous instruction. */ |
| 1421 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) |
| 1422 | { |
| 1423 | fdata->saved_ev = ev_reg; |
| 1424 | fdata->ev_offset = vr_saved_offset + offset; |
| 1425 | } |
| 1426 | vr_saved_offset = -1; |
| 1427 | ev_reg = -1; |
| 1428 | li_found_pc = 0; |
| 1429 | } |
| 1430 | continue; |
| 1431 | } |
| 1432 | /* Store gen register r31 at (rA+uimm). */ |
| 1433 | /* 000100 11111 aaaaa iiiii 01100100001 */ |
| 1434 | else if (arch_info->mach == bfd_mach_ppc_e500 |
| 1435 | && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ |
| 1436 | { |
| 1437 | /* Wwe know that the source register is 31 already, but |
| 1438 | it can't hurt to compute it. */ |
| 1439 | ev_reg = GET_SRC_REG (op); |
| 1440 | ev_offset = ((op >> 11) & 0x1f) * 8; |
| 1441 | /* If this is the first vector reg to be saved, or if |
| 1442 | it has a lower number than others previously seen, |
| 1443 | reupdate the frame info. */ |
| 1444 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) |
| 1445 | { |
| 1446 | fdata->saved_ev = ev_reg; |
| 1447 | fdata->ev_offset = ev_offset + offset; |
| 1448 | } |
| 1449 | |
| 1450 | continue; |
| 1451 | } |
| 1452 | /* Store gen register S at (r31+r0). |
| 1453 | Store param on stack when offset from SP bigger than 4 bytes. */ |
| 1454 | /* 000100 sssss 11111 00000 01100100000 */ |
| 1455 | else if (arch_info->mach == bfd_mach_ppc_e500 |
| 1456 | && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ |
| 1457 | { |
| 1458 | if (pc == (li_found_pc + 4)) |
| 1459 | { |
| 1460 | if ((op & 0x03e00000) >= 0x01a00000) |
| 1461 | { |
| 1462 | ev_reg = GET_SRC_REG (op); |
| 1463 | /* If this is the first vector reg to be saved, or if |
| 1464 | it has a lower number than others previously seen, |
| 1465 | reupdate the frame info. */ |
| 1466 | /* We know the contents of r0 from the previous |
| 1467 | instruction. */ |
| 1468 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) |
| 1469 | { |
| 1470 | fdata->saved_ev = ev_reg; |
| 1471 | fdata->ev_offset = vr_saved_offset + offset; |
| 1472 | } |
| 1473 | ev_reg = -1; |
| 1474 | } |
| 1475 | vr_saved_offset = -1; |
| 1476 | li_found_pc = 0; |
| 1477 | continue; |
| 1478 | } |
| 1479 | } |
| 1480 | /* End BookE related instructions. */ |
| 1481 | |
| 1482 | else |
| 1483 | { |
| 1484 | /* Not a recognized prologue instruction. |
| 1485 | Handle optimizer code motions into the prologue by continuing |
| 1486 | the search if we have no valid frame yet or if the return |
| 1487 | address is not yet saved in the frame. */ |
| 1488 | if (fdata->frameless == 0 && fdata->nosavedpc == 0) |
| 1489 | break; |
| 1490 | |
| 1491 | if (op == 0x4e800020 /* blr */ |
| 1492 | || op == 0x4e800420) /* bctr */ |
| 1493 | /* Do not scan past epilogue in frameless functions or |
| 1494 | trampolines. */ |
| 1495 | break; |
| 1496 | if ((op & 0xf4000000) == 0x40000000) /* bxx */ |
| 1497 | /* Never skip branches. */ |
| 1498 | break; |
| 1499 | |
| 1500 | if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) |
| 1501 | /* Do not scan too many insns, scanning insns is expensive with |
| 1502 | remote targets. */ |
| 1503 | break; |
| 1504 | |
| 1505 | /* Continue scanning. */ |
| 1506 | prev_insn_was_prologue_insn = 0; |
| 1507 | continue; |
| 1508 | } |
| 1509 | } |
| 1510 | |
| 1511 | #if 0 |
| 1512 | /* I have problems with skipping over __main() that I need to address |
| 1513 | * sometime. Previously, I used to use misc_function_vector which |
| 1514 | * didn't work as well as I wanted to be. -MGO */ |
| 1515 | |
| 1516 | /* If the first thing after skipping a prolog is a branch to a function, |
| 1517 | this might be a call to an initializer in main(), introduced by gcc2. |
| 1518 | We'd like to skip over it as well. Fortunately, xlc does some extra |
| 1519 | work before calling a function right after a prologue, thus we can |
| 1520 | single out such gcc2 behaviour. */ |
| 1521 | |
| 1522 | |
| 1523 | if ((op & 0xfc000001) == 0x48000001) |
| 1524 | { /* bl foo, an initializer function? */ |
| 1525 | op = read_memory_integer (pc + 4, 4); |
| 1526 | |
| 1527 | if (op == 0x4def7b82) |
| 1528 | { /* cror 0xf, 0xf, 0xf (nop) */ |
| 1529 | |
| 1530 | /* Check and see if we are in main. If so, skip over this |
| 1531 | initializer function as well. */ |
| 1532 | |
| 1533 | tmp = find_pc_misc_function (pc); |
| 1534 | if (tmp >= 0 |
| 1535 | && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) |
| 1536 | return pc + 8; |
| 1537 | } |
| 1538 | } |
| 1539 | #endif /* 0 */ |
| 1540 | |
| 1541 | fdata->offset = -fdata->offset; |
| 1542 | return last_prologue_pc; |
| 1543 | } |
| 1544 | |
| 1545 | |
| 1546 | /************************************************************************* |
| 1547 | Support for creating pushing a dummy frame into the stack, and popping |
| 1548 | frames, etc. |
| 1549 | *************************************************************************/ |
| 1550 | |
| 1551 | |
| 1552 | /* All the ABI's require 16 byte alignment. */ |
| 1553 | static CORE_ADDR |
| 1554 | rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 1555 | { |
| 1556 | return (addr & -16); |
| 1557 | } |
| 1558 | |
| 1559 | /* Pass the arguments in either registers, or in the stack. In RS/6000, |
| 1560 | the first eight words of the argument list (that might be less than |
| 1561 | eight parameters if some parameters occupy more than one word) are |
| 1562 | passed in r3..r10 registers. float and double parameters are |
| 1563 | passed in fpr's, in addition to that. Rest of the parameters if any |
| 1564 | are passed in user stack. There might be cases in which half of the |
| 1565 | parameter is copied into registers, the other half is pushed into |
| 1566 | stack. |
| 1567 | |
| 1568 | Stack must be aligned on 64-bit boundaries when synthesizing |
| 1569 | function calls. |
| 1570 | |
| 1571 | If the function is returning a structure, then the return address is passed |
| 1572 | in r3, then the first 7 words of the parameters can be passed in registers, |
| 1573 | starting from r4. */ |
| 1574 | |
| 1575 | static CORE_ADDR |
| 1576 | rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 1577 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 1578 | int nargs, struct value **args, CORE_ADDR sp, |
| 1579 | int struct_return, CORE_ADDR struct_addr) |
| 1580 | { |
| 1581 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 1582 | int ii; |
| 1583 | int len = 0; |
| 1584 | int argno; /* current argument number */ |
| 1585 | int argbytes; /* current argument byte */ |
| 1586 | gdb_byte tmp_buffer[50]; |
| 1587 | int f_argno = 0; /* current floating point argno */ |
| 1588 | int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; |
| 1589 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
| 1590 | |
| 1591 | struct value *arg = 0; |
| 1592 | struct type *type; |
| 1593 | |
| 1594 | ULONGEST saved_sp; |
| 1595 | |
| 1596 | /* The calling convention this function implements assumes the |
| 1597 | processor has floating-point registers. We shouldn't be using it |
| 1598 | on PPC variants that lack them. */ |
| 1599 | gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); |
| 1600 | |
| 1601 | /* The first eight words of ther arguments are passed in registers. |
| 1602 | Copy them appropriately. */ |
| 1603 | ii = 0; |
| 1604 | |
| 1605 | /* If the function is returning a `struct', then the first word |
| 1606 | (which will be passed in r3) is used for struct return address. |
| 1607 | In that case we should advance one word and start from r4 |
| 1608 | register to copy parameters. */ |
| 1609 | if (struct_return) |
| 1610 | { |
| 1611 | regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, |
| 1612 | struct_addr); |
| 1613 | ii++; |
| 1614 | } |
| 1615 | |
| 1616 | /* |
| 1617 | effectively indirect call... gcc does... |
| 1618 | |
| 1619 | return_val example( float, int); |
| 1620 | |
| 1621 | eabi: |
| 1622 | float in fp0, int in r3 |
| 1623 | offset of stack on overflow 8/16 |
| 1624 | for varargs, must go by type. |
| 1625 | power open: |
| 1626 | float in r3&r4, int in r5 |
| 1627 | offset of stack on overflow different |
| 1628 | both: |
| 1629 | return in r3 or f0. If no float, must study how gcc emulates floats; |
| 1630 | pay attention to arg promotion. |
| 1631 | User may have to cast\args to handle promotion correctly |
| 1632 | since gdb won't know if prototype supplied or not. |
| 1633 | */ |
| 1634 | |
| 1635 | for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii) |
| 1636 | { |
| 1637 | int reg_size = register_size (current_gdbarch, ii + 3); |
| 1638 | |
| 1639 | arg = args[argno]; |
| 1640 | type = check_typedef (value_type (arg)); |
| 1641 | len = TYPE_LENGTH (type); |
| 1642 | |
| 1643 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
| 1644 | { |
| 1645 | |
| 1646 | /* Floating point arguments are passed in fpr's, as well as gpr's. |
| 1647 | There are 13 fpr's reserved for passing parameters. At this point |
| 1648 | there is no way we would run out of them. */ |
| 1649 | |
| 1650 | gdb_assert (len <= 8); |
| 1651 | |
| 1652 | regcache_cooked_write (regcache, |
| 1653 | tdep->ppc_fp0_regnum + 1 + f_argno, |
| 1654 | value_contents (arg)); |
| 1655 | ++f_argno; |
| 1656 | } |
| 1657 | |
| 1658 | if (len > reg_size) |
| 1659 | { |
| 1660 | |
| 1661 | /* Argument takes more than one register. */ |
| 1662 | while (argbytes < len) |
| 1663 | { |
| 1664 | gdb_byte word[MAX_REGISTER_SIZE]; |
| 1665 | memset (word, 0, reg_size); |
| 1666 | memcpy (word, |
| 1667 | ((char *) value_contents (arg)) + argbytes, |
| 1668 | (len - argbytes) > reg_size |
| 1669 | ? reg_size : len - argbytes); |
| 1670 | regcache_cooked_write (regcache, |
| 1671 | tdep->ppc_gp0_regnum + 3 + ii, |
| 1672 | word); |
| 1673 | ++ii, argbytes += reg_size; |
| 1674 | |
| 1675 | if (ii >= 8) |
| 1676 | goto ran_out_of_registers_for_arguments; |
| 1677 | } |
| 1678 | argbytes = 0; |
| 1679 | --ii; |
| 1680 | } |
| 1681 | else |
| 1682 | { |
| 1683 | /* Argument can fit in one register. No problem. */ |
| 1684 | int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0; |
| 1685 | gdb_byte word[MAX_REGISTER_SIZE]; |
| 1686 | |
| 1687 | memset (word, 0, reg_size); |
| 1688 | memcpy (word, value_contents (arg), len); |
| 1689 | regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word); |
| 1690 | } |
| 1691 | ++argno; |
| 1692 | } |
| 1693 | |
| 1694 | ran_out_of_registers_for_arguments: |
| 1695 | |
| 1696 | regcache_cooked_read_unsigned (regcache, SP_REGNUM, &saved_sp); |
| 1697 | |
| 1698 | /* Location for 8 parameters are always reserved. */ |
| 1699 | sp -= wordsize * 8; |
| 1700 | |
| 1701 | /* Another six words for back chain, TOC register, link register, etc. */ |
| 1702 | sp -= wordsize * 6; |
| 1703 | |
| 1704 | /* Stack pointer must be quadword aligned. */ |
| 1705 | sp &= -16; |
| 1706 | |
| 1707 | /* If there are more arguments, allocate space for them in |
| 1708 | the stack, then push them starting from the ninth one. */ |
| 1709 | |
| 1710 | if ((argno < nargs) || argbytes) |
| 1711 | { |
| 1712 | int space = 0, jj; |
| 1713 | |
| 1714 | if (argbytes) |
| 1715 | { |
| 1716 | space += ((len - argbytes + 3) & -4); |
| 1717 | jj = argno + 1; |
| 1718 | } |
| 1719 | else |
| 1720 | jj = argno; |
| 1721 | |
| 1722 | for (; jj < nargs; ++jj) |
| 1723 | { |
| 1724 | struct value *val = args[jj]; |
| 1725 | space += ((TYPE_LENGTH (value_type (val))) + 3) & -4; |
| 1726 | } |
| 1727 | |
| 1728 | /* Add location required for the rest of the parameters. */ |
| 1729 | space = (space + 15) & -16; |
| 1730 | sp -= space; |
| 1731 | |
| 1732 | /* This is another instance we need to be concerned about |
| 1733 | securing our stack space. If we write anything underneath %sp |
| 1734 | (r1), we might conflict with the kernel who thinks he is free |
| 1735 | to use this area. So, update %sp first before doing anything |
| 1736 | else. */ |
| 1737 | |
| 1738 | regcache_raw_write_signed (regcache, SP_REGNUM, sp); |
| 1739 | |
| 1740 | /* If the last argument copied into the registers didn't fit there |
| 1741 | completely, push the rest of it into stack. */ |
| 1742 | |
| 1743 | if (argbytes) |
| 1744 | { |
| 1745 | write_memory (sp + 24 + (ii * 4), |
| 1746 | value_contents (arg) + argbytes, |
| 1747 | len - argbytes); |
| 1748 | ++argno; |
| 1749 | ii += ((len - argbytes + 3) & -4) / 4; |
| 1750 | } |
| 1751 | |
| 1752 | /* Push the rest of the arguments into stack. */ |
| 1753 | for (; argno < nargs; ++argno) |
| 1754 | { |
| 1755 | |
| 1756 | arg = args[argno]; |
| 1757 | type = check_typedef (value_type (arg)); |
| 1758 | len = TYPE_LENGTH (type); |
| 1759 | |
| 1760 | |
| 1761 | /* Float types should be passed in fpr's, as well as in the |
| 1762 | stack. */ |
| 1763 | if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13) |
| 1764 | { |
| 1765 | |
| 1766 | gdb_assert (len <= 8); |
| 1767 | |
| 1768 | regcache_cooked_write (regcache, |
| 1769 | tdep->ppc_fp0_regnum + 1 + f_argno, |
| 1770 | value_contents (arg)); |
| 1771 | ++f_argno; |
| 1772 | } |
| 1773 | |
| 1774 | write_memory (sp + 24 + (ii * 4), value_contents (arg), len); |
| 1775 | ii += ((len + 3) & -4) / 4; |
| 1776 | } |
| 1777 | } |
| 1778 | |
| 1779 | /* Set the stack pointer. According to the ABI, the SP is meant to |
| 1780 | be set _before_ the corresponding stack space is used. On AIX, |
| 1781 | this even applies when the target has been completely stopped! |
| 1782 | Not doing this can lead to conflicts with the kernel which thinks |
| 1783 | that it still has control over this not-yet-allocated stack |
| 1784 | region. */ |
| 1785 | regcache_raw_write_signed (regcache, SP_REGNUM, sp); |
| 1786 | |
| 1787 | /* Set back chain properly. */ |
| 1788 | store_unsigned_integer (tmp_buffer, wordsize, saved_sp); |
| 1789 | write_memory (sp, tmp_buffer, wordsize); |
| 1790 | |
| 1791 | /* Point the inferior function call's return address at the dummy's |
| 1792 | breakpoint. */ |
| 1793 | regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr); |
| 1794 | |
| 1795 | /* Set the TOC register, get the value from the objfile reader |
| 1796 | which, in turn, gets it from the VMAP table. */ |
| 1797 | if (rs6000_find_toc_address_hook != NULL) |
| 1798 | { |
| 1799 | CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr); |
| 1800 | regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue); |
| 1801 | } |
| 1802 | |
| 1803 | target_store_registers (regcache, -1); |
| 1804 | return sp; |
| 1805 | } |
| 1806 | |
| 1807 | static enum return_value_convention |
| 1808 | rs6000_return_value (struct gdbarch *gdbarch, struct type *valtype, |
| 1809 | struct regcache *regcache, gdb_byte *readbuf, |
| 1810 | const gdb_byte *writebuf) |
| 1811 | { |
| 1812 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 1813 | gdb_byte buf[8]; |
| 1814 | |
| 1815 | /* The calling convention this function implements assumes the |
| 1816 | processor has floating-point registers. We shouldn't be using it |
| 1817 | on PowerPC variants that lack them. */ |
| 1818 | gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); |
| 1819 | |
| 1820 | /* AltiVec extension: Functions that declare a vector data type as a |
| 1821 | return value place that return value in VR2. */ |
| 1822 | if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY && TYPE_VECTOR (valtype) |
| 1823 | && TYPE_LENGTH (valtype) == 16) |
| 1824 | { |
| 1825 | if (readbuf) |
| 1826 | regcache_cooked_read (regcache, tdep->ppc_vr0_regnum + 2, readbuf); |
| 1827 | if (writebuf) |
| 1828 | regcache_cooked_write (regcache, tdep->ppc_vr0_regnum + 2, writebuf); |
| 1829 | |
| 1830 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 1831 | } |
| 1832 | |
| 1833 | /* If the called subprogram returns an aggregate, there exists an |
| 1834 | implicit first argument, whose value is the address of a caller- |
| 1835 | allocated buffer into which the callee is assumed to store its |
| 1836 | return value. All explicit parameters are appropriately |
| 1837 | relabeled. */ |
| 1838 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
| 1839 | || TYPE_CODE (valtype) == TYPE_CODE_UNION |
| 1840 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) |
| 1841 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 1842 | |
| 1843 | /* Scalar floating-point values are returned in FPR1 for float or |
| 1844 | double, and in FPR1:FPR2 for quadword precision. Fortran |
| 1845 | complex*8 and complex*16 are returned in FPR1:FPR2, and |
| 1846 | complex*32 is returned in FPR1:FPR4. */ |
| 1847 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
| 1848 | && (TYPE_LENGTH (valtype) == 4 || TYPE_LENGTH (valtype) == 8)) |
| 1849 | { |
| 1850 | struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum); |
| 1851 | gdb_byte regval[8]; |
| 1852 | |
| 1853 | /* FIXME: kettenis/2007-01-01: Add support for quadword |
| 1854 | precision and complex. */ |
| 1855 | |
| 1856 | if (readbuf) |
| 1857 | { |
| 1858 | regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1, regval); |
| 1859 | convert_typed_floating (regval, regtype, readbuf, valtype); |
| 1860 | } |
| 1861 | if (writebuf) |
| 1862 | { |
| 1863 | convert_typed_floating (writebuf, valtype, regval, regtype); |
| 1864 | regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1, regval); |
| 1865 | } |
| 1866 | |
| 1867 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 1868 | } |
| 1869 | |
| 1870 | /* Values of the types int, long, short, pointer, and char (length |
| 1871 | is less than or equal to four bytes), as well as bit values of |
| 1872 | lengths less than or equal to 32 bits, must be returned right |
| 1873 | justified in GPR3 with signed values sign extended and unsigned |
| 1874 | values zero extended, as necessary. */ |
| 1875 | if (TYPE_LENGTH (valtype) <= tdep->wordsize) |
| 1876 | { |
| 1877 | if (readbuf) |
| 1878 | { |
| 1879 | ULONGEST regval; |
| 1880 | |
| 1881 | /* For reading we don't have to worry about sign extension. */ |
| 1882 | regcache_cooked_read_unsigned (regcache, tdep->ppc_gp0_regnum + 3, |
| 1883 | ®val); |
| 1884 | store_unsigned_integer (readbuf, TYPE_LENGTH (valtype), regval); |
| 1885 | } |
| 1886 | if (writebuf) |
| 1887 | { |
| 1888 | /* For writing, use unpack_long since that should handle any |
| 1889 | required sign extension. */ |
| 1890 | regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, |
| 1891 | unpack_long (valtype, writebuf)); |
| 1892 | } |
| 1893 | |
| 1894 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 1895 | } |
| 1896 | |
| 1897 | /* Eight-byte non-floating-point scalar values must be returned in |
| 1898 | GPR3:GPR4. */ |
| 1899 | |
| 1900 | if (TYPE_LENGTH (valtype) == 8) |
| 1901 | { |
| 1902 | gdb_assert (TYPE_CODE (valtype) != TYPE_CODE_FLT); |
| 1903 | gdb_assert (tdep->wordsize == 4); |
| 1904 | |
| 1905 | if (readbuf) |
| 1906 | { |
| 1907 | gdb_byte regval[8]; |
| 1908 | |
| 1909 | regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3, regval); |
| 1910 | regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 4, |
| 1911 | regval + 4); |
| 1912 | memcpy (readbuf, regval, 8); |
| 1913 | } |
| 1914 | if (writebuf) |
| 1915 | { |
| 1916 | regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3, writebuf); |
| 1917 | regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4, |
| 1918 | writebuf + 4); |
| 1919 | } |
| 1920 | |
| 1921 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 1922 | } |
| 1923 | |
| 1924 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 1925 | } |
| 1926 | |
| 1927 | /* Return whether handle_inferior_event() should proceed through code |
| 1928 | starting at PC in function NAME when stepping. |
| 1929 | |
| 1930 | The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to |
| 1931 | handle memory references that are too distant to fit in instructions |
| 1932 | generated by the compiler. For example, if 'foo' in the following |
| 1933 | instruction: |
| 1934 | |
| 1935 | lwz r9,foo(r2) |
| 1936 | |
| 1937 | is greater than 32767, the linker might replace the lwz with a branch to |
| 1938 | somewhere in @FIX1 that does the load in 2 instructions and then branches |
| 1939 | back to where execution should continue. |
| 1940 | |
| 1941 | GDB should silently step over @FIX code, just like AIX dbx does. |
| 1942 | Unfortunately, the linker uses the "b" instruction for the |
| 1943 | branches, meaning that the link register doesn't get set. |
| 1944 | Therefore, GDB's usual step_over_function () mechanism won't work. |
| 1945 | |
| 1946 | Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and |
| 1947 | SKIP_TRAMPOLINE_CODE hooks in handle_inferior_event() to skip past |
| 1948 | @FIX code. */ |
| 1949 | |
| 1950 | int |
| 1951 | rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name) |
| 1952 | { |
| 1953 | return name && !strncmp (name, "@FIX", 4); |
| 1954 | } |
| 1955 | |
| 1956 | /* Skip code that the user doesn't want to see when stepping: |
| 1957 | |
| 1958 | 1. Indirect function calls use a piece of trampoline code to do context |
| 1959 | switching, i.e. to set the new TOC table. Skip such code if we are on |
| 1960 | its first instruction (as when we have single-stepped to here). |
| 1961 | |
| 1962 | 2. Skip shared library trampoline code (which is different from |
| 1963 | indirect function call trampolines). |
| 1964 | |
| 1965 | 3. Skip bigtoc fixup code. |
| 1966 | |
| 1967 | Result is desired PC to step until, or NULL if we are not in |
| 1968 | code that should be skipped. */ |
| 1969 | |
| 1970 | CORE_ADDR |
| 1971 | rs6000_skip_trampoline_code (CORE_ADDR pc) |
| 1972 | { |
| 1973 | unsigned int ii, op; |
| 1974 | int rel; |
| 1975 | CORE_ADDR solib_target_pc; |
| 1976 | struct minimal_symbol *msymbol; |
| 1977 | |
| 1978 | static unsigned trampoline_code[] = |
| 1979 | { |
| 1980 | 0x800b0000, /* l r0,0x0(r11) */ |
| 1981 | 0x90410014, /* st r2,0x14(r1) */ |
| 1982 | 0x7c0903a6, /* mtctr r0 */ |
| 1983 | 0x804b0004, /* l r2,0x4(r11) */ |
| 1984 | 0x816b0008, /* l r11,0x8(r11) */ |
| 1985 | 0x4e800420, /* bctr */ |
| 1986 | 0x4e800020, /* br */ |
| 1987 | 0 |
| 1988 | }; |
| 1989 | |
| 1990 | /* Check for bigtoc fixup code. */ |
| 1991 | msymbol = lookup_minimal_symbol_by_pc (pc); |
| 1992 | if (msymbol |
| 1993 | && rs6000_in_solib_return_trampoline (pc, |
| 1994 | DEPRECATED_SYMBOL_NAME (msymbol))) |
| 1995 | { |
| 1996 | /* Double-check that the third instruction from PC is relative "b". */ |
| 1997 | op = read_memory_integer (pc + 8, 4); |
| 1998 | if ((op & 0xfc000003) == 0x48000000) |
| 1999 | { |
| 2000 | /* Extract bits 6-29 as a signed 24-bit relative word address and |
| 2001 | add it to the containing PC. */ |
| 2002 | rel = ((int)(op << 6) >> 6); |
| 2003 | return pc + 8 + rel; |
| 2004 | } |
| 2005 | } |
| 2006 | |
| 2007 | /* If pc is in a shared library trampoline, return its target. */ |
| 2008 | solib_target_pc = find_solib_trampoline_target (pc); |
| 2009 | if (solib_target_pc) |
| 2010 | return solib_target_pc; |
| 2011 | |
| 2012 | for (ii = 0; trampoline_code[ii]; ++ii) |
| 2013 | { |
| 2014 | op = read_memory_integer (pc + (ii * 4), 4); |
| 2015 | if (op != trampoline_code[ii]) |
| 2016 | return 0; |
| 2017 | } |
| 2018 | ii = read_register (11); /* r11 holds destination addr */ |
| 2019 | pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */ |
| 2020 | return pc; |
| 2021 | } |
| 2022 | |
| 2023 | /* Return the size of register REG when words are WORDSIZE bytes long. If REG |
| 2024 | isn't available with that word size, return 0. */ |
| 2025 | |
| 2026 | static int |
| 2027 | regsize (const struct reg *reg, int wordsize) |
| 2028 | { |
| 2029 | return wordsize == 8 ? reg->sz64 : reg->sz32; |
| 2030 | } |
| 2031 | |
| 2032 | /* Return the name of register number N, or null if no such register exists |
| 2033 | in the current architecture. */ |
| 2034 | |
| 2035 | static const char * |
| 2036 | rs6000_register_name (int n) |
| 2037 | { |
| 2038 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 2039 | const struct reg *reg = tdep->regs + n; |
| 2040 | |
| 2041 | if (!regsize (reg, tdep->wordsize)) |
| 2042 | return NULL; |
| 2043 | return reg->name; |
| 2044 | } |
| 2045 | |
| 2046 | /* Return the GDB type object for the "standard" data type |
| 2047 | of data in register N. */ |
| 2048 | |
| 2049 | static struct type * |
| 2050 | rs6000_register_type (struct gdbarch *gdbarch, int n) |
| 2051 | { |
| 2052 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2053 | const struct reg *reg = tdep->regs + n; |
| 2054 | |
| 2055 | if (reg->fpr) |
| 2056 | return builtin_type_double; |
| 2057 | else |
| 2058 | { |
| 2059 | int size = regsize (reg, tdep->wordsize); |
| 2060 | switch (size) |
| 2061 | { |
| 2062 | case 0: |
| 2063 | return builtin_type_int0; |
| 2064 | case 4: |
| 2065 | return builtin_type_uint32; |
| 2066 | case 8: |
| 2067 | if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum) |
| 2068 | return builtin_type_vec64; |
| 2069 | else |
| 2070 | return builtin_type_uint64; |
| 2071 | break; |
| 2072 | case 16: |
| 2073 | return builtin_type_vec128; |
| 2074 | break; |
| 2075 | default: |
| 2076 | internal_error (__FILE__, __LINE__, _("Register %d size %d unknown"), |
| 2077 | n, size); |
| 2078 | } |
| 2079 | } |
| 2080 | } |
| 2081 | |
| 2082 | /* Is REGNUM a member of REGGROUP? */ |
| 2083 | static int |
| 2084 | rs6000_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
| 2085 | struct reggroup *group) |
| 2086 | { |
| 2087 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2088 | int float_p; |
| 2089 | int vector_p; |
| 2090 | int general_p; |
| 2091 | |
| 2092 | if (REGISTER_NAME (regnum) == NULL |
| 2093 | || *REGISTER_NAME (regnum) == '\0') |
| 2094 | return 0; |
| 2095 | if (group == all_reggroup) |
| 2096 | return 1; |
| 2097 | |
| 2098 | float_p = (regnum == tdep->ppc_fpscr_regnum |
| 2099 | || (regnum >= tdep->ppc_fp0_regnum |
| 2100 | && regnum < tdep->ppc_fp0_regnum + 32)); |
| 2101 | if (group == float_reggroup) |
| 2102 | return float_p; |
| 2103 | |
| 2104 | vector_p = ((tdep->ppc_vr0_regnum >= 0 |
| 2105 | && regnum >= tdep->ppc_vr0_regnum |
| 2106 | && regnum < tdep->ppc_vr0_regnum + 32) |
| 2107 | || (tdep->ppc_ev0_regnum >= 0 |
| 2108 | && regnum >= tdep->ppc_ev0_regnum |
| 2109 | && regnum < tdep->ppc_ev0_regnum + 32) |
| 2110 | || regnum == tdep->ppc_vrsave_regnum - 1 /* vscr */ |
| 2111 | || regnum == tdep->ppc_vrsave_regnum |
| 2112 | || regnum == tdep->ppc_acc_regnum |
| 2113 | || regnum == tdep->ppc_spefscr_regnum); |
| 2114 | if (group == vector_reggroup) |
| 2115 | return vector_p; |
| 2116 | |
| 2117 | /* Note that PS aka MSR isn't included - it's a system register (and |
| 2118 | besides, due to GCC's CFI foobar you do not want to restore |
| 2119 | it). */ |
| 2120 | general_p = ((regnum >= tdep->ppc_gp0_regnum |
| 2121 | && regnum < tdep->ppc_gp0_regnum + 32) |
| 2122 | || regnum == tdep->ppc_toc_regnum |
| 2123 | || regnum == tdep->ppc_cr_regnum |
| 2124 | || regnum == tdep->ppc_lr_regnum |
| 2125 | || regnum == tdep->ppc_ctr_regnum |
| 2126 | || regnum == tdep->ppc_xer_regnum |
| 2127 | || regnum == PC_REGNUM); |
| 2128 | if (group == general_reggroup) |
| 2129 | return general_p; |
| 2130 | |
| 2131 | if (group == save_reggroup || group == restore_reggroup) |
| 2132 | return general_p || vector_p || float_p; |
| 2133 | |
| 2134 | return 0; |
| 2135 | } |
| 2136 | |
| 2137 | /* The register format for RS/6000 floating point registers is always |
| 2138 | double, we need a conversion if the memory format is float. */ |
| 2139 | |
| 2140 | static int |
| 2141 | rs6000_convert_register_p (int regnum, struct type *type) |
| 2142 | { |
| 2143 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; |
| 2144 | |
| 2145 | return (reg->fpr |
| 2146 | && TYPE_CODE (type) == TYPE_CODE_FLT |
| 2147 | && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double)); |
| 2148 | } |
| 2149 | |
| 2150 | static void |
| 2151 | rs6000_register_to_value (struct frame_info *frame, |
| 2152 | int regnum, |
| 2153 | struct type *type, |
| 2154 | gdb_byte *to) |
| 2155 | { |
| 2156 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; |
| 2157 | gdb_byte from[MAX_REGISTER_SIZE]; |
| 2158 | |
| 2159 | gdb_assert (reg->fpr); |
| 2160 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); |
| 2161 | |
| 2162 | get_frame_register (frame, regnum, from); |
| 2163 | convert_typed_floating (from, builtin_type_double, to, type); |
| 2164 | } |
| 2165 | |
| 2166 | static void |
| 2167 | rs6000_value_to_register (struct frame_info *frame, |
| 2168 | int regnum, |
| 2169 | struct type *type, |
| 2170 | const gdb_byte *from) |
| 2171 | { |
| 2172 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; |
| 2173 | gdb_byte to[MAX_REGISTER_SIZE]; |
| 2174 | |
| 2175 | gdb_assert (reg->fpr); |
| 2176 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); |
| 2177 | |
| 2178 | convert_typed_floating (from, type, to, builtin_type_double); |
| 2179 | put_frame_register (frame, regnum, to); |
| 2180 | } |
| 2181 | |
| 2182 | /* Move SPE vector register values between a 64-bit buffer and the two |
| 2183 | 32-bit raw register halves in a regcache. This function handles |
| 2184 | both splitting a 64-bit value into two 32-bit halves, and joining |
| 2185 | two halves into a whole 64-bit value, depending on the function |
| 2186 | passed as the MOVE argument. |
| 2187 | |
| 2188 | EV_REG must be the number of an SPE evN vector register --- a |
| 2189 | pseudoregister. REGCACHE must be a regcache, and BUFFER must be a |
| 2190 | 64-bit buffer. |
| 2191 | |
| 2192 | Call MOVE once for each 32-bit half of that register, passing |
| 2193 | REGCACHE, the number of the raw register corresponding to that |
| 2194 | half, and the address of the appropriate half of BUFFER. |
| 2195 | |
| 2196 | For example, passing 'regcache_raw_read' as the MOVE function will |
| 2197 | fill BUFFER with the full 64-bit contents of EV_REG. Or, passing |
| 2198 | 'regcache_raw_supply' will supply the contents of BUFFER to the |
| 2199 | appropriate pair of raw registers in REGCACHE. |
| 2200 | |
| 2201 | You may need to cast away some 'const' qualifiers when passing |
| 2202 | MOVE, since this function can't tell at compile-time which of |
| 2203 | REGCACHE or BUFFER is acting as the source of the data. If C had |
| 2204 | co-variant type qualifiers, ... */ |
| 2205 | static void |
| 2206 | e500_move_ev_register (void (*move) (struct regcache *regcache, |
| 2207 | int regnum, gdb_byte *buf), |
| 2208 | struct regcache *regcache, int ev_reg, |
| 2209 | gdb_byte *buffer) |
| 2210 | { |
| 2211 | struct gdbarch *arch = get_regcache_arch (regcache); |
| 2212 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
| 2213 | int reg_index; |
| 2214 | gdb_byte *byte_buffer = buffer; |
| 2215 | |
| 2216 | gdb_assert (tdep->ppc_ev0_regnum <= ev_reg |
| 2217 | && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs); |
| 2218 | |
| 2219 | reg_index = ev_reg - tdep->ppc_ev0_regnum; |
| 2220 | |
| 2221 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 2222 | { |
| 2223 | move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer); |
| 2224 | move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4); |
| 2225 | } |
| 2226 | else |
| 2227 | { |
| 2228 | move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer); |
| 2229 | move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4); |
| 2230 | } |
| 2231 | } |
| 2232 | |
| 2233 | static void |
| 2234 | e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
| 2235 | int reg_nr, gdb_byte *buffer) |
| 2236 | { |
| 2237 | struct gdbarch *regcache_arch = get_regcache_arch (regcache); |
| 2238 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2239 | |
| 2240 | gdb_assert (regcache_arch == gdbarch); |
| 2241 | |
| 2242 | if (tdep->ppc_ev0_regnum <= reg_nr |
| 2243 | && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs) |
| 2244 | e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer); |
| 2245 | else |
| 2246 | internal_error (__FILE__, __LINE__, |
| 2247 | _("e500_pseudo_register_read: " |
| 2248 | "called on unexpected register '%s' (%d)"), |
| 2249 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); |
| 2250 | } |
| 2251 | |
| 2252 | static void |
| 2253 | e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
| 2254 | int reg_nr, const gdb_byte *buffer) |
| 2255 | { |
| 2256 | struct gdbarch *regcache_arch = get_regcache_arch (regcache); |
| 2257 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2258 | |
| 2259 | gdb_assert (regcache_arch == gdbarch); |
| 2260 | |
| 2261 | if (tdep->ppc_ev0_regnum <= reg_nr |
| 2262 | && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs) |
| 2263 | e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *)) |
| 2264 | regcache_raw_write, |
| 2265 | regcache, reg_nr, (gdb_byte *) buffer); |
| 2266 | else |
| 2267 | internal_error (__FILE__, __LINE__, |
| 2268 | _("e500_pseudo_register_read: " |
| 2269 | "called on unexpected register '%s' (%d)"), |
| 2270 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); |
| 2271 | } |
| 2272 | |
| 2273 | /* The E500 needs a custom reggroup function: it has anonymous raw |
| 2274 | registers, and default_register_reggroup_p assumes that anonymous |
| 2275 | registers are not members of any reggroup. */ |
| 2276 | static int |
| 2277 | e500_register_reggroup_p (struct gdbarch *gdbarch, |
| 2278 | int regnum, |
| 2279 | struct reggroup *group) |
| 2280 | { |
| 2281 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2282 | |
| 2283 | /* The save and restore register groups need to include the |
| 2284 | upper-half registers, even though they're anonymous. */ |
| 2285 | if ((group == save_reggroup |
| 2286 | || group == restore_reggroup) |
| 2287 | && (tdep->ppc_ev0_upper_regnum <= regnum |
| 2288 | && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)) |
| 2289 | return 1; |
| 2290 | |
| 2291 | /* In all other regards, the default reggroup definition is fine. */ |
| 2292 | return default_register_reggroup_p (gdbarch, regnum, group); |
| 2293 | } |
| 2294 | |
| 2295 | /* Convert a DBX STABS register number to a GDB register number. */ |
| 2296 | static int |
| 2297 | rs6000_stab_reg_to_regnum (int num) |
| 2298 | { |
| 2299 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 2300 | |
| 2301 | if (0 <= num && num <= 31) |
| 2302 | return tdep->ppc_gp0_regnum + num; |
| 2303 | else if (32 <= num && num <= 63) |
| 2304 | /* FIXME: jimb/2004-05-05: What should we do when the debug info |
| 2305 | specifies registers the architecture doesn't have? Our |
| 2306 | callers don't check the value we return. */ |
| 2307 | return tdep->ppc_fp0_regnum + (num - 32); |
| 2308 | else if (77 <= num && num <= 108) |
| 2309 | return tdep->ppc_vr0_regnum + (num - 77); |
| 2310 | else if (1200 <= num && num < 1200 + 32) |
| 2311 | return tdep->ppc_ev0_regnum + (num - 1200); |
| 2312 | else |
| 2313 | switch (num) |
| 2314 | { |
| 2315 | case 64: |
| 2316 | return tdep->ppc_mq_regnum; |
| 2317 | case 65: |
| 2318 | return tdep->ppc_lr_regnum; |
| 2319 | case 66: |
| 2320 | return tdep->ppc_ctr_regnum; |
| 2321 | case 76: |
| 2322 | return tdep->ppc_xer_regnum; |
| 2323 | case 109: |
| 2324 | return tdep->ppc_vrsave_regnum; |
| 2325 | case 110: |
| 2326 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ |
| 2327 | case 111: |
| 2328 | return tdep->ppc_acc_regnum; |
| 2329 | case 112: |
| 2330 | return tdep->ppc_spefscr_regnum; |
| 2331 | default: |
| 2332 | return num; |
| 2333 | } |
| 2334 | } |
| 2335 | |
| 2336 | |
| 2337 | /* Convert a Dwarf 2 register number to a GDB register number. */ |
| 2338 | static int |
| 2339 | rs6000_dwarf2_reg_to_regnum (int num) |
| 2340 | { |
| 2341 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 2342 | |
| 2343 | if (0 <= num && num <= 31) |
| 2344 | return tdep->ppc_gp0_regnum + num; |
| 2345 | else if (32 <= num && num <= 63) |
| 2346 | /* FIXME: jimb/2004-05-05: What should we do when the debug info |
| 2347 | specifies registers the architecture doesn't have? Our |
| 2348 | callers don't check the value we return. */ |
| 2349 | return tdep->ppc_fp0_regnum + (num - 32); |
| 2350 | else if (1124 <= num && num < 1124 + 32) |
| 2351 | return tdep->ppc_vr0_regnum + (num - 1124); |
| 2352 | else if (1200 <= num && num < 1200 + 32) |
| 2353 | return tdep->ppc_ev0_regnum + (num - 1200); |
| 2354 | else |
| 2355 | switch (num) |
| 2356 | { |
| 2357 | case 64: |
| 2358 | return tdep->ppc_cr_regnum; |
| 2359 | case 67: |
| 2360 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ |
| 2361 | case 99: |
| 2362 | return tdep->ppc_acc_regnum; |
| 2363 | case 100: |
| 2364 | return tdep->ppc_mq_regnum; |
| 2365 | case 101: |
| 2366 | return tdep->ppc_xer_regnum; |
| 2367 | case 108: |
| 2368 | return tdep->ppc_lr_regnum; |
| 2369 | case 109: |
| 2370 | return tdep->ppc_ctr_regnum; |
| 2371 | case 356: |
| 2372 | return tdep->ppc_vrsave_regnum; |
| 2373 | case 612: |
| 2374 | return tdep->ppc_spefscr_regnum; |
| 2375 | default: |
| 2376 | return num; |
| 2377 | } |
| 2378 | } |
| 2379 | |
| 2380 | /* Translate a .eh_frame register to DWARF register, or adjust a |
| 2381 | .debug_frame register. */ |
| 2382 | |
| 2383 | static int |
| 2384 | rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p) |
| 2385 | { |
| 2386 | /* GCC releases before 3.4 use GCC internal register numbering in |
| 2387 | .debug_frame (and .debug_info, et cetera). The numbering is |
| 2388 | different from the standard SysV numbering for everything except |
| 2389 | for GPRs and FPRs. We can not detect this problem in most cases |
| 2390 | - to get accurate debug info for variables living in lr, ctr, v0, |
| 2391 | et cetera, use a newer version of GCC. But we must detect |
| 2392 | one important case - lr is in column 65 in .debug_frame output, |
| 2393 | instead of 108. |
| 2394 | |
| 2395 | GCC 3.4, and the "hammer" branch, have a related problem. They |
| 2396 | record lr register saves in .debug_frame as 108, but still record |
| 2397 | the return column as 65. We fix that up too. |
| 2398 | |
| 2399 | We can do this because 65 is assigned to fpsr, and GCC never |
| 2400 | generates debug info referring to it. To add support for |
| 2401 | handwritten debug info that restores fpsr, we would need to add a |
| 2402 | producer version check to this. */ |
| 2403 | if (!eh_frame_p) |
| 2404 | { |
| 2405 | if (num == 65) |
| 2406 | return 108; |
| 2407 | else |
| 2408 | return num; |
| 2409 | } |
| 2410 | |
| 2411 | /* .eh_frame is GCC specific. For binary compatibility, it uses GCC |
| 2412 | internal register numbering; translate that to the standard DWARF2 |
| 2413 | register numbering. */ |
| 2414 | if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */ |
| 2415 | return num; |
| 2416 | else if (68 <= num && num <= 75) /* cr0-cr8 */ |
| 2417 | return num - 68 + 86; |
| 2418 | else if (77 <= num && num <= 108) /* vr0-vr31 */ |
| 2419 | return num - 77 + 1124; |
| 2420 | else |
| 2421 | switch (num) |
| 2422 | { |
| 2423 | case 64: /* mq */ |
| 2424 | return 100; |
| 2425 | case 65: /* lr */ |
| 2426 | return 108; |
| 2427 | case 66: /* ctr */ |
| 2428 | return 109; |
| 2429 | case 76: /* xer */ |
| 2430 | return 101; |
| 2431 | case 109: /* vrsave */ |
| 2432 | return 356; |
| 2433 | case 110: /* vscr */ |
| 2434 | return 67; |
| 2435 | case 111: /* spe_acc */ |
| 2436 | return 99; |
| 2437 | case 112: /* spefscr */ |
| 2438 | return 612; |
| 2439 | default: |
| 2440 | return num; |
| 2441 | } |
| 2442 | } |
| 2443 | \f |
| 2444 | /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG). |
| 2445 | |
| 2446 | Usually a function pointer's representation is simply the address |
| 2447 | of the function. On the RS/6000 however, a function pointer is |
| 2448 | represented by a pointer to an OPD entry. This OPD entry contains |
| 2449 | three words, the first word is the address of the function, the |
| 2450 | second word is the TOC pointer (r2), and the third word is the |
| 2451 | static chain value. Throughout GDB it is currently assumed that a |
| 2452 | function pointer contains the address of the function, which is not |
| 2453 | easy to fix. In addition, the conversion of a function address to |
| 2454 | a function pointer would require allocation of an OPD entry in the |
| 2455 | inferior's memory space, with all its drawbacks. To be able to |
| 2456 | call C++ virtual methods in the inferior (which are called via |
| 2457 | function pointers), find_function_addr uses this function to get the |
| 2458 | function address from a function pointer. */ |
| 2459 | |
| 2460 | /* Return real function address if ADDR (a function pointer) is in the data |
| 2461 | space and is therefore a special function pointer. */ |
| 2462 | |
| 2463 | static CORE_ADDR |
| 2464 | rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch, |
| 2465 | CORE_ADDR addr, |
| 2466 | struct target_ops *targ) |
| 2467 | { |
| 2468 | struct obj_section *s; |
| 2469 | |
| 2470 | s = find_pc_section (addr); |
| 2471 | if (s && s->the_bfd_section->flags & SEC_CODE) |
| 2472 | return addr; |
| 2473 | |
| 2474 | /* ADDR is in the data space, so it's a special function pointer. */ |
| 2475 | return read_memory_addr (addr, gdbarch_tdep (gdbarch)->wordsize); |
| 2476 | } |
| 2477 | \f |
| 2478 | |
| 2479 | /* Handling the various POWER/PowerPC variants. */ |
| 2480 | |
| 2481 | |
| 2482 | /* The arrays here called registers_MUMBLE hold information about available |
| 2483 | registers. |
| 2484 | |
| 2485 | For each family of PPC variants, I've tried to isolate out the |
| 2486 | common registers and put them up front, so that as long as you get |
| 2487 | the general family right, GDB will correctly identify the registers |
| 2488 | common to that family. The common register sets are: |
| 2489 | |
| 2490 | For the 60x family: hid0 hid1 iabr dabr pir |
| 2491 | |
| 2492 | For the 505 and 860 family: eie eid nri |
| 2493 | |
| 2494 | For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi |
| 2495 | tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1 |
| 2496 | pbu1 pbl2 pbu2 |
| 2497 | |
| 2498 | Most of these register groups aren't anything formal. I arrived at |
| 2499 | them by looking at the registers that occurred in more than one |
| 2500 | processor. |
| 2501 | |
| 2502 | Note: kevinb/2002-04-30: Support for the fpscr register was added |
| 2503 | during April, 2002. Slot 70 is being used for PowerPC and slot 71 |
| 2504 | for Power. For PowerPC, slot 70 was unused and was already in the |
| 2505 | PPC_UISA_SPRS which is ideally where fpscr should go. For Power, |
| 2506 | slot 70 was being used for "mq", so the next available slot (71) |
| 2507 | was chosen. It would have been nice to be able to make the |
| 2508 | register numbers the same across processor cores, but this wasn't |
| 2509 | possible without either 1) renumbering some registers for some |
| 2510 | processors or 2) assigning fpscr to a really high slot that's |
| 2511 | larger than any current register number. Doing (1) is bad because |
| 2512 | existing stubs would break. Doing (2) is undesirable because it |
| 2513 | would introduce a really large gap between fpscr and the rest of |
| 2514 | the registers for most processors. */ |
| 2515 | |
| 2516 | /* Convenience macros for populating register arrays. */ |
| 2517 | |
| 2518 | /* Within another macro, convert S to a string. */ |
| 2519 | |
| 2520 | #define STR(s) #s |
| 2521 | |
| 2522 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems |
| 2523 | and 64 bits on 64-bit systems. */ |
| 2524 | #define R(name) { STR(name), 4, 8, 0, 0, -1 } |
| 2525 | |
| 2526 | /* Return a struct reg defining register NAME that's 32 bits on all |
| 2527 | systems. */ |
| 2528 | #define R4(name) { STR(name), 4, 4, 0, 0, -1 } |
| 2529 | |
| 2530 | /* Return a struct reg defining register NAME that's 64 bits on all |
| 2531 | systems. */ |
| 2532 | #define R8(name) { STR(name), 8, 8, 0, 0, -1 } |
| 2533 | |
| 2534 | /* Return a struct reg defining register NAME that's 128 bits on all |
| 2535 | systems. */ |
| 2536 | #define R16(name) { STR(name), 16, 16, 0, 0, -1 } |
| 2537 | |
| 2538 | /* Return a struct reg defining floating-point register NAME. */ |
| 2539 | #define F(name) { STR(name), 8, 8, 1, 0, -1 } |
| 2540 | |
| 2541 | /* Return a struct reg defining a pseudo register NAME that is 64 bits |
| 2542 | long on all systems. */ |
| 2543 | #define P8(name) { STR(name), 8, 8, 0, 1, -1 } |
| 2544 | |
| 2545 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit |
| 2546 | systems and that doesn't exist on 64-bit systems. */ |
| 2547 | #define R32(name) { STR(name), 4, 0, 0, 0, -1 } |
| 2548 | |
| 2549 | /* Return a struct reg defining register NAME that's 64 bits on 64-bit |
| 2550 | systems and that doesn't exist on 32-bit systems. */ |
| 2551 | #define R64(name) { STR(name), 0, 8, 0, 0, -1 } |
| 2552 | |
| 2553 | /* Return a struct reg placeholder for a register that doesn't exist. */ |
| 2554 | #define R0 { 0, 0, 0, 0, 0, -1 } |
| 2555 | |
| 2556 | /* Return a struct reg defining an anonymous raw register that's 32 |
| 2557 | bits on all systems. */ |
| 2558 | #define A4 { 0, 4, 4, 0, 0, -1 } |
| 2559 | |
| 2560 | /* Return a struct reg defining an SPR named NAME that is 32 bits on |
| 2561 | 32-bit systems and 64 bits on 64-bit systems. */ |
| 2562 | #define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name } |
| 2563 | |
| 2564 | /* Return a struct reg defining an SPR named NAME that is 32 bits on |
| 2565 | all systems. */ |
| 2566 | #define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name } |
| 2567 | |
| 2568 | /* Return a struct reg defining an SPR named NAME that is 32 bits on |
| 2569 | all systems, and whose SPR number is NUMBER. */ |
| 2570 | #define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) } |
| 2571 | |
| 2572 | /* Return a struct reg defining an SPR named NAME that's 64 bits on |
| 2573 | 64-bit systems and that doesn't exist on 32-bit systems. */ |
| 2574 | #define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name } |
| 2575 | |
| 2576 | /* UISA registers common across all architectures, including POWER. */ |
| 2577 | |
| 2578 | #define COMMON_UISA_REGS \ |
| 2579 | /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ |
| 2580 | /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ |
| 2581 | /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ |
| 2582 | /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ |
| 2583 | /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \ |
| 2584 | /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \ |
| 2585 | /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \ |
| 2586 | /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \ |
| 2587 | /* 64 */ R(pc), R(ps) |
| 2588 | |
| 2589 | /* UISA-level SPRs for PowerPC. */ |
| 2590 | #define PPC_UISA_SPRS \ |
| 2591 | /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr) |
| 2592 | |
| 2593 | /* UISA-level SPRs for PowerPC without floating point support. */ |
| 2594 | #define PPC_UISA_NOFP_SPRS \ |
| 2595 | /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0 |
| 2596 | |
| 2597 | /* Segment registers, for PowerPC. */ |
| 2598 | #define PPC_SEGMENT_REGS \ |
| 2599 | /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \ |
| 2600 | /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \ |
| 2601 | /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \ |
| 2602 | /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15) |
| 2603 | |
| 2604 | /* OEA SPRs for PowerPC. */ |
| 2605 | #define PPC_OEA_SPRS \ |
| 2606 | /* 87 */ S4(pvr), \ |
| 2607 | /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \ |
| 2608 | /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \ |
| 2609 | /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \ |
| 2610 | /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \ |
| 2611 | /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \ |
| 2612 | /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \ |
| 2613 | /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \ |
| 2614 | /* 116 */ S4(dec), S(dabr), S4(ear) |
| 2615 | |
| 2616 | /* AltiVec registers. */ |
| 2617 | #define PPC_ALTIVEC_REGS \ |
| 2618 | /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \ |
| 2619 | /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \ |
| 2620 | /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \ |
| 2621 | /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \ |
| 2622 | /*151*/R4(vscr), R4(vrsave) |
| 2623 | |
| 2624 | |
| 2625 | /* On machines supporting the SPE APU, the general-purpose registers |
| 2626 | are 64 bits long. There are SIMD vector instructions to treat them |
| 2627 | as pairs of floats, but the rest of the instruction set treats them |
| 2628 | as 32-bit registers, and only operates on their lower halves. |
| 2629 | |
| 2630 | In the GDB regcache, we treat their high and low halves as separate |
| 2631 | registers. The low halves we present as the general-purpose |
| 2632 | registers, and then we have pseudo-registers that stitch together |
| 2633 | the upper and lower halves and present them as pseudo-registers. */ |
| 2634 | |
| 2635 | /* SPE GPR lower halves --- raw registers. */ |
| 2636 | #define PPC_SPE_GP_REGS \ |
| 2637 | /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \ |
| 2638 | /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \ |
| 2639 | /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \ |
| 2640 | /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31) |
| 2641 | |
| 2642 | /* SPE GPR upper halves --- anonymous raw registers. */ |
| 2643 | #define PPC_SPE_UPPER_GP_REGS \ |
| 2644 | /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \ |
| 2645 | /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \ |
| 2646 | /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \ |
| 2647 | /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4 |
| 2648 | |
| 2649 | /* SPE GPR vector registers --- pseudo registers based on underlying |
| 2650 | gprs and the anonymous upper half raw registers. */ |
| 2651 | #define PPC_EV_PSEUDO_REGS \ |
| 2652 | /* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \ |
| 2653 | /* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\ |
| 2654 | /*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\ |
| 2655 | /*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31) |
| 2656 | |
| 2657 | /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover |
| 2658 | user-level SPR's. */ |
| 2659 | static const struct reg registers_power[] = |
| 2660 | { |
| 2661 | COMMON_UISA_REGS, |
| 2662 | /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq), |
| 2663 | /* 71 */ R4(fpscr) |
| 2664 | }; |
| 2665 | |
| 2666 | /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only |
| 2667 | view of the PowerPC. */ |
| 2668 | static const struct reg registers_powerpc[] = |
| 2669 | { |
| 2670 | COMMON_UISA_REGS, |
| 2671 | PPC_UISA_SPRS, |
| 2672 | PPC_ALTIVEC_REGS |
| 2673 | }; |
| 2674 | |
| 2675 | /* IBM PowerPC 403. |
| 2676 | |
| 2677 | Some notes about the "tcr" special-purpose register: |
| 2678 | - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the |
| 2679 | 403's programmable interval timer, fixed interval timer, and |
| 2680 | watchdog timer. |
| 2681 | - On the 602, SPR 984 is named "tcr", and it controls the 602's |
| 2682 | watchdog timer, and nothing else. |
| 2683 | |
| 2684 | Some of the fields are similar between the two, but they're not |
| 2685 | compatible with each other. Since the two variants have different |
| 2686 | registers, with different numbers, but the same name, we can't |
| 2687 | splice the register name to get the SPR number. */ |
| 2688 | static const struct reg registers_403[] = |
| 2689 | { |
| 2690 | COMMON_UISA_REGS, |
| 2691 | PPC_UISA_SPRS, |
| 2692 | PPC_SEGMENT_REGS, |
| 2693 | PPC_OEA_SPRS, |
| 2694 | /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr), |
| 2695 | /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit), |
| 2696 | /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3), |
| 2697 | /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2), |
| 2698 | /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr), |
| 2699 | /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2) |
| 2700 | }; |
| 2701 | |
| 2702 | /* IBM PowerPC 403GC. |
| 2703 | See the comments about 'tcr' for the 403, above. */ |
| 2704 | static const struct reg registers_403GC[] = |
| 2705 | { |
| 2706 | COMMON_UISA_REGS, |
| 2707 | PPC_UISA_SPRS, |
| 2708 | PPC_SEGMENT_REGS, |
| 2709 | PPC_OEA_SPRS, |
| 2710 | /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr), |
| 2711 | /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit), |
| 2712 | /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3), |
| 2713 | /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2), |
| 2714 | /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr), |
| 2715 | /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2), |
| 2716 | /* 143 */ S(zpr), S(pid), S(sgr), S(dcwr), |
| 2717 | /* 147 */ S(tbhu), S(tblu) |
| 2718 | }; |
| 2719 | |
| 2720 | /* Motorola PowerPC 505. */ |
| 2721 | static const struct reg registers_505[] = |
| 2722 | { |
| 2723 | COMMON_UISA_REGS, |
| 2724 | PPC_UISA_SPRS, |
| 2725 | PPC_SEGMENT_REGS, |
| 2726 | PPC_OEA_SPRS, |
| 2727 | /* 119 */ S(eie), S(eid), S(nri) |
| 2728 | }; |
| 2729 | |
| 2730 | /* Motorola PowerPC 860 or 850. */ |
| 2731 | static const struct reg registers_860[] = |
| 2732 | { |
| 2733 | COMMON_UISA_REGS, |
| 2734 | PPC_UISA_SPRS, |
| 2735 | PPC_SEGMENT_REGS, |
| 2736 | PPC_OEA_SPRS, |
| 2737 | /* 119 */ S(eie), S(eid), S(nri), S(cmpa), |
| 2738 | /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr), |
| 2739 | /* 127 */ S(der), S(counta), S(countb), S(cmpe), |
| 2740 | /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1), |
| 2741 | /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst), |
| 2742 | /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr), |
| 2743 | /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr), |
| 2744 | /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc), |
| 2745 | /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap), |
| 2746 | /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn), |
| 2747 | /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1), |
| 2748 | /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1) |
| 2749 | }; |
| 2750 | |
| 2751 | /* Motorola PowerPC 601. Note that the 601 has different register numbers |
| 2752 | for reading and writing RTCU and RTCL. However, how one reads and writes a |
| 2753 | register is the stub's problem. */ |
| 2754 | static const struct reg registers_601[] = |
| 2755 | { |
| 2756 | COMMON_UISA_REGS, |
| 2757 | PPC_UISA_SPRS, |
| 2758 | PPC_SEGMENT_REGS, |
| 2759 | PPC_OEA_SPRS, |
| 2760 | /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), |
| 2761 | /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl) |
| 2762 | }; |
| 2763 | |
| 2764 | /* Motorola PowerPC 602. |
| 2765 | See the notes under the 403 about 'tcr'. */ |
| 2766 | static const struct reg registers_602[] = |
| 2767 | { |
| 2768 | COMMON_UISA_REGS, |
| 2769 | PPC_UISA_SPRS, |
| 2770 | PPC_SEGMENT_REGS, |
| 2771 | PPC_OEA_SPRS, |
| 2772 | /* 119 */ S(hid0), S(hid1), S(iabr), R0, |
| 2773 | /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr), |
| 2774 | /* 127 */ S(sebr), S(ser), S(sp), S(lt) |
| 2775 | }; |
| 2776 | |
| 2777 | /* Motorola/IBM PowerPC 603 or 603e. */ |
| 2778 | static const struct reg registers_603[] = |
| 2779 | { |
| 2780 | COMMON_UISA_REGS, |
| 2781 | PPC_UISA_SPRS, |
| 2782 | PPC_SEGMENT_REGS, |
| 2783 | PPC_OEA_SPRS, |
| 2784 | /* 119 */ S(hid0), S(hid1), S(iabr), R0, |
| 2785 | /* 123 */ R0, S(dmiss), S(dcmp), S(hash1), |
| 2786 | /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa) |
| 2787 | }; |
| 2788 | |
| 2789 | /* Motorola PowerPC 604 or 604e. */ |
| 2790 | static const struct reg registers_604[] = |
| 2791 | { |
| 2792 | COMMON_UISA_REGS, |
| 2793 | PPC_UISA_SPRS, |
| 2794 | PPC_SEGMENT_REGS, |
| 2795 | PPC_OEA_SPRS, |
| 2796 | /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), |
| 2797 | /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2), |
| 2798 | /* 127 */ S(sia), S(sda) |
| 2799 | }; |
| 2800 | |
| 2801 | /* Motorola/IBM PowerPC 750 or 740. */ |
| 2802 | static const struct reg registers_750[] = |
| 2803 | { |
| 2804 | COMMON_UISA_REGS, |
| 2805 | PPC_UISA_SPRS, |
| 2806 | PPC_SEGMENT_REGS, |
| 2807 | PPC_OEA_SPRS, |
| 2808 | /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), |
| 2809 | /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2), |
| 2810 | /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4), |
| 2811 | /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia), |
| 2812 | /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr), |
| 2813 | /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3) |
| 2814 | }; |
| 2815 | |
| 2816 | |
| 2817 | /* Motorola PowerPC 7400. */ |
| 2818 | static const struct reg registers_7400[] = |
| 2819 | { |
| 2820 | /* gpr0-gpr31, fpr0-fpr31 */ |
| 2821 | COMMON_UISA_REGS, |
| 2822 | /* cr, lr, ctr, xer, fpscr */ |
| 2823 | PPC_UISA_SPRS, |
| 2824 | /* sr0-sr15 */ |
| 2825 | PPC_SEGMENT_REGS, |
| 2826 | PPC_OEA_SPRS, |
| 2827 | /* vr0-vr31, vrsave, vscr */ |
| 2828 | PPC_ALTIVEC_REGS |
| 2829 | /* FIXME? Add more registers? */ |
| 2830 | }; |
| 2831 | |
| 2832 | /* Motorola e500. */ |
| 2833 | static const struct reg registers_e500[] = |
| 2834 | { |
| 2835 | /* 0 .. 31 */ PPC_SPE_GP_REGS, |
| 2836 | /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS, |
| 2837 | /* 64 .. 65 */ R(pc), R(ps), |
| 2838 | /* 66 .. 70 */ PPC_UISA_NOFP_SPRS, |
| 2839 | /* 71 .. 72 */ R8(acc), S4(spefscr), |
| 2840 | /* NOTE: Add new registers here the end of the raw register |
| 2841 | list and just before the first pseudo register. */ |
| 2842 | /* 73 .. 104 */ PPC_EV_PSEUDO_REGS |
| 2843 | }; |
| 2844 | |
| 2845 | /* Information about a particular processor variant. */ |
| 2846 | |
| 2847 | struct variant |
| 2848 | { |
| 2849 | /* Name of this variant. */ |
| 2850 | char *name; |
| 2851 | |
| 2852 | /* English description of the variant. */ |
| 2853 | char *description; |
| 2854 | |
| 2855 | /* bfd_arch_info.arch corresponding to variant. */ |
| 2856 | enum bfd_architecture arch; |
| 2857 | |
| 2858 | /* bfd_arch_info.mach corresponding to variant. */ |
| 2859 | unsigned long mach; |
| 2860 | |
| 2861 | /* Number of real registers. */ |
| 2862 | int nregs; |
| 2863 | |
| 2864 | /* Number of pseudo registers. */ |
| 2865 | int npregs; |
| 2866 | |
| 2867 | /* Number of total registers (the sum of nregs and npregs). */ |
| 2868 | int num_tot_regs; |
| 2869 | |
| 2870 | /* Table of register names; registers[R] is the name of the register |
| 2871 | number R. */ |
| 2872 | const struct reg *regs; |
| 2873 | }; |
| 2874 | |
| 2875 | #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0])) |
| 2876 | |
| 2877 | static int |
| 2878 | num_registers (const struct reg *reg_list, int num_tot_regs) |
| 2879 | { |
| 2880 | int i; |
| 2881 | int nregs = 0; |
| 2882 | |
| 2883 | for (i = 0; i < num_tot_regs; i++) |
| 2884 | if (!reg_list[i].pseudo) |
| 2885 | nregs++; |
| 2886 | |
| 2887 | return nregs; |
| 2888 | } |
| 2889 | |
| 2890 | static int |
| 2891 | num_pseudo_registers (const struct reg *reg_list, int num_tot_regs) |
| 2892 | { |
| 2893 | int i; |
| 2894 | int npregs = 0; |
| 2895 | |
| 2896 | for (i = 0; i < num_tot_regs; i++) |
| 2897 | if (reg_list[i].pseudo) |
| 2898 | npregs ++; |
| 2899 | |
| 2900 | return npregs; |
| 2901 | } |
| 2902 | |
| 2903 | /* Information in this table comes from the following web sites: |
| 2904 | IBM: http://www.chips.ibm.com:80/products/embedded/ |
| 2905 | Motorola: http://www.mot.com/SPS/PowerPC/ |
| 2906 | |
| 2907 | I'm sure I've got some of the variant descriptions not quite right. |
| 2908 | Please report any inaccuracies you find to GDB's maintainer. |
| 2909 | |
| 2910 | If you add entries to this table, please be sure to allow the new |
| 2911 | value as an argument to the --with-cpu flag, in configure.in. */ |
| 2912 | |
| 2913 | static struct variant variants[] = |
| 2914 | { |
| 2915 | |
| 2916 | {"powerpc", "PowerPC user-level", bfd_arch_powerpc, |
| 2917 | bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc), |
| 2918 | registers_powerpc}, |
| 2919 | {"power", "POWER user-level", bfd_arch_rs6000, |
| 2920 | bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power), |
| 2921 | registers_power}, |
| 2922 | {"403", "IBM PowerPC 403", bfd_arch_powerpc, |
| 2923 | bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403), |
| 2924 | registers_403}, |
| 2925 | {"601", "Motorola PowerPC 601", bfd_arch_powerpc, |
| 2926 | bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601), |
| 2927 | registers_601}, |
| 2928 | {"602", "Motorola PowerPC 602", bfd_arch_powerpc, |
| 2929 | bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602), |
| 2930 | registers_602}, |
| 2931 | {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, |
| 2932 | bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603), |
| 2933 | registers_603}, |
| 2934 | {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, |
| 2935 | 604, -1, -1, tot_num_registers (registers_604), |
| 2936 | registers_604}, |
| 2937 | {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, |
| 2938 | bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC), |
| 2939 | registers_403GC}, |
| 2940 | {"505", "Motorola PowerPC 505", bfd_arch_powerpc, |
| 2941 | bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505), |
| 2942 | registers_505}, |
| 2943 | {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, |
| 2944 | bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860), |
| 2945 | registers_860}, |
| 2946 | {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, |
| 2947 | bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750), |
| 2948 | registers_750}, |
| 2949 | {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, |
| 2950 | bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400), |
| 2951 | registers_7400}, |
| 2952 | {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, |
| 2953 | bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500), |
| 2954 | registers_e500}, |
| 2955 | |
| 2956 | /* 64-bit */ |
| 2957 | {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, |
| 2958 | bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc), |
| 2959 | registers_powerpc}, |
| 2960 | {"620", "Motorola PowerPC 620", bfd_arch_powerpc, |
| 2961 | bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc), |
| 2962 | registers_powerpc}, |
| 2963 | {"630", "Motorola PowerPC 630", bfd_arch_powerpc, |
| 2964 | bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc), |
| 2965 | registers_powerpc}, |
| 2966 | {"a35", "PowerPC A35", bfd_arch_powerpc, |
| 2967 | bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc), |
| 2968 | registers_powerpc}, |
| 2969 | {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, |
| 2970 | bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc), |
| 2971 | registers_powerpc}, |
| 2972 | {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, |
| 2973 | bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc), |
| 2974 | registers_powerpc}, |
| 2975 | |
| 2976 | /* FIXME: I haven't checked the register sets of the following. */ |
| 2977 | {"rs1", "IBM POWER RS1", bfd_arch_rs6000, |
| 2978 | bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power), |
| 2979 | registers_power}, |
| 2980 | {"rsc", "IBM POWER RSC", bfd_arch_rs6000, |
| 2981 | bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power), |
| 2982 | registers_power}, |
| 2983 | {"rs2", "IBM POWER RS2", bfd_arch_rs6000, |
| 2984 | bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power), |
| 2985 | registers_power}, |
| 2986 | |
| 2987 | {0, 0, 0, 0, 0, 0, 0, 0} |
| 2988 | }; |
| 2989 | |
| 2990 | /* Initialize the number of registers and pseudo registers in each variant. */ |
| 2991 | |
| 2992 | static void |
| 2993 | init_variants (void) |
| 2994 | { |
| 2995 | struct variant *v; |
| 2996 | |
| 2997 | for (v = variants; v->name; v++) |
| 2998 | { |
| 2999 | if (v->nregs == -1) |
| 3000 | v->nregs = num_registers (v->regs, v->num_tot_regs); |
| 3001 | if (v->npregs == -1) |
| 3002 | v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs); |
| 3003 | } |
| 3004 | } |
| 3005 | |
| 3006 | /* Return the variant corresponding to architecture ARCH and machine number |
| 3007 | MACH. If no such variant exists, return null. */ |
| 3008 | |
| 3009 | static const struct variant * |
| 3010 | find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) |
| 3011 | { |
| 3012 | const struct variant *v; |
| 3013 | |
| 3014 | for (v = variants; v->name; v++) |
| 3015 | if (arch == v->arch && mach == v->mach) |
| 3016 | return v; |
| 3017 | |
| 3018 | return NULL; |
| 3019 | } |
| 3020 | |
| 3021 | static int |
| 3022 | gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) |
| 3023 | { |
| 3024 | if (!info->disassembler_options) |
| 3025 | info->disassembler_options = "any"; |
| 3026 | |
| 3027 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 3028 | return print_insn_big_powerpc (memaddr, info); |
| 3029 | else |
| 3030 | return print_insn_little_powerpc (memaddr, info); |
| 3031 | } |
| 3032 | \f |
| 3033 | static CORE_ADDR |
| 3034 | rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 3035 | { |
| 3036 | return frame_unwind_register_unsigned (next_frame, PC_REGNUM); |
| 3037 | } |
| 3038 | |
| 3039 | static struct frame_id |
| 3040 | rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 3041 | { |
| 3042 | return frame_id_build (frame_unwind_register_unsigned (next_frame, |
| 3043 | SP_REGNUM), |
| 3044 | frame_pc_unwind (next_frame)); |
| 3045 | } |
| 3046 | |
| 3047 | struct rs6000_frame_cache |
| 3048 | { |
| 3049 | CORE_ADDR base; |
| 3050 | CORE_ADDR initial_sp; |
| 3051 | struct trad_frame_saved_reg *saved_regs; |
| 3052 | }; |
| 3053 | |
| 3054 | static struct rs6000_frame_cache * |
| 3055 | rs6000_frame_cache (struct frame_info *next_frame, void **this_cache) |
| 3056 | { |
| 3057 | struct rs6000_frame_cache *cache; |
| 3058 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
| 3059 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3060 | struct rs6000_framedata fdata; |
| 3061 | int wordsize = tdep->wordsize; |
| 3062 | CORE_ADDR func, pc; |
| 3063 | |
| 3064 | if ((*this_cache) != NULL) |
| 3065 | return (*this_cache); |
| 3066 | cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); |
| 3067 | (*this_cache) = cache; |
| 3068 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
| 3069 | |
| 3070 | func = frame_func_unwind (next_frame, NORMAL_FRAME); |
| 3071 | pc = frame_pc_unwind (next_frame); |
| 3072 | skip_prologue (func, pc, &fdata); |
| 3073 | |
| 3074 | /* Figure out the parent's stack pointer. */ |
| 3075 | |
| 3076 | /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most |
| 3077 | address of the current frame. Things might be easier if the |
| 3078 | ->frame pointed to the outer-most address of the frame. In |
| 3079 | the mean time, the address of the prev frame is used as the |
| 3080 | base address of this frame. */ |
| 3081 | cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); |
| 3082 | |
| 3083 | /* If the function appears to be frameless, check a couple of likely |
| 3084 | indicators that we have simply failed to find the frame setup. |
| 3085 | Two common cases of this are missing symbols (i.e. |
| 3086 | frame_func_unwind returns the wrong address or 0), and assembly |
| 3087 | stubs which have a fast exit path but set up a frame on the slow |
| 3088 | path. |
| 3089 | |
| 3090 | If the LR appears to return to this function, then presume that |
| 3091 | we have an ABI compliant frame that we failed to find. */ |
| 3092 | if (fdata.frameless && fdata.lr_offset == 0) |
| 3093 | { |
| 3094 | CORE_ADDR saved_lr; |
| 3095 | int make_frame = 0; |
| 3096 | |
| 3097 | saved_lr = frame_unwind_register_unsigned (next_frame, |
| 3098 | tdep->ppc_lr_regnum); |
| 3099 | if (func == 0 && saved_lr == pc) |
| 3100 | make_frame = 1; |
| 3101 | else if (func != 0) |
| 3102 | { |
| 3103 | CORE_ADDR saved_func = get_pc_function_start (saved_lr); |
| 3104 | if (func == saved_func) |
| 3105 | make_frame = 1; |
| 3106 | } |
| 3107 | |
| 3108 | if (make_frame) |
| 3109 | { |
| 3110 | fdata.frameless = 0; |
| 3111 | fdata.lr_offset = tdep->lr_frame_offset; |
| 3112 | } |
| 3113 | } |
| 3114 | |
| 3115 | if (!fdata.frameless) |
| 3116 | /* Frameless really means stackless. */ |
| 3117 | cache->base = read_memory_addr (cache->base, wordsize); |
| 3118 | |
| 3119 | trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base); |
| 3120 | |
| 3121 | /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr. |
| 3122 | All fpr's from saved_fpr to fp31 are saved. */ |
| 3123 | |
| 3124 | if (fdata.saved_fpr >= 0) |
| 3125 | { |
| 3126 | int i; |
| 3127 | CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset; |
| 3128 | |
| 3129 | /* If skip_prologue says floating-point registers were saved, |
| 3130 | but the current architecture has no floating-point registers, |
| 3131 | then that's strange. But we have no indices to even record |
| 3132 | the addresses under, so we just ignore it. */ |
| 3133 | if (ppc_floating_point_unit_p (gdbarch)) |
| 3134 | for (i = fdata.saved_fpr; i < ppc_num_fprs; i++) |
| 3135 | { |
| 3136 | cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr; |
| 3137 | fpr_addr += 8; |
| 3138 | } |
| 3139 | } |
| 3140 | |
| 3141 | /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr. |
| 3142 | All gpr's from saved_gpr to gpr31 are saved. */ |
| 3143 | |
| 3144 | if (fdata.saved_gpr >= 0) |
| 3145 | { |
| 3146 | int i; |
| 3147 | CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset; |
| 3148 | for (i = fdata.saved_gpr; i < ppc_num_gprs; i++) |
| 3149 | { |
| 3150 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr; |
| 3151 | gpr_addr += wordsize; |
| 3152 | } |
| 3153 | } |
| 3154 | |
| 3155 | /* if != -1, fdata.saved_vr is the smallest number of saved_vr. |
| 3156 | All vr's from saved_vr to vr31 are saved. */ |
| 3157 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) |
| 3158 | { |
| 3159 | if (fdata.saved_vr >= 0) |
| 3160 | { |
| 3161 | int i; |
| 3162 | CORE_ADDR vr_addr = cache->base + fdata.vr_offset; |
| 3163 | for (i = fdata.saved_vr; i < 32; i++) |
| 3164 | { |
| 3165 | cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr; |
| 3166 | vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum); |
| 3167 | } |
| 3168 | } |
| 3169 | } |
| 3170 | |
| 3171 | /* if != -1, fdata.saved_ev is the smallest number of saved_ev. |
| 3172 | All vr's from saved_ev to ev31 are saved. ????? */ |
| 3173 | if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1) |
| 3174 | { |
| 3175 | if (fdata.saved_ev >= 0) |
| 3176 | { |
| 3177 | int i; |
| 3178 | CORE_ADDR ev_addr = cache->base + fdata.ev_offset; |
| 3179 | for (i = fdata.saved_ev; i < ppc_num_gprs; i++) |
| 3180 | { |
| 3181 | cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr; |
| 3182 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4; |
| 3183 | ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); |
| 3184 | } |
| 3185 | } |
| 3186 | } |
| 3187 | |
| 3188 | /* If != 0, fdata.cr_offset is the offset from the frame that |
| 3189 | holds the CR. */ |
| 3190 | if (fdata.cr_offset != 0) |
| 3191 | cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset; |
| 3192 | |
| 3193 | /* If != 0, fdata.lr_offset is the offset from the frame that |
| 3194 | holds the LR. */ |
| 3195 | if (fdata.lr_offset != 0) |
| 3196 | cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset; |
| 3197 | /* The PC is found in the link register. */ |
| 3198 | cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum]; |
| 3199 | |
| 3200 | /* If != 0, fdata.vrsave_offset is the offset from the frame that |
| 3201 | holds the VRSAVE. */ |
| 3202 | if (fdata.vrsave_offset != 0) |
| 3203 | cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset; |
| 3204 | |
| 3205 | if (fdata.alloca_reg < 0) |
| 3206 | /* If no alloca register used, then fi->frame is the value of the |
| 3207 | %sp for this frame, and it is good enough. */ |
| 3208 | cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM); |
| 3209 | else |
| 3210 | cache->initial_sp = frame_unwind_register_unsigned (next_frame, |
| 3211 | fdata.alloca_reg); |
| 3212 | |
| 3213 | return cache; |
| 3214 | } |
| 3215 | |
| 3216 | static void |
| 3217 | rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache, |
| 3218 | struct frame_id *this_id) |
| 3219 | { |
| 3220 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, |
| 3221 | this_cache); |
| 3222 | (*this_id) = frame_id_build (info->base, |
| 3223 | frame_func_unwind (next_frame, NORMAL_FRAME)); |
| 3224 | } |
| 3225 | |
| 3226 | static void |
| 3227 | rs6000_frame_prev_register (struct frame_info *next_frame, |
| 3228 | void **this_cache, |
| 3229 | int regnum, int *optimizedp, |
| 3230 | enum lval_type *lvalp, CORE_ADDR *addrp, |
| 3231 | int *realnump, gdb_byte *valuep) |
| 3232 | { |
| 3233 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, |
| 3234 | this_cache); |
| 3235 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
| 3236 | optimizedp, lvalp, addrp, realnump, valuep); |
| 3237 | } |
| 3238 | |
| 3239 | static const struct frame_unwind rs6000_frame_unwind = |
| 3240 | { |
| 3241 | NORMAL_FRAME, |
| 3242 | rs6000_frame_this_id, |
| 3243 | rs6000_frame_prev_register |
| 3244 | }; |
| 3245 | |
| 3246 | static const struct frame_unwind * |
| 3247 | rs6000_frame_sniffer (struct frame_info *next_frame) |
| 3248 | { |
| 3249 | return &rs6000_frame_unwind; |
| 3250 | } |
| 3251 | |
| 3252 | \f |
| 3253 | |
| 3254 | static CORE_ADDR |
| 3255 | rs6000_frame_base_address (struct frame_info *next_frame, |
| 3256 | void **this_cache) |
| 3257 | { |
| 3258 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, |
| 3259 | this_cache); |
| 3260 | return info->initial_sp; |
| 3261 | } |
| 3262 | |
| 3263 | static const struct frame_base rs6000_frame_base = { |
| 3264 | &rs6000_frame_unwind, |
| 3265 | rs6000_frame_base_address, |
| 3266 | rs6000_frame_base_address, |
| 3267 | rs6000_frame_base_address |
| 3268 | }; |
| 3269 | |
| 3270 | static const struct frame_base * |
| 3271 | rs6000_frame_base_sniffer (struct frame_info *next_frame) |
| 3272 | { |
| 3273 | return &rs6000_frame_base; |
| 3274 | } |
| 3275 | |
| 3276 | /* Initialize the current architecture based on INFO. If possible, re-use an |
| 3277 | architecture from ARCHES, which is a list of architectures already created |
| 3278 | during this debugging session. |
| 3279 | |
| 3280 | Called e.g. at program startup, when reading a core file, and when reading |
| 3281 | a binary file. */ |
| 3282 | |
| 3283 | static struct gdbarch * |
| 3284 | rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 3285 | { |
| 3286 | struct gdbarch *gdbarch; |
| 3287 | struct gdbarch_tdep *tdep; |
| 3288 | int wordsize, from_xcoff_exec, from_elf_exec, i, off; |
| 3289 | struct reg *regs; |
| 3290 | const struct variant *v; |
| 3291 | enum bfd_architecture arch; |
| 3292 | unsigned long mach; |
| 3293 | bfd abfd; |
| 3294 | int sysv_abi; |
| 3295 | asection *sect; |
| 3296 | |
| 3297 | from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && |
| 3298 | bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; |
| 3299 | |
| 3300 | from_elf_exec = info.abfd && info.abfd->format == bfd_object && |
| 3301 | bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; |
| 3302 | |
| 3303 | sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; |
| 3304 | |
| 3305 | /* Check word size. If INFO is from a binary file, infer it from |
| 3306 | that, else choose a likely default. */ |
| 3307 | if (from_xcoff_exec) |
| 3308 | { |
| 3309 | if (bfd_xcoff_is_xcoff64 (info.abfd)) |
| 3310 | wordsize = 8; |
| 3311 | else |
| 3312 | wordsize = 4; |
| 3313 | } |
| 3314 | else if (from_elf_exec) |
| 3315 | { |
| 3316 | if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) |
| 3317 | wordsize = 8; |
| 3318 | else |
| 3319 | wordsize = 4; |
| 3320 | } |
| 3321 | else |
| 3322 | { |
| 3323 | if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) |
| 3324 | wordsize = info.bfd_arch_info->bits_per_word / |
| 3325 | info.bfd_arch_info->bits_per_byte; |
| 3326 | else |
| 3327 | wordsize = 4; |
| 3328 | } |
| 3329 | |
| 3330 | /* Find a candidate among extant architectures. */ |
| 3331 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
| 3332 | arches != NULL; |
| 3333 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) |
| 3334 | { |
| 3335 | /* Word size in the various PowerPC bfd_arch_info structs isn't |
| 3336 | meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform |
| 3337 | separate word size check. */ |
| 3338 | tdep = gdbarch_tdep (arches->gdbarch); |
| 3339 | if (tdep && tdep->wordsize == wordsize) |
| 3340 | return arches->gdbarch; |
| 3341 | } |
| 3342 | |
| 3343 | /* None found, create a new architecture from INFO, whose bfd_arch_info |
| 3344 | validity depends on the source: |
| 3345 | - executable useless |
| 3346 | - rs6000_host_arch() good |
| 3347 | - core file good |
| 3348 | - "set arch" trust blindly |
| 3349 | - GDB startup useless but harmless */ |
| 3350 | |
| 3351 | if (!from_xcoff_exec) |
| 3352 | { |
| 3353 | arch = info.bfd_arch_info->arch; |
| 3354 | mach = info.bfd_arch_info->mach; |
| 3355 | } |
| 3356 | else |
| 3357 | { |
| 3358 | arch = bfd_arch_powerpc; |
| 3359 | bfd_default_set_arch_mach (&abfd, arch, 0); |
| 3360 | info.bfd_arch_info = bfd_get_arch_info (&abfd); |
| 3361 | mach = info.bfd_arch_info->mach; |
| 3362 | } |
| 3363 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); |
| 3364 | tdep->wordsize = wordsize; |
| 3365 | |
| 3366 | /* For e500 executables, the apuinfo section is of help here. Such |
| 3367 | section contains the identifier and revision number of each |
| 3368 | Application-specific Processing Unit that is present on the |
| 3369 | chip. The content of the section is determined by the assembler |
| 3370 | which looks at each instruction and determines which unit (and |
| 3371 | which version of it) can execute it. In our case we just look for |
| 3372 | the existance of the section. */ |
| 3373 | |
| 3374 | if (info.abfd) |
| 3375 | { |
| 3376 | sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo"); |
| 3377 | if (sect) |
| 3378 | { |
| 3379 | arch = info.bfd_arch_info->arch; |
| 3380 | mach = bfd_mach_ppc_e500; |
| 3381 | bfd_default_set_arch_mach (&abfd, arch, mach); |
| 3382 | info.bfd_arch_info = bfd_get_arch_info (&abfd); |
| 3383 | } |
| 3384 | } |
| 3385 | |
| 3386 | gdbarch = gdbarch_alloc (&info, tdep); |
| 3387 | |
| 3388 | /* Initialize the number of real and pseudo registers in each variant. */ |
| 3389 | init_variants (); |
| 3390 | |
| 3391 | /* Choose variant. */ |
| 3392 | v = find_variant_by_arch (arch, mach); |
| 3393 | if (!v) |
| 3394 | return NULL; |
| 3395 | |
| 3396 | tdep->regs = v->regs; |
| 3397 | |
| 3398 | tdep->ppc_gp0_regnum = 0; |
| 3399 | tdep->ppc_toc_regnum = 2; |
| 3400 | tdep->ppc_ps_regnum = 65; |
| 3401 | tdep->ppc_cr_regnum = 66; |
| 3402 | tdep->ppc_lr_regnum = 67; |
| 3403 | tdep->ppc_ctr_regnum = 68; |
| 3404 | tdep->ppc_xer_regnum = 69; |
| 3405 | if (v->mach == bfd_mach_ppc_601) |
| 3406 | tdep->ppc_mq_regnum = 124; |
| 3407 | else if (arch == bfd_arch_rs6000) |
| 3408 | tdep->ppc_mq_regnum = 70; |
| 3409 | else |
| 3410 | tdep->ppc_mq_regnum = -1; |
| 3411 | tdep->ppc_fp0_regnum = 32; |
| 3412 | tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70; |
| 3413 | tdep->ppc_sr0_regnum = 71; |
| 3414 | tdep->ppc_vr0_regnum = -1; |
| 3415 | tdep->ppc_vrsave_regnum = -1; |
| 3416 | tdep->ppc_ev0_upper_regnum = -1; |
| 3417 | tdep->ppc_ev0_regnum = -1; |
| 3418 | tdep->ppc_ev31_regnum = -1; |
| 3419 | tdep->ppc_acc_regnum = -1; |
| 3420 | tdep->ppc_spefscr_regnum = -1; |
| 3421 | |
| 3422 | set_gdbarch_pc_regnum (gdbarch, 64); |
| 3423 | set_gdbarch_sp_regnum (gdbarch, 1); |
| 3424 | set_gdbarch_deprecated_fp_regnum (gdbarch, 1); |
| 3425 | set_gdbarch_fp0_regnum (gdbarch, 32); |
| 3426 | set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno); |
| 3427 | if (sysv_abi && wordsize == 8) |
| 3428 | set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); |
| 3429 | else if (sysv_abi && wordsize == 4) |
| 3430 | set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); |
| 3431 | else |
| 3432 | set_gdbarch_return_value (gdbarch, rs6000_return_value); |
| 3433 | |
| 3434 | /* Set lr_frame_offset. */ |
| 3435 | if (wordsize == 8) |
| 3436 | tdep->lr_frame_offset = 16; |
| 3437 | else if (sysv_abi) |
| 3438 | tdep->lr_frame_offset = 4; |
| 3439 | else |
| 3440 | tdep->lr_frame_offset = 8; |
| 3441 | |
| 3442 | if (v->arch == bfd_arch_rs6000) |
| 3443 | tdep->ppc_sr0_regnum = -1; |
| 3444 | else if (v->arch == bfd_arch_powerpc) |
| 3445 | switch (v->mach) |
| 3446 | { |
| 3447 | case bfd_mach_ppc: |
| 3448 | tdep->ppc_sr0_regnum = -1; |
| 3449 | tdep->ppc_vr0_regnum = 71; |
| 3450 | tdep->ppc_vrsave_regnum = 104; |
| 3451 | break; |
| 3452 | case bfd_mach_ppc_7400: |
| 3453 | tdep->ppc_vr0_regnum = 119; |
| 3454 | tdep->ppc_vrsave_regnum = 152; |
| 3455 | break; |
| 3456 | case bfd_mach_ppc_e500: |
| 3457 | tdep->ppc_toc_regnum = -1; |
| 3458 | tdep->ppc_ev0_upper_regnum = 32; |
| 3459 | tdep->ppc_ev0_regnum = 73; |
| 3460 | tdep->ppc_ev31_regnum = 104; |
| 3461 | tdep->ppc_acc_regnum = 71; |
| 3462 | tdep->ppc_spefscr_regnum = 72; |
| 3463 | tdep->ppc_fp0_regnum = -1; |
| 3464 | tdep->ppc_fpscr_regnum = -1; |
| 3465 | tdep->ppc_sr0_regnum = -1; |
| 3466 | set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read); |
| 3467 | set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write); |
| 3468 | set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p); |
| 3469 | break; |
| 3470 | |
| 3471 | case bfd_mach_ppc64: |
| 3472 | case bfd_mach_ppc_620: |
| 3473 | case bfd_mach_ppc_630: |
| 3474 | case bfd_mach_ppc_a35: |
| 3475 | case bfd_mach_ppc_rs64ii: |
| 3476 | case bfd_mach_ppc_rs64iii: |
| 3477 | /* These processor's register sets don't have segment registers. */ |
| 3478 | tdep->ppc_sr0_regnum = -1; |
| 3479 | break; |
| 3480 | } |
| 3481 | else |
| 3482 | internal_error (__FILE__, __LINE__, |
| 3483 | _("rs6000_gdbarch_init: " |
| 3484 | "received unexpected BFD 'arch' value")); |
| 3485 | |
| 3486 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
| 3487 | |
| 3488 | /* Sanity check on registers. */ |
| 3489 | gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0); |
| 3490 | |
| 3491 | /* Select instruction printer. */ |
| 3492 | if (arch == bfd_arch_rs6000) |
| 3493 | set_gdbarch_print_insn (gdbarch, print_insn_rs6000); |
| 3494 | else |
| 3495 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); |
| 3496 | |
| 3497 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
| 3498 | |
| 3499 | set_gdbarch_num_regs (gdbarch, v->nregs); |
| 3500 | set_gdbarch_num_pseudo_regs (gdbarch, v->npregs); |
| 3501 | set_gdbarch_register_name (gdbarch, rs6000_register_name); |
| 3502 | set_gdbarch_register_type (gdbarch, rs6000_register_type); |
| 3503 | set_gdbarch_register_reggroup_p (gdbarch, rs6000_register_reggroup_p); |
| 3504 | |
| 3505 | set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); |
| 3506 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
| 3507 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 3508 | set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); |
| 3509 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 3510 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 3511 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 3512 | if (sysv_abi) |
| 3513 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); |
| 3514 | else |
| 3515 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 3516 | set_gdbarch_char_signed (gdbarch, 0); |
| 3517 | |
| 3518 | set_gdbarch_frame_align (gdbarch, rs6000_frame_align); |
| 3519 | if (sysv_abi && wordsize == 8) |
| 3520 | /* PPC64 SYSV. */ |
| 3521 | set_gdbarch_frame_red_zone_size (gdbarch, 288); |
| 3522 | else if (!sysv_abi && wordsize == 4) |
| 3523 | /* PowerOpen / AIX 32 bit. The saved area or red zone consists of |
| 3524 | 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes. |
| 3525 | Problem is, 220 isn't frame (16 byte) aligned. Round it up to |
| 3526 | 224. */ |
| 3527 | set_gdbarch_frame_red_zone_size (gdbarch, 224); |
| 3528 | |
| 3529 | set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p); |
| 3530 | set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value); |
| 3531 | set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register); |
| 3532 | |
| 3533 | set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); |
| 3534 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum); |
| 3535 | |
| 3536 | if (sysv_abi && wordsize == 4) |
| 3537 | set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); |
| 3538 | else if (sysv_abi && wordsize == 8) |
| 3539 | set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); |
| 3540 | else |
| 3541 | set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call); |
| 3542 | |
| 3543 | set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); |
| 3544 | set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p); |
| 3545 | |
| 3546 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 3547 | set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); |
| 3548 | |
| 3549 | /* Handles single stepping of atomic sequences. */ |
| 3550 | set_gdbarch_software_single_step (gdbarch, deal_with_atomic_sequence); |
| 3551 | |
| 3552 | /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN" |
| 3553 | for the descriptor and ".FN" for the entry-point -- a user |
| 3554 | specifying "break FN" will unexpectedly end up with a breakpoint |
| 3555 | on the descriptor and not the function. This architecture method |
| 3556 | transforms any breakpoints on descriptors into breakpoints on the |
| 3557 | corresponding entry point. */ |
| 3558 | if (sysv_abi && wordsize == 8) |
| 3559 | set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address); |
| 3560 | |
| 3561 | /* Not sure on this. FIXMEmgo */ |
| 3562 | set_gdbarch_frame_args_skip (gdbarch, 8); |
| 3563 | |
| 3564 | if (!sysv_abi) |
| 3565 | { |
| 3566 | /* Handle RS/6000 function pointers (which are really function |
| 3567 | descriptors). */ |
| 3568 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, |
| 3569 | rs6000_convert_from_func_ptr_addr); |
| 3570 | } |
| 3571 | |
| 3572 | /* Helpers for function argument information. */ |
| 3573 | set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); |
| 3574 | |
| 3575 | /* Trampoline. */ |
| 3576 | set_gdbarch_in_solib_return_trampoline |
| 3577 | (gdbarch, rs6000_in_solib_return_trampoline); |
| 3578 | set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code); |
| 3579 | |
| 3580 | /* Hook in the DWARF CFI frame unwinder. */ |
| 3581 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
| 3582 | dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum); |
| 3583 | |
| 3584 | /* Hook in ABI-specific overrides, if they have been registered. */ |
| 3585 | gdbarch_init_osabi (info, gdbarch); |
| 3586 | |
| 3587 | switch (info.osabi) |
| 3588 | { |
| 3589 | case GDB_OSABI_LINUX: |
| 3590 | /* FIXME: pgilliam/2005-10-21: Assume all PowerPC 64-bit linux systems |
| 3591 | have altivec registers. If not, ptrace will fail the first time it's |
| 3592 | called to access one and will not be called again. This wart will |
| 3593 | be removed when Daniel Jacobowitz's proposal for autodetecting target |
| 3594 | registers is implemented. */ |
| 3595 | if ((v->arch == bfd_arch_powerpc) && ((v->mach)== bfd_mach_ppc64)) |
| 3596 | { |
| 3597 | tdep->ppc_vr0_regnum = 71; |
| 3598 | tdep->ppc_vrsave_regnum = 104; |
| 3599 | } |
| 3600 | /* Fall Thru */ |
| 3601 | case GDB_OSABI_NETBSD_AOUT: |
| 3602 | case GDB_OSABI_NETBSD_ELF: |
| 3603 | case GDB_OSABI_UNKNOWN: |
| 3604 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); |
| 3605 | frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); |
| 3606 | set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); |
| 3607 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); |
| 3608 | break; |
| 3609 | default: |
| 3610 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
| 3611 | |
| 3612 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); |
| 3613 | frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); |
| 3614 | set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); |
| 3615 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); |
| 3616 | } |
| 3617 | |
| 3618 | init_sim_regno_table (gdbarch); |
| 3619 | |
| 3620 | return gdbarch; |
| 3621 | } |
| 3622 | |
| 3623 | static void |
| 3624 | rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) |
| 3625 | { |
| 3626 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 3627 | |
| 3628 | if (tdep == NULL) |
| 3629 | return; |
| 3630 | |
| 3631 | /* FIXME: Dump gdbarch_tdep. */ |
| 3632 | } |
| 3633 | |
| 3634 | /* Initialization code. */ |
| 3635 | |
| 3636 | extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */ |
| 3637 | |
| 3638 | void |
| 3639 | _initialize_rs6000_tdep (void) |
| 3640 | { |
| 3641 | gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); |
| 3642 | gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); |
| 3643 | } |