| 1 | /* Target-dependent code for Renesas Super-H, for GDB. |
| 2 | |
| 3 | Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
| 4 | 2003, 2004, 2005, 2007 Free Software Foundation, Inc. |
| 5 | |
| 6 | This file is part of GDB. |
| 7 | |
| 8 | This program is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 2 of the License, or |
| 11 | (at your option) any later version. |
| 12 | |
| 13 | This program is distributed in the hope that it will be useful, |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this program; if not, write to the Free Software |
| 20 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
| 21 | Boston, MA 02110-1301, USA. */ |
| 22 | |
| 23 | /* |
| 24 | Contributed by Steve Chamberlain |
| 25 | sac@cygnus.com |
| 26 | */ |
| 27 | |
| 28 | #include "defs.h" |
| 29 | #include "frame.h" |
| 30 | #include "frame-base.h" |
| 31 | #include "frame-unwind.h" |
| 32 | #include "dwarf2-frame.h" |
| 33 | #include "symtab.h" |
| 34 | #include "gdbtypes.h" |
| 35 | #include "gdbcmd.h" |
| 36 | #include "gdbcore.h" |
| 37 | #include "value.h" |
| 38 | #include "dis-asm.h" |
| 39 | #include "inferior.h" |
| 40 | #include "gdb_string.h" |
| 41 | #include "gdb_assert.h" |
| 42 | #include "arch-utils.h" |
| 43 | #include "regcache.h" |
| 44 | #include "osabi.h" |
| 45 | |
| 46 | #include "elf-bfd.h" |
| 47 | |
| 48 | /* sh flags */ |
| 49 | #include "elf/sh.h" |
| 50 | /* registers numbers shared with the simulator */ |
| 51 | #include "gdb/sim-sh.h" |
| 52 | |
| 53 | /* Information that is dependent on the processor variant. */ |
| 54 | enum sh_abi |
| 55 | { |
| 56 | SH_ABI_UNKNOWN, |
| 57 | SH_ABI_32, |
| 58 | SH_ABI_64 |
| 59 | }; |
| 60 | |
| 61 | struct gdbarch_tdep |
| 62 | { |
| 63 | enum sh_abi sh_abi; |
| 64 | }; |
| 65 | |
| 66 | struct sh64_frame_cache |
| 67 | { |
| 68 | /* Base address. */ |
| 69 | CORE_ADDR base; |
| 70 | LONGEST sp_offset; |
| 71 | CORE_ADDR pc; |
| 72 | |
| 73 | /* Flag showing that a frame has been created in the prologue code. */ |
| 74 | int uses_fp; |
| 75 | |
| 76 | int media_mode; |
| 77 | |
| 78 | /* Saved registers. */ |
| 79 | CORE_ADDR saved_regs[SIM_SH64_NR_REGS]; |
| 80 | CORE_ADDR saved_sp; |
| 81 | }; |
| 82 | |
| 83 | /* Registers of SH5 */ |
| 84 | enum |
| 85 | { |
| 86 | R0_REGNUM = 0, |
| 87 | DEFAULT_RETURN_REGNUM = 2, |
| 88 | STRUCT_RETURN_REGNUM = 2, |
| 89 | ARG0_REGNUM = 2, |
| 90 | ARGLAST_REGNUM = 9, |
| 91 | FLOAT_ARGLAST_REGNUM = 11, |
| 92 | MEDIA_FP_REGNUM = 14, |
| 93 | PR_REGNUM = 18, |
| 94 | SR_REGNUM = 65, |
| 95 | DR0_REGNUM = 141, |
| 96 | DR_LAST_REGNUM = 172, |
| 97 | /* FPP stands for Floating Point Pair, to avoid confusion with |
| 98 | GDB's FP0_REGNUM, which is the number of the first Floating |
| 99 | point register. Unfortunately on the sh5, the floating point |
| 100 | registers are called FR, and the floating point pairs are called FP. */ |
| 101 | FPP0_REGNUM = 173, |
| 102 | FPP_LAST_REGNUM = 204, |
| 103 | FV0_REGNUM = 205, |
| 104 | FV_LAST_REGNUM = 220, |
| 105 | R0_C_REGNUM = 221, |
| 106 | R_LAST_C_REGNUM = 236, |
| 107 | PC_C_REGNUM = 237, |
| 108 | GBR_C_REGNUM = 238, |
| 109 | MACH_C_REGNUM = 239, |
| 110 | MACL_C_REGNUM = 240, |
| 111 | PR_C_REGNUM = 241, |
| 112 | T_C_REGNUM = 242, |
| 113 | FPSCR_C_REGNUM = 243, |
| 114 | FPUL_C_REGNUM = 244, |
| 115 | FP0_C_REGNUM = 245, |
| 116 | FP_LAST_C_REGNUM = 260, |
| 117 | DR0_C_REGNUM = 261, |
| 118 | DR_LAST_C_REGNUM = 268, |
| 119 | FV0_C_REGNUM = 269, |
| 120 | FV_LAST_C_REGNUM = 272, |
| 121 | FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM, |
| 122 | SSR_REGNUM = SIM_SH64_SSR_REGNUM, |
| 123 | SPC_REGNUM = SIM_SH64_SPC_REGNUM, |
| 124 | TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7, |
| 125 | FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1 |
| 126 | }; |
| 127 | |
| 128 | static const char * |
| 129 | sh64_register_name (int reg_nr) |
| 130 | { |
| 131 | static char *register_names[] = |
| 132 | { |
| 133 | /* SH MEDIA MODE (ISA 32) */ |
| 134 | /* general registers (64-bit) 0-63 */ |
| 135 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 136 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 137 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
| 138 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
| 139 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", |
| 140 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", |
| 141 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", |
| 142 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", |
| 143 | |
| 144 | /* pc (64-bit) 64 */ |
| 145 | "pc", |
| 146 | |
| 147 | /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */ |
| 148 | "sr", "ssr", "spc", |
| 149 | |
| 150 | /* target registers (64-bit) 68-75*/ |
| 151 | "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", |
| 152 | |
| 153 | /* floating point state control register (32-bit) 76 */ |
| 154 | "fpscr", |
| 155 | |
| 156 | /* single precision floating point registers (32-bit) 77-140*/ |
| 157 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
| 158 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", |
| 159 | "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", |
| 160 | "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", |
| 161 | "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", |
| 162 | "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", |
| 163 | "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", |
| 164 | "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", |
| 165 | |
| 166 | /* double precision registers (pseudo) 141-172 */ |
| 167 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", |
| 168 | "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", |
| 169 | "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", |
| 170 | "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62", |
| 171 | |
| 172 | /* floating point pairs (pseudo) 173-204*/ |
| 173 | "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14", |
| 174 | "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30", |
| 175 | "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46", |
| 176 | "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62", |
| 177 | |
| 178 | /* floating point vectors (4 floating point regs) (pseudo) 205-220*/ |
| 179 | "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28", |
| 180 | "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60", |
| 181 | |
| 182 | /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/ |
| 183 | "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c", |
| 184 | "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c", |
| 185 | "pc_c", |
| 186 | "gbr_c", "mach_c", "macl_c", "pr_c", "t_c", |
| 187 | "fpscr_c", "fpul_c", |
| 188 | "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c", |
| 189 | "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c", |
| 190 | "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c", |
| 191 | "fv0_c", "fv4_c", "fv8_c", "fv12_c", |
| 192 | /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/ |
| 193 | }; |
| 194 | |
| 195 | if (reg_nr < 0) |
| 196 | return NULL; |
| 197 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) |
| 198 | return NULL; |
| 199 | return register_names[reg_nr]; |
| 200 | } |
| 201 | |
| 202 | #define NUM_PSEUDO_REGS_SH_MEDIA 80 |
| 203 | #define NUM_PSEUDO_REGS_SH_COMPACT 51 |
| 204 | |
| 205 | /* Macros and functions for setting and testing a bit in a minimal |
| 206 | symbol that marks it as 32-bit function. The MSB of the minimal |
| 207 | symbol's "info" field is used for this purpose. |
| 208 | |
| 209 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
| 210 | i.e. refers to a 32-bit function, and sets a "special" bit in a |
| 211 | minimal symbol to mark it as a 32-bit function |
| 212 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
| 213 | |
| 214 | #define MSYMBOL_IS_SPECIAL(msym) \ |
| 215 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) |
| 216 | |
| 217 | static void |
| 218 | sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) |
| 219 | { |
| 220 | if (msym == NULL) |
| 221 | return; |
| 222 | |
| 223 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32) |
| 224 | { |
| 225 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); |
| 226 | SYMBOL_VALUE_ADDRESS (msym) |= 1; |
| 227 | } |
| 228 | } |
| 229 | |
| 230 | /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here |
| 231 | are some macros to test, set, or clear bit 0 of addresses. */ |
| 232 | #define IS_ISA32_ADDR(addr) ((addr) & 1) |
| 233 | #define MAKE_ISA32_ADDR(addr) ((addr) | 1) |
| 234 | #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1) |
| 235 | |
| 236 | static int |
| 237 | pc_is_isa32 (bfd_vma memaddr) |
| 238 | { |
| 239 | struct minimal_symbol *sym; |
| 240 | |
| 241 | /* If bit 0 of the address is set, assume this is a |
| 242 | ISA32 (shmedia) address. */ |
| 243 | if (IS_ISA32_ADDR (memaddr)) |
| 244 | return 1; |
| 245 | |
| 246 | /* A flag indicating that this is a ISA32 function is stored by elfread.c in |
| 247 | the high bit of the info field. Use this to decide if the function is |
| 248 | ISA16 or ISA32. */ |
| 249 | sym = lookup_minimal_symbol_by_pc (memaddr); |
| 250 | if (sym) |
| 251 | return MSYMBOL_IS_SPECIAL (sym); |
| 252 | else |
| 253 | return 0; |
| 254 | } |
| 255 | |
| 256 | static const unsigned char * |
| 257 | sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
| 258 | { |
| 259 | /* The BRK instruction for shmedia is |
| 260 | 01101111 11110101 11111111 11110000 |
| 261 | which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0 |
| 262 | and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */ |
| 263 | |
| 264 | /* The BRK instruction for shcompact is |
| 265 | 00000000 00111011 |
| 266 | which translates in big endian mode to 0x0, 0x3b |
| 267 | and in little endian mode to 0x3b, 0x0*/ |
| 268 | |
| 269 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
| 270 | { |
| 271 | if (pc_is_isa32 (*pcptr)) |
| 272 | { |
| 273 | static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0}; |
| 274 | *pcptr = UNMAKE_ISA32_ADDR (*pcptr); |
| 275 | *lenptr = sizeof (big_breakpoint_media); |
| 276 | return big_breakpoint_media; |
| 277 | } |
| 278 | else |
| 279 | { |
| 280 | static unsigned char big_breakpoint_compact[] = {0x0, 0x3b}; |
| 281 | *lenptr = sizeof (big_breakpoint_compact); |
| 282 | return big_breakpoint_compact; |
| 283 | } |
| 284 | } |
| 285 | else |
| 286 | { |
| 287 | if (pc_is_isa32 (*pcptr)) |
| 288 | { |
| 289 | static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f}; |
| 290 | *pcptr = UNMAKE_ISA32_ADDR (*pcptr); |
| 291 | *lenptr = sizeof (little_breakpoint_media); |
| 292 | return little_breakpoint_media; |
| 293 | } |
| 294 | else |
| 295 | { |
| 296 | static unsigned char little_breakpoint_compact[] = {0x3b, 0x0}; |
| 297 | *lenptr = sizeof (little_breakpoint_compact); |
| 298 | return little_breakpoint_compact; |
| 299 | } |
| 300 | } |
| 301 | } |
| 302 | |
| 303 | /* Prologue looks like |
| 304 | [mov.l <regs>,@-r15]... |
| 305 | [sts.l pr,@-r15] |
| 306 | [mov.l r14,@-r15] |
| 307 | [mov r15,r14] |
| 308 | |
| 309 | Actually it can be more complicated than this. For instance, with |
| 310 | newer gcc's: |
| 311 | |
| 312 | mov.l r14,@-r15 |
| 313 | add #-12,r15 |
| 314 | mov r15,r14 |
| 315 | mov r4,r1 |
| 316 | mov r5,r2 |
| 317 | mov.l r6,@(4,r14) |
| 318 | mov.l r7,@(8,r14) |
| 319 | mov.b r1,@r14 |
| 320 | mov r14,r1 |
| 321 | mov r14,r1 |
| 322 | add #2,r1 |
| 323 | mov.w r2,@r1 |
| 324 | |
| 325 | */ |
| 326 | |
| 327 | /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000 |
| 328 | with l=1 and n = 18 0110101111110001010010100aaa0000 */ |
| 329 | #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00) |
| 330 | |
| 331 | /* STS.L PR,@-r0 0100000000100010 |
| 332 | r0-4-->r0, PR-->(r0) */ |
| 333 | #define IS_STS_R0(x) ((x) == 0x4022) |
| 334 | |
| 335 | /* STS PR, Rm 0000mmmm00101010 |
| 336 | PR-->Rm */ |
| 337 | #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a) |
| 338 | |
| 339 | /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd |
| 340 | Rm-->(dispx4+r15) */ |
| 341 | #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00) |
| 342 | |
| 343 | /* MOV.L R14,@(disp,r15) 000111111110dddd |
| 344 | R14-->(dispx4+r15) */ |
| 345 | #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0) |
| 346 | |
| 347 | /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000 |
| 348 | R18-->(dispx8+R14) */ |
| 349 | #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120) |
| 350 | |
| 351 | /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000 |
| 352 | R18-->(dispx8+R15) */ |
| 353 | #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120) |
| 354 | |
| 355 | /* ST.L R15, disp, R18 101010001111dddddddddd0100100000 |
| 356 | R18-->(dispx4+R15) */ |
| 357 | #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120) |
| 358 | |
| 359 | /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000 |
| 360 | R14-->(dispx8+R15) */ |
| 361 | #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0) |
| 362 | |
| 363 | /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000 |
| 364 | R14-->(dispx4+R15) */ |
| 365 | #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0) |
| 366 | |
| 367 | /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000 |
| 368 | R15 + imm --> R15 */ |
| 369 | #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0) |
| 370 | |
| 371 | /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000 |
| 372 | R15 + imm --> R15 */ |
| 373 | #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0) |
| 374 | |
| 375 | /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000 |
| 376 | R15 + R63 --> R14 */ |
| 377 | #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0) |
| 378 | |
| 379 | /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000 |
| 380 | R15 + R63 --> R14 */ |
| 381 | #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0) |
| 382 | |
| 383 | #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x)) |
| 384 | |
| 385 | /* MOV #imm, R0 1110 0000 ssss ssss |
| 386 | #imm-->R0 */ |
| 387 | #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000) |
| 388 | |
| 389 | /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */ |
| 390 | #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000) |
| 391 | |
| 392 | /* ADD r15,r0 0011 0000 1111 1100 |
| 393 | r15+r0-->r0 */ |
| 394 | #define IS_ADD_SP_R0(x) ((x) == 0x30fc) |
| 395 | |
| 396 | /* MOV.L R14 @-R0 0010 0000 1110 0110 |
| 397 | R14-->(R0-4), R0-4-->R0 */ |
| 398 | #define IS_MOV_R14_R0(x) ((x) == 0x20e6) |
| 399 | |
| 400 | /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000 |
| 401 | where Rm is one of r2-r9 which are the argument registers. */ |
| 402 | /* FIXME: Recognize the float and double register moves too! */ |
| 403 | #define IS_MEDIA_IND_ARG_MOV(x) \ |
| 404 | ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000)) |
| 405 | |
| 406 | /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000 |
| 407 | or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000 |
| 408 | where Rm is one of r2-r9 which are the argument registers. */ |
| 409 | #define IS_MEDIA_ARG_MOV(x) \ |
| 410 | (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \ |
| 411 | && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090)) |
| 412 | |
| 413 | /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/ |
| 414 | /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/ |
| 415 | /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/ |
| 416 | /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/ |
| 417 | /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/ |
| 418 | #define IS_MEDIA_MOV_TO_R14(x) \ |
| 419 | ((((x) & 0xfffffc0f) == 0xa0e00000) \ |
| 420 | || (((x) & 0xfffffc0f) == 0xa4e00000) \ |
| 421 | || (((x) & 0xfffffc0f) == 0xa8e00000) \ |
| 422 | || (((x) & 0xfffffc0f) == 0xb4e00000) \ |
| 423 | || (((x) & 0xfffffc0f) == 0xbce00000)) |
| 424 | |
| 425 | /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011 |
| 426 | where Rm is r2-r9 */ |
| 427 | #define IS_COMPACT_IND_ARG_MOV(x) \ |
| 428 | ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090)) |
| 429 | |
| 430 | /* compact direct arg move! |
| 431 | MOV.L Rn, @r14 0010 1110 mmmm 0010 */ |
| 432 | #define IS_COMPACT_ARG_MOV(x) \ |
| 433 | (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090)) |
| 434 | |
| 435 | /* MOV.B Rm, @R14 0010 1110 mmmm 0000 |
| 436 | MOV.W Rm, @R14 0010 1110 mmmm 0001 */ |
| 437 | #define IS_COMPACT_MOV_TO_R14(x) \ |
| 438 | ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01)) |
| 439 | |
| 440 | #define IS_JSR_R0(x) ((x) == 0x400b) |
| 441 | #define IS_NOP(x) ((x) == 0x0009) |
| 442 | |
| 443 | |
| 444 | /* MOV r15,r14 0110111011110011 |
| 445 | r15-->r14 */ |
| 446 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) |
| 447 | |
| 448 | /* ADD #imm,r15 01111111iiiiiiii |
| 449 | r15+imm-->r15 */ |
| 450 | #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00) |
| 451 | |
| 452 | /* Skip any prologue before the guts of a function */ |
| 453 | |
| 454 | /* Skip the prologue using the debug information. If this fails we'll |
| 455 | fall back on the 'guess' method below. */ |
| 456 | static CORE_ADDR |
| 457 | after_prologue (CORE_ADDR pc) |
| 458 | { |
| 459 | struct symtab_and_line sal; |
| 460 | CORE_ADDR func_addr, func_end; |
| 461 | |
| 462 | /* If we can not find the symbol in the partial symbol table, then |
| 463 | there is no hope we can determine the function's start address |
| 464 | with this code. */ |
| 465 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
| 466 | return 0; |
| 467 | |
| 468 | |
| 469 | /* Get the line associated with FUNC_ADDR. */ |
| 470 | sal = find_pc_line (func_addr, 0); |
| 471 | |
| 472 | /* There are only two cases to consider. First, the end of the source line |
| 473 | is within the function bounds. In that case we return the end of the |
| 474 | source line. Second is the end of the source line extends beyond the |
| 475 | bounds of the current function. We need to use the slow code to |
| 476 | examine instructions in that case. */ |
| 477 | if (sal.end < func_end) |
| 478 | return sal.end; |
| 479 | else |
| 480 | return 0; |
| 481 | } |
| 482 | |
| 483 | static CORE_ADDR |
| 484 | look_for_args_moves (CORE_ADDR start_pc, int media_mode) |
| 485 | { |
| 486 | CORE_ADDR here, end; |
| 487 | int w; |
| 488 | int insn_size = (media_mode ? 4 : 2); |
| 489 | |
| 490 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) |
| 491 | { |
| 492 | if (media_mode) |
| 493 | { |
| 494 | w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size); |
| 495 | here += insn_size; |
| 496 | if (IS_MEDIA_IND_ARG_MOV (w)) |
| 497 | { |
| 498 | /* This must be followed by a store to r14, so the argument |
| 499 | is where the debug info says it is. This can happen after |
| 500 | the SP has been saved, unfortunately. */ |
| 501 | |
| 502 | int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here), |
| 503 | insn_size); |
| 504 | here += insn_size; |
| 505 | if (IS_MEDIA_MOV_TO_R14 (next_insn)) |
| 506 | start_pc = here; |
| 507 | } |
| 508 | else if (IS_MEDIA_ARG_MOV (w)) |
| 509 | { |
| 510 | /* These instructions store directly the argument in r14. */ |
| 511 | start_pc = here; |
| 512 | } |
| 513 | else |
| 514 | break; |
| 515 | } |
| 516 | else |
| 517 | { |
| 518 | w = read_memory_integer (here, insn_size); |
| 519 | w = w & 0xffff; |
| 520 | here += insn_size; |
| 521 | if (IS_COMPACT_IND_ARG_MOV (w)) |
| 522 | { |
| 523 | /* This must be followed by a store to r14, so the argument |
| 524 | is where the debug info says it is. This can happen after |
| 525 | the SP has been saved, unfortunately. */ |
| 526 | |
| 527 | int next_insn = 0xffff & read_memory_integer (here, insn_size); |
| 528 | here += insn_size; |
| 529 | if (IS_COMPACT_MOV_TO_R14 (next_insn)) |
| 530 | start_pc = here; |
| 531 | } |
| 532 | else if (IS_COMPACT_ARG_MOV (w)) |
| 533 | { |
| 534 | /* These instructions store directly the argument in r14. */ |
| 535 | start_pc = here; |
| 536 | } |
| 537 | else if (IS_MOVL_R0 (w)) |
| 538 | { |
| 539 | /* There is a function that gcc calls to get the arguments |
| 540 | passed correctly to the function. Only after this |
| 541 | function call the arguments will be found at the place |
| 542 | where they are supposed to be. This happens in case the |
| 543 | argument has to be stored into a 64-bit register (for |
| 544 | instance doubles, long longs). SHcompact doesn't have |
| 545 | access to the full 64-bits, so we store the register in |
| 546 | stack slot and store the address of the stack slot in |
| 547 | the register, then do a call through a wrapper that |
| 548 | loads the memory value into the register. A SHcompact |
| 549 | callee calls an argument decoder |
| 550 | (GCC_shcompact_incoming_args) that stores the 64-bit |
| 551 | value in a stack slot and stores the address of the |
| 552 | stack slot in the register. GCC thinks the argument is |
| 553 | just passed by transparent reference, but this is only |
| 554 | true after the argument decoder is called. Such a call |
| 555 | needs to be considered part of the prologue. */ |
| 556 | |
| 557 | /* This must be followed by a JSR @r0 instruction and by |
| 558 | a NOP instruction. After these, the prologue is over! */ |
| 559 | |
| 560 | int next_insn = 0xffff & read_memory_integer (here, insn_size); |
| 561 | here += insn_size; |
| 562 | if (IS_JSR_R0 (next_insn)) |
| 563 | { |
| 564 | next_insn = 0xffff & read_memory_integer (here, insn_size); |
| 565 | here += insn_size; |
| 566 | |
| 567 | if (IS_NOP (next_insn)) |
| 568 | start_pc = here; |
| 569 | } |
| 570 | } |
| 571 | else |
| 572 | break; |
| 573 | } |
| 574 | } |
| 575 | |
| 576 | return start_pc; |
| 577 | } |
| 578 | |
| 579 | static CORE_ADDR |
| 580 | sh64_skip_prologue_hard_way (CORE_ADDR start_pc) |
| 581 | { |
| 582 | CORE_ADDR here, end; |
| 583 | int updated_fp = 0; |
| 584 | int insn_size = 4; |
| 585 | int media_mode = 1; |
| 586 | |
| 587 | if (!start_pc) |
| 588 | return 0; |
| 589 | |
| 590 | if (pc_is_isa32 (start_pc) == 0) |
| 591 | { |
| 592 | insn_size = 2; |
| 593 | media_mode = 0; |
| 594 | } |
| 595 | |
| 596 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) |
| 597 | { |
| 598 | |
| 599 | if (media_mode) |
| 600 | { |
| 601 | int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size); |
| 602 | here += insn_size; |
| 603 | if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w) |
| 604 | || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w) |
| 605 | || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w)) |
| 606 | { |
| 607 | start_pc = here; |
| 608 | } |
| 609 | else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w)) |
| 610 | { |
| 611 | start_pc = here; |
| 612 | updated_fp = 1; |
| 613 | } |
| 614 | else |
| 615 | if (updated_fp) |
| 616 | { |
| 617 | /* Don't bail out yet, we may have arguments stored in |
| 618 | registers here, according to the debug info, so that |
| 619 | gdb can print the frames correctly. */ |
| 620 | start_pc = look_for_args_moves (here - insn_size, media_mode); |
| 621 | break; |
| 622 | } |
| 623 | } |
| 624 | else |
| 625 | { |
| 626 | int w = 0xffff & read_memory_integer (here, insn_size); |
| 627 | here += insn_size; |
| 628 | |
| 629 | if (IS_STS_R0 (w) || IS_STS_PR (w) |
| 630 | || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w) |
| 631 | || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w)) |
| 632 | { |
| 633 | start_pc = here; |
| 634 | } |
| 635 | else if (IS_MOV_SP_FP (w)) |
| 636 | { |
| 637 | start_pc = here; |
| 638 | updated_fp = 1; |
| 639 | } |
| 640 | else |
| 641 | if (updated_fp) |
| 642 | { |
| 643 | /* Don't bail out yet, we may have arguments stored in |
| 644 | registers here, according to the debug info, so that |
| 645 | gdb can print the frames correctly. */ |
| 646 | start_pc = look_for_args_moves (here - insn_size, media_mode); |
| 647 | break; |
| 648 | } |
| 649 | } |
| 650 | } |
| 651 | |
| 652 | return start_pc; |
| 653 | } |
| 654 | |
| 655 | static CORE_ADDR |
| 656 | sh64_skip_prologue (CORE_ADDR pc) |
| 657 | { |
| 658 | CORE_ADDR post_prologue_pc; |
| 659 | |
| 660 | /* See if we can determine the end of the prologue via the symbol table. |
| 661 | If so, then return either PC, or the PC after the prologue, whichever |
| 662 | is greater. */ |
| 663 | post_prologue_pc = after_prologue (pc); |
| 664 | |
| 665 | /* If after_prologue returned a useful address, then use it. Else |
| 666 | fall back on the instruction skipping code. */ |
| 667 | if (post_prologue_pc != 0) |
| 668 | return max (pc, post_prologue_pc); |
| 669 | else |
| 670 | return sh64_skip_prologue_hard_way (pc); |
| 671 | } |
| 672 | |
| 673 | /* Should call_function allocate stack space for a struct return? */ |
| 674 | static int |
| 675 | sh64_use_struct_convention (struct type *type) |
| 676 | { |
| 677 | return (TYPE_LENGTH (type) > 8); |
| 678 | } |
| 679 | |
| 680 | /* Disassemble an instruction. */ |
| 681 | static int |
| 682 | gdb_print_insn_sh64 (bfd_vma memaddr, disassemble_info *info) |
| 683 | { |
| 684 | info->endian = gdbarch_byte_order (current_gdbarch); |
| 685 | return print_insn_sh (memaddr, info); |
| 686 | } |
| 687 | |
| 688 | /* For vectors of 4 floating point registers. */ |
| 689 | static int |
| 690 | sh64_fv_reg_base_num (int fv_regnum) |
| 691 | { |
| 692 | int fp_regnum; |
| 693 | |
| 694 | fp_regnum = FP0_REGNUM + |
| 695 | (fv_regnum - FV0_REGNUM) * 4; |
| 696 | return fp_regnum; |
| 697 | } |
| 698 | |
| 699 | /* For double precision floating point registers, i.e 2 fp regs.*/ |
| 700 | static int |
| 701 | sh64_dr_reg_base_num (int dr_regnum) |
| 702 | { |
| 703 | int fp_regnum; |
| 704 | |
| 705 | fp_regnum = FP0_REGNUM + |
| 706 | (dr_regnum - DR0_REGNUM) * 2; |
| 707 | return fp_regnum; |
| 708 | } |
| 709 | |
| 710 | /* For pairs of floating point registers */ |
| 711 | static int |
| 712 | sh64_fpp_reg_base_num (int fpp_regnum) |
| 713 | { |
| 714 | int fp_regnum; |
| 715 | |
| 716 | fp_regnum = FP0_REGNUM + |
| 717 | (fpp_regnum - FPP0_REGNUM) * 2; |
| 718 | return fp_regnum; |
| 719 | } |
| 720 | |
| 721 | /* *INDENT-OFF* */ |
| 722 | /* |
| 723 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 |
| 724 | GDB_REGNUM BASE_REGNUM |
| 725 | r0_c 221 0 |
| 726 | r1_c 222 1 |
| 727 | r2_c 223 2 |
| 728 | r3_c 224 3 |
| 729 | r4_c 225 4 |
| 730 | r5_c 226 5 |
| 731 | r6_c 227 6 |
| 732 | r7_c 228 7 |
| 733 | r8_c 229 8 |
| 734 | r9_c 230 9 |
| 735 | r10_c 231 10 |
| 736 | r11_c 232 11 |
| 737 | r12_c 233 12 |
| 738 | r13_c 234 13 |
| 739 | r14_c 235 14 |
| 740 | r15_c 236 15 |
| 741 | |
| 742 | pc_c 237 64 |
| 743 | gbr_c 238 16 |
| 744 | mach_c 239 17 |
| 745 | macl_c 240 17 |
| 746 | pr_c 241 18 |
| 747 | t_c 242 19 |
| 748 | fpscr_c 243 76 |
| 749 | fpul_c 244 109 |
| 750 | |
| 751 | fr0_c 245 77 |
| 752 | fr1_c 246 78 |
| 753 | fr2_c 247 79 |
| 754 | fr3_c 248 80 |
| 755 | fr4_c 249 81 |
| 756 | fr5_c 250 82 |
| 757 | fr6_c 251 83 |
| 758 | fr7_c 252 84 |
| 759 | fr8_c 253 85 |
| 760 | fr9_c 254 86 |
| 761 | fr10_c 255 87 |
| 762 | fr11_c 256 88 |
| 763 | fr12_c 257 89 |
| 764 | fr13_c 258 90 |
| 765 | fr14_c 259 91 |
| 766 | fr15_c 260 92 |
| 767 | |
| 768 | dr0_c 261 77 |
| 769 | dr2_c 262 79 |
| 770 | dr4_c 263 81 |
| 771 | dr6_c 264 83 |
| 772 | dr8_c 265 85 |
| 773 | dr10_c 266 87 |
| 774 | dr12_c 267 89 |
| 775 | dr14_c 268 91 |
| 776 | |
| 777 | fv0_c 269 77 |
| 778 | fv4_c 270 81 |
| 779 | fv8_c 271 85 |
| 780 | fv12_c 272 91 |
| 781 | */ |
| 782 | /* *INDENT-ON* */ |
| 783 | static int |
| 784 | sh64_compact_reg_base_num (int reg_nr) |
| 785 | { |
| 786 | int base_regnum = reg_nr; |
| 787 | |
| 788 | /* general register N maps to general register N */ |
| 789 | if (reg_nr >= R0_C_REGNUM |
| 790 | && reg_nr <= R_LAST_C_REGNUM) |
| 791 | base_regnum = reg_nr - R0_C_REGNUM; |
| 792 | |
| 793 | /* floating point register N maps to floating point register N */ |
| 794 | else if (reg_nr >= FP0_C_REGNUM |
| 795 | && reg_nr <= FP_LAST_C_REGNUM) |
| 796 | base_regnum = reg_nr - FP0_C_REGNUM + FP0_REGNUM; |
| 797 | |
| 798 | /* double prec register N maps to base regnum for double prec register N */ |
| 799 | else if (reg_nr >= DR0_C_REGNUM |
| 800 | && reg_nr <= DR_LAST_C_REGNUM) |
| 801 | base_regnum = sh64_dr_reg_base_num (DR0_REGNUM + reg_nr - DR0_C_REGNUM); |
| 802 | |
| 803 | /* vector N maps to base regnum for vector register N */ |
| 804 | else if (reg_nr >= FV0_C_REGNUM |
| 805 | && reg_nr <= FV_LAST_C_REGNUM) |
| 806 | base_regnum = sh64_fv_reg_base_num (FV0_REGNUM + reg_nr - FV0_C_REGNUM); |
| 807 | |
| 808 | else if (reg_nr == PC_C_REGNUM) |
| 809 | base_regnum = PC_REGNUM; |
| 810 | |
| 811 | else if (reg_nr == GBR_C_REGNUM) |
| 812 | base_regnum = 16; |
| 813 | |
| 814 | else if (reg_nr == MACH_C_REGNUM |
| 815 | || reg_nr == MACL_C_REGNUM) |
| 816 | base_regnum = 17; |
| 817 | |
| 818 | else if (reg_nr == PR_C_REGNUM) |
| 819 | base_regnum = PR_REGNUM; |
| 820 | |
| 821 | else if (reg_nr == T_C_REGNUM) |
| 822 | base_regnum = 19; |
| 823 | |
| 824 | else if (reg_nr == FPSCR_C_REGNUM) |
| 825 | base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */ |
| 826 | |
| 827 | else if (reg_nr == FPUL_C_REGNUM) |
| 828 | base_regnum = FP0_REGNUM + 32; |
| 829 | |
| 830 | return base_regnum; |
| 831 | } |
| 832 | |
| 833 | static int |
| 834 | sign_extend (int value, int bits) |
| 835 | { |
| 836 | value = value & ((1 << bits) - 1); |
| 837 | return (value & (1 << (bits - 1)) |
| 838 | ? value | (~((1 << bits) - 1)) |
| 839 | : value); |
| 840 | } |
| 841 | |
| 842 | static void |
| 843 | sh64_analyze_prologue (struct gdbarch *gdbarch, |
| 844 | struct sh64_frame_cache *cache, |
| 845 | CORE_ADDR func_pc, |
| 846 | CORE_ADDR current_pc) |
| 847 | { |
| 848 | int reg_nr; |
| 849 | int pc; |
| 850 | int opc; |
| 851 | int insn; |
| 852 | int r0_val = 0; |
| 853 | int insn_size; |
| 854 | int gdb_register_number; |
| 855 | int register_number; |
| 856 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 857 | |
| 858 | cache->sp_offset = 0; |
| 859 | |
| 860 | /* Loop around examining the prologue insns until we find something |
| 861 | that does not appear to be part of the prologue. But give up |
| 862 | after 20 of them, since we're getting silly then. */ |
| 863 | |
| 864 | pc = func_pc; |
| 865 | |
| 866 | if (cache->media_mode) |
| 867 | insn_size = 4; |
| 868 | else |
| 869 | insn_size = 2; |
| 870 | |
| 871 | opc = pc + (insn_size * 28); |
| 872 | if (opc > current_pc) |
| 873 | opc = current_pc; |
| 874 | for ( ; pc <= opc; pc += insn_size) |
| 875 | { |
| 876 | insn = read_memory_integer (cache->media_mode ? UNMAKE_ISA32_ADDR (pc) |
| 877 | : pc, |
| 878 | insn_size); |
| 879 | |
| 880 | if (!cache->media_mode) |
| 881 | { |
| 882 | if (IS_STS_PR (insn)) |
| 883 | { |
| 884 | int next_insn = read_memory_integer (pc + insn_size, insn_size); |
| 885 | if (IS_MOV_TO_R15 (next_insn)) |
| 886 | { |
| 887 | cache->saved_regs[PR_REGNUM] = |
| 888 | cache->sp_offset - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2); |
| 889 | pc += insn_size; |
| 890 | } |
| 891 | } |
| 892 | |
| 893 | else if (IS_MOV_R14 (insn)) |
| 894 | cache->saved_regs[MEDIA_FP_REGNUM] = |
| 895 | cache->sp_offset - ((((insn & 0xf) ^ 0x8) - 0x8) << 2); |
| 896 | |
| 897 | else if (IS_MOV_R0 (insn)) |
| 898 | { |
| 899 | /* Put in R0 the offset from SP at which to store some |
| 900 | registers. We are interested in this value, because it |
| 901 | will tell us where the given registers are stored within |
| 902 | the frame. */ |
| 903 | r0_val = ((insn & 0xff) ^ 0x80) - 0x80; |
| 904 | } |
| 905 | |
| 906 | else if (IS_ADD_SP_R0 (insn)) |
| 907 | { |
| 908 | /* This instruction still prepares r0, but we don't care. |
| 909 | We already have the offset in r0_val. */ |
| 910 | } |
| 911 | |
| 912 | else if (IS_STS_R0 (insn)) |
| 913 | { |
| 914 | /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/ |
| 915 | cache->saved_regs[PR_REGNUM] = cache->sp_offset - (r0_val - 4); |
| 916 | r0_val -= 4; |
| 917 | } |
| 918 | |
| 919 | else if (IS_MOV_R14_R0 (insn)) |
| 920 | { |
| 921 | /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */ |
| 922 | cache->saved_regs[MEDIA_FP_REGNUM] = cache->sp_offset |
| 923 | - (r0_val - 4); |
| 924 | r0_val -= 4; |
| 925 | } |
| 926 | |
| 927 | else if (IS_ADD_SP (insn)) |
| 928 | cache->sp_offset -= ((insn & 0xff) ^ 0x80) - 0x80; |
| 929 | |
| 930 | else if (IS_MOV_SP_FP (insn)) |
| 931 | break; |
| 932 | } |
| 933 | else |
| 934 | { |
| 935 | if (IS_ADDIL_SP_MEDIA (insn) || IS_ADDI_SP_MEDIA (insn)) |
| 936 | cache->sp_offset -= |
| 937 | sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9); |
| 938 | |
| 939 | else if (IS_STQ_R18_R15 (insn)) |
| 940 | cache->saved_regs[PR_REGNUM] = |
| 941 | cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3); |
| 942 | |
| 943 | else if (IS_STL_R18_R15 (insn)) |
| 944 | cache->saved_regs[PR_REGNUM] = |
| 945 | cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2); |
| 946 | |
| 947 | else if (IS_STQ_R14_R15 (insn)) |
| 948 | cache->saved_regs[MEDIA_FP_REGNUM] = |
| 949 | cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3); |
| 950 | |
| 951 | else if (IS_STL_R14_R15 (insn)) |
| 952 | cache->saved_regs[MEDIA_FP_REGNUM] = |
| 953 | cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2); |
| 954 | |
| 955 | else if (IS_MOV_SP_FP_MEDIA (insn)) |
| 956 | break; |
| 957 | } |
| 958 | } |
| 959 | |
| 960 | if (cache->saved_regs[MEDIA_FP_REGNUM] >= 0) |
| 961 | cache->uses_fp = 1; |
| 962 | } |
| 963 | |
| 964 | static CORE_ADDR |
| 965 | sh64_extract_struct_value_address (struct regcache *regcache) |
| 966 | { |
| 967 | /* FIXME: cagney/2004-01-17: Does the ABI guarantee that the return |
| 968 | address regster is preserved across function calls? Probably |
| 969 | not, making this function wrong. */ |
| 970 | ULONGEST val; |
| 971 | regcache_raw_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &val); |
| 972 | return val; |
| 973 | } |
| 974 | |
| 975 | static CORE_ADDR |
| 976 | sh64_frame_align (struct gdbarch *ignore, CORE_ADDR sp) |
| 977 | { |
| 978 | return sp & ~7; |
| 979 | } |
| 980 | |
| 981 | /* Function: push_dummy_call |
| 982 | Setup the function arguments for calling a function in the inferior. |
| 983 | |
| 984 | On the Renesas SH architecture, there are four registers (R4 to R7) |
| 985 | which are dedicated for passing function arguments. Up to the first |
| 986 | four arguments (depending on size) may go into these registers. |
| 987 | The rest go on the stack. |
| 988 | |
| 989 | Arguments that are smaller than 4 bytes will still take up a whole |
| 990 | register or a whole 32-bit word on the stack, and will be |
| 991 | right-justified in the register or the stack word. This includes |
| 992 | chars, shorts, and small aggregate types. |
| 993 | |
| 994 | Arguments that are larger than 4 bytes may be split between two or |
| 995 | more registers. If there are not enough registers free, an argument |
| 996 | may be passed partly in a register (or registers), and partly on the |
| 997 | stack. This includes doubles, long longs, and larger aggregates. |
| 998 | As far as I know, there is no upper limit to the size of aggregates |
| 999 | that will be passed in this way; in other words, the convention of |
| 1000 | passing a pointer to a large aggregate instead of a copy is not used. |
| 1001 | |
| 1002 | An exceptional case exists for struct arguments (and possibly other |
| 1003 | aggregates such as arrays) if the size is larger than 4 bytes but |
| 1004 | not a multiple of 4 bytes. In this case the argument is never split |
| 1005 | between the registers and the stack, but instead is copied in its |
| 1006 | entirety onto the stack, AND also copied into as many registers as |
| 1007 | there is room for. In other words, space in registers permitting, |
| 1008 | two copies of the same argument are passed in. As far as I can tell, |
| 1009 | only the one on the stack is used, although that may be a function |
| 1010 | of the level of compiler optimization. I suspect this is a compiler |
| 1011 | bug. Arguments of these odd sizes are left-justified within the |
| 1012 | word (as opposed to arguments smaller than 4 bytes, which are |
| 1013 | right-justified). |
| 1014 | |
| 1015 | If the function is to return an aggregate type such as a struct, it |
| 1016 | is either returned in the normal return value register R0 (if its |
| 1017 | size is no greater than one byte), or else the caller must allocate |
| 1018 | space into which the callee will copy the return value (if the size |
| 1019 | is greater than one byte). In this case, a pointer to the return |
| 1020 | value location is passed into the callee in register R2, which does |
| 1021 | not displace any of the other arguments passed in via registers R4 |
| 1022 | to R7. */ |
| 1023 | |
| 1024 | /* R2-R9 for integer types and integer equivalent (char, pointers) and |
| 1025 | non-scalar (struct, union) elements (even if the elements are |
| 1026 | floats). |
| 1027 | FR0-FR11 for single precision floating point (float) |
| 1028 | DR0-DR10 for double precision floating point (double) |
| 1029 | |
| 1030 | If a float is argument number 3 (for instance) and arguments number |
| 1031 | 1,2, and 4 are integer, the mapping will be: |
| 1032 | arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used. |
| 1033 | |
| 1034 | If a float is argument number 10 (for instance) and arguments number |
| 1035 | 1 through 10 are integer, the mapping will be: |
| 1036 | arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8, |
| 1037 | arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP). |
| 1038 | I.e. there is hole in the stack. |
| 1039 | |
| 1040 | Different rules apply for variable arguments functions, and for functions |
| 1041 | for which the prototype is not known. */ |
| 1042 | |
| 1043 | static CORE_ADDR |
| 1044 | sh64_push_dummy_call (struct gdbarch *gdbarch, |
| 1045 | struct value *function, |
| 1046 | struct regcache *regcache, |
| 1047 | CORE_ADDR bp_addr, |
| 1048 | int nargs, struct value **args, |
| 1049 | CORE_ADDR sp, int struct_return, |
| 1050 | CORE_ADDR struct_addr) |
| 1051 | { |
| 1052 | int stack_offset, stack_alloc; |
| 1053 | int int_argreg; |
| 1054 | int float_argreg; |
| 1055 | int double_argreg; |
| 1056 | int float_arg_index = 0; |
| 1057 | int double_arg_index = 0; |
| 1058 | int argnum; |
| 1059 | struct type *type; |
| 1060 | CORE_ADDR regval; |
| 1061 | char *val; |
| 1062 | char valbuf[8]; |
| 1063 | char valbuf_tmp[8]; |
| 1064 | int len; |
| 1065 | int argreg_size; |
| 1066 | int fp_args[12]; |
| 1067 | |
| 1068 | memset (fp_args, 0, sizeof (fp_args)); |
| 1069 | |
| 1070 | /* first force sp to a 8-byte alignment */ |
| 1071 | sp = sh64_frame_align (gdbarch, sp); |
| 1072 | |
| 1073 | /* The "struct return pointer" pseudo-argument has its own dedicated |
| 1074 | register */ |
| 1075 | |
| 1076 | if (struct_return) |
| 1077 | regcache_cooked_write_unsigned (regcache, |
| 1078 | STRUCT_RETURN_REGNUM, struct_addr); |
| 1079 | |
| 1080 | /* Now make sure there's space on the stack */ |
| 1081 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) |
| 1082 | stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 7) & ~7); |
| 1083 | sp -= stack_alloc; /* make room on stack for args */ |
| 1084 | |
| 1085 | /* Now load as many as possible of the first arguments into |
| 1086 | registers, and push the rest onto the stack. There are 64 bytes |
| 1087 | in eight registers available. Loop thru args from first to last. */ |
| 1088 | |
| 1089 | int_argreg = ARG0_REGNUM; |
| 1090 | float_argreg = FP0_REGNUM; |
| 1091 | double_argreg = DR0_REGNUM; |
| 1092 | |
| 1093 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) |
| 1094 | { |
| 1095 | type = value_type (args[argnum]); |
| 1096 | len = TYPE_LENGTH (type); |
| 1097 | memset (valbuf, 0, sizeof (valbuf)); |
| 1098 | |
| 1099 | if (TYPE_CODE (type) != TYPE_CODE_FLT) |
| 1100 | { |
| 1101 | argreg_size = register_size (current_gdbarch, int_argreg); |
| 1102 | |
| 1103 | if (len < argreg_size) |
| 1104 | { |
| 1105 | /* value gets right-justified in the register or stack word */ |
| 1106 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
| 1107 | memcpy (valbuf + argreg_size - len, |
| 1108 | (char *) value_contents (args[argnum]), len); |
| 1109 | else |
| 1110 | memcpy (valbuf, (char *) value_contents (args[argnum]), len); |
| 1111 | |
| 1112 | val = valbuf; |
| 1113 | } |
| 1114 | else |
| 1115 | val = (char *) value_contents (args[argnum]); |
| 1116 | |
| 1117 | while (len > 0) |
| 1118 | { |
| 1119 | if (int_argreg > ARGLAST_REGNUM) |
| 1120 | { |
| 1121 | /* must go on the stack */ |
| 1122 | write_memory (sp + stack_offset, (const bfd_byte *) val, |
| 1123 | argreg_size); |
| 1124 | stack_offset += 8;/*argreg_size;*/ |
| 1125 | } |
| 1126 | /* NOTE WELL!!!!! This is not an "else if" clause!!! |
| 1127 | That's because some *&^%$ things get passed on the stack |
| 1128 | AND in the registers! */ |
| 1129 | if (int_argreg <= ARGLAST_REGNUM) |
| 1130 | { |
| 1131 | /* there's room in a register */ |
| 1132 | regval = extract_unsigned_integer (val, argreg_size); |
| 1133 | regcache_cooked_write_unsigned (regcache, int_argreg, regval); |
| 1134 | } |
| 1135 | /* Store the value 8 bytes at a time. This means that |
| 1136 | things larger than 8 bytes may go partly in registers |
| 1137 | and partly on the stack. FIXME: argreg is incremented |
| 1138 | before we use its size. */ |
| 1139 | len -= argreg_size; |
| 1140 | val += argreg_size; |
| 1141 | int_argreg++; |
| 1142 | } |
| 1143 | } |
| 1144 | else |
| 1145 | { |
| 1146 | val = (char *) value_contents (args[argnum]); |
| 1147 | if (len == 4) |
| 1148 | { |
| 1149 | /* Where is it going to be stored? */ |
| 1150 | while (fp_args[float_arg_index]) |
| 1151 | float_arg_index ++; |
| 1152 | |
| 1153 | /* Now float_argreg points to the register where it |
| 1154 | should be stored. Are we still within the allowed |
| 1155 | register set? */ |
| 1156 | if (float_arg_index <= FLOAT_ARGLAST_REGNUM) |
| 1157 | { |
| 1158 | /* Goes in FR0...FR11 */ |
| 1159 | regcache_cooked_write (regcache, |
| 1160 | FP0_REGNUM + float_arg_index, |
| 1161 | val); |
| 1162 | fp_args[float_arg_index] = 1; |
| 1163 | /* Skip the corresponding general argument register. */ |
| 1164 | int_argreg ++; |
| 1165 | } |
| 1166 | else |
| 1167 | ; |
| 1168 | /* Store it as the integers, 8 bytes at the time, if |
| 1169 | necessary spilling on the stack. */ |
| 1170 | |
| 1171 | } |
| 1172 | else if (len == 8) |
| 1173 | { |
| 1174 | /* Where is it going to be stored? */ |
| 1175 | while (fp_args[double_arg_index]) |
| 1176 | double_arg_index += 2; |
| 1177 | /* Now double_argreg points to the register |
| 1178 | where it should be stored. |
| 1179 | Are we still within the allowed register set? */ |
| 1180 | if (double_arg_index < FLOAT_ARGLAST_REGNUM) |
| 1181 | { |
| 1182 | /* Goes in DR0...DR10 */ |
| 1183 | /* The numbering of the DRi registers is consecutive, |
| 1184 | i.e. includes odd numbers. */ |
| 1185 | int double_register_offset = double_arg_index / 2; |
| 1186 | int regnum = DR0_REGNUM + double_register_offset; |
| 1187 | regcache_cooked_write (regcache, regnum, val); |
| 1188 | fp_args[double_arg_index] = 1; |
| 1189 | fp_args[double_arg_index + 1] = 1; |
| 1190 | /* Skip the corresponding general argument register. */ |
| 1191 | int_argreg ++; |
| 1192 | } |
| 1193 | else |
| 1194 | ; |
| 1195 | /* Store it as the integers, 8 bytes at the time, if |
| 1196 | necessary spilling on the stack. */ |
| 1197 | } |
| 1198 | } |
| 1199 | } |
| 1200 | /* Store return address. */ |
| 1201 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
| 1202 | |
| 1203 | /* Update stack pointer. */ |
| 1204 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); |
| 1205 | |
| 1206 | return sp; |
| 1207 | } |
| 1208 | |
| 1209 | /* Find a function's return value in the appropriate registers (in |
| 1210 | regbuf), and copy it into valbuf. Extract from an array REGBUF |
| 1211 | containing the (raw) register state a function return value of type |
| 1212 | TYPE, and copy that, in virtual format, into VALBUF. */ |
| 1213 | static void |
| 1214 | sh64_extract_return_value (struct type *type, struct regcache *regcache, |
| 1215 | void *valbuf) |
| 1216 | { |
| 1217 | int len = TYPE_LENGTH (type); |
| 1218 | |
| 1219 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
| 1220 | { |
| 1221 | if (len == 4) |
| 1222 | { |
| 1223 | /* Return value stored in FP0_REGNUM */ |
| 1224 | regcache_raw_read (regcache, FP0_REGNUM, valbuf); |
| 1225 | } |
| 1226 | else if (len == 8) |
| 1227 | { |
| 1228 | /* return value stored in DR0_REGNUM */ |
| 1229 | DOUBLEST val; |
| 1230 | gdb_byte buf[8]; |
| 1231 | |
| 1232 | regcache_cooked_read (regcache, DR0_REGNUM, buf); |
| 1233 | |
| 1234 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
| 1235 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, |
| 1236 | buf, &val); |
| 1237 | else |
| 1238 | floatformat_to_doublest (&floatformat_ieee_double_big, |
| 1239 | buf, &val); |
| 1240 | store_typed_floating (valbuf, type, val); |
| 1241 | } |
| 1242 | } |
| 1243 | else |
| 1244 | { |
| 1245 | if (len <= 8) |
| 1246 | { |
| 1247 | int offset; |
| 1248 | char buf[8]; |
| 1249 | /* Result is in register 2. If smaller than 8 bytes, it is padded |
| 1250 | at the most significant end. */ |
| 1251 | regcache_raw_read (regcache, DEFAULT_RETURN_REGNUM, buf); |
| 1252 | |
| 1253 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
| 1254 | offset = register_size (current_gdbarch, DEFAULT_RETURN_REGNUM) |
| 1255 | - len; |
| 1256 | else |
| 1257 | offset = 0; |
| 1258 | memcpy (valbuf, buf + offset, len); |
| 1259 | } |
| 1260 | else |
| 1261 | error ("bad size for return value"); |
| 1262 | } |
| 1263 | } |
| 1264 | |
| 1265 | /* Write into appropriate registers a function return value |
| 1266 | of type TYPE, given in virtual format. |
| 1267 | If the architecture is sh4 or sh3e, store a function's return value |
| 1268 | in the R0 general register or in the FP0 floating point register, |
| 1269 | depending on the type of the return value. In all the other cases |
| 1270 | the result is stored in r0, left-justified. */ |
| 1271 | |
| 1272 | static void |
| 1273 | sh64_store_return_value (struct type *type, struct regcache *regcache, |
| 1274 | const void *valbuf) |
| 1275 | { |
| 1276 | char buf[64]; /* more than enough... */ |
| 1277 | int len = TYPE_LENGTH (type); |
| 1278 | |
| 1279 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
| 1280 | { |
| 1281 | int i, regnum = FP0_REGNUM; |
| 1282 | for (i = 0; i < len; i += 4) |
| 1283 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
| 1284 | regcache_raw_write (regcache, regnum++, |
| 1285 | (char *) valbuf + len - 4 - i); |
| 1286 | else |
| 1287 | regcache_raw_write (regcache, regnum++, (char *) valbuf + i); |
| 1288 | } |
| 1289 | else |
| 1290 | { |
| 1291 | int return_register = DEFAULT_RETURN_REGNUM; |
| 1292 | int offset = 0; |
| 1293 | |
| 1294 | if (len <= register_size (current_gdbarch, return_register)) |
| 1295 | { |
| 1296 | /* Pad with zeros. */ |
| 1297 | memset (buf, 0, register_size (current_gdbarch, return_register)); |
| 1298 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
| 1299 | offset = 0; /*register_size (current_gdbarch, |
| 1300 | return_register) - len;*/ |
| 1301 | else |
| 1302 | offset = register_size (current_gdbarch, return_register) - len; |
| 1303 | |
| 1304 | memcpy (buf + offset, valbuf, len); |
| 1305 | regcache_raw_write (regcache, return_register, buf); |
| 1306 | } |
| 1307 | else |
| 1308 | regcache_raw_write (regcache, return_register, valbuf); |
| 1309 | } |
| 1310 | } |
| 1311 | |
| 1312 | static enum return_value_convention |
| 1313 | sh64_return_value (struct gdbarch *gdbarch, struct type *type, |
| 1314 | struct regcache *regcache, |
| 1315 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 1316 | { |
| 1317 | if (sh64_use_struct_convention (type)) |
| 1318 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 1319 | if (writebuf) |
| 1320 | sh64_store_return_value (type, regcache, writebuf); |
| 1321 | else if (readbuf) |
| 1322 | sh64_extract_return_value (type, regcache, readbuf); |
| 1323 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 1324 | } |
| 1325 | |
| 1326 | static void |
| 1327 | sh64_show_media_regs (void) |
| 1328 | { |
| 1329 | int i; |
| 1330 | |
| 1331 | printf_filtered ("PC=%s SR=%016llx \n", |
| 1332 | paddr (read_register (PC_REGNUM)), |
| 1333 | (long long) read_register (SR_REGNUM)); |
| 1334 | |
| 1335 | printf_filtered ("SSR=%016llx SPC=%016llx \n", |
| 1336 | (long long) read_register (SSR_REGNUM), |
| 1337 | (long long) read_register (SPC_REGNUM)); |
| 1338 | printf_filtered ("FPSCR=%016lx\n ", |
| 1339 | (long) read_register (FPSCR_REGNUM)); |
| 1340 | |
| 1341 | for (i = 0; i < 64; i = i + 4) |
| 1342 | printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n", |
| 1343 | i, i + 3, |
| 1344 | (long long) read_register (i + 0), |
| 1345 | (long long) read_register (i + 1), |
| 1346 | (long long) read_register (i + 2), |
| 1347 | (long long) read_register (i + 3)); |
| 1348 | |
| 1349 | printf_filtered ("\n"); |
| 1350 | |
| 1351 | for (i = 0; i < 64; i = i + 8) |
| 1352 | printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
| 1353 | i, i + 7, |
| 1354 | (long) read_register (FP0_REGNUM + i + 0), |
| 1355 | (long) read_register (FP0_REGNUM + i + 1), |
| 1356 | (long) read_register (FP0_REGNUM + i + 2), |
| 1357 | (long) read_register (FP0_REGNUM + i + 3), |
| 1358 | (long) read_register (FP0_REGNUM + i + 4), |
| 1359 | (long) read_register (FP0_REGNUM + i + 5), |
| 1360 | (long) read_register (FP0_REGNUM + i + 6), |
| 1361 | (long) read_register (FP0_REGNUM + i + 7)); |
| 1362 | } |
| 1363 | |
| 1364 | static void |
| 1365 | sh64_show_compact_regs (void) |
| 1366 | { |
| 1367 | int i; |
| 1368 | |
| 1369 | printf_filtered ("PC=%s \n", |
| 1370 | paddr (read_register (PC_C_REGNUM))); |
| 1371 | |
| 1372 | printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n", |
| 1373 | (long) read_register (GBR_C_REGNUM), |
| 1374 | (long) read_register (MACH_C_REGNUM), |
| 1375 | (long) read_register (MACL_C_REGNUM), |
| 1376 | (long) read_register (PR_C_REGNUM), |
| 1377 | (long) read_register (T_C_REGNUM)); |
| 1378 | printf_filtered ("FPSCR=%08lx FPUL=%08lx\n", |
| 1379 | (long) read_register (FPSCR_C_REGNUM), |
| 1380 | (long) read_register (FPUL_C_REGNUM)); |
| 1381 | |
| 1382 | for (i = 0; i < 16; i = i + 4) |
| 1383 | printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n", |
| 1384 | i, i + 3, |
| 1385 | (long) read_register (i + 0), |
| 1386 | (long) read_register (i + 1), |
| 1387 | (long) read_register (i + 2), |
| 1388 | (long) read_register (i + 3)); |
| 1389 | |
| 1390 | printf_filtered ("\n"); |
| 1391 | |
| 1392 | for (i = 0; i < 16; i = i + 8) |
| 1393 | printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
| 1394 | i, i + 7, |
| 1395 | (long) read_register (FP0_REGNUM + i + 0), |
| 1396 | (long) read_register (FP0_REGNUM + i + 1), |
| 1397 | (long) read_register (FP0_REGNUM + i + 2), |
| 1398 | (long) read_register (FP0_REGNUM + i + 3), |
| 1399 | (long) read_register (FP0_REGNUM + i + 4), |
| 1400 | (long) read_register (FP0_REGNUM + i + 5), |
| 1401 | (long) read_register (FP0_REGNUM + i + 6), |
| 1402 | (long) read_register (FP0_REGNUM + i + 7)); |
| 1403 | } |
| 1404 | |
| 1405 | /* FIXME!!! This only shows the registers for shmedia, excluding the |
| 1406 | pseudo registers. */ |
| 1407 | void |
| 1408 | sh64_show_regs (void) |
| 1409 | { |
| 1410 | if (pc_is_isa32 (get_frame_pc (get_selected_frame (NULL)))) |
| 1411 | sh64_show_media_regs (); |
| 1412 | else |
| 1413 | sh64_show_compact_regs (); |
| 1414 | } |
| 1415 | |
| 1416 | /* *INDENT-OFF* */ |
| 1417 | /* |
| 1418 | SH MEDIA MODE (ISA 32) |
| 1419 | general registers (64-bit) 0-63 |
| 1420 | 0 r0, r1, r2, r3, r4, r5, r6, r7, |
| 1421 | 64 r8, r9, r10, r11, r12, r13, r14, r15, |
| 1422 | 128 r16, r17, r18, r19, r20, r21, r22, r23, |
| 1423 | 192 r24, r25, r26, r27, r28, r29, r30, r31, |
| 1424 | 256 r32, r33, r34, r35, r36, r37, r38, r39, |
| 1425 | 320 r40, r41, r42, r43, r44, r45, r46, r47, |
| 1426 | 384 r48, r49, r50, r51, r52, r53, r54, r55, |
| 1427 | 448 r56, r57, r58, r59, r60, r61, r62, r63, |
| 1428 | |
| 1429 | pc (64-bit) 64 |
| 1430 | 512 pc, |
| 1431 | |
| 1432 | status reg., saved status reg., saved pc reg. (64-bit) 65-67 |
| 1433 | 520 sr, ssr, spc, |
| 1434 | |
| 1435 | target registers (64-bit) 68-75 |
| 1436 | 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7, |
| 1437 | |
| 1438 | floating point state control register (32-bit) 76 |
| 1439 | 608 fpscr, |
| 1440 | |
| 1441 | single precision floating point registers (32-bit) 77-140 |
| 1442 | 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, |
| 1443 | 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15, |
| 1444 | 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23, |
| 1445 | 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31, |
| 1446 | 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39, |
| 1447 | 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47, |
| 1448 | 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55, |
| 1449 | 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63, |
| 1450 | |
| 1451 | TOTAL SPACE FOR REGISTERS: 868 bytes |
| 1452 | |
| 1453 | From here on they are all pseudo registers: no memory allocated. |
| 1454 | REGISTER_BYTE returns the register byte for the base register. |
| 1455 | |
| 1456 | double precision registers (pseudo) 141-172 |
| 1457 | dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14, |
| 1458 | dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30, |
| 1459 | dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46, |
| 1460 | dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62, |
| 1461 | |
| 1462 | floating point pairs (pseudo) 173-204 |
| 1463 | fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14, |
| 1464 | fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30, |
| 1465 | fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46, |
| 1466 | fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62, |
| 1467 | |
| 1468 | floating point vectors (4 floating point regs) (pseudo) 205-220 |
| 1469 | fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28, |
| 1470 | fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60, |
| 1471 | |
| 1472 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 |
| 1473 | r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c, |
| 1474 | r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c, |
| 1475 | pc_c, |
| 1476 | gbr_c, mach_c, macl_c, pr_c, t_c, |
| 1477 | fpscr_c, fpul_c, |
| 1478 | fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c, |
| 1479 | fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c |
| 1480 | dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c |
| 1481 | fv0_c, fv4_c, fv8_c, fv12_c |
| 1482 | */ |
| 1483 | |
| 1484 | static struct type * |
| 1485 | sh64_build_float_register_type (int high) |
| 1486 | { |
| 1487 | struct type *temp; |
| 1488 | |
| 1489 | temp = create_range_type (NULL, builtin_type_int, 0, high); |
| 1490 | return create_array_type (NULL, builtin_type_float, temp); |
| 1491 | } |
| 1492 | |
| 1493 | /* Return the GDB type object for the "standard" data type |
| 1494 | of data in register REG_NR. */ |
| 1495 | static struct type * |
| 1496 | sh64_register_type (struct gdbarch *gdbarch, int reg_nr) |
| 1497 | { |
| 1498 | if ((reg_nr >= FP0_REGNUM |
| 1499 | && reg_nr <= FP_LAST_REGNUM) |
| 1500 | || (reg_nr >= FP0_C_REGNUM |
| 1501 | && reg_nr <= FP_LAST_C_REGNUM)) |
| 1502 | return builtin_type_float; |
| 1503 | else if ((reg_nr >= DR0_REGNUM |
| 1504 | && reg_nr <= DR_LAST_REGNUM) |
| 1505 | || (reg_nr >= DR0_C_REGNUM |
| 1506 | && reg_nr <= DR_LAST_C_REGNUM)) |
| 1507 | return builtin_type_double; |
| 1508 | else if (reg_nr >= FPP0_REGNUM |
| 1509 | && reg_nr <= FPP_LAST_REGNUM) |
| 1510 | return sh64_build_float_register_type (1); |
| 1511 | else if ((reg_nr >= FV0_REGNUM |
| 1512 | && reg_nr <= FV_LAST_REGNUM) |
| 1513 | ||(reg_nr >= FV0_C_REGNUM |
| 1514 | && reg_nr <= FV_LAST_C_REGNUM)) |
| 1515 | return sh64_build_float_register_type (3); |
| 1516 | else if (reg_nr == FPSCR_REGNUM) |
| 1517 | return builtin_type_int; |
| 1518 | else if (reg_nr >= R0_C_REGNUM |
| 1519 | && reg_nr < FP0_C_REGNUM) |
| 1520 | return builtin_type_int; |
| 1521 | else |
| 1522 | return builtin_type_long_long; |
| 1523 | } |
| 1524 | |
| 1525 | static void |
| 1526 | sh64_register_convert_to_virtual (int regnum, struct type *type, |
| 1527 | char *from, char *to) |
| 1528 | { |
| 1529 | if (gdbarch_byte_order (current_gdbarch) != BFD_ENDIAN_LITTLE) |
| 1530 | { |
| 1531 | /* It is a no-op. */ |
| 1532 | memcpy (to, from, register_size (current_gdbarch, regnum)); |
| 1533 | return; |
| 1534 | } |
| 1535 | |
| 1536 | if ((regnum >= DR0_REGNUM |
| 1537 | && regnum <= DR_LAST_REGNUM) |
| 1538 | || (regnum >= DR0_C_REGNUM |
| 1539 | && regnum <= DR_LAST_C_REGNUM)) |
| 1540 | { |
| 1541 | DOUBLEST val; |
| 1542 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, |
| 1543 | from, &val); |
| 1544 | store_typed_floating (to, type, val); |
| 1545 | } |
| 1546 | else |
| 1547 | error ("sh64_register_convert_to_virtual called with non DR register number"); |
| 1548 | } |
| 1549 | |
| 1550 | static void |
| 1551 | sh64_register_convert_to_raw (struct type *type, int regnum, |
| 1552 | const void *from, void *to) |
| 1553 | { |
| 1554 | if (gdbarch_byte_order (current_gdbarch) != BFD_ENDIAN_LITTLE) |
| 1555 | { |
| 1556 | /* It is a no-op. */ |
| 1557 | memcpy (to, from, register_size (current_gdbarch, regnum)); |
| 1558 | return; |
| 1559 | } |
| 1560 | |
| 1561 | if ((regnum >= DR0_REGNUM |
| 1562 | && regnum <= DR_LAST_REGNUM) |
| 1563 | || (regnum >= DR0_C_REGNUM |
| 1564 | && regnum <= DR_LAST_C_REGNUM)) |
| 1565 | { |
| 1566 | DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type)); |
| 1567 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, |
| 1568 | &val, to); |
| 1569 | } |
| 1570 | else |
| 1571 | error ("sh64_register_convert_to_raw called with non DR register number"); |
| 1572 | } |
| 1573 | |
| 1574 | static void |
| 1575 | sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
| 1576 | int reg_nr, gdb_byte *buffer) |
| 1577 | { |
| 1578 | int base_regnum; |
| 1579 | int portion; |
| 1580 | int offset = 0; |
| 1581 | char temp_buffer[MAX_REGISTER_SIZE]; |
| 1582 | |
| 1583 | if (reg_nr >= DR0_REGNUM |
| 1584 | && reg_nr <= DR_LAST_REGNUM) |
| 1585 | { |
| 1586 | base_regnum = sh64_dr_reg_base_num (reg_nr); |
| 1587 | |
| 1588 | /* Build the value in the provided buffer. */ |
| 1589 | /* DR regs are double precision registers obtained by |
| 1590 | concatenating 2 single precision floating point registers. */ |
| 1591 | for (portion = 0; portion < 2; portion++) |
| 1592 | regcache_raw_read (regcache, base_regnum + portion, |
| 1593 | (temp_buffer |
| 1594 | + register_size (gdbarch, base_regnum) * portion)); |
| 1595 | |
| 1596 | /* We must pay attention to the endianness. */ |
| 1597 | sh64_register_convert_to_virtual (reg_nr, |
| 1598 | register_type (gdbarch, reg_nr), |
| 1599 | temp_buffer, buffer); |
| 1600 | |
| 1601 | } |
| 1602 | |
| 1603 | else if (reg_nr >= FPP0_REGNUM |
| 1604 | && reg_nr <= FPP_LAST_REGNUM) |
| 1605 | { |
| 1606 | base_regnum = sh64_fpp_reg_base_num (reg_nr); |
| 1607 | |
| 1608 | /* Build the value in the provided buffer. */ |
| 1609 | /* FPP regs are pairs of single precision registers obtained by |
| 1610 | concatenating 2 single precision floating point registers. */ |
| 1611 | for (portion = 0; portion < 2; portion++) |
| 1612 | regcache_raw_read (regcache, base_regnum + portion, |
| 1613 | ((char *) buffer |
| 1614 | + register_size (gdbarch, base_regnum) * portion)); |
| 1615 | } |
| 1616 | |
| 1617 | else if (reg_nr >= FV0_REGNUM |
| 1618 | && reg_nr <= FV_LAST_REGNUM) |
| 1619 | { |
| 1620 | base_regnum = sh64_fv_reg_base_num (reg_nr); |
| 1621 | |
| 1622 | /* Build the value in the provided buffer. */ |
| 1623 | /* FV regs are vectors of single precision registers obtained by |
| 1624 | concatenating 4 single precision floating point registers. */ |
| 1625 | for (portion = 0; portion < 4; portion++) |
| 1626 | regcache_raw_read (regcache, base_regnum + portion, |
| 1627 | ((char *) buffer |
| 1628 | + register_size (gdbarch, base_regnum) * portion)); |
| 1629 | } |
| 1630 | |
| 1631 | /* sh compact pseudo registers. 1-to-1 with a shmedia register */ |
| 1632 | else if (reg_nr >= R0_C_REGNUM |
| 1633 | && reg_nr <= T_C_REGNUM) |
| 1634 | { |
| 1635 | base_regnum = sh64_compact_reg_base_num (reg_nr); |
| 1636 | |
| 1637 | /* Build the value in the provided buffer. */ |
| 1638 | regcache_raw_read (regcache, base_regnum, temp_buffer); |
| 1639 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
| 1640 | offset = 4; |
| 1641 | memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/ |
| 1642 | } |
| 1643 | |
| 1644 | else if (reg_nr >= FP0_C_REGNUM |
| 1645 | && reg_nr <= FP_LAST_C_REGNUM) |
| 1646 | { |
| 1647 | base_regnum = sh64_compact_reg_base_num (reg_nr); |
| 1648 | |
| 1649 | /* Build the value in the provided buffer. */ |
| 1650 | /* Floating point registers map 1-1 to the media fp regs, |
| 1651 | they have the same size and endianness. */ |
| 1652 | regcache_raw_read (regcache, base_regnum, buffer); |
| 1653 | } |
| 1654 | |
| 1655 | else if (reg_nr >= DR0_C_REGNUM |
| 1656 | && reg_nr <= DR_LAST_C_REGNUM) |
| 1657 | { |
| 1658 | base_regnum = sh64_compact_reg_base_num (reg_nr); |
| 1659 | |
| 1660 | /* DR_C regs are double precision registers obtained by |
| 1661 | concatenating 2 single precision floating point registers. */ |
| 1662 | for (portion = 0; portion < 2; portion++) |
| 1663 | regcache_raw_read (regcache, base_regnum + portion, |
| 1664 | (temp_buffer |
| 1665 | + register_size (gdbarch, base_regnum) * portion)); |
| 1666 | |
| 1667 | /* We must pay attention to the endianness. */ |
| 1668 | sh64_register_convert_to_virtual (reg_nr, |
| 1669 | register_type (gdbarch, reg_nr), |
| 1670 | temp_buffer, buffer); |
| 1671 | } |
| 1672 | |
| 1673 | else if (reg_nr >= FV0_C_REGNUM |
| 1674 | && reg_nr <= FV_LAST_C_REGNUM) |
| 1675 | { |
| 1676 | base_regnum = sh64_compact_reg_base_num (reg_nr); |
| 1677 | |
| 1678 | /* Build the value in the provided buffer. */ |
| 1679 | /* FV_C regs are vectors of single precision registers obtained by |
| 1680 | concatenating 4 single precision floating point registers. */ |
| 1681 | for (portion = 0; portion < 4; portion++) |
| 1682 | regcache_raw_read (regcache, base_regnum + portion, |
| 1683 | ((char *) buffer |
| 1684 | + register_size (gdbarch, base_regnum) * portion)); |
| 1685 | } |
| 1686 | |
| 1687 | else if (reg_nr == FPSCR_C_REGNUM) |
| 1688 | { |
| 1689 | int fpscr_base_regnum; |
| 1690 | int sr_base_regnum; |
| 1691 | unsigned int fpscr_value; |
| 1692 | unsigned int sr_value; |
| 1693 | unsigned int fpscr_c_value; |
| 1694 | unsigned int fpscr_c_part1_value; |
| 1695 | unsigned int fpscr_c_part2_value; |
| 1696 | |
| 1697 | fpscr_base_regnum = FPSCR_REGNUM; |
| 1698 | sr_base_regnum = SR_REGNUM; |
| 1699 | |
| 1700 | /* Build the value in the provided buffer. */ |
| 1701 | /* FPSCR_C is a very weird register that contains sparse bits |
| 1702 | from the FPSCR and the SR architectural registers. |
| 1703 | Specifically: */ |
| 1704 | /* *INDENT-OFF* */ |
| 1705 | /* |
| 1706 | FPSRC_C bit |
| 1707 | 0 Bit 0 of FPSCR |
| 1708 | 1 reserved |
| 1709 | 2-17 Bit 2-18 of FPSCR |
| 1710 | 18-20 Bits 12,13,14 of SR |
| 1711 | 21-31 reserved |
| 1712 | */ |
| 1713 | /* *INDENT-ON* */ |
| 1714 | /* Get FPSCR into a local buffer */ |
| 1715 | regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer); |
| 1716 | /* Get value as an int. */ |
| 1717 | fpscr_value = extract_unsigned_integer (temp_buffer, 4); |
| 1718 | /* Get SR into a local buffer */ |
| 1719 | regcache_raw_read (regcache, sr_base_regnum, temp_buffer); |
| 1720 | /* Get value as an int. */ |
| 1721 | sr_value = extract_unsigned_integer (temp_buffer, 4); |
| 1722 | /* Build the new value. */ |
| 1723 | fpscr_c_part1_value = fpscr_value & 0x3fffd; |
| 1724 | fpscr_c_part2_value = (sr_value & 0x7000) << 6; |
| 1725 | fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value; |
| 1726 | /* Store that in out buffer!!! */ |
| 1727 | store_unsigned_integer (buffer, 4, fpscr_c_value); |
| 1728 | /* FIXME There is surely an endianness gotcha here. */ |
| 1729 | } |
| 1730 | |
| 1731 | else if (reg_nr == FPUL_C_REGNUM) |
| 1732 | { |
| 1733 | base_regnum = sh64_compact_reg_base_num (reg_nr); |
| 1734 | |
| 1735 | /* FPUL_C register is floating point register 32, |
| 1736 | same size, same endianness. */ |
| 1737 | regcache_raw_read (regcache, base_regnum, buffer); |
| 1738 | } |
| 1739 | } |
| 1740 | |
| 1741 | static void |
| 1742 | sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
| 1743 | int reg_nr, const gdb_byte *buffer) |
| 1744 | { |
| 1745 | int base_regnum, portion; |
| 1746 | int offset; |
| 1747 | char temp_buffer[MAX_REGISTER_SIZE]; |
| 1748 | |
| 1749 | if (reg_nr >= DR0_REGNUM |
| 1750 | && reg_nr <= DR_LAST_REGNUM) |
| 1751 | { |
| 1752 | base_regnum = sh64_dr_reg_base_num (reg_nr); |
| 1753 | /* We must pay attention to the endianness. */ |
| 1754 | sh64_register_convert_to_raw (register_type (gdbarch, reg_nr), |
| 1755 | reg_nr, |
| 1756 | buffer, temp_buffer); |
| 1757 | |
| 1758 | /* Write the real regs for which this one is an alias. */ |
| 1759 | for (portion = 0; portion < 2; portion++) |
| 1760 | regcache_raw_write (regcache, base_regnum + portion, |
| 1761 | (temp_buffer |
| 1762 | + register_size (gdbarch, |
| 1763 | base_regnum) * portion)); |
| 1764 | } |
| 1765 | |
| 1766 | else if (reg_nr >= FPP0_REGNUM |
| 1767 | && reg_nr <= FPP_LAST_REGNUM) |
| 1768 | { |
| 1769 | base_regnum = sh64_fpp_reg_base_num (reg_nr); |
| 1770 | |
| 1771 | /* Write the real regs for which this one is an alias. */ |
| 1772 | for (portion = 0; portion < 2; portion++) |
| 1773 | regcache_raw_write (regcache, base_regnum + portion, |
| 1774 | ((char *) buffer |
| 1775 | + register_size (gdbarch, |
| 1776 | base_regnum) * portion)); |
| 1777 | } |
| 1778 | |
| 1779 | else if (reg_nr >= FV0_REGNUM |
| 1780 | && reg_nr <= FV_LAST_REGNUM) |
| 1781 | { |
| 1782 | base_regnum = sh64_fv_reg_base_num (reg_nr); |
| 1783 | |
| 1784 | /* Write the real regs for which this one is an alias. */ |
| 1785 | for (portion = 0; portion < 4; portion++) |
| 1786 | regcache_raw_write (regcache, base_regnum + portion, |
| 1787 | ((char *) buffer |
| 1788 | + register_size (gdbarch, |
| 1789 | base_regnum) * portion)); |
| 1790 | } |
| 1791 | |
| 1792 | /* sh compact general pseudo registers. 1-to-1 with a shmedia |
| 1793 | register but only 4 bytes of it. */ |
| 1794 | else if (reg_nr >= R0_C_REGNUM |
| 1795 | && reg_nr <= T_C_REGNUM) |
| 1796 | { |
| 1797 | base_regnum = sh64_compact_reg_base_num (reg_nr); |
| 1798 | /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ |
| 1799 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
| 1800 | offset = 4; |
| 1801 | else |
| 1802 | offset = 0; |
| 1803 | /* Let's read the value of the base register into a temporary |
| 1804 | buffer, so that overwriting the last four bytes with the new |
| 1805 | value of the pseudo will leave the upper 4 bytes unchanged. */ |
| 1806 | regcache_raw_read (regcache, base_regnum, temp_buffer); |
| 1807 | /* Write as an 8 byte quantity */ |
| 1808 | memcpy (temp_buffer + offset, buffer, 4); |
| 1809 | regcache_raw_write (regcache, base_regnum, temp_buffer); |
| 1810 | } |
| 1811 | |
| 1812 | /* sh floating point compact pseudo registers. 1-to-1 with a shmedia |
| 1813 | registers. Both are 4 bytes. */ |
| 1814 | else if (reg_nr >= FP0_C_REGNUM |
| 1815 | && reg_nr <= FP_LAST_C_REGNUM) |
| 1816 | { |
| 1817 | base_regnum = sh64_compact_reg_base_num (reg_nr); |
| 1818 | regcache_raw_write (regcache, base_regnum, buffer); |
| 1819 | } |
| 1820 | |
| 1821 | else if (reg_nr >= DR0_C_REGNUM |
| 1822 | && reg_nr <= DR_LAST_C_REGNUM) |
| 1823 | { |
| 1824 | base_regnum = sh64_compact_reg_base_num (reg_nr); |
| 1825 | for (portion = 0; portion < 2; portion++) |
| 1826 | { |
| 1827 | /* We must pay attention to the endianness. */ |
| 1828 | sh64_register_convert_to_raw (register_type (gdbarch, reg_nr), |
| 1829 | reg_nr, |
| 1830 | buffer, temp_buffer); |
| 1831 | |
| 1832 | regcache_raw_write (regcache, base_regnum + portion, |
| 1833 | (temp_buffer |
| 1834 | + register_size (gdbarch, |
| 1835 | base_regnum) * portion)); |
| 1836 | } |
| 1837 | } |
| 1838 | |
| 1839 | else if (reg_nr >= FV0_C_REGNUM |
| 1840 | && reg_nr <= FV_LAST_C_REGNUM) |
| 1841 | { |
| 1842 | base_regnum = sh64_compact_reg_base_num (reg_nr); |
| 1843 | |
| 1844 | for (portion = 0; portion < 4; portion++) |
| 1845 | { |
| 1846 | regcache_raw_write (regcache, base_regnum + portion, |
| 1847 | ((char *) buffer |
| 1848 | + register_size (gdbarch, |
| 1849 | base_regnum) * portion)); |
| 1850 | } |
| 1851 | } |
| 1852 | |
| 1853 | else if (reg_nr == FPSCR_C_REGNUM) |
| 1854 | { |
| 1855 | int fpscr_base_regnum; |
| 1856 | int sr_base_regnum; |
| 1857 | unsigned int fpscr_value; |
| 1858 | unsigned int sr_value; |
| 1859 | unsigned int old_fpscr_value; |
| 1860 | unsigned int old_sr_value; |
| 1861 | unsigned int fpscr_c_value; |
| 1862 | unsigned int fpscr_mask; |
| 1863 | unsigned int sr_mask; |
| 1864 | |
| 1865 | fpscr_base_regnum = FPSCR_REGNUM; |
| 1866 | sr_base_regnum = SR_REGNUM; |
| 1867 | |
| 1868 | /* FPSCR_C is a very weird register that contains sparse bits |
| 1869 | from the FPSCR and the SR architectural registers. |
| 1870 | Specifically: */ |
| 1871 | /* *INDENT-OFF* */ |
| 1872 | /* |
| 1873 | FPSRC_C bit |
| 1874 | 0 Bit 0 of FPSCR |
| 1875 | 1 reserved |
| 1876 | 2-17 Bit 2-18 of FPSCR |
| 1877 | 18-20 Bits 12,13,14 of SR |
| 1878 | 21-31 reserved |
| 1879 | */ |
| 1880 | /* *INDENT-ON* */ |
| 1881 | /* Get value as an int. */ |
| 1882 | fpscr_c_value = extract_unsigned_integer (buffer, 4); |
| 1883 | |
| 1884 | /* Build the new values. */ |
| 1885 | fpscr_mask = 0x0003fffd; |
| 1886 | sr_mask = 0x001c0000; |
| 1887 | |
| 1888 | fpscr_value = fpscr_c_value & fpscr_mask; |
| 1889 | sr_value = (fpscr_value & sr_mask) >> 6; |
| 1890 | |
| 1891 | regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer); |
| 1892 | old_fpscr_value = extract_unsigned_integer (temp_buffer, 4); |
| 1893 | old_fpscr_value &= 0xfffc0002; |
| 1894 | fpscr_value |= old_fpscr_value; |
| 1895 | store_unsigned_integer (temp_buffer, 4, fpscr_value); |
| 1896 | regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer); |
| 1897 | |
| 1898 | regcache_raw_read (regcache, sr_base_regnum, temp_buffer); |
| 1899 | old_sr_value = extract_unsigned_integer (temp_buffer, 4); |
| 1900 | old_sr_value &= 0xffff8fff; |
| 1901 | sr_value |= old_sr_value; |
| 1902 | store_unsigned_integer (temp_buffer, 4, sr_value); |
| 1903 | regcache_raw_write (regcache, sr_base_regnum, temp_buffer); |
| 1904 | } |
| 1905 | |
| 1906 | else if (reg_nr == FPUL_C_REGNUM) |
| 1907 | { |
| 1908 | base_regnum = sh64_compact_reg_base_num (reg_nr); |
| 1909 | regcache_raw_write (regcache, base_regnum, buffer); |
| 1910 | } |
| 1911 | } |
| 1912 | |
| 1913 | /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE |
| 1914 | shmedia REGISTERS. */ |
| 1915 | /* Control registers, compact mode. */ |
| 1916 | static void |
| 1917 | sh64_do_cr_c_register_info (struct ui_file *file, struct frame_info *frame, |
| 1918 | int cr_c_regnum) |
| 1919 | { |
| 1920 | switch (cr_c_regnum) |
| 1921 | { |
| 1922 | case PC_C_REGNUM: |
| 1923 | fprintf_filtered (file, "pc_c\t0x%08x\n", |
| 1924 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); |
| 1925 | break; |
| 1926 | case GBR_C_REGNUM: |
| 1927 | fprintf_filtered (file, "gbr_c\t0x%08x\n", |
| 1928 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); |
| 1929 | break; |
| 1930 | case MACH_C_REGNUM: |
| 1931 | fprintf_filtered (file, "mach_c\t0x%08x\n", |
| 1932 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); |
| 1933 | break; |
| 1934 | case MACL_C_REGNUM: |
| 1935 | fprintf_filtered (file, "macl_c\t0x%08x\n", |
| 1936 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); |
| 1937 | break; |
| 1938 | case PR_C_REGNUM: |
| 1939 | fprintf_filtered (file, "pr_c\t0x%08x\n", |
| 1940 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); |
| 1941 | break; |
| 1942 | case T_C_REGNUM: |
| 1943 | fprintf_filtered (file, "t_c\t0x%08x\n", |
| 1944 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); |
| 1945 | break; |
| 1946 | case FPSCR_C_REGNUM: |
| 1947 | fprintf_filtered (file, "fpscr_c\t0x%08x\n", |
| 1948 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); |
| 1949 | break; |
| 1950 | case FPUL_C_REGNUM: |
| 1951 | fprintf_filtered (file, "fpul_c\t0x%08x\n", |
| 1952 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); |
| 1953 | break; |
| 1954 | } |
| 1955 | } |
| 1956 | |
| 1957 | static void |
| 1958 | sh64_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, |
| 1959 | struct frame_info *frame, int regnum) |
| 1960 | { /* do values for FP (float) regs */ |
| 1961 | unsigned char *raw_buffer; |
| 1962 | double flt; /* double extracted from raw hex data */ |
| 1963 | int inv; |
| 1964 | int j; |
| 1965 | |
| 1966 | /* Allocate space for the float. */ |
| 1967 | raw_buffer = (unsigned char *) alloca (register_size (gdbarch, FP0_REGNUM)); |
| 1968 | |
| 1969 | /* Get the data in raw format. */ |
| 1970 | if (!frame_register_read (frame, regnum, raw_buffer)) |
| 1971 | error ("can't read register %d (%s)", |
| 1972 | regnum, gdbarch_register_name (current_gdbarch, regnum)); |
| 1973 | |
| 1974 | /* Get the register as a number */ |
| 1975 | flt = unpack_double (builtin_type_float, raw_buffer, &inv); |
| 1976 | |
| 1977 | /* Print the name and some spaces. */ |
| 1978 | fputs_filtered (gdbarch_register_name (current_gdbarch, regnum), file); |
| 1979 | print_spaces_filtered (15 - strlen (gdbarch_register_name |
| 1980 | (current_gdbarch, regnum)), file); |
| 1981 | |
| 1982 | /* Print the value. */ |
| 1983 | if (inv) |
| 1984 | fprintf_filtered (file, "<invalid float>"); |
| 1985 | else |
| 1986 | fprintf_filtered (file, "%-10.9g", flt); |
| 1987 | |
| 1988 | /* Print the fp register as hex. */ |
| 1989 | fprintf_filtered (file, "\t(raw 0x"); |
| 1990 | for (j = 0; j < register_size (gdbarch, regnum); j++) |
| 1991 | { |
| 1992 | int idx = gdbarch_byte_order (current_gdbarch) |
| 1993 | == BFD_ENDIAN_BIG ? j : register_size |
| 1994 | (gdbarch, regnum) - 1 - j; |
| 1995 | fprintf_filtered (file, "%02x", raw_buffer[idx]); |
| 1996 | } |
| 1997 | fprintf_filtered (file, ")"); |
| 1998 | fprintf_filtered (file, "\n"); |
| 1999 | } |
| 2000 | |
| 2001 | static void |
| 2002 | sh64_do_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file, |
| 2003 | struct frame_info *frame, int regnum) |
| 2004 | { |
| 2005 | /* All the sh64-compact mode registers are pseudo registers. */ |
| 2006 | |
| 2007 | if (regnum < gdbarch_num_regs (current_gdbarch) |
| 2008 | || regnum >= gdbarch_num_regs (current_gdbarch) |
| 2009 | + NUM_PSEUDO_REGS_SH_MEDIA |
| 2010 | + NUM_PSEUDO_REGS_SH_COMPACT) |
| 2011 | internal_error (__FILE__, __LINE__, |
| 2012 | _("Invalid pseudo register number %d\n"), regnum); |
| 2013 | |
| 2014 | else if ((regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)) |
| 2015 | { |
| 2016 | int fp_regnum = sh64_dr_reg_base_num (regnum); |
| 2017 | fprintf_filtered (file, "dr%d\t0x%08x%08x\n", regnum - DR0_REGNUM, |
| 2018 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), |
| 2019 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1)); |
| 2020 | } |
| 2021 | |
| 2022 | else if ((regnum >= DR0_C_REGNUM && regnum <= DR_LAST_C_REGNUM)) |
| 2023 | { |
| 2024 | int fp_regnum = sh64_compact_reg_base_num (regnum); |
| 2025 | fprintf_filtered (file, "dr%d_c\t0x%08x%08x\n", regnum - DR0_C_REGNUM, |
| 2026 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), |
| 2027 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1)); |
| 2028 | } |
| 2029 | |
| 2030 | else if ((regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)) |
| 2031 | { |
| 2032 | int fp_regnum = sh64_fv_reg_base_num (regnum); |
| 2033 | fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", |
| 2034 | regnum - FV0_REGNUM, |
| 2035 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), |
| 2036 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1), |
| 2037 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2), |
| 2038 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3)); |
| 2039 | } |
| 2040 | |
| 2041 | else if ((regnum >= FV0_C_REGNUM && regnum <= FV_LAST_C_REGNUM)) |
| 2042 | { |
| 2043 | int fp_regnum = sh64_compact_reg_base_num (regnum); |
| 2044 | fprintf_filtered (file, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", |
| 2045 | regnum - FV0_C_REGNUM, |
| 2046 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), |
| 2047 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1), |
| 2048 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2), |
| 2049 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3)); |
| 2050 | } |
| 2051 | |
| 2052 | else if (regnum >= FPP0_REGNUM && regnum <= FPP_LAST_REGNUM) |
| 2053 | { |
| 2054 | int fp_regnum = sh64_fpp_reg_base_num (regnum); |
| 2055 | fprintf_filtered (file, "fpp%d\t0x%08x\t0x%08x\n", regnum - FPP0_REGNUM, |
| 2056 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), |
| 2057 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1)); |
| 2058 | } |
| 2059 | |
| 2060 | else if (regnum >= R0_C_REGNUM && regnum <= R_LAST_C_REGNUM) |
| 2061 | { |
| 2062 | int c_regnum = sh64_compact_reg_base_num (regnum); |
| 2063 | fprintf_filtered (file, "r%d_c\t0x%08x\n", regnum - R0_C_REGNUM, |
| 2064 | (unsigned) get_frame_register_unsigned (frame, c_regnum)); |
| 2065 | } |
| 2066 | else if (regnum >= FP0_C_REGNUM && regnum <= FP_LAST_C_REGNUM) |
| 2067 | /* This should work also for pseudoregs. */ |
| 2068 | sh64_do_fp_register (gdbarch, file, frame, regnum); |
| 2069 | else if (regnum >= PC_C_REGNUM && regnum <= FPUL_C_REGNUM) |
| 2070 | sh64_do_cr_c_register_info (file, frame, regnum); |
| 2071 | } |
| 2072 | |
| 2073 | static void |
| 2074 | sh64_do_register (struct gdbarch *gdbarch, struct ui_file *file, |
| 2075 | struct frame_info *frame, int regnum) |
| 2076 | { |
| 2077 | unsigned char raw_buffer[MAX_REGISTER_SIZE]; |
| 2078 | |
| 2079 | fputs_filtered (gdbarch_register_name (current_gdbarch, regnum), file); |
| 2080 | print_spaces_filtered (15 - strlen (gdbarch_register_name |
| 2081 | (current_gdbarch, regnum)), file); |
| 2082 | |
| 2083 | /* Get the data in raw format. */ |
| 2084 | if (!frame_register_read (frame, regnum, raw_buffer)) |
| 2085 | fprintf_filtered (file, "*value not available*\n"); |
| 2086 | |
| 2087 | val_print (register_type (gdbarch, regnum), raw_buffer, 0, 0, |
| 2088 | file, 'x', 1, 0, Val_pretty_default); |
| 2089 | fprintf_filtered (file, "\t"); |
| 2090 | val_print (register_type (gdbarch, regnum), raw_buffer, 0, 0, |
| 2091 | file, 0, 1, 0, Val_pretty_default); |
| 2092 | fprintf_filtered (file, "\n"); |
| 2093 | } |
| 2094 | |
| 2095 | static void |
| 2096 | sh64_print_register (struct gdbarch *gdbarch, struct ui_file *file, |
| 2097 | struct frame_info *frame, int regnum) |
| 2098 | { |
| 2099 | if (regnum < 0 || regnum >= gdbarch_num_regs (current_gdbarch) |
| 2100 | + gdbarch_num_pseudo_regs (current_gdbarch)) |
| 2101 | internal_error (__FILE__, __LINE__, |
| 2102 | _("Invalid register number %d\n"), regnum); |
| 2103 | |
| 2104 | else if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)) |
| 2105 | { |
| 2106 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
| 2107 | sh64_do_fp_register (gdbarch, file, frame, regnum); /* FP regs */ |
| 2108 | else |
| 2109 | sh64_do_register (gdbarch, file, frame, regnum); |
| 2110 | } |
| 2111 | |
| 2112 | else if (regnum < gdbarch_num_regs (current_gdbarch) |
| 2113 | + gdbarch_num_pseudo_regs (current_gdbarch)) |
| 2114 | sh64_do_pseudo_register (gdbarch, file, frame, regnum); |
| 2115 | } |
| 2116 | |
| 2117 | static void |
| 2118 | sh64_media_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
| 2119 | struct frame_info *frame, int regnum, |
| 2120 | int fpregs) |
| 2121 | { |
| 2122 | if (regnum != -1) /* do one specified register */ |
| 2123 | { |
| 2124 | if (*(gdbarch_register_name (current_gdbarch, regnum)) == '\0') |
| 2125 | error ("Not a valid register for the current processor type"); |
| 2126 | |
| 2127 | sh64_print_register (gdbarch, file, frame, regnum); |
| 2128 | } |
| 2129 | else |
| 2130 | /* do all (or most) registers */ |
| 2131 | { |
| 2132 | regnum = 0; |
| 2133 | while (regnum < gdbarch_num_regs (current_gdbarch)) |
| 2134 | { |
| 2135 | /* If the register name is empty, it is undefined for this |
| 2136 | processor, so don't display anything. */ |
| 2137 | if (gdbarch_register_name (current_gdbarch, regnum) == NULL |
| 2138 | || *(gdbarch_register_name (current_gdbarch, regnum)) == '\0') |
| 2139 | { |
| 2140 | regnum++; |
| 2141 | continue; |
| 2142 | } |
| 2143 | |
| 2144 | if (TYPE_CODE (register_type (gdbarch, regnum)) |
| 2145 | == TYPE_CODE_FLT) |
| 2146 | { |
| 2147 | if (fpregs) |
| 2148 | { |
| 2149 | /* true for "INFO ALL-REGISTERS" command */ |
| 2150 | sh64_do_fp_register (gdbarch, file, frame, regnum); |
| 2151 | regnum ++; |
| 2152 | } |
| 2153 | else |
| 2154 | regnum += FP_LAST_REGNUM - FP0_REGNUM; /* skip FP regs */ |
| 2155 | } |
| 2156 | else |
| 2157 | { |
| 2158 | sh64_do_register (gdbarch, file, frame, regnum); |
| 2159 | regnum++; |
| 2160 | } |
| 2161 | } |
| 2162 | |
| 2163 | if (fpregs) |
| 2164 | while (regnum < gdbarch_num_regs (current_gdbarch) |
| 2165 | + gdbarch_num_pseudo_regs (current_gdbarch)) |
| 2166 | { |
| 2167 | sh64_do_pseudo_register (gdbarch, file, frame, regnum); |
| 2168 | regnum++; |
| 2169 | } |
| 2170 | } |
| 2171 | } |
| 2172 | |
| 2173 | static void |
| 2174 | sh64_compact_print_registers_info (struct gdbarch *gdbarch, |
| 2175 | struct ui_file *file, |
| 2176 | struct frame_info *frame, int regnum, |
| 2177 | int fpregs) |
| 2178 | { |
| 2179 | if (regnum != -1) /* do one specified register */ |
| 2180 | { |
| 2181 | if (*(gdbarch_register_name (current_gdbarch, regnum)) == '\0') |
| 2182 | error ("Not a valid register for the current processor type"); |
| 2183 | |
| 2184 | if (regnum >= 0 && regnum < R0_C_REGNUM) |
| 2185 | error ("Not a valid register for the current processor mode."); |
| 2186 | |
| 2187 | sh64_print_register (gdbarch, file, frame, regnum); |
| 2188 | } |
| 2189 | else |
| 2190 | /* do all compact registers */ |
| 2191 | { |
| 2192 | regnum = R0_C_REGNUM; |
| 2193 | while (regnum < gdbarch_num_regs (current_gdbarch) |
| 2194 | + gdbarch_num_pseudo_regs (current_gdbarch)) |
| 2195 | { |
| 2196 | sh64_do_pseudo_register (gdbarch, file, frame, regnum); |
| 2197 | regnum++; |
| 2198 | } |
| 2199 | } |
| 2200 | } |
| 2201 | |
| 2202 | static void |
| 2203 | sh64_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
| 2204 | struct frame_info *frame, int regnum, int fpregs) |
| 2205 | { |
| 2206 | if (pc_is_isa32 (get_frame_pc (frame))) |
| 2207 | sh64_media_print_registers_info (gdbarch, file, frame, regnum, fpregs); |
| 2208 | else |
| 2209 | sh64_compact_print_registers_info (gdbarch, file, frame, regnum, fpregs); |
| 2210 | } |
| 2211 | |
| 2212 | static struct sh64_frame_cache * |
| 2213 | sh64_alloc_frame_cache (void) |
| 2214 | { |
| 2215 | struct sh64_frame_cache *cache; |
| 2216 | int i; |
| 2217 | |
| 2218 | cache = FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache); |
| 2219 | |
| 2220 | /* Base address. */ |
| 2221 | cache->base = 0; |
| 2222 | cache->saved_sp = 0; |
| 2223 | cache->sp_offset = 0; |
| 2224 | cache->pc = 0; |
| 2225 | |
| 2226 | /* Frameless until proven otherwise. */ |
| 2227 | cache->uses_fp = 0; |
| 2228 | |
| 2229 | /* Saved registers. We initialize these to -1 since zero is a valid |
| 2230 | offset (that's where fp is supposed to be stored). */ |
| 2231 | for (i = 0; i < SIM_SH64_NR_REGS; i++) |
| 2232 | { |
| 2233 | cache->saved_regs[i] = -1; |
| 2234 | } |
| 2235 | |
| 2236 | return cache; |
| 2237 | } |
| 2238 | |
| 2239 | static struct sh64_frame_cache * |
| 2240 | sh64_frame_cache (struct frame_info *next_frame, void **this_cache) |
| 2241 | { |
| 2242 | struct sh64_frame_cache *cache; |
| 2243 | CORE_ADDR current_pc; |
| 2244 | int i; |
| 2245 | |
| 2246 | if (*this_cache) |
| 2247 | return *this_cache; |
| 2248 | |
| 2249 | cache = sh64_alloc_frame_cache (); |
| 2250 | *this_cache = cache; |
| 2251 | |
| 2252 | current_pc = frame_pc_unwind (next_frame); |
| 2253 | cache->media_mode = pc_is_isa32 (current_pc); |
| 2254 | |
| 2255 | /* In principle, for normal frames, fp holds the frame pointer, |
| 2256 | which holds the base address for the current stack frame. |
| 2257 | However, for functions that don't need it, the frame pointer is |
| 2258 | optional. For these "frameless" functions the frame pointer is |
| 2259 | actually the frame pointer of the calling frame. */ |
| 2260 | cache->base = frame_unwind_register_unsigned (next_frame, MEDIA_FP_REGNUM); |
| 2261 | if (cache->base == 0) |
| 2262 | return cache; |
| 2263 | |
| 2264 | cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME); |
| 2265 | if (cache->pc != 0) |
| 2266 | sh64_analyze_prologue (current_gdbarch, cache, cache->pc, current_pc); |
| 2267 | |
| 2268 | if (!cache->uses_fp) |
| 2269 | { |
| 2270 | /* We didn't find a valid frame, which means that CACHE->base |
| 2271 | currently holds the frame pointer for our calling frame. If |
| 2272 | we're at the start of a function, or somewhere half-way its |
| 2273 | prologue, the function's frame probably hasn't been fully |
| 2274 | setup yet. Try to reconstruct the base address for the stack |
| 2275 | frame by looking at the stack pointer. For truly "frameless" |
| 2276 | functions this might work too. */ |
| 2277 | cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); |
| 2278 | } |
| 2279 | |
| 2280 | /* Now that we have the base address for the stack frame we can |
| 2281 | calculate the value of sp in the calling frame. */ |
| 2282 | cache->saved_sp = cache->base + cache->sp_offset; |
| 2283 | |
| 2284 | /* Adjust all the saved registers such that they contain addresses |
| 2285 | instead of offsets. */ |
| 2286 | for (i = 0; i < SIM_SH64_NR_REGS; i++) |
| 2287 | if (cache->saved_regs[i] != -1) |
| 2288 | cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i]; |
| 2289 | |
| 2290 | return cache; |
| 2291 | } |
| 2292 | |
| 2293 | static void |
| 2294 | sh64_frame_prev_register (struct frame_info *next_frame, void **this_cache, |
| 2295 | int regnum, int *optimizedp, |
| 2296 | enum lval_type *lvalp, CORE_ADDR *addrp, |
| 2297 | int *realnump, gdb_byte *valuep) |
| 2298 | { |
| 2299 | struct sh64_frame_cache *cache = sh64_frame_cache (next_frame, this_cache); |
| 2300 | |
| 2301 | gdb_assert (regnum >= 0); |
| 2302 | |
| 2303 | if (regnum == SP_REGNUM && cache->saved_sp) |
| 2304 | { |
| 2305 | *optimizedp = 0; |
| 2306 | *lvalp = not_lval; |
| 2307 | *addrp = 0; |
| 2308 | *realnump = -1; |
| 2309 | if (valuep) |
| 2310 | { |
| 2311 | /* Store the value. */ |
| 2312 | store_unsigned_integer (valuep, |
| 2313 | register_size (current_gdbarch, SP_REGNUM), |
| 2314 | cache->saved_sp); |
| 2315 | } |
| 2316 | return; |
| 2317 | } |
| 2318 | |
| 2319 | /* The PC of the previous frame is stored in the PR register of |
| 2320 | the current frame. Frob regnum so that we pull the value from |
| 2321 | the correct place. */ |
| 2322 | if (regnum == PC_REGNUM) |
| 2323 | regnum = PR_REGNUM; |
| 2324 | |
| 2325 | if (regnum < SIM_SH64_NR_REGS && cache->saved_regs[regnum] != -1) |
| 2326 | { |
| 2327 | int reg_size = register_size (current_gdbarch, regnum); |
| 2328 | int size; |
| 2329 | |
| 2330 | *optimizedp = 0; |
| 2331 | *lvalp = lval_memory; |
| 2332 | *addrp = cache->saved_regs[regnum]; |
| 2333 | *realnump = -1; |
| 2334 | if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32 |
| 2335 | && (regnum == MEDIA_FP_REGNUM || regnum == PR_REGNUM)) |
| 2336 | size = 4; |
| 2337 | else |
| 2338 | size = reg_size; |
| 2339 | if (valuep) |
| 2340 | { |
| 2341 | memset (valuep, 0, reg_size); |
| 2342 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
| 2343 | read_memory (*addrp, valuep, size); |
| 2344 | else |
| 2345 | read_memory (*addrp, (char *) valuep + reg_size - size, size); |
| 2346 | } |
| 2347 | return; |
| 2348 | } |
| 2349 | |
| 2350 | *optimizedp = 0; |
| 2351 | *lvalp = lval_register; |
| 2352 | *addrp = 0; |
| 2353 | *realnump = regnum; |
| 2354 | if (valuep) |
| 2355 | frame_unwind_register (next_frame, (*realnump), valuep); |
| 2356 | } |
| 2357 | |
| 2358 | static void |
| 2359 | sh64_frame_this_id (struct frame_info *next_frame, void **this_cache, |
| 2360 | struct frame_id *this_id) |
| 2361 | { |
| 2362 | struct sh64_frame_cache *cache = sh64_frame_cache (next_frame, this_cache); |
| 2363 | |
| 2364 | /* This marks the outermost frame. */ |
| 2365 | if (cache->base == 0) |
| 2366 | return; |
| 2367 | |
| 2368 | *this_id = frame_id_build (cache->saved_sp, cache->pc); |
| 2369 | } |
| 2370 | |
| 2371 | static const struct frame_unwind sh64_frame_unwind = { |
| 2372 | NORMAL_FRAME, |
| 2373 | sh64_frame_this_id, |
| 2374 | sh64_frame_prev_register |
| 2375 | }; |
| 2376 | |
| 2377 | static const struct frame_unwind * |
| 2378 | sh64_frame_sniffer (struct frame_info *next_frame) |
| 2379 | { |
| 2380 | return &sh64_frame_unwind; |
| 2381 | } |
| 2382 | |
| 2383 | static CORE_ADDR |
| 2384 | sh64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 2385 | { |
| 2386 | return frame_unwind_register_unsigned (next_frame, SP_REGNUM); |
| 2387 | } |
| 2388 | |
| 2389 | static CORE_ADDR |
| 2390 | sh64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 2391 | { |
| 2392 | return frame_unwind_register_unsigned (next_frame, PC_REGNUM); |
| 2393 | } |
| 2394 | |
| 2395 | static struct frame_id |
| 2396 | sh64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 2397 | { |
| 2398 | return frame_id_build (sh64_unwind_sp (gdbarch, next_frame), |
| 2399 | frame_pc_unwind (next_frame)); |
| 2400 | } |
| 2401 | |
| 2402 | static CORE_ADDR |
| 2403 | sh64_frame_base_address (struct frame_info *next_frame, void **this_cache) |
| 2404 | { |
| 2405 | struct sh64_frame_cache *cache = sh64_frame_cache (next_frame, this_cache); |
| 2406 | |
| 2407 | return cache->base; |
| 2408 | } |
| 2409 | |
| 2410 | static const struct frame_base sh64_frame_base = { |
| 2411 | &sh64_frame_unwind, |
| 2412 | sh64_frame_base_address, |
| 2413 | sh64_frame_base_address, |
| 2414 | sh64_frame_base_address |
| 2415 | }; |
| 2416 | |
| 2417 | |
| 2418 | struct gdbarch * |
| 2419 | sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 2420 | { |
| 2421 | struct gdbarch *gdbarch; |
| 2422 | struct gdbarch_tdep *tdep; |
| 2423 | |
| 2424 | /* If there is already a candidate, use it. */ |
| 2425 | arches = gdbarch_list_lookup_by_info (arches, &info); |
| 2426 | if (arches != NULL) |
| 2427 | return arches->gdbarch; |
| 2428 | |
| 2429 | /* None found, create a new architecture from the information |
| 2430 | provided. */ |
| 2431 | tdep = XMALLOC (struct gdbarch_tdep); |
| 2432 | gdbarch = gdbarch_alloc (&info, tdep); |
| 2433 | |
| 2434 | /* Determine the ABI */ |
| 2435 | if (info.abfd && bfd_get_arch_size (info.abfd) == 64) |
| 2436 | { |
| 2437 | /* If the ABI is the 64-bit one, it can only be sh-media. */ |
| 2438 | tdep->sh_abi = SH_ABI_64; |
| 2439 | set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 2440 | set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 2441 | } |
| 2442 | else |
| 2443 | { |
| 2444 | /* If the ABI is the 32-bit one it could be either media or |
| 2445 | compact. */ |
| 2446 | tdep->sh_abi = SH_ABI_32; |
| 2447 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 2448 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 2449 | } |
| 2450 | |
| 2451 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
| 2452 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 2453 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 2454 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 2455 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 2456 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 2457 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 2458 | |
| 2459 | /* The number of real registers is the same whether we are in |
| 2460 | ISA16(compact) or ISA32(media). */ |
| 2461 | set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS); |
| 2462 | set_gdbarch_sp_regnum (gdbarch, 15); |
| 2463 | set_gdbarch_pc_regnum (gdbarch, 64); |
| 2464 | set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM); |
| 2465 | set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA |
| 2466 | + NUM_PSEUDO_REGS_SH_COMPACT); |
| 2467 | |
| 2468 | set_gdbarch_register_name (gdbarch, sh64_register_name); |
| 2469 | set_gdbarch_register_type (gdbarch, sh64_register_type); |
| 2470 | |
| 2471 | set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read); |
| 2472 | set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write); |
| 2473 | |
| 2474 | set_gdbarch_breakpoint_from_pc (gdbarch, sh64_breakpoint_from_pc); |
| 2475 | |
| 2476 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh64); |
| 2477 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
| 2478 | |
| 2479 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
| 2480 | |
| 2481 | set_gdbarch_return_value (gdbarch, sh64_return_value); |
| 2482 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, |
| 2483 | sh64_extract_struct_value_address); |
| 2484 | |
| 2485 | set_gdbarch_skip_prologue (gdbarch, sh64_skip_prologue); |
| 2486 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 2487 | |
| 2488 | set_gdbarch_push_dummy_call (gdbarch, sh64_push_dummy_call); |
| 2489 | |
| 2490 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
| 2491 | |
| 2492 | set_gdbarch_frame_align (gdbarch, sh64_frame_align); |
| 2493 | set_gdbarch_unwind_sp (gdbarch, sh64_unwind_sp); |
| 2494 | set_gdbarch_unwind_pc (gdbarch, sh64_unwind_pc); |
| 2495 | set_gdbarch_unwind_dummy_id (gdbarch, sh64_unwind_dummy_id); |
| 2496 | frame_base_set_default (gdbarch, &sh64_frame_base); |
| 2497 | |
| 2498 | set_gdbarch_print_registers_info (gdbarch, sh64_print_registers_info); |
| 2499 | |
| 2500 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
| 2501 | sh64_elf_make_msymbol_special); |
| 2502 | |
| 2503 | /* Hook in ABI-specific overrides, if they have been registered. */ |
| 2504 | gdbarch_init_osabi (info, gdbarch); |
| 2505 | |
| 2506 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
| 2507 | frame_unwind_append_sniffer (gdbarch, sh64_frame_sniffer); |
| 2508 | |
| 2509 | return gdbarch; |
| 2510 | } |