| 1 | /* Target-dependent code for the SPARC for GDB, the GNU debugger. |
| 2 | |
| 3 | Copyright 1986, 1987, 1989, 1990, 1991, 1992, 1993, 1994, 1995, |
| 4 | 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, |
| 5 | Inc. |
| 6 | |
| 7 | This file is part of GDB. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 2 of the License, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program; if not, write to the Free Software |
| 21 | Foundation, Inc., 59 Temple Place - Suite 330, |
| 22 | Boston, MA 02111-1307, USA. */ |
| 23 | |
| 24 | /* ??? Support for calling functions from gdb in sparc64 is unfinished. */ |
| 25 | |
| 26 | #include "defs.h" |
| 27 | #include "arch-utils.h" |
| 28 | #include "frame.h" |
| 29 | #include "inferior.h" |
| 30 | #include "obstack.h" |
| 31 | #include "target.h" |
| 32 | #include "value.h" |
| 33 | #include "bfd.h" |
| 34 | #include "gdb_string.h" |
| 35 | #include "regcache.h" |
| 36 | #include "osabi.h" |
| 37 | |
| 38 | #ifdef USE_PROC_FS |
| 39 | #include <sys/procfs.h> |
| 40 | /* Prototypes for supply_gregset etc. */ |
| 41 | #include "gregset.h" |
| 42 | #endif |
| 43 | |
| 44 | #include "gdbcore.h" |
| 45 | |
| 46 | #include "symfile.h" /* for 'entry_point_address' */ |
| 47 | |
| 48 | /* |
| 49 | * Some local macros that have multi-arch and non-multi-arch versions: |
| 50 | */ |
| 51 | |
| 52 | #if (GDB_MULTI_ARCH > 0) |
| 53 | |
| 54 | /* Does the target have Floating Point registers? */ |
| 55 | #define SPARC_HAS_FPU (gdbarch_tdep (current_gdbarch)->has_fpu) |
| 56 | /* Number of bytes devoted to Floating Point registers: */ |
| 57 | #define FP_REGISTER_BYTES (gdbarch_tdep (current_gdbarch)->fp_register_bytes) |
| 58 | /* Highest numbered Floating Point register. */ |
| 59 | #define FP_MAX_REGNUM (gdbarch_tdep (current_gdbarch)->fp_max_regnum) |
| 60 | /* Size of a general (integer) register: */ |
| 61 | #define SPARC_INTREG_SIZE (gdbarch_tdep (current_gdbarch)->intreg_size) |
| 62 | /* Offset within the call dummy stack of the saved registers. */ |
| 63 | #define DUMMY_REG_SAVE_OFFSET (gdbarch_tdep (current_gdbarch)->reg_save_offset) |
| 64 | |
| 65 | #else /* non-multi-arch */ |
| 66 | |
| 67 | |
| 68 | /* Does the target have Floating Point registers? */ |
| 69 | #if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE) |
| 70 | #define SPARC_HAS_FPU 0 |
| 71 | #else |
| 72 | #define SPARC_HAS_FPU 1 |
| 73 | #endif |
| 74 | |
| 75 | /* Number of bytes devoted to Floating Point registers: */ |
| 76 | #if (GDB_TARGET_IS_SPARC64) |
| 77 | #define FP_REGISTER_BYTES (64 * 4) |
| 78 | #else |
| 79 | #if (SPARC_HAS_FPU) |
| 80 | #define FP_REGISTER_BYTES (32 * 4) |
| 81 | #else |
| 82 | #define FP_REGISTER_BYTES 0 |
| 83 | #endif |
| 84 | #endif |
| 85 | |
| 86 | /* Highest numbered Floating Point register. */ |
| 87 | #if (GDB_TARGET_IS_SPARC64) |
| 88 | #define FP_MAX_REGNUM (FP0_REGNUM + 48) |
| 89 | #else |
| 90 | #define FP_MAX_REGNUM (FP0_REGNUM + 32) |
| 91 | #endif |
| 92 | |
| 93 | /* Size of a general (integer) register: */ |
| 94 | #define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM)) |
| 95 | |
| 96 | /* Offset within the call dummy stack of the saved registers. */ |
| 97 | #if (GDB_TARGET_IS_SPARC64) |
| 98 | #define DUMMY_REG_SAVE_OFFSET (128 + 16) |
| 99 | #else |
| 100 | #define DUMMY_REG_SAVE_OFFSET 0x60 |
| 101 | #endif |
| 102 | |
| 103 | #endif /* GDB_MULTI_ARCH */ |
| 104 | |
| 105 | struct gdbarch_tdep |
| 106 | { |
| 107 | int has_fpu; |
| 108 | int fp_register_bytes; |
| 109 | int y_regnum; |
| 110 | int fp_max_regnum; |
| 111 | int intreg_size; |
| 112 | int reg_save_offset; |
| 113 | int call_dummy_call_offset; |
| 114 | int print_insn_mach; |
| 115 | |
| 116 | enum gdb_osabi osabi; |
| 117 | }; |
| 118 | |
| 119 | /* Now make GDB_TARGET_IS_SPARC64 a runtime test. */ |
| 120 | /* FIXME MVS: or try testing bfd_arch_info.arch and bfd_arch_info.mach ... |
| 121 | * define GDB_TARGET_IS_SPARC64 \ |
| 122 | * (TARGET_ARCHITECTURE->arch == bfd_arch_sparc && \ |
| 123 | * (TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9 || \ |
| 124 | * TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9a)) |
| 125 | */ |
| 126 | |
| 127 | /* From infrun.c */ |
| 128 | extern int stop_after_trap; |
| 129 | |
| 130 | /* We don't store all registers immediately when requested, since they |
| 131 | get sent over in large chunks anyway. Instead, we accumulate most |
| 132 | of the changes and send them over once. "deferred_stores" keeps |
| 133 | track of which sets of registers we have locally-changed copies of, |
| 134 | so we only need send the groups that have changed. */ |
| 135 | |
| 136 | int deferred_stores = 0; /* Accumulated stores we want to do eventually. */ |
| 137 | |
| 138 | |
| 139 | /* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode |
| 140 | where instructions are big-endian and data are little-endian. |
| 141 | This flag is set when we detect that the target is of this type. */ |
| 142 | |
| 143 | int bi_endian = 0; |
| 144 | |
| 145 | |
| 146 | /* Fetch a single instruction. Even on bi-endian machines |
| 147 | such as sparc86x, instructions are always big-endian. */ |
| 148 | |
| 149 | static unsigned long |
| 150 | fetch_instruction (CORE_ADDR pc) |
| 151 | { |
| 152 | unsigned long retval; |
| 153 | int i; |
| 154 | unsigned char buf[4]; |
| 155 | |
| 156 | read_memory (pc, buf, sizeof (buf)); |
| 157 | |
| 158 | /* Start at the most significant end of the integer, and work towards |
| 159 | the least significant. */ |
| 160 | retval = 0; |
| 161 | for (i = 0; i < sizeof (buf); ++i) |
| 162 | retval = (retval << 8) | buf[i]; |
| 163 | return retval; |
| 164 | } |
| 165 | |
| 166 | |
| 167 | /* Branches with prediction are treated like their non-predicting cousins. */ |
| 168 | /* FIXME: What about floating point branches? */ |
| 169 | |
| 170 | /* Macros to extract fields from sparc instructions. */ |
| 171 | #define X_OP(i) (((i) >> 30) & 0x3) |
| 172 | #define X_RD(i) (((i) >> 25) & 0x1f) |
| 173 | #define X_A(i) (((i) >> 29) & 1) |
| 174 | #define X_COND(i) (((i) >> 25) & 0xf) |
| 175 | #define X_OP2(i) (((i) >> 22) & 0x7) |
| 176 | #define X_IMM22(i) ((i) & 0x3fffff) |
| 177 | #define X_OP3(i) (((i) >> 19) & 0x3f) |
| 178 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
| 179 | #define X_I(i) (((i) >> 13) & 1) |
| 180 | #define X_IMM13(i) ((i) & 0x1fff) |
| 181 | /* Sign extension macros. */ |
| 182 | #define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000) |
| 183 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
| 184 | #define X_CC(i) (((i) >> 20) & 3) |
| 185 | #define X_P(i) (((i) >> 19) & 1) |
| 186 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
| 187 | #define X_RCOND(i) (((i) >> 25) & 7) |
| 188 | #define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000) |
| 189 | #define X_FCN(i) (((i) >> 25) & 31) |
| 190 | |
| 191 | typedef enum |
| 192 | { |
| 193 | Error, not_branch, bicc, bicca, ba, baa, ticc, ta, done_retry |
| 194 | } branch_type; |
| 195 | |
| 196 | /* Simulate single-step ptrace call for sun4. Code written by Gary |
| 197 | Beihl (beihl@mcc.com). */ |
| 198 | |
| 199 | /* npc4 and next_pc describe the situation at the time that the |
| 200 | step-breakpoint was set, not necessary the current value of NPC_REGNUM. */ |
| 201 | static CORE_ADDR next_pc, npc4, target; |
| 202 | static int brknpc4, brktrg; |
| 203 | typedef char binsn_quantum[BREAKPOINT_MAX]; |
| 204 | static binsn_quantum break_mem[3]; |
| 205 | |
| 206 | static branch_type isbranch (long, CORE_ADDR, CORE_ADDR *); |
| 207 | |
| 208 | /* single_step() is called just before we want to resume the inferior, |
| 209 | if we want to single-step it but there is no hardware or kernel single-step |
| 210 | support (as on all SPARCs). We find all the possible targets of the |
| 211 | coming instruction and breakpoint them. |
| 212 | |
| 213 | single_step is also called just after the inferior stops. If we had |
| 214 | set up a simulated single-step, we undo our damage. */ |
| 215 | |
| 216 | void |
| 217 | sparc_software_single_step (enum target_signal ignore, /* pid, but we don't need it */ |
| 218 | int insert_breakpoints_p) |
| 219 | { |
| 220 | branch_type br; |
| 221 | CORE_ADDR pc; |
| 222 | long pc_instruction; |
| 223 | |
| 224 | if (insert_breakpoints_p) |
| 225 | { |
| 226 | /* Always set breakpoint for NPC. */ |
| 227 | next_pc = read_register (NPC_REGNUM); |
| 228 | npc4 = next_pc + 4; /* branch not taken */ |
| 229 | |
| 230 | target_insert_breakpoint (next_pc, break_mem[0]); |
| 231 | /* printf_unfiltered ("set break at %x\n",next_pc); */ |
| 232 | |
| 233 | pc = read_register (PC_REGNUM); |
| 234 | pc_instruction = fetch_instruction (pc); |
| 235 | br = isbranch (pc_instruction, pc, &target); |
| 236 | brknpc4 = brktrg = 0; |
| 237 | |
| 238 | if (br == bicca) |
| 239 | { |
| 240 | /* Conditional annulled branch will either end up at |
| 241 | npc (if taken) or at npc+4 (if not taken). |
| 242 | Trap npc+4. */ |
| 243 | brknpc4 = 1; |
| 244 | target_insert_breakpoint (npc4, break_mem[1]); |
| 245 | } |
| 246 | else if (br == baa && target != next_pc) |
| 247 | { |
| 248 | /* Unconditional annulled branch will always end up at |
| 249 | the target. */ |
| 250 | brktrg = 1; |
| 251 | target_insert_breakpoint (target, break_mem[2]); |
| 252 | } |
| 253 | else if (GDB_TARGET_IS_SPARC64 && br == done_retry) |
| 254 | { |
| 255 | brktrg = 1; |
| 256 | target_insert_breakpoint (target, break_mem[2]); |
| 257 | } |
| 258 | } |
| 259 | else |
| 260 | { |
| 261 | /* Remove breakpoints */ |
| 262 | target_remove_breakpoint (next_pc, break_mem[0]); |
| 263 | |
| 264 | if (brknpc4) |
| 265 | target_remove_breakpoint (npc4, break_mem[1]); |
| 266 | |
| 267 | if (brktrg) |
| 268 | target_remove_breakpoint (target, break_mem[2]); |
| 269 | } |
| 270 | } |
| 271 | \f |
| 272 | struct frame_extra_info |
| 273 | { |
| 274 | CORE_ADDR bottom; |
| 275 | int in_prologue; |
| 276 | int flat; |
| 277 | /* Following fields only relevant for flat frames. */ |
| 278 | CORE_ADDR pc_addr; |
| 279 | CORE_ADDR fp_addr; |
| 280 | /* Add this to ->frame to get the value of the stack pointer at the |
| 281 | time of the register saves. */ |
| 282 | int sp_offset; |
| 283 | }; |
| 284 | |
| 285 | /* Call this for each newly created frame. For SPARC, we need to |
| 286 | calculate the bottom of the frame, and do some extra work if the |
| 287 | prologue has been generated via the -mflat option to GCC. In |
| 288 | particular, we need to know where the previous fp and the pc have |
| 289 | been stashed, since their exact position within the frame may vary. */ |
| 290 | |
| 291 | void |
| 292 | sparc_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
| 293 | { |
| 294 | char *name; |
| 295 | CORE_ADDR prologue_start, prologue_end; |
| 296 | int insn; |
| 297 | |
| 298 | fi->extra_info = (struct frame_extra_info *) |
| 299 | frame_obstack_alloc (sizeof (struct frame_extra_info)); |
| 300 | frame_saved_regs_zalloc (fi); |
| 301 | |
| 302 | fi->extra_info->bottom = |
| 303 | (fi->next ? |
| 304 | (fi->frame == fi->next->frame ? fi->next->extra_info->bottom : |
| 305 | fi->next->frame) : read_sp ()); |
| 306 | |
| 307 | /* If fi->next is NULL, then we already set ->frame by passing read_fp() |
| 308 | to create_new_frame. */ |
| 309 | if (fi->next) |
| 310 | { |
| 311 | char *buf; |
| 312 | |
| 313 | buf = alloca (MAX_REGISTER_RAW_SIZE); |
| 314 | |
| 315 | /* Compute ->frame as if not flat. If it is flat, we'll change |
| 316 | it later. */ |
| 317 | if (fi->next->next != NULL |
| 318 | && (fi->next->next->signal_handler_caller |
| 319 | || frame_in_dummy (fi->next->next)) |
| 320 | && frameless_look_for_prologue (fi->next)) |
| 321 | { |
| 322 | /* A frameless function interrupted by a signal did not change |
| 323 | the frame pointer, fix up frame pointer accordingly. */ |
| 324 | fi->frame = FRAME_FP (fi->next); |
| 325 | fi->extra_info->bottom = fi->next->extra_info->bottom; |
| 326 | } |
| 327 | else |
| 328 | { |
| 329 | /* Should we adjust for stack bias here? */ |
| 330 | get_saved_register (buf, 0, 0, fi, FP_REGNUM, 0); |
| 331 | fi->frame = extract_address (buf, REGISTER_RAW_SIZE (FP_REGNUM)); |
| 332 | |
| 333 | if (GDB_TARGET_IS_SPARC64 && (fi->frame & 1)) |
| 334 | fi->frame += 2047; |
| 335 | } |
| 336 | } |
| 337 | |
| 338 | /* Decide whether this is a function with a ``flat register window'' |
| 339 | frame. For such functions, the frame pointer is actually in %i7. */ |
| 340 | fi->extra_info->flat = 0; |
| 341 | fi->extra_info->in_prologue = 0; |
| 342 | if (find_pc_partial_function (fi->pc, &name, &prologue_start, &prologue_end)) |
| 343 | { |
| 344 | /* See if the function starts with an add (which will be of a |
| 345 | negative number if a flat frame) to the sp. FIXME: Does not |
| 346 | handle large frames which will need more than one instruction |
| 347 | to adjust the sp. */ |
| 348 | insn = fetch_instruction (prologue_start); |
| 349 | if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0 |
| 350 | && X_I (insn) && X_SIMM13 (insn) < 0) |
| 351 | { |
| 352 | int offset = X_SIMM13 (insn); |
| 353 | |
| 354 | /* Then look for a save of %i7 into the frame. */ |
| 355 | insn = fetch_instruction (prologue_start + 4); |
| 356 | if (X_OP (insn) == 3 |
| 357 | && X_RD (insn) == 31 |
| 358 | && X_OP3 (insn) == 4 |
| 359 | && X_RS1 (insn) == 14) |
| 360 | { |
| 361 | char *buf; |
| 362 | |
| 363 | buf = alloca (MAX_REGISTER_RAW_SIZE); |
| 364 | |
| 365 | /* We definitely have a flat frame now. */ |
| 366 | fi->extra_info->flat = 1; |
| 367 | |
| 368 | fi->extra_info->sp_offset = offset; |
| 369 | |
| 370 | /* Overwrite the frame's address with the value in %i7. */ |
| 371 | get_saved_register (buf, 0, 0, fi, I7_REGNUM, 0); |
| 372 | fi->frame = extract_address (buf, REGISTER_RAW_SIZE (I7_REGNUM)); |
| 373 | |
| 374 | if (GDB_TARGET_IS_SPARC64 && (fi->frame & 1)) |
| 375 | fi->frame += 2047; |
| 376 | |
| 377 | /* Record where the fp got saved. */ |
| 378 | fi->extra_info->fp_addr = |
| 379 | fi->frame + fi->extra_info->sp_offset + X_SIMM13 (insn); |
| 380 | |
| 381 | /* Also try to collect where the pc got saved to. */ |
| 382 | fi->extra_info->pc_addr = 0; |
| 383 | insn = fetch_instruction (prologue_start + 12); |
| 384 | if (X_OP (insn) == 3 |
| 385 | && X_RD (insn) == 15 |
| 386 | && X_OP3 (insn) == 4 |
| 387 | && X_RS1 (insn) == 14) |
| 388 | fi->extra_info->pc_addr = |
| 389 | fi->frame + fi->extra_info->sp_offset + X_SIMM13 (insn); |
| 390 | } |
| 391 | } |
| 392 | else |
| 393 | { |
| 394 | /* Check if the PC is in the function prologue before a SAVE |
| 395 | instruction has been executed yet. If so, set the frame |
| 396 | to the current value of the stack pointer and set |
| 397 | the in_prologue flag. */ |
| 398 | CORE_ADDR addr; |
| 399 | struct symtab_and_line sal; |
| 400 | |
| 401 | sal = find_pc_line (prologue_start, 0); |
| 402 | if (sal.line == 0) /* no line info, use PC */ |
| 403 | prologue_end = fi->pc; |
| 404 | else if (sal.end < prologue_end) |
| 405 | prologue_end = sal.end; |
| 406 | if (fi->pc < prologue_end) |
| 407 | { |
| 408 | for (addr = prologue_start; addr < fi->pc; addr += 4) |
| 409 | { |
| 410 | insn = read_memory_integer (addr, 4); |
| 411 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) |
| 412 | break; /* SAVE seen, stop searching */ |
| 413 | } |
| 414 | if (addr >= fi->pc) |
| 415 | { |
| 416 | fi->extra_info->in_prologue = 1; |
| 417 | fi->frame = read_register (SP_REGNUM); |
| 418 | } |
| 419 | } |
| 420 | } |
| 421 | } |
| 422 | if (fi->next && fi->frame == 0) |
| 423 | { |
| 424 | /* Kludge to cause init_prev_frame_info to destroy the new frame. */ |
| 425 | fi->frame = fi->next->frame; |
| 426 | fi->pc = fi->next->pc; |
| 427 | } |
| 428 | } |
| 429 | |
| 430 | CORE_ADDR |
| 431 | sparc_frame_chain (struct frame_info *frame) |
| 432 | { |
| 433 | /* Value that will cause FRAME_CHAIN_VALID to not worry about the chain |
| 434 | value. If it really is zero, we detect it later in |
| 435 | sparc_init_prev_frame. */ |
| 436 | return (CORE_ADDR) 1; |
| 437 | } |
| 438 | |
| 439 | CORE_ADDR |
| 440 | sparc_extract_struct_value_address (char *regbuf) |
| 441 | { |
| 442 | return extract_address (regbuf + REGISTER_BYTE (O0_REGNUM), |
| 443 | REGISTER_RAW_SIZE (O0_REGNUM)); |
| 444 | } |
| 445 | |
| 446 | /* Find the pc saved in frame FRAME. */ |
| 447 | |
| 448 | CORE_ADDR |
| 449 | sparc_frame_saved_pc (struct frame_info *frame) |
| 450 | { |
| 451 | char *buf; |
| 452 | CORE_ADDR addr; |
| 453 | |
| 454 | buf = alloca (MAX_REGISTER_RAW_SIZE); |
| 455 | if (frame->signal_handler_caller) |
| 456 | { |
| 457 | /* This is the signal trampoline frame. |
| 458 | Get the saved PC from the sigcontext structure. */ |
| 459 | |
| 460 | #ifndef SIGCONTEXT_PC_OFFSET |
| 461 | #define SIGCONTEXT_PC_OFFSET 12 |
| 462 | #endif |
| 463 | |
| 464 | CORE_ADDR sigcontext_addr; |
| 465 | char *scbuf; |
| 466 | int saved_pc_offset = SIGCONTEXT_PC_OFFSET; |
| 467 | char *name = NULL; |
| 468 | |
| 469 | scbuf = alloca (TARGET_PTR_BIT / HOST_CHAR_BIT); |
| 470 | |
| 471 | /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext |
| 472 | as the third parameter. The offset to the saved pc is 12. */ |
| 473 | find_pc_partial_function (frame->pc, &name, |
| 474 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
| 475 | if (name && STREQ (name, "ucbsigvechandler")) |
| 476 | saved_pc_offset = 12; |
| 477 | |
| 478 | /* The sigcontext address is contained in register O2. */ |
| 479 | get_saved_register (buf, (int *) NULL, (CORE_ADDR *) NULL, |
| 480 | frame, O0_REGNUM + 2, (enum lval_type *) NULL); |
| 481 | sigcontext_addr = extract_address (buf, REGISTER_RAW_SIZE (O0_REGNUM + 2)); |
| 482 | |
| 483 | /* Don't cause a memory_error when accessing sigcontext in case the |
| 484 | stack layout has changed or the stack is corrupt. */ |
| 485 | target_read_memory (sigcontext_addr + saved_pc_offset, |
| 486 | scbuf, sizeof (scbuf)); |
| 487 | return extract_address (scbuf, sizeof (scbuf)); |
| 488 | } |
| 489 | else if (frame->extra_info->in_prologue || |
| 490 | (frame->next != NULL && |
| 491 | (frame->next->signal_handler_caller || |
| 492 | frame_in_dummy (frame->next)) && |
| 493 | frameless_look_for_prologue (frame))) |
| 494 | { |
| 495 | /* A frameless function interrupted by a signal did not save |
| 496 | the PC, it is still in %o7. */ |
| 497 | get_saved_register (buf, (int *) NULL, (CORE_ADDR *) NULL, |
| 498 | frame, O7_REGNUM, (enum lval_type *) NULL); |
| 499 | return PC_ADJUST (extract_address (buf, SPARC_INTREG_SIZE)); |
| 500 | } |
| 501 | if (frame->extra_info->flat) |
| 502 | addr = frame->extra_info->pc_addr; |
| 503 | else |
| 504 | addr = frame->extra_info->bottom + FRAME_SAVED_I0 + |
| 505 | SPARC_INTREG_SIZE * (I7_REGNUM - I0_REGNUM); |
| 506 | |
| 507 | if (addr == 0) |
| 508 | /* A flat frame leaf function might not save the PC anywhere, |
| 509 | just leave it in %o7. */ |
| 510 | return PC_ADJUST (read_register (O7_REGNUM)); |
| 511 | |
| 512 | read_memory (addr, buf, SPARC_INTREG_SIZE); |
| 513 | return PC_ADJUST (extract_address (buf, SPARC_INTREG_SIZE)); |
| 514 | } |
| 515 | |
| 516 | /* Since an individual frame in the frame cache is defined by two |
| 517 | arguments (a frame pointer and a stack pointer), we need two |
| 518 | arguments to get info for an arbitrary stack frame. This routine |
| 519 | takes two arguments and makes the cached frames look as if these |
| 520 | two arguments defined a frame on the cache. This allows the rest |
| 521 | of info frame to extract the important arguments without |
| 522 | difficulty. */ |
| 523 | |
| 524 | struct frame_info * |
| 525 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
| 526 | { |
| 527 | struct frame_info *frame; |
| 528 | |
| 529 | if (argc != 2) |
| 530 | error ("Sparc frame specifications require two arguments: fp and sp"); |
| 531 | |
| 532 | frame = create_new_frame (argv[0], 0); |
| 533 | |
| 534 | if (!frame) |
| 535 | internal_error (__FILE__, __LINE__, |
| 536 | "create_new_frame returned invalid frame"); |
| 537 | |
| 538 | frame->extra_info->bottom = argv[1]; |
| 539 | frame->pc = FRAME_SAVED_PC (frame); |
| 540 | return frame; |
| 541 | } |
| 542 | |
| 543 | /* Given a pc value, skip it forward past the function prologue by |
| 544 | disassembling instructions that appear to be a prologue. |
| 545 | |
| 546 | If FRAMELESS_P is set, we are only testing to see if the function |
| 547 | is frameless. This allows a quicker answer. |
| 548 | |
| 549 | This routine should be more specific in its actions; making sure |
| 550 | that it uses the same register in the initial prologue section. */ |
| 551 | |
| 552 | static CORE_ADDR examine_prologue (CORE_ADDR, int, struct frame_info *, |
| 553 | CORE_ADDR *); |
| 554 | |
| 555 | static CORE_ADDR |
| 556 | examine_prologue (CORE_ADDR start_pc, int frameless_p, struct frame_info *fi, |
| 557 | CORE_ADDR *saved_regs) |
| 558 | { |
| 559 | int insn; |
| 560 | int dest = -1; |
| 561 | CORE_ADDR pc = start_pc; |
| 562 | int is_flat = 0; |
| 563 | |
| 564 | insn = fetch_instruction (pc); |
| 565 | |
| 566 | /* Recognize the `sethi' insn and record its destination. */ |
| 567 | if (X_OP (insn) == 0 && X_OP2 (insn) == 4) |
| 568 | { |
| 569 | dest = X_RD (insn); |
| 570 | pc += 4; |
| 571 | insn = fetch_instruction (pc); |
| 572 | } |
| 573 | |
| 574 | /* Recognize an add immediate value to register to either %g1 or |
| 575 | the destination register recorded above. Actually, this might |
| 576 | well recognize several different arithmetic operations. |
| 577 | It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1" |
| 578 | followed by "save %sp, %g1, %sp" is a valid prologue (Not that |
| 579 | I imagine any compiler really does that, however). */ |
| 580 | if (X_OP (insn) == 2 |
| 581 | && X_I (insn) |
| 582 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
| 583 | { |
| 584 | pc += 4; |
| 585 | insn = fetch_instruction (pc); |
| 586 | } |
| 587 | |
| 588 | /* Recognize any SAVE insn. */ |
| 589 | if (X_OP (insn) == 2 && X_OP3 (insn) == 60) |
| 590 | { |
| 591 | pc += 4; |
| 592 | if (frameless_p) /* If the save is all we care about, */ |
| 593 | return pc; /* return before doing more work */ |
| 594 | insn = fetch_instruction (pc); |
| 595 | } |
| 596 | /* Recognize add to %sp. */ |
| 597 | else if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0) |
| 598 | { |
| 599 | pc += 4; |
| 600 | if (frameless_p) /* If the add is all we care about, */ |
| 601 | return pc; /* return before doing more work */ |
| 602 | is_flat = 1; |
| 603 | insn = fetch_instruction (pc); |
| 604 | /* Recognize store of frame pointer (i7). */ |
| 605 | if (X_OP (insn) == 3 |
| 606 | && X_RD (insn) == 31 |
| 607 | && X_OP3 (insn) == 4 |
| 608 | && X_RS1 (insn) == 14) |
| 609 | { |
| 610 | pc += 4; |
| 611 | insn = fetch_instruction (pc); |
| 612 | |
| 613 | /* Recognize sub %sp, <anything>, %i7. */ |
| 614 | if (X_OP (insn) == 2 |
| 615 | && X_OP3 (insn) == 4 |
| 616 | && X_RS1 (insn) == 14 |
| 617 | && X_RD (insn) == 31) |
| 618 | { |
| 619 | pc += 4; |
| 620 | insn = fetch_instruction (pc); |
| 621 | } |
| 622 | else |
| 623 | return pc; |
| 624 | } |
| 625 | else |
| 626 | return pc; |
| 627 | } |
| 628 | else |
| 629 | /* Without a save or add instruction, it's not a prologue. */ |
| 630 | return start_pc; |
| 631 | |
| 632 | while (1) |
| 633 | { |
| 634 | /* Recognize stores into the frame from the input registers. |
| 635 | This recognizes all non alternate stores of an input register, |
| 636 | into a location offset from the frame pointer between |
| 637 | +68 and +92. */ |
| 638 | |
| 639 | /* The above will fail for arguments that are promoted |
| 640 | (eg. shorts to ints or floats to doubles), because the compiler |
| 641 | will pass them in positive-offset frame space, but the prologue |
| 642 | will save them (after conversion) in negative frame space at an |
| 643 | unpredictable offset. Therefore I am going to remove the |
| 644 | restriction on the target-address of the save, on the theory |
| 645 | that any unbroken sequence of saves from input registers must |
| 646 | be part of the prologue. In un-optimized code (at least), I'm |
| 647 | fairly sure that the compiler would emit SOME other instruction |
| 648 | (eg. a move or add) before emitting another save that is actually |
| 649 | a part of the function body. |
| 650 | |
| 651 | Besides, the reserved stack space is different for SPARC64 anyway. |
| 652 | |
| 653 | MVS 4/23/2000 */ |
| 654 | |
| 655 | if (X_OP (insn) == 3 |
| 656 | && (X_OP3 (insn) & 0x3c) == 4 /* Store, non-alternate. */ |
| 657 | && (X_RD (insn) & 0x18) == 0x18 /* Input register. */ |
| 658 | && X_I (insn) /* Immediate mode. */ |
| 659 | && X_RS1 (insn) == 30) /* Off of frame pointer. */ |
| 660 | ; /* empty statement -- fall thru to end of loop */ |
| 661 | else if (GDB_TARGET_IS_SPARC64 |
| 662 | && X_OP (insn) == 3 |
| 663 | && (X_OP3 (insn) & 0x3c) == 12 /* store, extended (64-bit) */ |
| 664 | && (X_RD (insn) & 0x18) == 0x18 /* input register */ |
| 665 | && X_I (insn) /* immediate mode */ |
| 666 | && X_RS1 (insn) == 30) /* off of frame pointer */ |
| 667 | ; /* empty statement -- fall thru to end of loop */ |
| 668 | else if (X_OP (insn) == 3 |
| 669 | && (X_OP3 (insn) & 0x3c) == 36 /* store, floating-point */ |
| 670 | && X_I (insn) /* immediate mode */ |
| 671 | && X_RS1 (insn) == 30) /* off of frame pointer */ |
| 672 | ; /* empty statement -- fall thru to end of loop */ |
| 673 | else if (is_flat |
| 674 | && X_OP (insn) == 3 |
| 675 | && X_OP3 (insn) == 4 /* store? */ |
| 676 | && X_RS1 (insn) == 14) /* off of frame pointer */ |
| 677 | { |
| 678 | if (saved_regs && X_I (insn)) |
| 679 | saved_regs[X_RD (insn)] = |
| 680 | fi->frame + fi->extra_info->sp_offset + X_SIMM13 (insn); |
| 681 | } |
| 682 | else |
| 683 | break; |
| 684 | pc += 4; |
| 685 | insn = fetch_instruction (pc); |
| 686 | } |
| 687 | |
| 688 | return pc; |
| 689 | } |
| 690 | |
| 691 | /* Advance PC across any function entry prologue instructions to reach |
| 692 | some "real" code. */ |
| 693 | |
| 694 | CORE_ADDR |
| 695 | sparc_skip_prologue (CORE_ADDR start_pc) |
| 696 | { |
| 697 | struct symtab_and_line sal; |
| 698 | CORE_ADDR func_start, func_end; |
| 699 | |
| 700 | /* This is the preferred method, find the end of the prologue by |
| 701 | using the debugging information. */ |
| 702 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) |
| 703 | { |
| 704 | sal = find_pc_line (func_start, 0); |
| 705 | |
| 706 | if (sal.end < func_end |
| 707 | && start_pc <= sal.end) |
| 708 | return sal.end; |
| 709 | } |
| 710 | |
| 711 | /* Oh well, examine the code by hand. */ |
| 712 | return examine_prologue (start_pc, 0, NULL, NULL); |
| 713 | } |
| 714 | |
| 715 | /* Is the prologue at IP frameless? */ |
| 716 | |
| 717 | int |
| 718 | sparc_prologue_frameless_p (CORE_ADDR ip) |
| 719 | { |
| 720 | return ip == examine_prologue (ip, 1, NULL, NULL); |
| 721 | } |
| 722 | |
| 723 | /* Check instruction at ADDR to see if it is a branch. |
| 724 | All non-annulled instructions will go to NPC or will trap. |
| 725 | Set *TARGET if we find a candidate branch; set to zero if not. |
| 726 | |
| 727 | This isn't static as it's used by remote-sa.sparc.c. */ |
| 728 | |
| 729 | static branch_type |
| 730 | isbranch (long instruction, CORE_ADDR addr, CORE_ADDR *target) |
| 731 | { |
| 732 | branch_type val = not_branch; |
| 733 | long int offset = 0; /* Must be signed for sign-extend. */ |
| 734 | |
| 735 | *target = 0; |
| 736 | |
| 737 | if (X_OP (instruction) == 0 |
| 738 | && (X_OP2 (instruction) == 2 |
| 739 | || X_OP2 (instruction) == 6 |
| 740 | || X_OP2 (instruction) == 1 |
| 741 | || X_OP2 (instruction) == 3 |
| 742 | || X_OP2 (instruction) == 5 |
| 743 | || (GDB_TARGET_IS_SPARC64 && X_OP2 (instruction) == 7))) |
| 744 | { |
| 745 | if (X_COND (instruction) == 8) |
| 746 | val = X_A (instruction) ? baa : ba; |
| 747 | else |
| 748 | val = X_A (instruction) ? bicca : bicc; |
| 749 | switch (X_OP2 (instruction)) |
| 750 | { |
| 751 | case 7: |
| 752 | if (!GDB_TARGET_IS_SPARC64) |
| 753 | break; |
| 754 | /* else fall thru */ |
| 755 | case 2: |
| 756 | case 6: |
| 757 | offset = 4 * X_DISP22 (instruction); |
| 758 | break; |
| 759 | case 1: |
| 760 | case 5: |
| 761 | offset = 4 * X_DISP19 (instruction); |
| 762 | break; |
| 763 | case 3: |
| 764 | offset = 4 * X_DISP16 (instruction); |
| 765 | break; |
| 766 | } |
| 767 | *target = addr + offset; |
| 768 | } |
| 769 | else if (GDB_TARGET_IS_SPARC64 |
| 770 | && X_OP (instruction) == 2 |
| 771 | && X_OP3 (instruction) == 62) |
| 772 | { |
| 773 | if (X_FCN (instruction) == 0) |
| 774 | { |
| 775 | /* done */ |
| 776 | *target = read_register (TNPC_REGNUM); |
| 777 | val = done_retry; |
| 778 | } |
| 779 | else if (X_FCN (instruction) == 1) |
| 780 | { |
| 781 | /* retry */ |
| 782 | *target = read_register (TPC_REGNUM); |
| 783 | val = done_retry; |
| 784 | } |
| 785 | } |
| 786 | |
| 787 | return val; |
| 788 | } |
| 789 | \f |
| 790 | /* Find register number REGNUM relative to FRAME and put its |
| 791 | (raw) contents in *RAW_BUFFER. Set *OPTIMIZED if the variable |
| 792 | was optimized out (and thus can't be fetched). If the variable |
| 793 | was fetched from memory, set *ADDRP to where it was fetched from, |
| 794 | otherwise it was fetched from a register. |
| 795 | |
| 796 | The argument RAW_BUFFER must point to aligned memory. */ |
| 797 | |
| 798 | void |
| 799 | sparc_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp, |
| 800 | struct frame_info *frame, int regnum, |
| 801 | enum lval_type *lval) |
| 802 | { |
| 803 | struct frame_info *frame1; |
| 804 | CORE_ADDR addr; |
| 805 | |
| 806 | if (!target_has_registers) |
| 807 | error ("No registers."); |
| 808 | |
| 809 | if (optimized) |
| 810 | *optimized = 0; |
| 811 | |
| 812 | addr = 0; |
| 813 | |
| 814 | /* FIXME This code extracted from infcmd.c; should put elsewhere! */ |
| 815 | if (frame == NULL) |
| 816 | { |
| 817 | /* error ("No selected frame."); */ |
| 818 | if (!target_has_registers) |
| 819 | error ("The program has no registers now."); |
| 820 | if (selected_frame == NULL) |
| 821 | error ("No selected frame."); |
| 822 | /* Try to use selected frame */ |
| 823 | frame = get_prev_frame (selected_frame); |
| 824 | if (frame == 0) |
| 825 | error ("Cmd not meaningful in the outermost frame."); |
| 826 | } |
| 827 | |
| 828 | |
| 829 | frame1 = frame->next; |
| 830 | |
| 831 | /* Get saved PC from the frame info if not in innermost frame. */ |
| 832 | if (regnum == PC_REGNUM && frame1 != NULL) |
| 833 | { |
| 834 | if (lval != NULL) |
| 835 | *lval = not_lval; |
| 836 | if (raw_buffer != NULL) |
| 837 | { |
| 838 | /* Put it back in target format. */ |
| 839 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), frame->pc); |
| 840 | } |
| 841 | if (addrp != NULL) |
| 842 | *addrp = 0; |
| 843 | return; |
| 844 | } |
| 845 | |
| 846 | while (frame1 != NULL) |
| 847 | { |
| 848 | /* FIXME MVS: wrong test for dummy frame at entry. */ |
| 849 | |
| 850 | if (frame1->pc >= (frame1->extra_info->bottom ? |
| 851 | frame1->extra_info->bottom : read_sp ()) |
| 852 | && frame1->pc <= FRAME_FP (frame1)) |
| 853 | { |
| 854 | /* Dummy frame. All but the window regs are in there somewhere. |
| 855 | The window registers are saved on the stack, just like in a |
| 856 | normal frame. */ |
| 857 | if (regnum >= G1_REGNUM && regnum < G1_REGNUM + 7) |
| 858 | addr = frame1->frame + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE |
| 859 | - (FP_REGISTER_BYTES + 8 * SPARC_INTREG_SIZE); |
| 860 | else if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8) |
| 861 | /* NOTE: cagney/2002-05-04: The call to get_prev_frame() |
| 862 | is safe/cheap - there will always be a prev frame. |
| 863 | This is because frame1 is initialized to frame->next |
| 864 | (frame1->prev == frame) and is then advanced towards |
| 865 | the innermost (next) frame. */ |
| 866 | addr = (get_prev_frame (frame1)->extra_info->bottom |
| 867 | + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
| 868 | + FRAME_SAVED_I0); |
| 869 | else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8) |
| 870 | /* NOTE: cagney/2002-05-04: The call to get_prev_frame() |
| 871 | is safe/cheap - there will always be a prev frame. |
| 872 | This is because frame1 is initialized to frame->next |
| 873 | (frame1->prev == frame) and is then advanced towards |
| 874 | the innermost (next) frame. */ |
| 875 | addr = (get_prev_frame (frame1)->extra_info->bottom |
| 876 | + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE |
| 877 | + FRAME_SAVED_L0); |
| 878 | else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8) |
| 879 | addr = frame1->frame + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE |
| 880 | - (FP_REGISTER_BYTES + 16 * SPARC_INTREG_SIZE); |
| 881 | else if (SPARC_HAS_FPU && |
| 882 | regnum >= FP0_REGNUM && regnum < FP0_REGNUM + 32) |
| 883 | addr = frame1->frame + (regnum - FP0_REGNUM) * 4 |
| 884 | - (FP_REGISTER_BYTES); |
| 885 | else if (GDB_TARGET_IS_SPARC64 && SPARC_HAS_FPU && |
| 886 | regnum >= FP0_REGNUM + 32 && regnum < FP_MAX_REGNUM) |
| 887 | addr = frame1->frame + 32 * 4 + (regnum - FP0_REGNUM - 32) * 8 |
| 888 | - (FP_REGISTER_BYTES); |
| 889 | else if (regnum >= Y_REGNUM && regnum < NUM_REGS) |
| 890 | addr = frame1->frame + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE |
| 891 | - (FP_REGISTER_BYTES + 24 * SPARC_INTREG_SIZE); |
| 892 | } |
| 893 | else if (frame1->extra_info->flat) |
| 894 | { |
| 895 | |
| 896 | if (regnum == RP_REGNUM) |
| 897 | addr = frame1->extra_info->pc_addr; |
| 898 | else if (regnum == I7_REGNUM) |
| 899 | addr = frame1->extra_info->fp_addr; |
| 900 | else |
| 901 | { |
| 902 | CORE_ADDR func_start; |
| 903 | CORE_ADDR *regs; |
| 904 | |
| 905 | regs = alloca (NUM_REGS * sizeof (CORE_ADDR)); |
| 906 | memset (regs, 0, NUM_REGS * sizeof (CORE_ADDR)); |
| 907 | |
| 908 | find_pc_partial_function (frame1->pc, NULL, &func_start, NULL); |
| 909 | examine_prologue (func_start, 0, frame1, regs); |
| 910 | addr = regs[regnum]; |
| 911 | } |
| 912 | } |
| 913 | else |
| 914 | { |
| 915 | /* Normal frame. Local and In registers are saved on stack. */ |
| 916 | if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8) |
| 917 | addr = (get_prev_frame (frame1)->extra_info->bottom |
| 918 | + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
| 919 | + FRAME_SAVED_I0); |
| 920 | else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8) |
| 921 | addr = (get_prev_frame (frame1)->extra_info->bottom |
| 922 | + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE |
| 923 | + FRAME_SAVED_L0); |
| 924 | else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8) |
| 925 | { |
| 926 | /* Outs become ins. */ |
| 927 | get_saved_register (raw_buffer, optimized, addrp, frame1, |
| 928 | (regnum - O0_REGNUM + I0_REGNUM), lval); |
| 929 | return; |
| 930 | } |
| 931 | } |
| 932 | if (addr != 0) |
| 933 | break; |
| 934 | frame1 = frame1->next; |
| 935 | } |
| 936 | if (addr != 0) |
| 937 | { |
| 938 | if (lval != NULL) |
| 939 | *lval = lval_memory; |
| 940 | if (regnum == SP_REGNUM) |
| 941 | { |
| 942 | if (raw_buffer != NULL) |
| 943 | { |
| 944 | /* Put it back in target format. */ |
| 945 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), addr); |
| 946 | } |
| 947 | if (addrp != NULL) |
| 948 | *addrp = 0; |
| 949 | return; |
| 950 | } |
| 951 | if (raw_buffer != NULL) |
| 952 | read_memory (addr, raw_buffer, REGISTER_RAW_SIZE (regnum)); |
| 953 | } |
| 954 | else |
| 955 | { |
| 956 | if (lval != NULL) |
| 957 | *lval = lval_register; |
| 958 | addr = REGISTER_BYTE (regnum); |
| 959 | if (raw_buffer != NULL) |
| 960 | read_register_gen (regnum, raw_buffer); |
| 961 | } |
| 962 | if (addrp != NULL) |
| 963 | *addrp = addr; |
| 964 | } |
| 965 | |
| 966 | /* Push an empty stack frame, and record in it the current PC, regs, etc. |
| 967 | |
| 968 | We save the non-windowed registers and the ins. The locals and outs |
| 969 | are new; they don't need to be saved. The i's and l's of |
| 970 | the last frame were already saved on the stack. */ |
| 971 | |
| 972 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ |
| 973 | |
| 974 | /* See tm-sparc.h for how this is calculated. */ |
| 975 | |
| 976 | #define DUMMY_STACK_REG_BUF_SIZE \ |
| 977 | (((8+8+8) * SPARC_INTREG_SIZE) + FP_REGISTER_BYTES) |
| 978 | #define DUMMY_STACK_SIZE \ |
| 979 | (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET) |
| 980 | |
| 981 | void |
| 982 | sparc_push_dummy_frame (void) |
| 983 | { |
| 984 | CORE_ADDR sp, old_sp; |
| 985 | char *register_temp; |
| 986 | |
| 987 | register_temp = alloca (DUMMY_STACK_SIZE); |
| 988 | |
| 989 | old_sp = sp = read_sp (); |
| 990 | |
| 991 | if (GDB_TARGET_IS_SPARC64) |
| 992 | { |
| 993 | /* PC, NPC, CCR, FSR, FPRS, Y, ASI */ |
| 994 | read_register_bytes (REGISTER_BYTE (PC_REGNUM), ®ister_temp[0], |
| 995 | REGISTER_RAW_SIZE (PC_REGNUM) * 7); |
| 996 | read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM), |
| 997 | ®ister_temp[7 * SPARC_INTREG_SIZE], |
| 998 | REGISTER_RAW_SIZE (PSTATE_REGNUM)); |
| 999 | /* FIXME: not sure what needs to be saved here. */ |
| 1000 | } |
| 1001 | else |
| 1002 | { |
| 1003 | /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */ |
| 1004 | read_register_bytes (REGISTER_BYTE (Y_REGNUM), ®ister_temp[0], |
| 1005 | REGISTER_RAW_SIZE (Y_REGNUM) * 8); |
| 1006 | } |
| 1007 | |
| 1008 | read_register_bytes (REGISTER_BYTE (O0_REGNUM), |
| 1009 | ®ister_temp[8 * SPARC_INTREG_SIZE], |
| 1010 | SPARC_INTREG_SIZE * 8); |
| 1011 | |
| 1012 | read_register_bytes (REGISTER_BYTE (G0_REGNUM), |
| 1013 | ®ister_temp[16 * SPARC_INTREG_SIZE], |
| 1014 | SPARC_INTREG_SIZE * 8); |
| 1015 | |
| 1016 | if (SPARC_HAS_FPU) |
| 1017 | read_register_bytes (REGISTER_BYTE (FP0_REGNUM), |
| 1018 | ®ister_temp[24 * SPARC_INTREG_SIZE], |
| 1019 | FP_REGISTER_BYTES); |
| 1020 | |
| 1021 | sp -= DUMMY_STACK_SIZE; |
| 1022 | |
| 1023 | write_sp (sp); |
| 1024 | |
| 1025 | write_memory (sp + DUMMY_REG_SAVE_OFFSET, ®ister_temp[0], |
| 1026 | DUMMY_STACK_REG_BUF_SIZE); |
| 1027 | |
| 1028 | if (strcmp (target_shortname, "sim") != 0) |
| 1029 | { |
| 1030 | /* NOTE: cagney/2002-04-04: The code below originally contained |
| 1031 | GDB's _only_ call to write_fp(). That call was eliminated by |
| 1032 | inlining the corresponding code. For the 64 bit case, the |
| 1033 | old function (sparc64_write_fp) did the below although I'm |
| 1034 | not clear why. The same goes for why this is only done when |
| 1035 | the underlying target is a simulator. */ |
| 1036 | if (GDB_TARGET_IS_SPARC64) |
| 1037 | { |
| 1038 | /* Target is a 64 bit SPARC. */ |
| 1039 | CORE_ADDR oldfp = read_register (FP_REGNUM); |
| 1040 | if (oldfp & 1) |
| 1041 | write_register (FP_REGNUM, old_sp - 2047); |
| 1042 | else |
| 1043 | write_register (FP_REGNUM, old_sp); |
| 1044 | } |
| 1045 | else |
| 1046 | { |
| 1047 | /* Target is a 32 bit SPARC. */ |
| 1048 | write_register (FP_REGNUM, old_sp); |
| 1049 | } |
| 1050 | /* Set return address register for the call dummy to the current PC. */ |
| 1051 | write_register (I7_REGNUM, read_pc () - 8); |
| 1052 | } |
| 1053 | else |
| 1054 | { |
| 1055 | /* The call dummy will write this value to FP before executing |
| 1056 | the 'save'. This ensures that register window flushes work |
| 1057 | correctly in the simulator. */ |
| 1058 | write_register (G0_REGNUM + 1, read_register (FP_REGNUM)); |
| 1059 | |
| 1060 | /* The call dummy will write this value to FP after executing |
| 1061 | the 'save'. */ |
| 1062 | write_register (G0_REGNUM + 2, old_sp); |
| 1063 | |
| 1064 | /* The call dummy will write this value to the return address (%i7) after |
| 1065 | executing the 'save'. */ |
| 1066 | write_register (G0_REGNUM + 3, read_pc () - 8); |
| 1067 | |
| 1068 | /* Set the FP that the call dummy will be using after the 'save'. |
| 1069 | This makes backtraces from an inferior function call work properly. */ |
| 1070 | write_register (FP_REGNUM, old_sp); |
| 1071 | } |
| 1072 | } |
| 1073 | |
| 1074 | /* sparc_frame_find_saved_regs (). This function is here only because |
| 1075 | pop_frame uses it. Note there is an interesting corner case which |
| 1076 | I think few ports of GDB get right--if you are popping a frame |
| 1077 | which does not save some register that *is* saved by a more inner |
| 1078 | frame (such a frame will never be a dummy frame because dummy |
| 1079 | frames save all registers). Rewriting pop_frame to use |
| 1080 | get_saved_register would solve this problem and also get rid of the |
| 1081 | ugly duplication between sparc_frame_find_saved_regs and |
| 1082 | get_saved_register. |
| 1083 | |
| 1084 | Stores, into an array of CORE_ADDR, |
| 1085 | the addresses of the saved registers of frame described by FRAME_INFO. |
| 1086 | This includes special registers such as pc and fp saved in special |
| 1087 | ways in the stack frame. sp is even more special: |
| 1088 | the address we return for it IS the sp for the next frame. |
| 1089 | |
| 1090 | Note that on register window machines, we are currently making the |
| 1091 | assumption that window registers are being saved somewhere in the |
| 1092 | frame in which they are being used. If they are stored in an |
| 1093 | inferior frame, find_saved_register will break. |
| 1094 | |
| 1095 | On the Sun 4, the only time all registers are saved is when |
| 1096 | a dummy frame is involved. Otherwise, the only saved registers |
| 1097 | are the LOCAL and IN registers which are saved as a result |
| 1098 | of the "save/restore" opcodes. This condition is determined |
| 1099 | by address rather than by value. |
| 1100 | |
| 1101 | The "pc" is not stored in a frame on the SPARC. (What is stored |
| 1102 | is a return address minus 8.) sparc_pop_frame knows how to |
| 1103 | deal with that. Other routines might or might not. |
| 1104 | |
| 1105 | See tm-sparc.h (PUSH_DUMMY_FRAME and friends) for CRITICAL information |
| 1106 | about how this works. */ |
| 1107 | |
| 1108 | static void sparc_frame_find_saved_regs (struct frame_info *, CORE_ADDR *); |
| 1109 | |
| 1110 | static void |
| 1111 | sparc_frame_find_saved_regs (struct frame_info *fi, CORE_ADDR *saved_regs_addr) |
| 1112 | { |
| 1113 | register int regnum; |
| 1114 | CORE_ADDR frame_addr = FRAME_FP (fi); |
| 1115 | |
| 1116 | if (!fi) |
| 1117 | internal_error (__FILE__, __LINE__, |
| 1118 | "Bad frame info struct in FRAME_FIND_SAVED_REGS"); |
| 1119 | |
| 1120 | memset (saved_regs_addr, 0, NUM_REGS * sizeof (CORE_ADDR)); |
| 1121 | |
| 1122 | if (fi->pc >= (fi->extra_info->bottom ? |
| 1123 | fi->extra_info->bottom : read_sp ()) |
| 1124 | && fi->pc <= FRAME_FP (fi)) |
| 1125 | { |
| 1126 | /* Dummy frame. All but the window regs are in there somewhere. */ |
| 1127 | for (regnum = G1_REGNUM; regnum < G1_REGNUM + 7; regnum++) |
| 1128 | saved_regs_addr[regnum] = |
| 1129 | frame_addr + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE |
| 1130 | - DUMMY_STACK_REG_BUF_SIZE + 16 * SPARC_INTREG_SIZE; |
| 1131 | |
| 1132 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; regnum++) |
| 1133 | saved_regs_addr[regnum] = |
| 1134 | frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
| 1135 | - DUMMY_STACK_REG_BUF_SIZE + 8 * SPARC_INTREG_SIZE; |
| 1136 | |
| 1137 | if (SPARC_HAS_FPU) |
| 1138 | for (regnum = FP0_REGNUM; regnum < FP_MAX_REGNUM; regnum++) |
| 1139 | saved_regs_addr[regnum] = frame_addr + (regnum - FP0_REGNUM) * 4 |
| 1140 | - DUMMY_STACK_REG_BUF_SIZE + 24 * SPARC_INTREG_SIZE; |
| 1141 | |
| 1142 | if (GDB_TARGET_IS_SPARC64) |
| 1143 | { |
| 1144 | for (regnum = PC_REGNUM; regnum < PC_REGNUM + 7; regnum++) |
| 1145 | { |
| 1146 | saved_regs_addr[regnum] = |
| 1147 | frame_addr + (regnum - PC_REGNUM) * SPARC_INTREG_SIZE |
| 1148 | - DUMMY_STACK_REG_BUF_SIZE; |
| 1149 | } |
| 1150 | saved_regs_addr[PSTATE_REGNUM] = |
| 1151 | frame_addr + 8 * SPARC_INTREG_SIZE - DUMMY_STACK_REG_BUF_SIZE; |
| 1152 | } |
| 1153 | else |
| 1154 | for (regnum = Y_REGNUM; regnum < NUM_REGS; regnum++) |
| 1155 | saved_regs_addr[regnum] = |
| 1156 | frame_addr + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE |
| 1157 | - DUMMY_STACK_REG_BUF_SIZE; |
| 1158 | |
| 1159 | frame_addr = fi->extra_info->bottom ? |
| 1160 | fi->extra_info->bottom : read_sp (); |
| 1161 | } |
| 1162 | else if (fi->extra_info->flat) |
| 1163 | { |
| 1164 | CORE_ADDR func_start; |
| 1165 | find_pc_partial_function (fi->pc, NULL, &func_start, NULL); |
| 1166 | examine_prologue (func_start, 0, fi, saved_regs_addr); |
| 1167 | |
| 1168 | /* Flat register window frame. */ |
| 1169 | saved_regs_addr[RP_REGNUM] = fi->extra_info->pc_addr; |
| 1170 | saved_regs_addr[I7_REGNUM] = fi->extra_info->fp_addr; |
| 1171 | } |
| 1172 | else |
| 1173 | { |
| 1174 | /* Normal frame. Just Local and In registers */ |
| 1175 | frame_addr = fi->extra_info->bottom ? |
| 1176 | fi->extra_info->bottom : read_sp (); |
| 1177 | for (regnum = L0_REGNUM; regnum < L0_REGNUM + 8; regnum++) |
| 1178 | saved_regs_addr[regnum] = |
| 1179 | (frame_addr + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE |
| 1180 | + FRAME_SAVED_L0); |
| 1181 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; regnum++) |
| 1182 | saved_regs_addr[regnum] = |
| 1183 | (frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
| 1184 | + FRAME_SAVED_I0); |
| 1185 | } |
| 1186 | if (fi->next) |
| 1187 | { |
| 1188 | if (fi->extra_info->flat) |
| 1189 | { |
| 1190 | saved_regs_addr[O7_REGNUM] = fi->extra_info->pc_addr; |
| 1191 | } |
| 1192 | else |
| 1193 | { |
| 1194 | /* Pull off either the next frame pointer or the stack pointer */ |
| 1195 | CORE_ADDR next_next_frame_addr = |
| 1196 | (fi->next->extra_info->bottom ? |
| 1197 | fi->next->extra_info->bottom : read_sp ()); |
| 1198 | for (regnum = O0_REGNUM; regnum < O0_REGNUM + 8; regnum++) |
| 1199 | saved_regs_addr[regnum] = |
| 1200 | (next_next_frame_addr |
| 1201 | + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE |
| 1202 | + FRAME_SAVED_I0); |
| 1203 | } |
| 1204 | } |
| 1205 | /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */ |
| 1206 | /* FIXME -- should this adjust for the sparc64 offset? */ |
| 1207 | saved_regs_addr[SP_REGNUM] = FRAME_FP (fi); |
| 1208 | } |
| 1209 | |
| 1210 | /* Discard from the stack the innermost frame, restoring all saved registers. |
| 1211 | |
| 1212 | Note that the values stored in fsr by get_frame_saved_regs are *in |
| 1213 | the context of the called frame*. What this means is that the i |
| 1214 | regs of fsr must be restored into the o regs of the (calling) frame that |
| 1215 | we pop into. We don't care about the output regs of the calling frame, |
| 1216 | since unless it's a dummy frame, it won't have any output regs in it. |
| 1217 | |
| 1218 | We never have to bother with %l (local) regs, since the called routine's |
| 1219 | locals get tossed, and the calling routine's locals are already saved |
| 1220 | on its stack. */ |
| 1221 | |
| 1222 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ |
| 1223 | |
| 1224 | void |
| 1225 | sparc_pop_frame (void) |
| 1226 | { |
| 1227 | register struct frame_info *frame = get_current_frame (); |
| 1228 | register CORE_ADDR pc; |
| 1229 | CORE_ADDR *fsr; |
| 1230 | char *raw_buffer; |
| 1231 | int regnum; |
| 1232 | |
| 1233 | fsr = alloca (NUM_REGS * sizeof (CORE_ADDR)); |
| 1234 | raw_buffer = alloca (REGISTER_BYTES); |
| 1235 | sparc_frame_find_saved_regs (frame, &fsr[0]); |
| 1236 | if (SPARC_HAS_FPU) |
| 1237 | { |
| 1238 | if (fsr[FP0_REGNUM]) |
| 1239 | { |
| 1240 | read_memory (fsr[FP0_REGNUM], raw_buffer, FP_REGISTER_BYTES); |
| 1241 | write_register_bytes (REGISTER_BYTE (FP0_REGNUM), |
| 1242 | raw_buffer, FP_REGISTER_BYTES); |
| 1243 | } |
| 1244 | if (!(GDB_TARGET_IS_SPARC64)) |
| 1245 | { |
| 1246 | if (fsr[FPS_REGNUM]) |
| 1247 | { |
| 1248 | read_memory (fsr[FPS_REGNUM], raw_buffer, SPARC_INTREG_SIZE); |
| 1249 | write_register_gen (FPS_REGNUM, raw_buffer); |
| 1250 | } |
| 1251 | if (fsr[CPS_REGNUM]) |
| 1252 | { |
| 1253 | read_memory (fsr[CPS_REGNUM], raw_buffer, SPARC_INTREG_SIZE); |
| 1254 | write_register_gen (CPS_REGNUM, raw_buffer); |
| 1255 | } |
| 1256 | } |
| 1257 | } |
| 1258 | if (fsr[G1_REGNUM]) |
| 1259 | { |
| 1260 | read_memory (fsr[G1_REGNUM], raw_buffer, 7 * SPARC_INTREG_SIZE); |
| 1261 | write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer, |
| 1262 | 7 * SPARC_INTREG_SIZE); |
| 1263 | } |
| 1264 | |
| 1265 | if (frame->extra_info->flat) |
| 1266 | { |
| 1267 | /* Each register might or might not have been saved, need to test |
| 1268 | individually. */ |
| 1269 | for (regnum = L0_REGNUM; regnum < L0_REGNUM + 8; ++regnum) |
| 1270 | if (fsr[regnum]) |
| 1271 | write_register (regnum, read_memory_integer (fsr[regnum], |
| 1272 | SPARC_INTREG_SIZE)); |
| 1273 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; ++regnum) |
| 1274 | if (fsr[regnum]) |
| 1275 | write_register (regnum, read_memory_integer (fsr[regnum], |
| 1276 | SPARC_INTREG_SIZE)); |
| 1277 | |
| 1278 | /* Handle all outs except stack pointer (o0-o5; o7). */ |
| 1279 | for (regnum = O0_REGNUM; regnum < O0_REGNUM + 6; ++regnum) |
| 1280 | if (fsr[regnum]) |
| 1281 | write_register (regnum, read_memory_integer (fsr[regnum], |
| 1282 | SPARC_INTREG_SIZE)); |
| 1283 | if (fsr[O0_REGNUM + 7]) |
| 1284 | write_register (O0_REGNUM + 7, |
| 1285 | read_memory_integer (fsr[O0_REGNUM + 7], |
| 1286 | SPARC_INTREG_SIZE)); |
| 1287 | |
| 1288 | write_sp (frame->frame); |
| 1289 | } |
| 1290 | else if (fsr[I0_REGNUM]) |
| 1291 | { |
| 1292 | CORE_ADDR sp; |
| 1293 | |
| 1294 | char *reg_temp; |
| 1295 | |
| 1296 | reg_temp = alloca (SPARC_INTREG_SIZE * 16); |
| 1297 | |
| 1298 | read_memory (fsr[I0_REGNUM], raw_buffer, 8 * SPARC_INTREG_SIZE); |
| 1299 | |
| 1300 | /* Get the ins and locals which we are about to restore. Just |
| 1301 | moving the stack pointer is all that is really needed, except |
| 1302 | store_inferior_registers is then going to write the ins and |
| 1303 | locals from the registers array, so we need to muck with the |
| 1304 | registers array. */ |
| 1305 | sp = fsr[SP_REGNUM]; |
| 1306 | |
| 1307 | if (GDB_TARGET_IS_SPARC64 && (sp & 1)) |
| 1308 | sp += 2047; |
| 1309 | |
| 1310 | read_memory (sp, reg_temp, SPARC_INTREG_SIZE * 16); |
| 1311 | |
| 1312 | /* Restore the out registers. |
| 1313 | Among other things this writes the new stack pointer. */ |
| 1314 | write_register_bytes (REGISTER_BYTE (O0_REGNUM), raw_buffer, |
| 1315 | SPARC_INTREG_SIZE * 8); |
| 1316 | |
| 1317 | write_register_bytes (REGISTER_BYTE (L0_REGNUM), reg_temp, |
| 1318 | SPARC_INTREG_SIZE * 16); |
| 1319 | } |
| 1320 | |
| 1321 | if (!(GDB_TARGET_IS_SPARC64)) |
| 1322 | if (fsr[PS_REGNUM]) |
| 1323 | write_register (PS_REGNUM, |
| 1324 | read_memory_integer (fsr[PS_REGNUM], |
| 1325 | REGISTER_RAW_SIZE (PS_REGNUM))); |
| 1326 | |
| 1327 | if (fsr[Y_REGNUM]) |
| 1328 | write_register (Y_REGNUM, |
| 1329 | read_memory_integer (fsr[Y_REGNUM], |
| 1330 | REGISTER_RAW_SIZE (Y_REGNUM))); |
| 1331 | if (fsr[PC_REGNUM]) |
| 1332 | { |
| 1333 | /* Explicitly specified PC (and maybe NPC) -- just restore them. */ |
| 1334 | write_register (PC_REGNUM, |
| 1335 | read_memory_integer (fsr[PC_REGNUM], |
| 1336 | REGISTER_RAW_SIZE (PC_REGNUM))); |
| 1337 | if (fsr[NPC_REGNUM]) |
| 1338 | write_register (NPC_REGNUM, |
| 1339 | read_memory_integer (fsr[NPC_REGNUM], |
| 1340 | REGISTER_RAW_SIZE (NPC_REGNUM))); |
| 1341 | } |
| 1342 | else if (frame->extra_info->flat) |
| 1343 | { |
| 1344 | if (frame->extra_info->pc_addr) |
| 1345 | pc = PC_ADJUST ((CORE_ADDR) |
| 1346 | read_memory_integer (frame->extra_info->pc_addr, |
| 1347 | REGISTER_RAW_SIZE (PC_REGNUM))); |
| 1348 | else |
| 1349 | { |
| 1350 | /* I think this happens only in the innermost frame, if so then |
| 1351 | it is a complicated way of saying |
| 1352 | "pc = read_register (O7_REGNUM);". */ |
| 1353 | char *buf; |
| 1354 | |
| 1355 | buf = alloca (MAX_REGISTER_RAW_SIZE); |
| 1356 | get_saved_register (buf, 0, 0, frame, O7_REGNUM, 0); |
| 1357 | pc = PC_ADJUST (extract_address |
| 1358 | (buf, REGISTER_RAW_SIZE (O7_REGNUM))); |
| 1359 | } |
| 1360 | |
| 1361 | write_register (PC_REGNUM, pc); |
| 1362 | write_register (NPC_REGNUM, pc + 4); |
| 1363 | } |
| 1364 | else if (fsr[I7_REGNUM]) |
| 1365 | { |
| 1366 | /* Return address in %i7 -- adjust it, then restore PC and NPC from it */ |
| 1367 | pc = PC_ADJUST ((CORE_ADDR) read_memory_integer (fsr[I7_REGNUM], |
| 1368 | SPARC_INTREG_SIZE)); |
| 1369 | write_register (PC_REGNUM, pc); |
| 1370 | write_register (NPC_REGNUM, pc + 4); |
| 1371 | } |
| 1372 | flush_cached_frames (); |
| 1373 | } |
| 1374 | |
| 1375 | /* On the Sun 4 under SunOS, the compile will leave a fake insn which |
| 1376 | encodes the structure size being returned. If we detect such |
| 1377 | a fake insn, step past it. */ |
| 1378 | |
| 1379 | CORE_ADDR |
| 1380 | sparc_pc_adjust (CORE_ADDR pc) |
| 1381 | { |
| 1382 | unsigned long insn; |
| 1383 | char buf[4]; |
| 1384 | int err; |
| 1385 | |
| 1386 | err = target_read_memory (pc + 8, buf, 4); |
| 1387 | insn = extract_unsigned_integer (buf, 4); |
| 1388 | if ((err == 0) && (insn & 0xffc00000) == 0) |
| 1389 | return pc + 12; |
| 1390 | else |
| 1391 | return pc + 8; |
| 1392 | } |
| 1393 | |
| 1394 | /* If pc is in a shared library trampoline, return its target. |
| 1395 | The SunOs 4.x linker rewrites the jump table entries for PIC |
| 1396 | compiled modules in the main executable to bypass the dynamic linker |
| 1397 | with jumps of the form |
| 1398 | sethi %hi(addr),%g1 |
| 1399 | jmp %g1+%lo(addr) |
| 1400 | and removes the corresponding jump table relocation entry in the |
| 1401 | dynamic relocations. |
| 1402 | find_solib_trampoline_target relies on the presence of the jump |
| 1403 | table relocation entry, so we have to detect these jump instructions |
| 1404 | by hand. */ |
| 1405 | |
| 1406 | CORE_ADDR |
| 1407 | sunos4_skip_trampoline_code (CORE_ADDR pc) |
| 1408 | { |
| 1409 | unsigned long insn1; |
| 1410 | char buf[4]; |
| 1411 | int err; |
| 1412 | |
| 1413 | err = target_read_memory (pc, buf, 4); |
| 1414 | insn1 = extract_unsigned_integer (buf, 4); |
| 1415 | if (err == 0 && (insn1 & 0xffc00000) == 0x03000000) |
| 1416 | { |
| 1417 | unsigned long insn2; |
| 1418 | |
| 1419 | err = target_read_memory (pc + 4, buf, 4); |
| 1420 | insn2 = extract_unsigned_integer (buf, 4); |
| 1421 | if (err == 0 && (insn2 & 0xffffe000) == 0x81c06000) |
| 1422 | { |
| 1423 | CORE_ADDR target_pc = (insn1 & 0x3fffff) << 10; |
| 1424 | int delta = insn2 & 0x1fff; |
| 1425 | |
| 1426 | /* Sign extend the displacement. */ |
| 1427 | if (delta & 0x1000) |
| 1428 | delta |= ~0x1fff; |
| 1429 | return target_pc + delta; |
| 1430 | } |
| 1431 | } |
| 1432 | return find_solib_trampoline_target (pc); |
| 1433 | } |
| 1434 | \f |
| 1435 | #ifdef USE_PROC_FS /* Target dependent support for /proc */ |
| 1436 | /* *INDENT-OFF* */ |
| 1437 | /* The /proc interface divides the target machine's register set up into |
| 1438 | two different sets, the general register set (gregset) and the floating |
| 1439 | point register set (fpregset). For each set, there is an ioctl to get |
| 1440 | the current register set and another ioctl to set the current values. |
| 1441 | |
| 1442 | The actual structure passed through the ioctl interface is, of course, |
| 1443 | naturally machine dependent, and is different for each set of registers. |
| 1444 | For the sparc for example, the general register set is typically defined |
| 1445 | by: |
| 1446 | |
| 1447 | typedef int gregset_t[38]; |
| 1448 | |
| 1449 | #define R_G0 0 |
| 1450 | ... |
| 1451 | #define R_TBR 37 |
| 1452 | |
| 1453 | and the floating point set by: |
| 1454 | |
| 1455 | typedef struct prfpregset { |
| 1456 | union { |
| 1457 | u_long pr_regs[32]; |
| 1458 | double pr_dregs[16]; |
| 1459 | } pr_fr; |
| 1460 | void * pr_filler; |
| 1461 | u_long pr_fsr; |
| 1462 | u_char pr_qcnt; |
| 1463 | u_char pr_q_entrysize; |
| 1464 | u_char pr_en; |
| 1465 | u_long pr_q[64]; |
| 1466 | } prfpregset_t; |
| 1467 | |
| 1468 | These routines provide the packing and unpacking of gregset_t and |
| 1469 | fpregset_t formatted data. |
| 1470 | |
| 1471 | */ |
| 1472 | /* *INDENT-ON* */ |
| 1473 | |
| 1474 | /* Given a pointer to a general register set in /proc format (gregset_t *), |
| 1475 | unpack the register contents and supply them as gdb's idea of the current |
| 1476 | register values. */ |
| 1477 | |
| 1478 | void |
| 1479 | supply_gregset (gdb_gregset_t *gregsetp) |
| 1480 | { |
| 1481 | prgreg_t *regp = (prgreg_t *) gregsetp; |
| 1482 | int regi, offset = 0; |
| 1483 | |
| 1484 | /* If the host is 64-bit sparc, but the target is 32-bit sparc, |
| 1485 | then the gregset may contain 64-bit ints while supply_register |
| 1486 | is expecting 32-bit ints. Compensate. */ |
| 1487 | if (sizeof (regp[0]) == 8 && SPARC_INTREG_SIZE == 4) |
| 1488 | offset = 4; |
| 1489 | |
| 1490 | /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */ |
| 1491 | /* FIXME MVS: assumes the order of the first 32 elements... */ |
| 1492 | for (regi = G0_REGNUM; regi <= I7_REGNUM; regi++) |
| 1493 | { |
| 1494 | supply_register (regi, ((char *) (regp + regi)) + offset); |
| 1495 | } |
| 1496 | |
| 1497 | /* These require a bit more care. */ |
| 1498 | supply_register (PC_REGNUM, ((char *) (regp + R_PC)) + offset); |
| 1499 | supply_register (NPC_REGNUM, ((char *) (regp + R_nPC)) + offset); |
| 1500 | supply_register (Y_REGNUM, ((char *) (regp + R_Y)) + offset); |
| 1501 | |
| 1502 | if (GDB_TARGET_IS_SPARC64) |
| 1503 | { |
| 1504 | #ifdef R_CCR |
| 1505 | supply_register (CCR_REGNUM, ((char *) (regp + R_CCR)) + offset); |
| 1506 | #else |
| 1507 | supply_register (CCR_REGNUM, NULL); |
| 1508 | #endif |
| 1509 | #ifdef R_FPRS |
| 1510 | supply_register (FPRS_REGNUM, ((char *) (regp + R_FPRS)) + offset); |
| 1511 | #else |
| 1512 | supply_register (FPRS_REGNUM, NULL); |
| 1513 | #endif |
| 1514 | #ifdef R_ASI |
| 1515 | supply_register (ASI_REGNUM, ((char *) (regp + R_ASI)) + offset); |
| 1516 | #else |
| 1517 | supply_register (ASI_REGNUM, NULL); |
| 1518 | #endif |
| 1519 | } |
| 1520 | else /* sparc32 */ |
| 1521 | { |
| 1522 | #ifdef R_PS |
| 1523 | supply_register (PS_REGNUM, ((char *) (regp + R_PS)) + offset); |
| 1524 | #else |
| 1525 | supply_register (PS_REGNUM, NULL); |
| 1526 | #endif |
| 1527 | |
| 1528 | /* For 64-bit hosts, R_WIM and R_TBR may not be defined. |
| 1529 | Steal R_ASI and R_FPRS, and hope for the best! */ |
| 1530 | |
| 1531 | #if !defined (R_WIM) && defined (R_ASI) |
| 1532 | #define R_WIM R_ASI |
| 1533 | #endif |
| 1534 | |
| 1535 | #if !defined (R_TBR) && defined (R_FPRS) |
| 1536 | #define R_TBR R_FPRS |
| 1537 | #endif |
| 1538 | |
| 1539 | #if defined (R_WIM) |
| 1540 | supply_register (WIM_REGNUM, ((char *) (regp + R_WIM)) + offset); |
| 1541 | #else |
| 1542 | supply_register (WIM_REGNUM, NULL); |
| 1543 | #endif |
| 1544 | |
| 1545 | #if defined (R_TBR) |
| 1546 | supply_register (TBR_REGNUM, ((char *) (regp + R_TBR)) + offset); |
| 1547 | #else |
| 1548 | supply_register (TBR_REGNUM, NULL); |
| 1549 | #endif |
| 1550 | } |
| 1551 | |
| 1552 | /* Fill inaccessible registers with zero. */ |
| 1553 | if (GDB_TARGET_IS_SPARC64) |
| 1554 | { |
| 1555 | /* |
| 1556 | * don't know how to get value of any of the following: |
| 1557 | */ |
| 1558 | supply_register (VER_REGNUM, NULL); |
| 1559 | supply_register (TICK_REGNUM, NULL); |
| 1560 | supply_register (PIL_REGNUM, NULL); |
| 1561 | supply_register (PSTATE_REGNUM, NULL); |
| 1562 | supply_register (TSTATE_REGNUM, NULL); |
| 1563 | supply_register (TBA_REGNUM, NULL); |
| 1564 | supply_register (TL_REGNUM, NULL); |
| 1565 | supply_register (TT_REGNUM, NULL); |
| 1566 | supply_register (TPC_REGNUM, NULL); |
| 1567 | supply_register (TNPC_REGNUM, NULL); |
| 1568 | supply_register (WSTATE_REGNUM, NULL); |
| 1569 | supply_register (CWP_REGNUM, NULL); |
| 1570 | supply_register (CANSAVE_REGNUM, NULL); |
| 1571 | supply_register (CANRESTORE_REGNUM, NULL); |
| 1572 | supply_register (CLEANWIN_REGNUM, NULL); |
| 1573 | supply_register (OTHERWIN_REGNUM, NULL); |
| 1574 | supply_register (ASR16_REGNUM, NULL); |
| 1575 | supply_register (ASR17_REGNUM, NULL); |
| 1576 | supply_register (ASR18_REGNUM, NULL); |
| 1577 | supply_register (ASR19_REGNUM, NULL); |
| 1578 | supply_register (ASR20_REGNUM, NULL); |
| 1579 | supply_register (ASR21_REGNUM, NULL); |
| 1580 | supply_register (ASR22_REGNUM, NULL); |
| 1581 | supply_register (ASR23_REGNUM, NULL); |
| 1582 | supply_register (ASR24_REGNUM, NULL); |
| 1583 | supply_register (ASR25_REGNUM, NULL); |
| 1584 | supply_register (ASR26_REGNUM, NULL); |
| 1585 | supply_register (ASR27_REGNUM, NULL); |
| 1586 | supply_register (ASR28_REGNUM, NULL); |
| 1587 | supply_register (ASR29_REGNUM, NULL); |
| 1588 | supply_register (ASR30_REGNUM, NULL); |
| 1589 | supply_register (ASR31_REGNUM, NULL); |
| 1590 | supply_register (ICC_REGNUM, NULL); |
| 1591 | supply_register (XCC_REGNUM, NULL); |
| 1592 | } |
| 1593 | else |
| 1594 | { |
| 1595 | supply_register (CPS_REGNUM, NULL); |
| 1596 | } |
| 1597 | } |
| 1598 | |
| 1599 | void |
| 1600 | fill_gregset (gdb_gregset_t *gregsetp, int regno) |
| 1601 | { |
| 1602 | prgreg_t *regp = (prgreg_t *) gregsetp; |
| 1603 | int regi, offset = 0; |
| 1604 | |
| 1605 | /* If the host is 64-bit sparc, but the target is 32-bit sparc, |
| 1606 | then the gregset may contain 64-bit ints while supply_register |
| 1607 | is expecting 32-bit ints. Compensate. */ |
| 1608 | if (sizeof (regp[0]) == 8 && SPARC_INTREG_SIZE == 4) |
| 1609 | offset = 4; |
| 1610 | |
| 1611 | for (regi = 0; regi <= R_I7; regi++) |
| 1612 | if ((regno == -1) || (regno == regi)) |
| 1613 | read_register_gen (regi, (char *) (regp + regi) + offset); |
| 1614 | |
| 1615 | if ((regno == -1) || (regno == PC_REGNUM)) |
| 1616 | read_register_gen (PC_REGNUM, (char *) (regp + R_PC) + offset); |
| 1617 | |
| 1618 | if ((regno == -1) || (regno == NPC_REGNUM)) |
| 1619 | read_register_gen (NPC_REGNUM, (char *) (regp + R_nPC) + offset); |
| 1620 | |
| 1621 | if ((regno == -1) || (regno == Y_REGNUM)) |
| 1622 | read_register_gen (Y_REGNUM, (char *) (regp + R_Y) + offset); |
| 1623 | |
| 1624 | if (GDB_TARGET_IS_SPARC64) |
| 1625 | { |
| 1626 | #ifdef R_CCR |
| 1627 | if (regno == -1 || regno == CCR_REGNUM) |
| 1628 | read_register_gen (CCR_REGNUM, ((char *) (regp + R_CCR)) + offset); |
| 1629 | #endif |
| 1630 | #ifdef R_FPRS |
| 1631 | if (regno == -1 || regno == FPRS_REGNUM) |
| 1632 | read_register_gen (FPRS_REGNUM, ((char *) (regp + R_FPRS)) + offset); |
| 1633 | #endif |
| 1634 | #ifdef R_ASI |
| 1635 | if (regno == -1 || regno == ASI_REGNUM) |
| 1636 | read_register_gen (ASI_REGNUM, ((char *) (regp + R_ASI)) + offset); |
| 1637 | #endif |
| 1638 | } |
| 1639 | else /* sparc32 */ |
| 1640 | { |
| 1641 | #ifdef R_PS |
| 1642 | if (regno == -1 || regno == PS_REGNUM) |
| 1643 | read_register_gen (PS_REGNUM, ((char *) (regp + R_PS)) + offset); |
| 1644 | #endif |
| 1645 | |
| 1646 | /* For 64-bit hosts, R_WIM and R_TBR may not be defined. |
| 1647 | Steal R_ASI and R_FPRS, and hope for the best! */ |
| 1648 | |
| 1649 | #if !defined (R_WIM) && defined (R_ASI) |
| 1650 | #define R_WIM R_ASI |
| 1651 | #endif |
| 1652 | |
| 1653 | #if !defined (R_TBR) && defined (R_FPRS) |
| 1654 | #define R_TBR R_FPRS |
| 1655 | #endif |
| 1656 | |
| 1657 | #if defined (R_WIM) |
| 1658 | if (regno == -1 || regno == WIM_REGNUM) |
| 1659 | read_register_gen (WIM_REGNUM, ((char *) (regp + R_WIM)) + offset); |
| 1660 | #else |
| 1661 | if (regno == -1 || regno == WIM_REGNUM) |
| 1662 | read_register_gen (WIM_REGNUM, NULL); |
| 1663 | #endif |
| 1664 | |
| 1665 | #if defined (R_TBR) |
| 1666 | if (regno == -1 || regno == TBR_REGNUM) |
| 1667 | read_register_gen (TBR_REGNUM, ((char *) (regp + R_TBR)) + offset); |
| 1668 | #else |
| 1669 | if (regno == -1 || regno == TBR_REGNUM) |
| 1670 | read_register_gen (TBR_REGNUM, NULL); |
| 1671 | #endif |
| 1672 | } |
| 1673 | } |
| 1674 | |
| 1675 | /* Given a pointer to a floating point register set in /proc format |
| 1676 | (fpregset_t *), unpack the register contents and supply them as gdb's |
| 1677 | idea of the current floating point register values. */ |
| 1678 | |
| 1679 | void |
| 1680 | supply_fpregset (gdb_fpregset_t *fpregsetp) |
| 1681 | { |
| 1682 | register int regi; |
| 1683 | char *from; |
| 1684 | |
| 1685 | if (!SPARC_HAS_FPU) |
| 1686 | return; |
| 1687 | |
| 1688 | for (regi = FP0_REGNUM; regi < FP_MAX_REGNUM; regi++) |
| 1689 | { |
| 1690 | from = (char *) &fpregsetp->pr_fr.pr_regs[regi - FP0_REGNUM]; |
| 1691 | supply_register (regi, from); |
| 1692 | } |
| 1693 | |
| 1694 | if (GDB_TARGET_IS_SPARC64) |
| 1695 | { |
| 1696 | /* |
| 1697 | * don't know how to get value of the following. |
| 1698 | */ |
| 1699 | supply_register (FSR_REGNUM, NULL); /* zero it out for now */ |
| 1700 | supply_register (FCC0_REGNUM, NULL); |
| 1701 | supply_register (FCC1_REGNUM, NULL); /* don't know how to get value */ |
| 1702 | supply_register (FCC2_REGNUM, NULL); /* don't know how to get value */ |
| 1703 | supply_register (FCC3_REGNUM, NULL); /* don't know how to get value */ |
| 1704 | } |
| 1705 | else |
| 1706 | { |
| 1707 | supply_register (FPS_REGNUM, (char *) &(fpregsetp->pr_fsr)); |
| 1708 | } |
| 1709 | } |
| 1710 | |
| 1711 | /* Given a pointer to a floating point register set in /proc format |
| 1712 | (fpregset_t *), update the register specified by REGNO from gdb's idea |
| 1713 | of the current floating point register set. If REGNO is -1, update |
| 1714 | them all. */ |
| 1715 | /* This will probably need some changes for sparc64. */ |
| 1716 | |
| 1717 | void |
| 1718 | fill_fpregset (gdb_fpregset_t *fpregsetp, int regno) |
| 1719 | { |
| 1720 | int regi; |
| 1721 | char *to; |
| 1722 | char *from; |
| 1723 | |
| 1724 | if (!SPARC_HAS_FPU) |
| 1725 | return; |
| 1726 | |
| 1727 | for (regi = FP0_REGNUM; regi < FP_MAX_REGNUM; regi++) |
| 1728 | { |
| 1729 | if ((regno == -1) || (regno == regi)) |
| 1730 | { |
| 1731 | from = (char *) ®isters[REGISTER_BYTE (regi)]; |
| 1732 | to = (char *) &fpregsetp->pr_fr.pr_regs[regi - FP0_REGNUM]; |
| 1733 | memcpy (to, from, REGISTER_RAW_SIZE (regi)); |
| 1734 | } |
| 1735 | } |
| 1736 | |
| 1737 | if (!(GDB_TARGET_IS_SPARC64)) /* FIXME: does Sparc64 have this register? */ |
| 1738 | if ((regno == -1) || (regno == FPS_REGNUM)) |
| 1739 | { |
| 1740 | from = (char *)®isters[REGISTER_BYTE (FPS_REGNUM)]; |
| 1741 | to = (char *) &fpregsetp->pr_fsr; |
| 1742 | memcpy (to, from, REGISTER_RAW_SIZE (FPS_REGNUM)); |
| 1743 | } |
| 1744 | } |
| 1745 | |
| 1746 | #endif /* USE_PROC_FS */ |
| 1747 | |
| 1748 | /* Because of Multi-arch, GET_LONGJMP_TARGET is always defined. So test |
| 1749 | for a definition of JB_PC. */ |
| 1750 | #ifdef JB_PC |
| 1751 | |
| 1752 | /* Figure out where the longjmp will land. We expect that we have just entered |
| 1753 | longjmp and haven't yet setup the stack frame, so the args are still in the |
| 1754 | output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we |
| 1755 | extract the pc (JB_PC) that we will land at. The pc is copied into ADDR. |
| 1756 | This routine returns true on success */ |
| 1757 | |
| 1758 | int |
| 1759 | get_longjmp_target (CORE_ADDR *pc) |
| 1760 | { |
| 1761 | CORE_ADDR jb_addr; |
| 1762 | #define LONGJMP_TARGET_SIZE 4 |
| 1763 | char buf[LONGJMP_TARGET_SIZE]; |
| 1764 | |
| 1765 | jb_addr = read_register (O0_REGNUM); |
| 1766 | |
| 1767 | if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf, |
| 1768 | LONGJMP_TARGET_SIZE)) |
| 1769 | return 0; |
| 1770 | |
| 1771 | *pc = extract_address (buf, LONGJMP_TARGET_SIZE); |
| 1772 | |
| 1773 | return 1; |
| 1774 | } |
| 1775 | #endif /* GET_LONGJMP_TARGET */ |
| 1776 | \f |
| 1777 | #ifdef STATIC_TRANSFORM_NAME |
| 1778 | /* SunPRO (3.0 at least), encodes the static variables. This is not |
| 1779 | related to C++ mangling, it is done for C too. */ |
| 1780 | |
| 1781 | char * |
| 1782 | sunpro_static_transform_name (char *name) |
| 1783 | { |
| 1784 | char *p; |
| 1785 | if (name[0] == '$') |
| 1786 | { |
| 1787 | /* For file-local statics there will be a dollar sign, a bunch |
| 1788 | of junk (the contents of which match a string given in the |
| 1789 | N_OPT), a period and the name. For function-local statics |
| 1790 | there will be a bunch of junk (which seems to change the |
| 1791 | second character from 'A' to 'B'), a period, the name of the |
| 1792 | function, and the name. So just skip everything before the |
| 1793 | last period. */ |
| 1794 | p = strrchr (name, '.'); |
| 1795 | if (p != NULL) |
| 1796 | name = p + 1; |
| 1797 | } |
| 1798 | return name; |
| 1799 | } |
| 1800 | #endif /* STATIC_TRANSFORM_NAME */ |
| 1801 | \f |
| 1802 | |
| 1803 | /* Utilities for printing registers. |
| 1804 | Page numbers refer to the SPARC Architecture Manual. */ |
| 1805 | |
| 1806 | static void dump_ccreg (char *, int); |
| 1807 | |
| 1808 | static void |
| 1809 | dump_ccreg (char *reg, int val) |
| 1810 | { |
| 1811 | /* page 41 */ |
| 1812 | printf_unfiltered ("%s:%s,%s,%s,%s", reg, |
| 1813 | val & 8 ? "N" : "NN", |
| 1814 | val & 4 ? "Z" : "NZ", |
| 1815 | val & 2 ? "O" : "NO", |
| 1816 | val & 1 ? "C" : "NC"); |
| 1817 | } |
| 1818 | |
| 1819 | static char * |
| 1820 | decode_asi (int val) |
| 1821 | { |
| 1822 | /* page 72 */ |
| 1823 | switch (val) |
| 1824 | { |
| 1825 | case 4: |
| 1826 | return "ASI_NUCLEUS"; |
| 1827 | case 0x0c: |
| 1828 | return "ASI_NUCLEUS_LITTLE"; |
| 1829 | case 0x10: |
| 1830 | return "ASI_AS_IF_USER_PRIMARY"; |
| 1831 | case 0x11: |
| 1832 | return "ASI_AS_IF_USER_SECONDARY"; |
| 1833 | case 0x18: |
| 1834 | return "ASI_AS_IF_USER_PRIMARY_LITTLE"; |
| 1835 | case 0x19: |
| 1836 | return "ASI_AS_IF_USER_SECONDARY_LITTLE"; |
| 1837 | case 0x80: |
| 1838 | return "ASI_PRIMARY"; |
| 1839 | case 0x81: |
| 1840 | return "ASI_SECONDARY"; |
| 1841 | case 0x82: |
| 1842 | return "ASI_PRIMARY_NOFAULT"; |
| 1843 | case 0x83: |
| 1844 | return "ASI_SECONDARY_NOFAULT"; |
| 1845 | case 0x88: |
| 1846 | return "ASI_PRIMARY_LITTLE"; |
| 1847 | case 0x89: |
| 1848 | return "ASI_SECONDARY_LITTLE"; |
| 1849 | case 0x8a: |
| 1850 | return "ASI_PRIMARY_NOFAULT_LITTLE"; |
| 1851 | case 0x8b: |
| 1852 | return "ASI_SECONDARY_NOFAULT_LITTLE"; |
| 1853 | default: |
| 1854 | return NULL; |
| 1855 | } |
| 1856 | } |
| 1857 | |
| 1858 | /* PRINT_REGISTER_HOOK routine. |
| 1859 | Pretty print various registers. */ |
| 1860 | /* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */ |
| 1861 | |
| 1862 | void |
| 1863 | sparc_print_register_hook (int regno) |
| 1864 | { |
| 1865 | ULONGEST val; |
| 1866 | |
| 1867 | /* Handle double/quad versions of lower 32 fp regs. */ |
| 1868 | if (regno >= FP0_REGNUM && regno < FP0_REGNUM + 32 |
| 1869 | && (regno & 1) == 0) |
| 1870 | { |
| 1871 | char value[16]; |
| 1872 | |
| 1873 | if (frame_register_read (selected_frame, regno, value) |
| 1874 | && frame_register_read (selected_frame, regno + 1, value + 4)) |
| 1875 | { |
| 1876 | printf_unfiltered ("\t"); |
| 1877 | print_floating (value, builtin_type_double, gdb_stdout); |
| 1878 | } |
| 1879 | #if 0 /* FIXME: gdb doesn't handle long doubles */ |
| 1880 | if ((regno & 3) == 0) |
| 1881 | { |
| 1882 | if (frame_register_read (selected_frame, regno + 2, value + 8) |
| 1883 | && frame_register_read (selected_frame, regno + 3, value + 12)) |
| 1884 | { |
| 1885 | printf_unfiltered ("\t"); |
| 1886 | print_floating (value, builtin_type_long_double, gdb_stdout); |
| 1887 | } |
| 1888 | } |
| 1889 | #endif |
| 1890 | return; |
| 1891 | } |
| 1892 | |
| 1893 | #if 0 /* FIXME: gdb doesn't handle long doubles */ |
| 1894 | /* Print upper fp regs as long double if appropriate. */ |
| 1895 | if (regno >= FP0_REGNUM + 32 && regno < FP_MAX_REGNUM |
| 1896 | /* We test for even numbered regs and not a multiple of 4 because |
| 1897 | the upper fp regs are recorded as doubles. */ |
| 1898 | && (regno & 1) == 0) |
| 1899 | { |
| 1900 | char value[16]; |
| 1901 | |
| 1902 | if (frame_register_read (selected_frame, regno, value) |
| 1903 | && frame_register_read (selected_frame, regno + 1, value + 8)) |
| 1904 | { |
| 1905 | printf_unfiltered ("\t"); |
| 1906 | print_floating (value, builtin_type_long_double, gdb_stdout); |
| 1907 | } |
| 1908 | return; |
| 1909 | } |
| 1910 | #endif |
| 1911 | |
| 1912 | /* FIXME: Some of these are priviledged registers. |
| 1913 | Not sure how they should be handled. */ |
| 1914 | |
| 1915 | #define BITS(n, mask) ((int) (((val) >> (n)) & (mask))) |
| 1916 | |
| 1917 | val = read_register (regno); |
| 1918 | |
| 1919 | /* pages 40 - 60 */ |
| 1920 | if (GDB_TARGET_IS_SPARC64) |
| 1921 | switch (regno) |
| 1922 | { |
| 1923 | case CCR_REGNUM: |
| 1924 | printf_unfiltered ("\t"); |
| 1925 | dump_ccreg ("xcc", val >> 4); |
| 1926 | printf_unfiltered (", "); |
| 1927 | dump_ccreg ("icc", val & 15); |
| 1928 | break; |
| 1929 | case FPRS_REGNUM: |
| 1930 | printf ("\tfef:%d, du:%d, dl:%d", |
| 1931 | BITS (2, 1), BITS (1, 1), BITS (0, 1)); |
| 1932 | break; |
| 1933 | case FSR_REGNUM: |
| 1934 | { |
| 1935 | static char *fcc[4] = |
| 1936 | {"=", "<", ">", "?"}; |
| 1937 | static char *rd[4] = |
| 1938 | {"N", "0", "+", "-"}; |
| 1939 | /* Long, but I'd rather leave it as is and use a wide screen. */ |
| 1940 | printf_filtered ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ", |
| 1941 | fcc[BITS (10, 3)], fcc[BITS (32, 3)], |
| 1942 | fcc[BITS (34, 3)], fcc[BITS (36, 3)], |
| 1943 | rd[BITS (30, 3)], BITS (23, 31)); |
| 1944 | printf_filtered ("ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d", |
| 1945 | BITS (22, 1), BITS (17, 7), BITS (14, 7), |
| 1946 | BITS (13, 1), BITS (5, 31), BITS (0, 31)); |
| 1947 | break; |
| 1948 | } |
| 1949 | case ASI_REGNUM: |
| 1950 | { |
| 1951 | char *asi = decode_asi (val); |
| 1952 | if (asi != NULL) |
| 1953 | printf ("\t%s", asi); |
| 1954 | break; |
| 1955 | } |
| 1956 | case VER_REGNUM: |
| 1957 | printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d", |
| 1958 | BITS (48, 0xffff), BITS (32, 0xffff), |
| 1959 | BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31)); |
| 1960 | break; |
| 1961 | case PSTATE_REGNUM: |
| 1962 | { |
| 1963 | static char *mm[4] = |
| 1964 | {"tso", "pso", "rso", "?"}; |
| 1965 | printf_filtered ("\tcle:%d, tle:%d, mm:%s, red:%d, ", |
| 1966 | BITS (9, 1), BITS (8, 1), |
| 1967 | mm[BITS (6, 3)], BITS (5, 1)); |
| 1968 | printf_filtered ("pef:%d, am:%d, priv:%d, ie:%d, ag:%d", |
| 1969 | BITS (4, 1), BITS (3, 1), BITS (2, 1), |
| 1970 | BITS (1, 1), BITS (0, 1)); |
| 1971 | break; |
| 1972 | } |
| 1973 | case TSTATE_REGNUM: |
| 1974 | /* FIXME: print all 4? */ |
| 1975 | break; |
| 1976 | case TT_REGNUM: |
| 1977 | /* FIXME: print all 4? */ |
| 1978 | break; |
| 1979 | case TPC_REGNUM: |
| 1980 | /* FIXME: print all 4? */ |
| 1981 | break; |
| 1982 | case TNPC_REGNUM: |
| 1983 | /* FIXME: print all 4? */ |
| 1984 | break; |
| 1985 | case WSTATE_REGNUM: |
| 1986 | printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7)); |
| 1987 | break; |
| 1988 | case CWP_REGNUM: |
| 1989 | printf ("\t%d", BITS (0, 31)); |
| 1990 | break; |
| 1991 | case CANSAVE_REGNUM: |
| 1992 | printf ("\t%-2d before spill", BITS (0, 31)); |
| 1993 | break; |
| 1994 | case CANRESTORE_REGNUM: |
| 1995 | printf ("\t%-2d before fill", BITS (0, 31)); |
| 1996 | break; |
| 1997 | case CLEANWIN_REGNUM: |
| 1998 | printf ("\t%-2d before clean", BITS (0, 31)); |
| 1999 | break; |
| 2000 | case OTHERWIN_REGNUM: |
| 2001 | printf ("\t%d", BITS (0, 31)); |
| 2002 | break; |
| 2003 | } |
| 2004 | else /* Sparc32 */ |
| 2005 | switch (regno) |
| 2006 | { |
| 2007 | case PS_REGNUM: |
| 2008 | printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d", |
| 2009 | BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-', |
| 2010 | BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-', |
| 2011 | BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1), |
| 2012 | BITS (0, 31)); |
| 2013 | break; |
| 2014 | case FPS_REGNUM: |
| 2015 | { |
| 2016 | static char *fcc[4] = |
| 2017 | {"=", "<", ">", "?"}; |
| 2018 | static char *rd[4] = |
| 2019 | {"N", "0", "+", "-"}; |
| 2020 | /* Long, but I'd rather leave it as is and use a wide screen. */ |
| 2021 | printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, " |
| 2022 | "fcc:%s, aexc:%d, cexc:%d", |
| 2023 | rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7), |
| 2024 | BITS (14, 7), BITS (13, 1), fcc[BITS (10, 3)], BITS (5, 31), |
| 2025 | BITS (0, 31)); |
| 2026 | break; |
| 2027 | } |
| 2028 | } |
| 2029 | |
| 2030 | #undef BITS |
| 2031 | } |
| 2032 | \f |
| 2033 | int |
| 2034 | gdb_print_insn_sparc (bfd_vma memaddr, disassemble_info *info) |
| 2035 | { |
| 2036 | /* It's necessary to override mach again because print_insn messes it up. */ |
| 2037 | info->mach = TARGET_ARCHITECTURE->mach; |
| 2038 | return print_insn_sparc (memaddr, info); |
| 2039 | } |
| 2040 | \f |
| 2041 | /* The SPARC passes the arguments on the stack; arguments smaller |
| 2042 | than an int are promoted to an int. The first 6 words worth of |
| 2043 | args are also passed in registers o0 - o5. */ |
| 2044 | |
| 2045 | CORE_ADDR |
| 2046 | sparc32_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
| 2047 | int struct_return, CORE_ADDR struct_addr) |
| 2048 | { |
| 2049 | int i, j, oregnum; |
| 2050 | int accumulate_size = 0; |
| 2051 | struct sparc_arg |
| 2052 | { |
| 2053 | char *contents; |
| 2054 | int len; |
| 2055 | int offset; |
| 2056 | }; |
| 2057 | struct sparc_arg *sparc_args = |
| 2058 | (struct sparc_arg *) alloca (nargs * sizeof (struct sparc_arg)); |
| 2059 | struct sparc_arg *m_arg; |
| 2060 | |
| 2061 | /* Promote arguments if necessary, and calculate their stack offsets |
| 2062 | and sizes. */ |
| 2063 | for (i = 0, m_arg = sparc_args; i < nargs; i++, m_arg++) |
| 2064 | { |
| 2065 | struct value *arg = args[i]; |
| 2066 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
| 2067 | /* Cast argument to long if necessary as the compiler does it too. */ |
| 2068 | switch (TYPE_CODE (arg_type)) |
| 2069 | { |
| 2070 | case TYPE_CODE_INT: |
| 2071 | case TYPE_CODE_BOOL: |
| 2072 | case TYPE_CODE_CHAR: |
| 2073 | case TYPE_CODE_RANGE: |
| 2074 | case TYPE_CODE_ENUM: |
| 2075 | if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long)) |
| 2076 | { |
| 2077 | arg_type = builtin_type_long; |
| 2078 | arg = value_cast (arg_type, arg); |
| 2079 | } |
| 2080 | break; |
| 2081 | default: |
| 2082 | break; |
| 2083 | } |
| 2084 | m_arg->len = TYPE_LENGTH (arg_type); |
| 2085 | m_arg->offset = accumulate_size; |
| 2086 | accumulate_size = (accumulate_size + m_arg->len + 3) & ~3; |
| 2087 | m_arg->contents = VALUE_CONTENTS (arg); |
| 2088 | } |
| 2089 | |
| 2090 | /* Make room for the arguments on the stack. */ |
| 2091 | accumulate_size += CALL_DUMMY_STACK_ADJUST; |
| 2092 | sp = ((sp - accumulate_size) & ~7) + CALL_DUMMY_STACK_ADJUST; |
| 2093 | |
| 2094 | /* `Push' arguments on the stack. */ |
| 2095 | for (i = 0, oregnum = 0, m_arg = sparc_args; |
| 2096 | i < nargs; |
| 2097 | i++, m_arg++) |
| 2098 | { |
| 2099 | write_memory (sp + m_arg->offset, m_arg->contents, m_arg->len); |
| 2100 | for (j = 0; |
| 2101 | j < m_arg->len && oregnum < 6; |
| 2102 | j += SPARC_INTREG_SIZE, oregnum++) |
| 2103 | write_register_gen (O0_REGNUM + oregnum, m_arg->contents + j); |
| 2104 | } |
| 2105 | |
| 2106 | return sp; |
| 2107 | } |
| 2108 | |
| 2109 | |
| 2110 | /* Extract from an array REGBUF containing the (raw) register state |
| 2111 | a function return value of type TYPE, and copy that, in virtual format, |
| 2112 | into VALBUF. */ |
| 2113 | |
| 2114 | void |
| 2115 | sparc32_extract_return_value (struct type *type, char *regbuf, char *valbuf) |
| 2116 | { |
| 2117 | int typelen = TYPE_LENGTH (type); |
| 2118 | int regsize = REGISTER_RAW_SIZE (O0_REGNUM); |
| 2119 | |
| 2120 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) |
| 2121 | memcpy (valbuf, ®buf[REGISTER_BYTE (FP0_REGNUM)], typelen); |
| 2122 | else |
| 2123 | memcpy (valbuf, |
| 2124 | ®buf[O0_REGNUM * regsize + |
| 2125 | (typelen >= regsize |
| 2126 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE ? 0 |
| 2127 | : regsize - typelen)], |
| 2128 | typelen); |
| 2129 | } |
| 2130 | |
| 2131 | |
| 2132 | /* Write into appropriate registers a function return value |
| 2133 | of type TYPE, given in virtual format. On SPARCs with FPUs, |
| 2134 | float values are returned in %f0 (and %f1). In all other cases, |
| 2135 | values are returned in register %o0. */ |
| 2136 | |
| 2137 | void |
| 2138 | sparc_store_return_value (struct type *type, char *valbuf) |
| 2139 | { |
| 2140 | int regno; |
| 2141 | char *buffer; |
| 2142 | |
| 2143 | buffer = alloca (MAX_REGISTER_RAW_SIZE); |
| 2144 | |
| 2145 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) |
| 2146 | /* Floating-point values are returned in the register pair */ |
| 2147 | /* formed by %f0 and %f1 (doubles are, anyway). */ |
| 2148 | regno = FP0_REGNUM; |
| 2149 | else |
| 2150 | /* Other values are returned in register %o0. */ |
| 2151 | regno = O0_REGNUM; |
| 2152 | |
| 2153 | /* Add leading zeros to the value. */ |
| 2154 | if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (regno)) |
| 2155 | { |
| 2156 | memset (buffer, 0, REGISTER_RAW_SIZE (regno)); |
| 2157 | memcpy (buffer + REGISTER_RAW_SIZE (regno) - TYPE_LENGTH (type), valbuf, |
| 2158 | TYPE_LENGTH (type)); |
| 2159 | write_register_gen (regno, buffer); |
| 2160 | } |
| 2161 | else |
| 2162 | write_register_bytes (REGISTER_BYTE (regno), valbuf, TYPE_LENGTH (type)); |
| 2163 | } |
| 2164 | |
| 2165 | extern void |
| 2166 | sparclet_store_return_value (struct type *type, char *valbuf) |
| 2167 | { |
| 2168 | /* Other values are returned in register %o0. */ |
| 2169 | write_register_bytes (REGISTER_BYTE (O0_REGNUM), valbuf, |
| 2170 | TYPE_LENGTH (type)); |
| 2171 | } |
| 2172 | |
| 2173 | |
| 2174 | #ifndef CALL_DUMMY_CALL_OFFSET |
| 2175 | #define CALL_DUMMY_CALL_OFFSET \ |
| 2176 | (gdbarch_tdep (current_gdbarch)->call_dummy_call_offset) |
| 2177 | #endif /* CALL_DUMMY_CALL_OFFSET */ |
| 2178 | |
| 2179 | /* Insert the function address into a call dummy instruction sequence |
| 2180 | stored at DUMMY. |
| 2181 | |
| 2182 | For structs and unions, if the function was compiled with Sun cc, |
| 2183 | it expects 'unimp' after the call. But gcc doesn't use that |
| 2184 | (twisted) convention. So leave a nop there for gcc (FIX_CALL_DUMMY |
| 2185 | can assume it is operating on a pristine CALL_DUMMY, not one that |
| 2186 | has already been customized for a different function). */ |
| 2187 | |
| 2188 | void |
| 2189 | sparc_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, |
| 2190 | struct type *value_type, int using_gcc) |
| 2191 | { |
| 2192 | int i; |
| 2193 | |
| 2194 | /* Store the relative adddress of the target function into the |
| 2195 | 'call' instruction. */ |
| 2196 | store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET, 4, |
| 2197 | (0x40000000 |
| 2198 | | (((fun - (pc + CALL_DUMMY_CALL_OFFSET)) >> 2) |
| 2199 | & 0x3fffffff))); |
| 2200 | |
| 2201 | /* If the called function returns an aggregate value, fill in the UNIMP |
| 2202 | instruction containing the size of the returned aggregate return value, |
| 2203 | which follows the call instruction. |
| 2204 | For details see the SPARC Architecture Manual Version 8, Appendix D.3. |
| 2205 | |
| 2206 | Adjust the call_dummy_breakpoint_offset for the bp_call_dummy breakpoint |
| 2207 | to the proper address in the call dummy, so that `finish' after a stop |
| 2208 | in a call dummy works. |
| 2209 | Tweeking current_gdbarch is not an optimal solution, but the call to |
| 2210 | sparc_fix_call_dummy is immediately followed by a call to run_stack_dummy, |
| 2211 | which is the only function where dummy_breakpoint_offset is actually |
| 2212 | used, if it is non-zero. */ |
| 2213 | if (TYPE_CODE (value_type) == TYPE_CODE_STRUCT |
| 2214 | || TYPE_CODE (value_type) == TYPE_CODE_UNION) |
| 2215 | { |
| 2216 | store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET + 8, 4, |
| 2217 | TYPE_LENGTH (value_type) & 0x1fff); |
| 2218 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 0x30); |
| 2219 | } |
| 2220 | else |
| 2221 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 0x2c); |
| 2222 | |
| 2223 | if (!(GDB_TARGET_IS_SPARC64)) |
| 2224 | { |
| 2225 | /* If this is not a simulator target, change the first four |
| 2226 | instructions of the call dummy to NOPs. Those instructions |
| 2227 | include a 'save' instruction and are designed to work around |
| 2228 | problems with register window flushing in the simulator. */ |
| 2229 | |
| 2230 | if (strcmp (target_shortname, "sim") != 0) |
| 2231 | { |
| 2232 | for (i = 0; i < 4; i++) |
| 2233 | store_unsigned_integer (dummy + (i * 4), 4, 0x01000000); |
| 2234 | } |
| 2235 | } |
| 2236 | |
| 2237 | /* If this is a bi-endian target, GDB has written the call dummy |
| 2238 | in little-endian order. We must byte-swap it back to big-endian. */ |
| 2239 | if (bi_endian) |
| 2240 | { |
| 2241 | for (i = 0; i < CALL_DUMMY_LENGTH; i += 4) |
| 2242 | { |
| 2243 | char tmp = dummy[i]; |
| 2244 | dummy[i] = dummy[i + 3]; |
| 2245 | dummy[i + 3] = tmp; |
| 2246 | tmp = dummy[i + 1]; |
| 2247 | dummy[i + 1] = dummy[i + 2]; |
| 2248 | dummy[i + 2] = tmp; |
| 2249 | } |
| 2250 | } |
| 2251 | } |
| 2252 | |
| 2253 | |
| 2254 | /* Set target byte order based on machine type. */ |
| 2255 | |
| 2256 | static int |
| 2257 | sparc_target_architecture_hook (const bfd_arch_info_type *ap) |
| 2258 | { |
| 2259 | int i, j; |
| 2260 | |
| 2261 | if (ap->mach == bfd_mach_sparc_sparclite_le) |
| 2262 | { |
| 2263 | target_byte_order = BFD_ENDIAN_LITTLE; |
| 2264 | bi_endian = 1; |
| 2265 | } |
| 2266 | else |
| 2267 | bi_endian = 0; |
| 2268 | return 1; |
| 2269 | } |
| 2270 | \f |
| 2271 | |
| 2272 | /* |
| 2273 | * Module "constructor" function. |
| 2274 | */ |
| 2275 | |
| 2276 | static struct gdbarch * sparc_gdbarch_init (struct gdbarch_info info, |
| 2277 | struct gdbarch_list *arches); |
| 2278 | static void sparc_dump_tdep (struct gdbarch *, struct ui_file *); |
| 2279 | |
| 2280 | void |
| 2281 | _initialize_sparc_tdep (void) |
| 2282 | { |
| 2283 | /* Hook us into the gdbarch mechanism. */ |
| 2284 | gdbarch_register (bfd_arch_sparc, sparc_gdbarch_init, sparc_dump_tdep); |
| 2285 | |
| 2286 | tm_print_insn = gdb_print_insn_sparc; |
| 2287 | tm_print_insn_info.mach = TM_PRINT_INSN_MACH; /* Selects sparc/sparclite */ |
| 2288 | target_architecture_hook = sparc_target_architecture_hook; |
| 2289 | } |
| 2290 | |
| 2291 | /* Compensate for stack bias. Note that we currently don't handle |
| 2292 | mixed 32/64 bit code. */ |
| 2293 | |
| 2294 | CORE_ADDR |
| 2295 | sparc64_read_sp (void) |
| 2296 | { |
| 2297 | CORE_ADDR sp = read_register (SP_REGNUM); |
| 2298 | |
| 2299 | if (sp & 1) |
| 2300 | sp += 2047; |
| 2301 | return sp; |
| 2302 | } |
| 2303 | |
| 2304 | CORE_ADDR |
| 2305 | sparc64_read_fp (void) |
| 2306 | { |
| 2307 | CORE_ADDR fp = read_register (FP_REGNUM); |
| 2308 | |
| 2309 | if (fp & 1) |
| 2310 | fp += 2047; |
| 2311 | return fp; |
| 2312 | } |
| 2313 | |
| 2314 | void |
| 2315 | sparc64_write_sp (CORE_ADDR val) |
| 2316 | { |
| 2317 | CORE_ADDR oldsp = read_register (SP_REGNUM); |
| 2318 | if (oldsp & 1) |
| 2319 | write_register (SP_REGNUM, val - 2047); |
| 2320 | else |
| 2321 | write_register (SP_REGNUM, val); |
| 2322 | } |
| 2323 | |
| 2324 | /* The SPARC 64 ABI passes floating-point arguments in FP0 to FP31, |
| 2325 | and all other arguments in O0 to O5. They are also copied onto |
| 2326 | the stack in the correct places. Apparently (empirically), |
| 2327 | structs of less than 16 bytes are passed member-by-member in |
| 2328 | separate registers, but I am unable to figure out the algorithm. |
| 2329 | Some members go in floating point regs, but I don't know which. |
| 2330 | |
| 2331 | FIXME: Handle small structs (less than 16 bytes containing floats). |
| 2332 | |
| 2333 | The counting regimen for using both integer and FP registers |
| 2334 | for argument passing is rather odd -- a single counter is used |
| 2335 | for both; this means that if the arguments alternate between |
| 2336 | int and float, we will waste every other register of both types. */ |
| 2337 | |
| 2338 | CORE_ADDR |
| 2339 | sparc64_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
| 2340 | int struct_return, CORE_ADDR struct_retaddr) |
| 2341 | { |
| 2342 | int i, j, register_counter = 0; |
| 2343 | CORE_ADDR tempsp; |
| 2344 | struct type *sparc_intreg_type = |
| 2345 | TYPE_LENGTH (builtin_type_long) == SPARC_INTREG_SIZE ? |
| 2346 | builtin_type_long : builtin_type_long_long; |
| 2347 | |
| 2348 | sp = (sp & ~(((unsigned long) SPARC_INTREG_SIZE) - 1UL)); |
| 2349 | |
| 2350 | /* Figure out how much space we'll need. */ |
| 2351 | for (i = nargs - 1; i >= 0; i--) |
| 2352 | { |
| 2353 | int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[i]))); |
| 2354 | struct value *copyarg = args[i]; |
| 2355 | int copylen = len; |
| 2356 | |
| 2357 | if (copylen < SPARC_INTREG_SIZE) |
| 2358 | { |
| 2359 | copyarg = value_cast (sparc_intreg_type, copyarg); |
| 2360 | copylen = SPARC_INTREG_SIZE; |
| 2361 | } |
| 2362 | sp -= copylen; |
| 2363 | } |
| 2364 | |
| 2365 | /* Round down. */ |
| 2366 | sp = sp & ~7; |
| 2367 | tempsp = sp; |
| 2368 | |
| 2369 | /* if STRUCT_RETURN, then first argument is the struct return location. */ |
| 2370 | if (struct_return) |
| 2371 | write_register (O0_REGNUM + register_counter++, struct_retaddr); |
| 2372 | |
| 2373 | /* Now write the arguments onto the stack, while writing FP |
| 2374 | arguments into the FP registers, and other arguments into the |
| 2375 | first six 'O' registers. */ |
| 2376 | |
| 2377 | for (i = 0; i < nargs; i++) |
| 2378 | { |
| 2379 | int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[i]))); |
| 2380 | struct value *copyarg = args[i]; |
| 2381 | enum type_code typecode = TYPE_CODE (VALUE_TYPE (args[i])); |
| 2382 | int copylen = len; |
| 2383 | |
| 2384 | if (typecode == TYPE_CODE_INT || |
| 2385 | typecode == TYPE_CODE_BOOL || |
| 2386 | typecode == TYPE_CODE_CHAR || |
| 2387 | typecode == TYPE_CODE_RANGE || |
| 2388 | typecode == TYPE_CODE_ENUM) |
| 2389 | if (len < SPARC_INTREG_SIZE) |
| 2390 | { |
| 2391 | /* Small ints will all take up the size of one intreg on |
| 2392 | the stack. */ |
| 2393 | copyarg = value_cast (sparc_intreg_type, copyarg); |
| 2394 | copylen = SPARC_INTREG_SIZE; |
| 2395 | } |
| 2396 | |
| 2397 | write_memory (tempsp, VALUE_CONTENTS (copyarg), copylen); |
| 2398 | tempsp += copylen; |
| 2399 | |
| 2400 | /* Corner case: Structs consisting of a single float member are floats. |
| 2401 | * FIXME! I don't know about structs containing multiple floats! |
| 2402 | * Structs containing mixed floats and ints are even more weird. |
| 2403 | */ |
| 2404 | |
| 2405 | |
| 2406 | |
| 2407 | /* Separate float args from all other args. */ |
| 2408 | if (typecode == TYPE_CODE_FLT && SPARC_HAS_FPU) |
| 2409 | { |
| 2410 | if (register_counter < 16) |
| 2411 | { |
| 2412 | /* This arg gets copied into a FP register. */ |
| 2413 | int fpreg; |
| 2414 | |
| 2415 | switch (len) { |
| 2416 | case 4: /* Single-precision (float) */ |
| 2417 | fpreg = FP0_REGNUM + 2 * register_counter + 1; |
| 2418 | register_counter += 1; |
| 2419 | break; |
| 2420 | case 8: /* Double-precision (double) */ |
| 2421 | fpreg = FP0_REGNUM + 2 * register_counter; |
| 2422 | register_counter += 1; |
| 2423 | break; |
| 2424 | case 16: /* Quad-precision (long double) */ |
| 2425 | fpreg = FP0_REGNUM + 2 * register_counter; |
| 2426 | register_counter += 2; |
| 2427 | break; |
| 2428 | default: |
| 2429 | internal_error (__FILE__, __LINE__, "bad switch"); |
| 2430 | } |
| 2431 | write_register_bytes (REGISTER_BYTE (fpreg), |
| 2432 | VALUE_CONTENTS (args[i]), |
| 2433 | len); |
| 2434 | } |
| 2435 | } |
| 2436 | else /* all other args go into the first six 'o' registers */ |
| 2437 | { |
| 2438 | for (j = 0; |
| 2439 | j < len && register_counter < 6; |
| 2440 | j += SPARC_INTREG_SIZE) |
| 2441 | { |
| 2442 | int oreg = O0_REGNUM + register_counter; |
| 2443 | |
| 2444 | write_register_gen (oreg, VALUE_CONTENTS (copyarg) + j); |
| 2445 | register_counter += 1; |
| 2446 | } |
| 2447 | } |
| 2448 | } |
| 2449 | return sp; |
| 2450 | } |
| 2451 | |
| 2452 | /* Values <= 32 bytes are returned in o0-o3 (floating-point values are |
| 2453 | returned in f0-f3). */ |
| 2454 | |
| 2455 | void |
| 2456 | sp64_extract_return_value (struct type *type, char *regbuf, char *valbuf, |
| 2457 | int bitoffset) |
| 2458 | { |
| 2459 | int typelen = TYPE_LENGTH (type); |
| 2460 | int regsize = REGISTER_RAW_SIZE (O0_REGNUM); |
| 2461 | |
| 2462 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) |
| 2463 | { |
| 2464 | memcpy (valbuf, ®buf[REGISTER_BYTE (FP0_REGNUM)], typelen); |
| 2465 | return; |
| 2466 | } |
| 2467 | |
| 2468 | if (TYPE_CODE (type) != TYPE_CODE_STRUCT |
| 2469 | || (TYPE_LENGTH (type) > 32)) |
| 2470 | { |
| 2471 | memcpy (valbuf, |
| 2472 | ®buf[O0_REGNUM * regsize + |
| 2473 | (typelen >= regsize ? 0 : regsize - typelen)], |
| 2474 | typelen); |
| 2475 | return; |
| 2476 | } |
| 2477 | else |
| 2478 | { |
| 2479 | char *o0 = ®buf[O0_REGNUM * regsize]; |
| 2480 | char *f0 = ®buf[FP0_REGNUM * regsize]; |
| 2481 | int x; |
| 2482 | |
| 2483 | for (x = 0; x < TYPE_NFIELDS (type); x++) |
| 2484 | { |
| 2485 | struct field *f = &TYPE_FIELDS (type)[x]; |
| 2486 | /* FIXME: We may need to handle static fields here. */ |
| 2487 | int whichreg = (f->loc.bitpos + bitoffset) / 32; |
| 2488 | int remainder = ((f->loc.bitpos + bitoffset) % 32) / 8; |
| 2489 | int where = (f->loc.bitpos + bitoffset) / 8; |
| 2490 | int size = TYPE_LENGTH (f->type); |
| 2491 | int typecode = TYPE_CODE (f->type); |
| 2492 | |
| 2493 | if (typecode == TYPE_CODE_STRUCT) |
| 2494 | { |
| 2495 | sp64_extract_return_value (f->type, |
| 2496 | regbuf, |
| 2497 | valbuf, |
| 2498 | bitoffset + f->loc.bitpos); |
| 2499 | } |
| 2500 | else if (typecode == TYPE_CODE_FLT && SPARC_HAS_FPU) |
| 2501 | { |
| 2502 | memcpy (valbuf + where, &f0[whichreg * 4] + remainder, size); |
| 2503 | } |
| 2504 | else |
| 2505 | { |
| 2506 | memcpy (valbuf + where, &o0[whichreg * 4] + remainder, size); |
| 2507 | } |
| 2508 | } |
| 2509 | } |
| 2510 | } |
| 2511 | |
| 2512 | extern void |
| 2513 | sparc64_extract_return_value (struct type *type, char *regbuf, char *valbuf) |
| 2514 | { |
| 2515 | sp64_extract_return_value (type, regbuf, valbuf, 0); |
| 2516 | } |
| 2517 | |
| 2518 | extern void |
| 2519 | sparclet_extract_return_value (struct type *type, |
| 2520 | char *regbuf, |
| 2521 | char *valbuf) |
| 2522 | { |
| 2523 | regbuf += REGISTER_RAW_SIZE (O0_REGNUM) * 8; |
| 2524 | if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (O0_REGNUM)) |
| 2525 | regbuf += REGISTER_RAW_SIZE (O0_REGNUM) - TYPE_LENGTH (type); |
| 2526 | |
| 2527 | memcpy ((void *) valbuf, regbuf, TYPE_LENGTH (type)); |
| 2528 | } |
| 2529 | |
| 2530 | |
| 2531 | extern CORE_ADDR |
| 2532 | sparc32_stack_align (CORE_ADDR addr) |
| 2533 | { |
| 2534 | return ((addr + 7) & -8); |
| 2535 | } |
| 2536 | |
| 2537 | extern CORE_ADDR |
| 2538 | sparc64_stack_align (CORE_ADDR addr) |
| 2539 | { |
| 2540 | return ((addr + 15) & -16); |
| 2541 | } |
| 2542 | |
| 2543 | extern void |
| 2544 | sparc_print_extra_frame_info (struct frame_info *fi) |
| 2545 | { |
| 2546 | if (fi && fi->extra_info && fi->extra_info->flat) |
| 2547 | printf_filtered (" flat, pc saved at 0x%s, fp saved at 0x%s\n", |
| 2548 | paddr_nz (fi->extra_info->pc_addr), |
| 2549 | paddr_nz (fi->extra_info->fp_addr)); |
| 2550 | } |
| 2551 | |
| 2552 | /* MULTI_ARCH support */ |
| 2553 | |
| 2554 | static const char * |
| 2555 | sparc32_register_name (int regno) |
| 2556 | { |
| 2557 | static char *register_names[] = |
| 2558 | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
| 2559 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", |
| 2560 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", |
| 2561 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", |
| 2562 | |
| 2563 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 2564 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 2565 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 2566 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 2567 | |
| 2568 | "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" |
| 2569 | }; |
| 2570 | |
| 2571 | if (regno < 0 || |
| 2572 | regno >= (sizeof (register_names) / sizeof (register_names[0]))) |
| 2573 | return NULL; |
| 2574 | else |
| 2575 | return register_names[regno]; |
| 2576 | } |
| 2577 | |
| 2578 | static const char * |
| 2579 | sparc64_register_name (int regno) |
| 2580 | { |
| 2581 | static char *register_names[] = |
| 2582 | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
| 2583 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", |
| 2584 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", |
| 2585 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", |
| 2586 | |
| 2587 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 2588 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 2589 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 2590 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 2591 | "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46", |
| 2592 | "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62", |
| 2593 | |
| 2594 | "pc", "npc", "ccr", "fsr", "fprs", "y", "asi", "ver", |
| 2595 | "tick", "pil", "pstate", "tstate", "tba", "tl", "tt", "tpc", |
| 2596 | "tnpc", "wstate", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", |
| 2597 | "asr16", "asr17", "asr18", "asr19", "asr20", "asr21", "asr22", "asr23", |
| 2598 | "asr24", "asr25", "asr26", "asr27", "asr28", "asr29", "asr30", "asr31", |
| 2599 | /* These are here at the end to simplify removing them if we have to. */ |
| 2600 | "icc", "xcc", "fcc0", "fcc1", "fcc2", "fcc3" |
| 2601 | }; |
| 2602 | |
| 2603 | if (regno < 0 || |
| 2604 | regno >= (sizeof (register_names) / sizeof (register_names[0]))) |
| 2605 | return NULL; |
| 2606 | else |
| 2607 | return register_names[regno]; |
| 2608 | } |
| 2609 | |
| 2610 | static const char * |
| 2611 | sparclite_register_name (int regno) |
| 2612 | { |
| 2613 | static char *register_names[] = |
| 2614 | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
| 2615 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", |
| 2616 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", |
| 2617 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", |
| 2618 | |
| 2619 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 2620 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 2621 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 2622 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 2623 | |
| 2624 | "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr", |
| 2625 | "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr" |
| 2626 | }; |
| 2627 | |
| 2628 | if (regno < 0 || |
| 2629 | regno >= (sizeof (register_names) / sizeof (register_names[0]))) |
| 2630 | return NULL; |
| 2631 | else |
| 2632 | return register_names[regno]; |
| 2633 | } |
| 2634 | |
| 2635 | static const char * |
| 2636 | sparclet_register_name (int regno) |
| 2637 | { |
| 2638 | static char *register_names[] = |
| 2639 | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
| 2640 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", |
| 2641 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", |
| 2642 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", |
| 2643 | |
| 2644 | "", "", "", "", "", "", "", "", /* no floating point registers */ |
| 2645 | "", "", "", "", "", "", "", "", |
| 2646 | "", "", "", "", "", "", "", "", |
| 2647 | "", "", "", "", "", "", "", "", |
| 2648 | |
| 2649 | "y", "psr", "wim", "tbr", "pc", "npc", "", "", /* no FPSR or CPSR */ |
| 2650 | "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "", |
| 2651 | |
| 2652 | /* ASR15 ASR19 (don't display them) */ |
| 2653 | "asr1", "", "asr17", "asr18", "", "asr20", "asr21", "asr22" |
| 2654 | /* None of the rest get displayed */ |
| 2655 | #if 0 |
| 2656 | "awr0", "awr1", "awr2", "awr3", "awr4", "awr5", "awr6", "awr7", |
| 2657 | "awr8", "awr9", "awr10", "awr11", "awr12", "awr13", "awr14", "awr15", |
| 2658 | "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23", |
| 2659 | "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31", |
| 2660 | "apsr" |
| 2661 | #endif /* 0 */ |
| 2662 | }; |
| 2663 | |
| 2664 | if (regno < 0 || |
| 2665 | regno >= (sizeof (register_names) / sizeof (register_names[0]))) |
| 2666 | return NULL; |
| 2667 | else |
| 2668 | return register_names[regno]; |
| 2669 | } |
| 2670 | |
| 2671 | CORE_ADDR |
| 2672 | sparc_push_return_address (CORE_ADDR pc_unused, CORE_ADDR sp) |
| 2673 | { |
| 2674 | if (CALL_DUMMY_LOCATION == AT_ENTRY_POINT) |
| 2675 | { |
| 2676 | /* The return PC of the dummy_frame is the former 'current' PC |
| 2677 | (where we were before we made the target function call). |
| 2678 | This is saved in %i7 by push_dummy_frame. |
| 2679 | |
| 2680 | We will save the 'call dummy location' (ie. the address |
| 2681 | to which the target function will return) in %o7. |
| 2682 | This address will actually be the program's entry point. |
| 2683 | There will be a special call_dummy breakpoint there. */ |
| 2684 | |
| 2685 | write_register (O7_REGNUM, |
| 2686 | CALL_DUMMY_ADDRESS () - 8); |
| 2687 | } |
| 2688 | |
| 2689 | return sp; |
| 2690 | } |
| 2691 | |
| 2692 | /* Should call_function allocate stack space for a struct return? */ |
| 2693 | |
| 2694 | static int |
| 2695 | sparc64_use_struct_convention (int gcc_p, struct type *type) |
| 2696 | { |
| 2697 | return (TYPE_LENGTH (type) > 32); |
| 2698 | } |
| 2699 | |
| 2700 | /* Store the address of the place in which to copy the structure the |
| 2701 | subroutine will return. This is called from call_function_by_hand. |
| 2702 | The ultimate mystery is, tho, what is the value "16"? |
| 2703 | |
| 2704 | MVS: That's the offset from where the sp is now, to where the |
| 2705 | subroutine is gonna expect to find the struct return address. */ |
| 2706 | |
| 2707 | static void |
| 2708 | sparc32_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
| 2709 | { |
| 2710 | char *val; |
| 2711 | CORE_ADDR o7; |
| 2712 | |
| 2713 | val = alloca (SPARC_INTREG_SIZE); |
| 2714 | store_unsigned_integer (val, SPARC_INTREG_SIZE, addr); |
| 2715 | write_memory (sp + (16 * SPARC_INTREG_SIZE), val, SPARC_INTREG_SIZE); |
| 2716 | |
| 2717 | if (CALL_DUMMY_LOCATION == AT_ENTRY_POINT) |
| 2718 | { |
| 2719 | /* Now adjust the value of the link register, which was previously |
| 2720 | stored by push_return_address. Functions that return structs are |
| 2721 | peculiar in that they return to link register + 12, rather than |
| 2722 | link register + 8. */ |
| 2723 | |
| 2724 | o7 = read_register (O7_REGNUM); |
| 2725 | write_register (O7_REGNUM, o7 - 4); |
| 2726 | } |
| 2727 | } |
| 2728 | |
| 2729 | static void |
| 2730 | sparc64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
| 2731 | { |
| 2732 | /* FIXME: V9 uses %o0 for this. */ |
| 2733 | /* FIXME MVS: Only for small enough structs!!! */ |
| 2734 | |
| 2735 | target_write_memory (sp + (16 * SPARC_INTREG_SIZE), |
| 2736 | (char *) &addr, SPARC_INTREG_SIZE); |
| 2737 | #if 0 |
| 2738 | if (CALL_DUMMY_LOCATION == AT_ENTRY_POINT) |
| 2739 | { |
| 2740 | /* Now adjust the value of the link register, which was previously |
| 2741 | stored by push_return_address. Functions that return structs are |
| 2742 | peculiar in that they return to link register + 12, rather than |
| 2743 | link register + 8. */ |
| 2744 | |
| 2745 | write_register (O7_REGNUM, read_register (O7_REGNUM) - 4); |
| 2746 | } |
| 2747 | #endif |
| 2748 | } |
| 2749 | |
| 2750 | /* Default target data type for register REGNO. */ |
| 2751 | |
| 2752 | static struct type * |
| 2753 | sparc32_register_virtual_type (int regno) |
| 2754 | { |
| 2755 | if (regno == PC_REGNUM || |
| 2756 | regno == FP_REGNUM || |
| 2757 | regno == SP_REGNUM) |
| 2758 | return builtin_type_unsigned_int; |
| 2759 | if (regno < 32) |
| 2760 | return builtin_type_int; |
| 2761 | if (regno < 64) |
| 2762 | return builtin_type_float; |
| 2763 | return builtin_type_int; |
| 2764 | } |
| 2765 | |
| 2766 | static struct type * |
| 2767 | sparc64_register_virtual_type (int regno) |
| 2768 | { |
| 2769 | if (regno == PC_REGNUM || |
| 2770 | regno == FP_REGNUM || |
| 2771 | regno == SP_REGNUM) |
| 2772 | return builtin_type_unsigned_long_long; |
| 2773 | if (regno < 32) |
| 2774 | return builtin_type_long_long; |
| 2775 | if (regno < 64) |
| 2776 | return builtin_type_float; |
| 2777 | if (regno < 80) |
| 2778 | return builtin_type_double; |
| 2779 | return builtin_type_long_long; |
| 2780 | } |
| 2781 | |
| 2782 | /* Number of bytes of storage in the actual machine representation for |
| 2783 | register REGNO. */ |
| 2784 | |
| 2785 | static int |
| 2786 | sparc32_register_size (int regno) |
| 2787 | { |
| 2788 | return 4; |
| 2789 | } |
| 2790 | |
| 2791 | static int |
| 2792 | sparc64_register_size (int regno) |
| 2793 | { |
| 2794 | return (regno < 32 ? 8 : regno < 64 ? 4 : 8); |
| 2795 | } |
| 2796 | |
| 2797 | /* Index within the `registers' buffer of the first byte of the space |
| 2798 | for register REGNO. */ |
| 2799 | |
| 2800 | static int |
| 2801 | sparc32_register_byte (int regno) |
| 2802 | { |
| 2803 | return (regno * 4); |
| 2804 | } |
| 2805 | |
| 2806 | static int |
| 2807 | sparc64_register_byte (int regno) |
| 2808 | { |
| 2809 | if (regno < 32) |
| 2810 | return regno * 8; |
| 2811 | else if (regno < 64) |
| 2812 | return 32 * 8 + (regno - 32) * 4; |
| 2813 | else if (regno < 80) |
| 2814 | return 32 * 8 + 32 * 4 + (regno - 64) * 8; |
| 2815 | else |
| 2816 | return 64 * 8 + (regno - 80) * 8; |
| 2817 | } |
| 2818 | |
| 2819 | /* Immediately after a function call, return the saved pc. |
| 2820 | Can't go through the frames for this because on some machines |
| 2821 | the new frame is not set up until the new function executes |
| 2822 | some instructions. */ |
| 2823 | |
| 2824 | static CORE_ADDR |
| 2825 | sparc_saved_pc_after_call (struct frame_info *fi) |
| 2826 | { |
| 2827 | return sparc_pc_adjust (read_register (RP_REGNUM)); |
| 2828 | } |
| 2829 | |
| 2830 | /* Convert registers between 'raw' and 'virtual' formats. |
| 2831 | They are the same on sparc, so there's nothing to do. */ |
| 2832 | |
| 2833 | static void |
| 2834 | sparc_convert_to_virtual (int regnum, struct type *type, char *from, char *to) |
| 2835 | { /* do nothing (should never be called) */ |
| 2836 | } |
| 2837 | |
| 2838 | static void |
| 2839 | sparc_convert_to_raw (struct type *type, int regnum, char *from, char *to) |
| 2840 | { /* do nothing (should never be called) */ |
| 2841 | } |
| 2842 | |
| 2843 | /* Init saved regs: nothing to do, just a place-holder function. */ |
| 2844 | |
| 2845 | static void |
| 2846 | sparc_frame_init_saved_regs (struct frame_info *fi_ignored) |
| 2847 | { /* no-op */ |
| 2848 | } |
| 2849 | |
| 2850 | /* gdbarch fix call dummy: |
| 2851 | All this function does is rearrange the arguments before calling |
| 2852 | sparc_fix_call_dummy (which does the real work). */ |
| 2853 | |
| 2854 | static void |
| 2855 | sparc_gdbarch_fix_call_dummy (char *dummy, |
| 2856 | CORE_ADDR pc, |
| 2857 | CORE_ADDR fun, |
| 2858 | int nargs, |
| 2859 | struct value **args, |
| 2860 | struct type *type, |
| 2861 | int gcc_p) |
| 2862 | { |
| 2863 | if (CALL_DUMMY_LOCATION == ON_STACK) |
| 2864 | sparc_fix_call_dummy (dummy, pc, fun, type, gcc_p); |
| 2865 | } |
| 2866 | |
| 2867 | /* Coerce float to double: a no-op. */ |
| 2868 | |
| 2869 | static int |
| 2870 | sparc_coerce_float_to_double (struct type *formal, struct type *actual) |
| 2871 | { |
| 2872 | return 1; |
| 2873 | } |
| 2874 | |
| 2875 | /* CALL_DUMMY_ADDRESS: fetch the breakpoint address for a call dummy. */ |
| 2876 | |
| 2877 | static CORE_ADDR |
| 2878 | sparc_call_dummy_address (void) |
| 2879 | { |
| 2880 | return (CALL_DUMMY_START_OFFSET) + CALL_DUMMY_BREAKPOINT_OFFSET; |
| 2881 | } |
| 2882 | |
| 2883 | /* Supply the Y register number to those that need it. */ |
| 2884 | |
| 2885 | int |
| 2886 | sparc_y_regnum (void) |
| 2887 | { |
| 2888 | return gdbarch_tdep (current_gdbarch)->y_regnum; |
| 2889 | } |
| 2890 | |
| 2891 | int |
| 2892 | sparc_reg_struct_has_addr (int gcc_p, struct type *type) |
| 2893 | { |
| 2894 | if (GDB_TARGET_IS_SPARC64) |
| 2895 | return (TYPE_LENGTH (type) > 32); |
| 2896 | else |
| 2897 | return (gcc_p != 1); |
| 2898 | } |
| 2899 | |
| 2900 | int |
| 2901 | sparc_intreg_size (void) |
| 2902 | { |
| 2903 | return SPARC_INTREG_SIZE; |
| 2904 | } |
| 2905 | |
| 2906 | static int |
| 2907 | sparc_return_value_on_stack (struct type *type) |
| 2908 | { |
| 2909 | if (TYPE_CODE (type) == TYPE_CODE_FLT && |
| 2910 | TYPE_LENGTH (type) > 8) |
| 2911 | return 1; |
| 2912 | else |
| 2913 | return 0; |
| 2914 | } |
| 2915 | |
| 2916 | /* |
| 2917 | * Gdbarch "constructor" function. |
| 2918 | */ |
| 2919 | |
| 2920 | #define SPARC32_CALL_DUMMY_ON_STACK |
| 2921 | |
| 2922 | #define SPARC_SP_REGNUM 14 |
| 2923 | #define SPARC_FP_REGNUM 30 |
| 2924 | #define SPARC_FP0_REGNUM 32 |
| 2925 | #define SPARC32_NPC_REGNUM 69 |
| 2926 | #define SPARC32_PC_REGNUM 68 |
| 2927 | #define SPARC32_Y_REGNUM 64 |
| 2928 | #define SPARC64_PC_REGNUM 80 |
| 2929 | #define SPARC64_NPC_REGNUM 81 |
| 2930 | #define SPARC64_Y_REGNUM 85 |
| 2931 | |
| 2932 | static struct gdbarch * |
| 2933 | sparc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 2934 | { |
| 2935 | struct gdbarch *gdbarch; |
| 2936 | struct gdbarch_tdep *tdep; |
| 2937 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
| 2938 | |
| 2939 | static LONGEST call_dummy_32[] = |
| 2940 | { 0xbc100001, 0x9de38000, 0xbc100002, 0xbe100003, |
| 2941 | 0xda03a058, 0xd803a054, 0xd603a050, 0xd403a04c, |
| 2942 | 0xd203a048, 0x40000000, 0xd003a044, 0x01000000, |
| 2943 | 0x91d02001, 0x01000000 |
| 2944 | }; |
| 2945 | static LONGEST call_dummy_64[] = |
| 2946 | { 0x9de3bec0fd3fa7f7LL, 0xf93fa7eff53fa7e7LL, |
| 2947 | 0xf13fa7dfed3fa7d7LL, 0xe93fa7cfe53fa7c7LL, |
| 2948 | 0xe13fa7bfdd3fa7b7LL, 0xd93fa7afd53fa7a7LL, |
| 2949 | 0xd13fa79fcd3fa797LL, 0xc93fa78fc53fa787LL, |
| 2950 | 0xc13fa77fcc3fa777LL, 0xc83fa76fc43fa767LL, |
| 2951 | 0xc03fa75ffc3fa757LL, 0xf83fa74ff43fa747LL, |
| 2952 | 0xf03fa73f01000000LL, 0x0100000001000000LL, |
| 2953 | 0x0100000091580000LL, 0xd027a72b93500000LL, |
| 2954 | 0xd027a72791480000LL, 0xd027a72391400000LL, |
| 2955 | 0xd027a71fda5ba8a7LL, 0xd85ba89fd65ba897LL, |
| 2956 | 0xd45ba88fd25ba887LL, 0x9fc02000d05ba87fLL, |
| 2957 | 0x0100000091d02001LL, 0x0100000001000000LL |
| 2958 | }; |
| 2959 | static LONGEST call_dummy_nil[] = {0}; |
| 2960 | |
| 2961 | /* Try to determine the OS ABI of the object we are loading. */ |
| 2962 | |
| 2963 | if (info.abfd != NULL) |
| 2964 | { |
| 2965 | osabi = gdbarch_lookup_osabi (info.abfd); |
| 2966 | if (osabi == GDB_OSABI_UNKNOWN) |
| 2967 | { |
| 2968 | /* If it's an ELF file, assume it's Solaris. */ |
| 2969 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) |
| 2970 | osabi = GDB_OSABI_SOLARIS; |
| 2971 | } |
| 2972 | } |
| 2973 | |
| 2974 | /* First see if there is already a gdbarch that can satisfy the request. */ |
| 2975 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
| 2976 | arches != NULL; |
| 2977 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) |
| 2978 | { |
| 2979 | /* Make sure the ABI selection matches. */ |
| 2980 | tdep = gdbarch_tdep (arches->gdbarch); |
| 2981 | if (tdep && tdep->osabi == osabi) |
| 2982 | return arches->gdbarch; |
| 2983 | } |
| 2984 | |
| 2985 | /* None found: is the request for a sparc architecture? */ |
| 2986 | if (info.bfd_arch_info->arch != bfd_arch_sparc) |
| 2987 | return NULL; /* No; then it's not for us. */ |
| 2988 | |
| 2989 | /* Yes: create a new gdbarch for the specified machine type. */ |
| 2990 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
| 2991 | gdbarch = gdbarch_alloc (&info, tdep); |
| 2992 | |
| 2993 | tdep->osabi = osabi; |
| 2994 | |
| 2995 | /* First set settings that are common for all sparc architectures. */ |
| 2996 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
| 2997 | set_gdbarch_breakpoint_from_pc (gdbarch, memory_breakpoint_from_pc); |
| 2998 | set_gdbarch_coerce_float_to_double (gdbarch, |
| 2999 | sparc_coerce_float_to_double); |
| 3000 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); |
| 3001 | set_gdbarch_call_dummy_p (gdbarch, 1); |
| 3002 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 1); |
| 3003 | set_gdbarch_decr_pc_after_break (gdbarch, 0); |
| 3004 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 3005 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sparc_extract_struct_value_address); |
| 3006 | set_gdbarch_fix_call_dummy (gdbarch, sparc_gdbarch_fix_call_dummy); |
| 3007 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 3008 | set_gdbarch_fp_regnum (gdbarch, SPARC_FP_REGNUM); |
| 3009 | set_gdbarch_fp0_regnum (gdbarch, SPARC_FP0_REGNUM); |
| 3010 | set_gdbarch_frame_args_address (gdbarch, default_frame_address); |
| 3011 | set_gdbarch_frame_chain (gdbarch, sparc_frame_chain); |
| 3012 | set_gdbarch_frame_init_saved_regs (gdbarch, sparc_frame_init_saved_regs); |
| 3013 | set_gdbarch_frame_locals_address (gdbarch, default_frame_address); |
| 3014 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); |
| 3015 | set_gdbarch_frame_saved_pc (gdbarch, sparc_frame_saved_pc); |
| 3016 | set_gdbarch_frameless_function_invocation (gdbarch, |
| 3017 | frameless_look_for_prologue); |
| 3018 | set_gdbarch_get_saved_register (gdbarch, sparc_get_saved_register); |
| 3019 | set_gdbarch_init_extra_frame_info (gdbarch, sparc_init_extra_frame_info); |
| 3020 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 3021 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 3022 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); |
| 3023 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 3024 | set_gdbarch_max_register_raw_size (gdbarch, 8); |
| 3025 | set_gdbarch_max_register_virtual_size (gdbarch, 8); |
| 3026 | set_gdbarch_pop_frame (gdbarch, sparc_pop_frame); |
| 3027 | set_gdbarch_push_return_address (gdbarch, sparc_push_return_address); |
| 3028 | set_gdbarch_push_dummy_frame (gdbarch, sparc_push_dummy_frame); |
| 3029 | set_gdbarch_read_pc (gdbarch, generic_target_read_pc); |
| 3030 | set_gdbarch_register_convert_to_raw (gdbarch, sparc_convert_to_raw); |
| 3031 | set_gdbarch_register_convert_to_virtual (gdbarch, |
| 3032 | sparc_convert_to_virtual); |
| 3033 | set_gdbarch_register_convertible (gdbarch, |
| 3034 | generic_register_convertible_not); |
| 3035 | set_gdbarch_reg_struct_has_addr (gdbarch, sparc_reg_struct_has_addr); |
| 3036 | set_gdbarch_return_value_on_stack (gdbarch, sparc_return_value_on_stack); |
| 3037 | set_gdbarch_saved_pc_after_call (gdbarch, sparc_saved_pc_after_call); |
| 3038 | set_gdbarch_prologue_frameless_p (gdbarch, sparc_prologue_frameless_p); |
| 3039 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
| 3040 | set_gdbarch_skip_prologue (gdbarch, sparc_skip_prologue); |
| 3041 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); |
| 3042 | set_gdbarch_use_generic_dummy_frames (gdbarch, 0); |
| 3043 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
| 3044 | |
| 3045 | /* |
| 3046 | * Settings that depend only on 32/64 bit word size |
| 3047 | */ |
| 3048 | |
| 3049 | switch (info.bfd_arch_info->mach) |
| 3050 | { |
| 3051 | case bfd_mach_sparc: |
| 3052 | case bfd_mach_sparc_sparclet: |
| 3053 | case bfd_mach_sparc_sparclite: |
| 3054 | case bfd_mach_sparc_v8plus: |
| 3055 | case bfd_mach_sparc_v8plusa: |
| 3056 | case bfd_mach_sparc_sparclite_le: |
| 3057 | /* 32-bit machine types: */ |
| 3058 | |
| 3059 | #ifdef SPARC32_CALL_DUMMY_ON_STACK |
| 3060 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_on_stack); |
| 3061 | set_gdbarch_call_dummy_address (gdbarch, sparc_call_dummy_address); |
| 3062 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0x30); |
| 3063 | set_gdbarch_call_dummy_length (gdbarch, 0x38); |
| 3064 | |
| 3065 | /* NOTE: cagney/2002-04-26: Based from info posted by Peter |
| 3066 | Schauer around Oct '99. Briefly, due to aspects of the SPARC |
| 3067 | ABI, it isn't possible to use ON_STACK with a strictly |
| 3068 | compliant compiler. |
| 3069 | |
| 3070 | Peter Schauer writes ... |
| 3071 | |
| 3072 | No, any call from GDB to a user function returning a |
| 3073 | struct/union will fail miserably. Try this: |
| 3074 | |
| 3075 | *NOINDENT* |
| 3076 | struct x |
| 3077 | { |
| 3078 | int a[4]; |
| 3079 | }; |
| 3080 | |
| 3081 | struct x gx; |
| 3082 | |
| 3083 | struct x |
| 3084 | sret () |
| 3085 | { |
| 3086 | return gx; |
| 3087 | } |
| 3088 | |
| 3089 | main () |
| 3090 | { |
| 3091 | int i; |
| 3092 | for (i = 0; i < 4; i++) |
| 3093 | gx.a[i] = i + 1; |
| 3094 | gx = sret (); |
| 3095 | } |
| 3096 | *INDENT* |
| 3097 | |
| 3098 | Set a breakpoint at the gx = sret () statement, run to it and |
| 3099 | issue a `print sret()'. It will not succed with your |
| 3100 | approach, and I doubt that continuing the program will work |
| 3101 | as well. |
| 3102 | |
| 3103 | For details of the ABI see the Sparc Architecture Manual. I |
| 3104 | have Version 8 (Prentice Hall ISBN 0-13-825001-4) and the |
| 3105 | calling conventions for functions returning aggregate values |
| 3106 | are explained in Appendix D.3. */ |
| 3107 | |
| 3108 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
| 3109 | set_gdbarch_call_dummy_words (gdbarch, call_dummy_32); |
| 3110 | #else |
| 3111 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point); |
| 3112 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); |
| 3113 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); |
| 3114 | set_gdbarch_call_dummy_length (gdbarch, 0); |
| 3115 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); |
| 3116 | set_gdbarch_call_dummy_words (gdbarch, call_dummy_nil); |
| 3117 | #endif |
| 3118 | set_gdbarch_call_dummy_stack_adjust (gdbarch, 68); |
| 3119 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); |
| 3120 | set_gdbarch_frame_args_skip (gdbarch, 68); |
| 3121 | set_gdbarch_function_start_offset (gdbarch, 0); |
| 3122 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 3123 | set_gdbarch_npc_regnum (gdbarch, SPARC32_NPC_REGNUM); |
| 3124 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); |
| 3125 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 3126 | set_gdbarch_push_arguments (gdbarch, sparc32_push_arguments); |
| 3127 | set_gdbarch_read_fp (gdbarch, generic_target_read_fp); |
| 3128 | set_gdbarch_read_sp (gdbarch, generic_target_read_sp); |
| 3129 | |
| 3130 | set_gdbarch_register_byte (gdbarch, sparc32_register_byte); |
| 3131 | set_gdbarch_register_raw_size (gdbarch, sparc32_register_size); |
| 3132 | set_gdbarch_register_size (gdbarch, 4); |
| 3133 | set_gdbarch_register_virtual_size (gdbarch, sparc32_register_size); |
| 3134 | set_gdbarch_register_virtual_type (gdbarch, |
| 3135 | sparc32_register_virtual_type); |
| 3136 | #ifdef SPARC32_CALL_DUMMY_ON_STACK |
| 3137 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (call_dummy_32)); |
| 3138 | #else |
| 3139 | set_gdbarch_sizeof_call_dummy_words (gdbarch, 0); |
| 3140 | #endif |
| 3141 | set_gdbarch_stack_align (gdbarch, sparc32_stack_align); |
| 3142 | set_gdbarch_store_struct_return (gdbarch, sparc32_store_struct_return); |
| 3143 | set_gdbarch_use_struct_convention (gdbarch, |
| 3144 | generic_use_struct_convention); |
| 3145 | set_gdbarch_write_sp (gdbarch, generic_target_write_sp); |
| 3146 | tdep->y_regnum = SPARC32_Y_REGNUM; |
| 3147 | tdep->fp_max_regnum = SPARC_FP0_REGNUM + 32; |
| 3148 | tdep->intreg_size = 4; |
| 3149 | tdep->reg_save_offset = 0x60; |
| 3150 | tdep->call_dummy_call_offset = 0x24; |
| 3151 | break; |
| 3152 | |
| 3153 | case bfd_mach_sparc_v9: |
| 3154 | case bfd_mach_sparc_v9a: |
| 3155 | /* 64-bit machine types: */ |
| 3156 | default: /* Any new machine type is likely to be 64-bit. */ |
| 3157 | |
| 3158 | #ifdef SPARC64_CALL_DUMMY_ON_STACK |
| 3159 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_on_stack); |
| 3160 | set_gdbarch_call_dummy_address (gdbarch, sparc_call_dummy_address); |
| 3161 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 8 * 4); |
| 3162 | set_gdbarch_call_dummy_length (gdbarch, 192); |
| 3163 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
| 3164 | set_gdbarch_call_dummy_start_offset (gdbarch, 148); |
| 3165 | set_gdbarch_call_dummy_words (gdbarch, call_dummy_64); |
| 3166 | #else |
| 3167 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point); |
| 3168 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); |
| 3169 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); |
| 3170 | set_gdbarch_call_dummy_length (gdbarch, 0); |
| 3171 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); |
| 3172 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); |
| 3173 | set_gdbarch_call_dummy_words (gdbarch, call_dummy_nil); |
| 3174 | #endif |
| 3175 | set_gdbarch_call_dummy_stack_adjust (gdbarch, 128); |
| 3176 | set_gdbarch_frame_args_skip (gdbarch, 136); |
| 3177 | set_gdbarch_function_start_offset (gdbarch, 0); |
| 3178 | set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 3179 | set_gdbarch_npc_regnum (gdbarch, SPARC64_NPC_REGNUM); |
| 3180 | set_gdbarch_pc_regnum (gdbarch, SPARC64_PC_REGNUM); |
| 3181 | set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 3182 | set_gdbarch_push_arguments (gdbarch, sparc64_push_arguments); |
| 3183 | /* NOTE different for at_entry */ |
| 3184 | set_gdbarch_read_fp (gdbarch, sparc64_read_fp); |
| 3185 | set_gdbarch_read_sp (gdbarch, sparc64_read_sp); |
| 3186 | /* Some of the registers aren't 64 bits, but it's a lot simpler just |
| 3187 | to assume they all are (since most of them are). */ |
| 3188 | set_gdbarch_register_byte (gdbarch, sparc64_register_byte); |
| 3189 | set_gdbarch_register_raw_size (gdbarch, sparc64_register_size); |
| 3190 | set_gdbarch_register_size (gdbarch, 8); |
| 3191 | set_gdbarch_register_virtual_size (gdbarch, sparc64_register_size); |
| 3192 | set_gdbarch_register_virtual_type (gdbarch, |
| 3193 | sparc64_register_virtual_type); |
| 3194 | #ifdef SPARC64_CALL_DUMMY_ON_STACK |
| 3195 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (call_dummy_64)); |
| 3196 | #else |
| 3197 | set_gdbarch_sizeof_call_dummy_words (gdbarch, 0); |
| 3198 | #endif |
| 3199 | set_gdbarch_stack_align (gdbarch, sparc64_stack_align); |
| 3200 | set_gdbarch_store_struct_return (gdbarch, sparc64_store_struct_return); |
| 3201 | set_gdbarch_use_struct_convention (gdbarch, |
| 3202 | sparc64_use_struct_convention); |
| 3203 | set_gdbarch_write_sp (gdbarch, sparc64_write_sp); |
| 3204 | tdep->y_regnum = SPARC64_Y_REGNUM; |
| 3205 | tdep->fp_max_regnum = SPARC_FP0_REGNUM + 48; |
| 3206 | tdep->intreg_size = 8; |
| 3207 | tdep->reg_save_offset = 0x90; |
| 3208 | tdep->call_dummy_call_offset = 148 + 4 * 5; |
| 3209 | break; |
| 3210 | } |
| 3211 | |
| 3212 | /* |
| 3213 | * Settings that vary per-architecture: |
| 3214 | */ |
| 3215 | |
| 3216 | switch (info.bfd_arch_info->mach) |
| 3217 | { |
| 3218 | case bfd_mach_sparc: |
| 3219 | set_gdbarch_deprecated_extract_return_value (gdbarch, sparc32_extract_return_value); |
| 3220 | set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid); |
| 3221 | set_gdbarch_num_regs (gdbarch, 72); |
| 3222 | set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4); |
| 3223 | set_gdbarch_register_name (gdbarch, sparc32_register_name); |
| 3224 | set_gdbarch_store_return_value (gdbarch, sparc_store_return_value); |
| 3225 | tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ |
| 3226 | tdep->fp_register_bytes = 32 * 4; |
| 3227 | tdep->print_insn_mach = bfd_mach_sparc; |
| 3228 | break; |
| 3229 | case bfd_mach_sparc_sparclet: |
| 3230 | set_gdbarch_deprecated_extract_return_value (gdbarch, sparclet_extract_return_value); |
| 3231 | set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid); |
| 3232 | set_gdbarch_num_regs (gdbarch, 32 + 32 + 8 + 8 + 8); |
| 3233 | set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4 + 8*4); |
| 3234 | set_gdbarch_register_name (gdbarch, sparclet_register_name); |
| 3235 | set_gdbarch_store_return_value (gdbarch, sparclet_store_return_value); |
| 3236 | tdep->has_fpu = 0; /* (all but sparclet and sparclite) */ |
| 3237 | tdep->fp_register_bytes = 0; |
| 3238 | tdep->print_insn_mach = bfd_mach_sparc_sparclet; |
| 3239 | break; |
| 3240 | case bfd_mach_sparc_sparclite: |
| 3241 | set_gdbarch_deprecated_extract_return_value (gdbarch, sparc32_extract_return_value); |
| 3242 | set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid); |
| 3243 | set_gdbarch_num_regs (gdbarch, 80); |
| 3244 | set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4); |
| 3245 | set_gdbarch_register_name (gdbarch, sparclite_register_name); |
| 3246 | set_gdbarch_store_return_value (gdbarch, sparc_store_return_value); |
| 3247 | tdep->has_fpu = 0; /* (all but sparclet and sparclite) */ |
| 3248 | tdep->fp_register_bytes = 0; |
| 3249 | tdep->print_insn_mach = bfd_mach_sparc_sparclite; |
| 3250 | break; |
| 3251 | case bfd_mach_sparc_v8plus: |
| 3252 | set_gdbarch_deprecated_extract_return_value (gdbarch, sparc32_extract_return_value); |
| 3253 | set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid); |
| 3254 | set_gdbarch_num_regs (gdbarch, 72); |
| 3255 | set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4); |
| 3256 | set_gdbarch_register_name (gdbarch, sparc32_register_name); |
| 3257 | set_gdbarch_store_return_value (gdbarch, sparc_store_return_value); |
| 3258 | tdep->print_insn_mach = bfd_mach_sparc; |
| 3259 | tdep->fp_register_bytes = 32 * 4; |
| 3260 | tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ |
| 3261 | break; |
| 3262 | case bfd_mach_sparc_v8plusa: |
| 3263 | set_gdbarch_deprecated_extract_return_value (gdbarch, sparc32_extract_return_value); |
| 3264 | set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid); |
| 3265 | set_gdbarch_num_regs (gdbarch, 72); |
| 3266 | set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4); |
| 3267 | set_gdbarch_register_name (gdbarch, sparc32_register_name); |
| 3268 | set_gdbarch_store_return_value (gdbarch, sparc_store_return_value); |
| 3269 | tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ |
| 3270 | tdep->fp_register_bytes = 32 * 4; |
| 3271 | tdep->print_insn_mach = bfd_mach_sparc; |
| 3272 | break; |
| 3273 | case bfd_mach_sparc_sparclite_le: |
| 3274 | set_gdbarch_deprecated_extract_return_value (gdbarch, sparc32_extract_return_value); |
| 3275 | set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid); |
| 3276 | set_gdbarch_num_regs (gdbarch, 80); |
| 3277 | set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4); |
| 3278 | set_gdbarch_register_name (gdbarch, sparclite_register_name); |
| 3279 | set_gdbarch_store_return_value (gdbarch, sparc_store_return_value); |
| 3280 | tdep->has_fpu = 0; /* (all but sparclet and sparclite) */ |
| 3281 | tdep->fp_register_bytes = 0; |
| 3282 | tdep->print_insn_mach = bfd_mach_sparc_sparclite; |
| 3283 | break; |
| 3284 | case bfd_mach_sparc_v9: |
| 3285 | set_gdbarch_deprecated_extract_return_value (gdbarch, sparc64_extract_return_value); |
| 3286 | set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid); |
| 3287 | set_gdbarch_num_regs (gdbarch, 125); |
| 3288 | set_gdbarch_register_bytes (gdbarch, 32*8 + 32*8 + 45*8); |
| 3289 | set_gdbarch_register_name (gdbarch, sparc64_register_name); |
| 3290 | set_gdbarch_store_return_value (gdbarch, sparc_store_return_value); |
| 3291 | tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ |
| 3292 | tdep->fp_register_bytes = 64 * 4; |
| 3293 | tdep->print_insn_mach = bfd_mach_sparc_v9a; |
| 3294 | break; |
| 3295 | case bfd_mach_sparc_v9a: |
| 3296 | set_gdbarch_deprecated_extract_return_value (gdbarch, sparc64_extract_return_value); |
| 3297 | set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid); |
| 3298 | set_gdbarch_num_regs (gdbarch, 125); |
| 3299 | set_gdbarch_register_bytes (gdbarch, 32*8 + 32*8 + 45*8); |
| 3300 | set_gdbarch_register_name (gdbarch, sparc64_register_name); |
| 3301 | set_gdbarch_store_return_value (gdbarch, sparc_store_return_value); |
| 3302 | tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ |
| 3303 | tdep->fp_register_bytes = 64 * 4; |
| 3304 | tdep->print_insn_mach = bfd_mach_sparc_v9a; |
| 3305 | break; |
| 3306 | } |
| 3307 | |
| 3308 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
| 3309 | gdbarch_init_osabi (info, gdbarch, osabi); |
| 3310 | |
| 3311 | return gdbarch; |
| 3312 | } |
| 3313 | |
| 3314 | static void |
| 3315 | sparc_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) |
| 3316 | { |
| 3317 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 3318 | |
| 3319 | if (tdep == NULL) |
| 3320 | return; |
| 3321 | |
| 3322 | fprintf_unfiltered (file, "sparc_dump_tdep: OS ABI = %s\n", |
| 3323 | gdbarch_osabi_name (tdep->osabi)); |
| 3324 | } |