| 1 | /* Target-dependent code for the SPARC for GDB, the GNU debugger. |
| 2 | Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997 |
| 3 | Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program; if not, write to the Free Software |
| 19 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
| 20 | |
| 21 | /* ??? Support for calling functions from gdb in sparc64 is unfinished. */ |
| 22 | |
| 23 | #include "defs.h" |
| 24 | #include "frame.h" |
| 25 | #include "inferior.h" |
| 26 | #include "obstack.h" |
| 27 | #include "target.h" |
| 28 | #include "value.h" |
| 29 | #include "bfd.h" |
| 30 | #include "gdb_string.h" |
| 31 | |
| 32 | #ifdef USE_PROC_FS |
| 33 | #include <sys/procfs.h> |
| 34 | #endif |
| 35 | |
| 36 | #include "gdbcore.h" |
| 37 | |
| 38 | #if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE) |
| 39 | #define SPARC_HAS_FPU 0 |
| 40 | #else |
| 41 | #define SPARC_HAS_FPU 1 |
| 42 | #endif |
| 43 | |
| 44 | #ifdef GDB_TARGET_IS_SPARC64 |
| 45 | #define FP_REGISTER_BYTES (64 * 4) |
| 46 | #else |
| 47 | #define FP_REGISTER_BYTES (32 * 4) |
| 48 | #endif |
| 49 | |
| 50 | /* If not defined, assume 32 bit sparc. */ |
| 51 | #ifndef FP_MAX_REGNUM |
| 52 | #define FP_MAX_REGNUM (FP0_REGNUM + 32) |
| 53 | #endif |
| 54 | |
| 55 | #define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM)) |
| 56 | |
| 57 | /* From infrun.c */ |
| 58 | extern int stop_after_trap; |
| 59 | |
| 60 | /* We don't store all registers immediately when requested, since they |
| 61 | get sent over in large chunks anyway. Instead, we accumulate most |
| 62 | of the changes and send them over once. "deferred_stores" keeps |
| 63 | track of which sets of registers we have locally-changed copies of, |
| 64 | so we only need send the groups that have changed. */ |
| 65 | |
| 66 | int deferred_stores = 0; /* Cumulates stores we want to do eventually. */ |
| 67 | |
| 68 | |
| 69 | /* Fetch a single instruction. Even on bi-endian machines |
| 70 | such as sparc86x, instructions are always big-endian. */ |
| 71 | |
| 72 | static unsigned long |
| 73 | fetch_instruction (pc) |
| 74 | CORE_ADDR pc; |
| 75 | { |
| 76 | unsigned long retval; |
| 77 | int i; |
| 78 | unsigned char buf[4]; |
| 79 | |
| 80 | read_memory (pc, buf, sizeof (buf)); |
| 81 | |
| 82 | /* Start at the most significant end of the integer, and work towards |
| 83 | the least significant. */ |
| 84 | retval = 0; |
| 85 | for (i = 0; i < sizeof (buf); ++i) |
| 86 | retval = (retval << 8) | buf[i]; |
| 87 | return retval; |
| 88 | } |
| 89 | |
| 90 | |
| 91 | /* Branches with prediction are treated like their non-predicting cousins. */ |
| 92 | /* FIXME: What about floating point branches? */ |
| 93 | |
| 94 | /* Macros to extract fields from sparc instructions. */ |
| 95 | #define X_OP(i) (((i) >> 30) & 0x3) |
| 96 | #define X_RD(i) (((i) >> 25) & 0x1f) |
| 97 | #define X_A(i) (((i) >> 29) & 1) |
| 98 | #define X_COND(i) (((i) >> 25) & 0xf) |
| 99 | #define X_OP2(i) (((i) >> 22) & 0x7) |
| 100 | #define X_IMM22(i) ((i) & 0x3fffff) |
| 101 | #define X_OP3(i) (((i) >> 19) & 0x3f) |
| 102 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
| 103 | #define X_I(i) (((i) >> 13) & 1) |
| 104 | #define X_IMM13(i) ((i) & 0x1fff) |
| 105 | /* Sign extension macros. */ |
| 106 | #define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000) |
| 107 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
| 108 | #define X_CC(i) (((i) >> 20) & 3) |
| 109 | #define X_P(i) (((i) >> 19) & 1) |
| 110 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
| 111 | #define X_RCOND(i) (((i) >> 25) & 7) |
| 112 | #define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000) |
| 113 | #define X_FCN(i) (((i) >> 25) & 31) |
| 114 | |
| 115 | typedef enum |
| 116 | { |
| 117 | Error, not_branch, bicc, bicca, ba, baa, ticc, ta, |
| 118 | #ifdef GDB_TARGET_IS_SPARC64 |
| 119 | done_retry |
| 120 | #endif |
| 121 | } branch_type; |
| 122 | |
| 123 | /* Simulate single-step ptrace call for sun4. Code written by Gary |
| 124 | Beihl (beihl@mcc.com). */ |
| 125 | |
| 126 | /* npc4 and next_pc describe the situation at the time that the |
| 127 | step-breakpoint was set, not necessary the current value of NPC_REGNUM. */ |
| 128 | static CORE_ADDR next_pc, npc4, target; |
| 129 | static int brknpc4, brktrg; |
| 130 | typedef char binsn_quantum[BREAKPOINT_MAX]; |
| 131 | static binsn_quantum break_mem[3]; |
| 132 | |
| 133 | /* Non-zero if we just simulated a single-step ptrace call. This is |
| 134 | needed because we cannot remove the breakpoints in the inferior |
| 135 | process until after the `wait' in `wait_for_inferior'. Used for |
| 136 | sun4. */ |
| 137 | |
| 138 | int one_stepped; |
| 139 | |
| 140 | static branch_type isbranch PARAMS ((long, CORE_ADDR, CORE_ADDR *)); |
| 141 | |
| 142 | /* single_step() is called just before we want to resume the inferior, |
| 143 | if we want to single-step it but there is no hardware or kernel single-step |
| 144 | support (as on all SPARCs). We find all the possible targets of the |
| 145 | coming instruction and breakpoint them. |
| 146 | |
| 147 | single_step is also called just after the inferior stops. If we had |
| 148 | set up a simulated single-step, we undo our damage. */ |
| 149 | |
| 150 | void |
| 151 | single_step (ignore) |
| 152 | enum target_signal ignore; /* pid, but we don't need it */ |
| 153 | { |
| 154 | branch_type br; |
| 155 | CORE_ADDR pc; |
| 156 | long pc_instruction; |
| 157 | |
| 158 | if (!one_stepped) |
| 159 | { |
| 160 | /* Always set breakpoint for NPC. */ |
| 161 | next_pc = read_register (NPC_REGNUM); |
| 162 | npc4 = next_pc + 4; /* branch not taken */ |
| 163 | |
| 164 | target_insert_breakpoint (next_pc, break_mem[0]); |
| 165 | /* printf_unfiltered ("set break at %x\n",next_pc); */ |
| 166 | |
| 167 | pc = read_register (PC_REGNUM); |
| 168 | pc_instruction = fetch_instruction (pc); |
| 169 | br = isbranch (pc_instruction, pc, &target); |
| 170 | brknpc4 = brktrg = 0; |
| 171 | |
| 172 | if (br == bicca) |
| 173 | { |
| 174 | /* Conditional annulled branch will either end up at |
| 175 | npc (if taken) or at npc+4 (if not taken). |
| 176 | Trap npc+4. */ |
| 177 | brknpc4 = 1; |
| 178 | target_insert_breakpoint (npc4, break_mem[1]); |
| 179 | } |
| 180 | else if (br == baa && target != next_pc) |
| 181 | { |
| 182 | /* Unconditional annulled branch will always end up at |
| 183 | the target. */ |
| 184 | brktrg = 1; |
| 185 | target_insert_breakpoint (target, break_mem[2]); |
| 186 | } |
| 187 | #ifdef GDB_TARGET_IS_SPARC64 |
| 188 | else if (br == done_retry) |
| 189 | { |
| 190 | brktrg = 1; |
| 191 | target_insert_breakpoint (target, break_mem[2]); |
| 192 | } |
| 193 | #endif |
| 194 | |
| 195 | /* We are ready to let it go */ |
| 196 | one_stepped = 1; |
| 197 | return; |
| 198 | } |
| 199 | else |
| 200 | { |
| 201 | /* Remove breakpoints */ |
| 202 | target_remove_breakpoint (next_pc, break_mem[0]); |
| 203 | |
| 204 | if (brknpc4) |
| 205 | target_remove_breakpoint (npc4, break_mem[1]); |
| 206 | |
| 207 | if (brktrg) |
| 208 | target_remove_breakpoint (target, break_mem[2]); |
| 209 | |
| 210 | one_stepped = 0; |
| 211 | } |
| 212 | } |
| 213 | \f |
| 214 | /* Call this for each newly created frame. For SPARC, we need to calculate |
| 215 | the bottom of the frame, and do some extra work if the prologue |
| 216 | has been generated via the -mflat option to GCC. In particular, |
| 217 | we need to know where the previous fp and the pc have been stashed, |
| 218 | since their exact position within the frame may vary. */ |
| 219 | |
| 220 | void |
| 221 | sparc_init_extra_frame_info (fromleaf, fi) |
| 222 | int fromleaf; |
| 223 | struct frame_info *fi; |
| 224 | { |
| 225 | char *name; |
| 226 | CORE_ADDR addr; |
| 227 | int insn; |
| 228 | |
| 229 | fi->bottom = |
| 230 | (fi->next ? |
| 231 | (fi->frame == fi->next->frame ? fi->next->bottom : fi->next->frame) : |
| 232 | read_sp ()); |
| 233 | |
| 234 | /* If fi->next is NULL, then we already set ->frame by passing read_fp() |
| 235 | to create_new_frame. */ |
| 236 | if (fi->next) |
| 237 | { |
| 238 | char buf[MAX_REGISTER_RAW_SIZE]; |
| 239 | |
| 240 | /* Compute ->frame as if not flat. If it is flat, we'll change |
| 241 | it later. */ |
| 242 | if (fi->next->next != NULL |
| 243 | && (fi->next->next->signal_handler_caller |
| 244 | || frame_in_dummy (fi->next->next)) |
| 245 | && frameless_look_for_prologue (fi->next)) |
| 246 | { |
| 247 | /* A frameless function interrupted by a signal did not change |
| 248 | the frame pointer, fix up frame pointer accordingly. */ |
| 249 | fi->frame = FRAME_FP (fi->next); |
| 250 | fi->bottom = fi->next->bottom; |
| 251 | } |
| 252 | else |
| 253 | { |
| 254 | /* Should we adjust for stack bias here? */ |
| 255 | get_saved_register (buf, 0, 0, fi, FP_REGNUM, 0); |
| 256 | fi->frame = extract_address (buf, REGISTER_RAW_SIZE (FP_REGNUM)); |
| 257 | #ifdef GDB_TARGET_IS_SPARC64 |
| 258 | if (fi->frame & 1) |
| 259 | fi->frame += 2047; |
| 260 | #endif |
| 261 | |
| 262 | } |
| 263 | } |
| 264 | |
| 265 | /* Decide whether this is a function with a ``flat register window'' |
| 266 | frame. For such functions, the frame pointer is actually in %i7. */ |
| 267 | fi->flat = 0; |
| 268 | if (find_pc_partial_function (fi->pc, &name, &addr, NULL)) |
| 269 | { |
| 270 | /* See if the function starts with an add (which will be of a |
| 271 | negative number if a flat frame) to the sp. FIXME: Does not |
| 272 | handle large frames which will need more than one instruction |
| 273 | to adjust the sp. */ |
| 274 | insn = fetch_instruction (addr); |
| 275 | if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0 |
| 276 | && X_I (insn) && X_SIMM13 (insn) < 0) |
| 277 | { |
| 278 | int offset = X_SIMM13 (insn); |
| 279 | |
| 280 | /* Then look for a save of %i7 into the frame. */ |
| 281 | insn = fetch_instruction (addr + 4); |
| 282 | if (X_OP (insn) == 3 |
| 283 | && X_RD (insn) == 31 |
| 284 | && X_OP3 (insn) == 4 |
| 285 | && X_RS1 (insn) == 14) |
| 286 | { |
| 287 | char buf[MAX_REGISTER_RAW_SIZE]; |
| 288 | |
| 289 | /* We definitely have a flat frame now. */ |
| 290 | fi->flat = 1; |
| 291 | |
| 292 | fi->sp_offset = offset; |
| 293 | |
| 294 | /* Overwrite the frame's address with the value in %i7. */ |
| 295 | get_saved_register (buf, 0, 0, fi, I7_REGNUM, 0); |
| 296 | fi->frame = extract_address (buf, REGISTER_RAW_SIZE (I7_REGNUM)); |
| 297 | #ifdef GDB_TARGET_IS_SPARC64 |
| 298 | if (fi->frame & 1) |
| 299 | fi->frame += 2047; |
| 300 | #endif |
| 301 | /* Record where the fp got saved. */ |
| 302 | fi->fp_addr = fi->frame + fi->sp_offset + X_SIMM13 (insn); |
| 303 | |
| 304 | /* Also try to collect where the pc got saved to. */ |
| 305 | fi->pc_addr = 0; |
| 306 | insn = fetch_instruction (addr + 12); |
| 307 | if (X_OP (insn) == 3 |
| 308 | && X_RD (insn) == 15 |
| 309 | && X_OP3 (insn) == 4 |
| 310 | && X_RS1 (insn) == 14) |
| 311 | fi->pc_addr = fi->frame + fi->sp_offset + X_SIMM13 (insn); |
| 312 | } |
| 313 | } |
| 314 | } |
| 315 | if (fi->next && fi->frame == 0) |
| 316 | { |
| 317 | /* Kludge to cause init_prev_frame_info to destroy the new frame. */ |
| 318 | fi->frame = fi->next->frame; |
| 319 | fi->pc = fi->next->pc; |
| 320 | } |
| 321 | } |
| 322 | |
| 323 | CORE_ADDR |
| 324 | sparc_frame_chain (frame) |
| 325 | struct frame_info *frame; |
| 326 | { |
| 327 | /* Value that will cause FRAME_CHAIN_VALID to not worry about the chain |
| 328 | value. If it realy is zero, we detect it later in |
| 329 | sparc_init_prev_frame. */ |
| 330 | return (CORE_ADDR)1; |
| 331 | } |
| 332 | |
| 333 | CORE_ADDR |
| 334 | sparc_extract_struct_value_address (regbuf) |
| 335 | char regbuf[REGISTER_BYTES]; |
| 336 | { |
| 337 | #ifdef GDB_TARGET_IS_SPARC64 |
| 338 | return extract_address (regbuf + REGISTER_BYTE (O0_REGNUM), |
| 339 | REGISTER_RAW_SIZE (O0_REGNUM)); |
| 340 | #else |
| 341 | CORE_ADDR sp = extract_address (®buf [REGISTER_BYTE (SP_REGNUM)], |
| 342 | REGISTER_RAW_SIZE (SP_REGNUM)); |
| 343 | return read_memory_integer (sp + (16 * SPARC_INTREG_SIZE), |
| 344 | TARGET_PTR_BIT / TARGET_CHAR_BIT); |
| 345 | #endif |
| 346 | } |
| 347 | |
| 348 | /* Find the pc saved in frame FRAME. */ |
| 349 | |
| 350 | CORE_ADDR |
| 351 | sparc_frame_saved_pc (frame) |
| 352 | struct frame_info *frame; |
| 353 | { |
| 354 | char buf[MAX_REGISTER_RAW_SIZE]; |
| 355 | CORE_ADDR addr; |
| 356 | |
| 357 | if (frame->signal_handler_caller) |
| 358 | { |
| 359 | /* This is the signal trampoline frame. |
| 360 | Get the saved PC from the sigcontext structure. */ |
| 361 | |
| 362 | #ifndef SIGCONTEXT_PC_OFFSET |
| 363 | #define SIGCONTEXT_PC_OFFSET 12 |
| 364 | #endif |
| 365 | |
| 366 | CORE_ADDR sigcontext_addr; |
| 367 | char scbuf[TARGET_PTR_BIT / HOST_CHAR_BIT]; |
| 368 | int saved_pc_offset = SIGCONTEXT_PC_OFFSET; |
| 369 | char *name = NULL; |
| 370 | |
| 371 | /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext |
| 372 | as the third parameter. The offset to the saved pc is 12. */ |
| 373 | find_pc_partial_function (frame->pc, &name, |
| 374 | (CORE_ADDR *)NULL,(CORE_ADDR *)NULL); |
| 375 | if (name && STREQ (name, "ucbsigvechandler")) |
| 376 | saved_pc_offset = 12; |
| 377 | |
| 378 | /* The sigcontext address is contained in register O2. */ |
| 379 | get_saved_register (buf, (int *)NULL, (CORE_ADDR *)NULL, |
| 380 | frame, O0_REGNUM + 2, (enum lval_type *)NULL); |
| 381 | sigcontext_addr = extract_address (buf, REGISTER_RAW_SIZE (O0_REGNUM + 2)); |
| 382 | |
| 383 | /* Don't cause a memory_error when accessing sigcontext in case the |
| 384 | stack layout has changed or the stack is corrupt. */ |
| 385 | target_read_memory (sigcontext_addr + saved_pc_offset, |
| 386 | scbuf, sizeof (scbuf)); |
| 387 | return extract_address (scbuf, sizeof (scbuf)); |
| 388 | } |
| 389 | else if (frame->next != NULL |
| 390 | && (frame->next->signal_handler_caller |
| 391 | || frame_in_dummy (frame->next)) |
| 392 | && frameless_look_for_prologue (frame)) |
| 393 | { |
| 394 | /* A frameless function interrupted by a signal did not save |
| 395 | the PC, it is still in %o7. */ |
| 396 | get_saved_register (buf, (int *)NULL, (CORE_ADDR *)NULL, |
| 397 | frame, O7_REGNUM, (enum lval_type *)NULL); |
| 398 | return PC_ADJUST (extract_address (buf, SPARC_INTREG_SIZE)); |
| 399 | } |
| 400 | if (frame->flat) |
| 401 | addr = frame->pc_addr; |
| 402 | else |
| 403 | addr = frame->bottom + FRAME_SAVED_I0 + |
| 404 | SPARC_INTREG_SIZE * (I7_REGNUM - I0_REGNUM); |
| 405 | |
| 406 | if (addr == 0) |
| 407 | /* A flat frame leaf function might not save the PC anywhere, |
| 408 | just leave it in %o7. */ |
| 409 | return PC_ADJUST (read_register (O7_REGNUM)); |
| 410 | |
| 411 | read_memory (addr, buf, SPARC_INTREG_SIZE); |
| 412 | return PC_ADJUST (extract_address (buf, SPARC_INTREG_SIZE)); |
| 413 | } |
| 414 | |
| 415 | /* Since an individual frame in the frame cache is defined by two |
| 416 | arguments (a frame pointer and a stack pointer), we need two |
| 417 | arguments to get info for an arbitrary stack frame. This routine |
| 418 | takes two arguments and makes the cached frames look as if these |
| 419 | two arguments defined a frame on the cache. This allows the rest |
| 420 | of info frame to extract the important arguments without |
| 421 | difficulty. */ |
| 422 | |
| 423 | struct frame_info * |
| 424 | setup_arbitrary_frame (argc, argv) |
| 425 | int argc; |
| 426 | CORE_ADDR *argv; |
| 427 | { |
| 428 | struct frame_info *frame; |
| 429 | |
| 430 | if (argc != 2) |
| 431 | error ("Sparc frame specifications require two arguments: fp and sp"); |
| 432 | |
| 433 | frame = create_new_frame (argv[0], 0); |
| 434 | |
| 435 | if (!frame) |
| 436 | fatal ("internal: create_new_frame returned invalid frame"); |
| 437 | |
| 438 | frame->bottom = argv[1]; |
| 439 | frame->pc = FRAME_SAVED_PC (frame); |
| 440 | return frame; |
| 441 | } |
| 442 | |
| 443 | /* Given a pc value, skip it forward past the function prologue by |
| 444 | disassembling instructions that appear to be a prologue. |
| 445 | |
| 446 | If FRAMELESS_P is set, we are only testing to see if the function |
| 447 | is frameless. This allows a quicker answer. |
| 448 | |
| 449 | This routine should be more specific in its actions; making sure |
| 450 | that it uses the same register in the initial prologue section. */ |
| 451 | |
| 452 | static CORE_ADDR examine_prologue PARAMS ((CORE_ADDR, int, struct frame_info *, |
| 453 | struct frame_saved_regs *)); |
| 454 | |
| 455 | static CORE_ADDR |
| 456 | examine_prologue (start_pc, frameless_p, fi, saved_regs) |
| 457 | CORE_ADDR start_pc; |
| 458 | int frameless_p; |
| 459 | struct frame_info *fi; |
| 460 | struct frame_saved_regs *saved_regs; |
| 461 | { |
| 462 | int insn; |
| 463 | int dest = -1; |
| 464 | CORE_ADDR pc = start_pc; |
| 465 | int is_flat = 0; |
| 466 | |
| 467 | insn = fetch_instruction (pc); |
| 468 | |
| 469 | /* Recognize the `sethi' insn and record its destination. */ |
| 470 | if (X_OP (insn) == 0 && X_OP2 (insn) == 4) |
| 471 | { |
| 472 | dest = X_RD (insn); |
| 473 | pc += 4; |
| 474 | insn = fetch_instruction (pc); |
| 475 | } |
| 476 | |
| 477 | /* Recognize an add immediate value to register to either %g1 or |
| 478 | the destination register recorded above. Actually, this might |
| 479 | well recognize several different arithmetic operations. |
| 480 | It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1" |
| 481 | followed by "save %sp, %g1, %sp" is a valid prologue (Not that |
| 482 | I imagine any compiler really does that, however). */ |
| 483 | if (X_OP (insn) == 2 |
| 484 | && X_I (insn) |
| 485 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
| 486 | { |
| 487 | pc += 4; |
| 488 | insn = fetch_instruction (pc); |
| 489 | } |
| 490 | |
| 491 | /* Recognize any SAVE insn. */ |
| 492 | if (X_OP (insn) == 2 && X_OP3 (insn) == 60) |
| 493 | { |
| 494 | pc += 4; |
| 495 | if (frameless_p) /* If the save is all we care about, */ |
| 496 | return pc; /* return before doing more work */ |
| 497 | insn = fetch_instruction (pc); |
| 498 | } |
| 499 | /* Recognize add to %sp. */ |
| 500 | else if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0) |
| 501 | { |
| 502 | pc += 4; |
| 503 | if (frameless_p) /* If the add is all we care about, */ |
| 504 | return pc; /* return before doing more work */ |
| 505 | is_flat = 1; |
| 506 | insn = fetch_instruction (pc); |
| 507 | /* Recognize store of frame pointer (i7). */ |
| 508 | if (X_OP (insn) == 3 |
| 509 | && X_RD (insn) == 31 |
| 510 | && X_OP3 (insn) == 4 |
| 511 | && X_RS1 (insn) == 14) |
| 512 | { |
| 513 | pc += 4; |
| 514 | insn = fetch_instruction (pc); |
| 515 | |
| 516 | /* Recognize sub %sp, <anything>, %i7. */ |
| 517 | if (X_OP (insn) == 2 |
| 518 | && X_OP3 (insn) == 4 |
| 519 | && X_RS1 (insn) == 14 |
| 520 | && X_RD (insn) == 31) |
| 521 | { |
| 522 | pc += 4; |
| 523 | insn = fetch_instruction (pc); |
| 524 | } |
| 525 | else |
| 526 | return pc; |
| 527 | } |
| 528 | else |
| 529 | return pc; |
| 530 | } |
| 531 | else |
| 532 | /* Without a save or add instruction, it's not a prologue. */ |
| 533 | return start_pc; |
| 534 | |
| 535 | while (1) |
| 536 | { |
| 537 | /* Recognize stores into the frame from the input registers. |
| 538 | This recognizes all non alternate stores of input register, |
| 539 | into a location offset from the frame pointer. */ |
| 540 | if ((X_OP (insn) == 3 |
| 541 | && (X_OP3 (insn) & 0x3c) == 4 /* Store, non-alternate. */ |
| 542 | && (X_RD (insn) & 0x18) == 0x18 /* Input register. */ |
| 543 | && X_I (insn) /* Immediate mode. */ |
| 544 | && X_RS1 (insn) == 30 /* Off of frame pointer. */ |
| 545 | /* Into reserved stack space. */ |
| 546 | && X_SIMM13 (insn) >= 0x44 |
| 547 | && X_SIMM13 (insn) < 0x5b)) |
| 548 | ; |
| 549 | else if (is_flat |
| 550 | && X_OP (insn) == 3 |
| 551 | && X_OP3 (insn) == 4 |
| 552 | && X_RS1 (insn) == 14 |
| 553 | ) |
| 554 | { |
| 555 | if (saved_regs && X_I (insn)) |
| 556 | saved_regs->regs[X_RD (insn)] = |
| 557 | fi->frame + fi->sp_offset + X_SIMM13 (insn); |
| 558 | } |
| 559 | else |
| 560 | break; |
| 561 | pc += 4; |
| 562 | insn = fetch_instruction (pc); |
| 563 | } |
| 564 | |
| 565 | return pc; |
| 566 | } |
| 567 | |
| 568 | CORE_ADDR |
| 569 | skip_prologue (start_pc, frameless_p) |
| 570 | CORE_ADDR start_pc; |
| 571 | int frameless_p; |
| 572 | { |
| 573 | return examine_prologue (start_pc, frameless_p, NULL, NULL); |
| 574 | } |
| 575 | |
| 576 | /* Check instruction at ADDR to see if it is a branch. |
| 577 | All non-annulled instructions will go to NPC or will trap. |
| 578 | Set *TARGET if we find a candidate branch; set to zero if not. |
| 579 | |
| 580 | This isn't static as it's used by remote-sa.sparc.c. */ |
| 581 | |
| 582 | static branch_type |
| 583 | isbranch (instruction, addr, target) |
| 584 | long instruction; |
| 585 | CORE_ADDR addr, *target; |
| 586 | { |
| 587 | branch_type val = not_branch; |
| 588 | long int offset = 0; /* Must be signed for sign-extend. */ |
| 589 | |
| 590 | *target = 0; |
| 591 | |
| 592 | if (X_OP (instruction) == 0 |
| 593 | && (X_OP2 (instruction) == 2 |
| 594 | || X_OP2 (instruction) == 6 |
| 595 | || X_OP2 (instruction) == 1 |
| 596 | || X_OP2 (instruction) == 3 |
| 597 | || X_OP2 (instruction) == 5 |
| 598 | #ifndef GDB_TARGET_IS_SPARC64 |
| 599 | || X_OP2 (instruction) == 7 |
| 600 | #endif |
| 601 | )) |
| 602 | { |
| 603 | if (X_COND (instruction) == 8) |
| 604 | val = X_A (instruction) ? baa : ba; |
| 605 | else |
| 606 | val = X_A (instruction) ? bicca : bicc; |
| 607 | switch (X_OP2 (instruction)) |
| 608 | { |
| 609 | case 2: |
| 610 | case 6: |
| 611 | #ifndef GDB_TARGET_IS_SPARC64 |
| 612 | case 7: |
| 613 | #endif |
| 614 | offset = 4 * X_DISP22 (instruction); |
| 615 | break; |
| 616 | case 1: |
| 617 | case 5: |
| 618 | offset = 4 * X_DISP19 (instruction); |
| 619 | break; |
| 620 | case 3: |
| 621 | offset = 4 * X_DISP16 (instruction); |
| 622 | break; |
| 623 | } |
| 624 | *target = addr + offset; |
| 625 | } |
| 626 | #ifdef GDB_TARGET_IS_SPARC64 |
| 627 | else if (X_OP (instruction) == 2 |
| 628 | && X_OP3 (instruction) == 62) |
| 629 | { |
| 630 | if (X_FCN (instruction) == 0) |
| 631 | { |
| 632 | /* done */ |
| 633 | *target = read_register (TNPC_REGNUM); |
| 634 | val = done_retry; |
| 635 | } |
| 636 | else if (X_FCN (instruction) == 1) |
| 637 | { |
| 638 | /* retry */ |
| 639 | *target = read_register (TPC_REGNUM); |
| 640 | val = done_retry; |
| 641 | } |
| 642 | } |
| 643 | #endif |
| 644 | |
| 645 | return val; |
| 646 | } |
| 647 | \f |
| 648 | /* Find register number REGNUM relative to FRAME and put its |
| 649 | (raw) contents in *RAW_BUFFER. Set *OPTIMIZED if the variable |
| 650 | was optimized out (and thus can't be fetched). If the variable |
| 651 | was fetched from memory, set *ADDRP to where it was fetched from, |
| 652 | otherwise it was fetched from a register. |
| 653 | |
| 654 | The argument RAW_BUFFER must point to aligned memory. */ |
| 655 | |
| 656 | void |
| 657 | get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval) |
| 658 | char *raw_buffer; |
| 659 | int *optimized; |
| 660 | CORE_ADDR *addrp; |
| 661 | struct frame_info *frame; |
| 662 | int regnum; |
| 663 | enum lval_type *lval; |
| 664 | { |
| 665 | struct frame_info *frame1; |
| 666 | CORE_ADDR addr; |
| 667 | |
| 668 | if (!target_has_registers) |
| 669 | error ("No registers."); |
| 670 | |
| 671 | if (optimized) |
| 672 | *optimized = 0; |
| 673 | |
| 674 | addr = 0; |
| 675 | |
| 676 | /* FIXME This code extracted from infcmd.c; should put elsewhere! */ |
| 677 | if (frame == NULL) |
| 678 | { |
| 679 | /* error ("No selected frame."); */ |
| 680 | if (!target_has_registers) |
| 681 | error ("The program has no registers now."); |
| 682 | if (selected_frame == NULL) |
| 683 | error ("No selected frame."); |
| 684 | /* Try to use selected frame */ |
| 685 | frame = get_prev_frame (selected_frame); |
| 686 | if (frame == 0) |
| 687 | error ("Cmd not meaningful in the outermost frame."); |
| 688 | } |
| 689 | |
| 690 | |
| 691 | frame1 = frame->next; |
| 692 | |
| 693 | /* Get saved PC from the frame info if not in innermost frame. */ |
| 694 | if (regnum == PC_REGNUM && frame1 != NULL) |
| 695 | { |
| 696 | if (lval != NULL) |
| 697 | *lval = not_lval; |
| 698 | if (raw_buffer != NULL) |
| 699 | { |
| 700 | /* Put it back in target format. */ |
| 701 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), frame->pc); |
| 702 | } |
| 703 | if (addrp != NULL) |
| 704 | *addrp = 0; |
| 705 | return; |
| 706 | } |
| 707 | |
| 708 | while (frame1 != NULL) |
| 709 | { |
| 710 | if (frame1->pc >= (frame1->bottom ? frame1->bottom : |
| 711 | read_sp ()) |
| 712 | && frame1->pc <= FRAME_FP (frame1)) |
| 713 | { |
| 714 | /* Dummy frame. All but the window regs are in there somewhere. |
| 715 | The window registers are saved on the stack, just like in a |
| 716 | normal frame. */ |
| 717 | if (regnum >= G1_REGNUM && regnum < G1_REGNUM + 7) |
| 718 | addr = frame1->frame + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE |
| 719 | - (FP_REGISTER_BYTES + 8 * SPARC_INTREG_SIZE); |
| 720 | else if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8) |
| 721 | addr = (frame1->prev->bottom |
| 722 | + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
| 723 | + FRAME_SAVED_I0); |
| 724 | else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8) |
| 725 | addr = (frame1->prev->bottom |
| 726 | + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE |
| 727 | + FRAME_SAVED_L0); |
| 728 | else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8) |
| 729 | addr = frame1->frame + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE |
| 730 | - (FP_REGISTER_BYTES + 16 * SPARC_INTREG_SIZE); |
| 731 | #ifdef FP0_REGNUM |
| 732 | else if (regnum >= FP0_REGNUM && regnum < FP0_REGNUM + 32) |
| 733 | addr = frame1->frame + (regnum - FP0_REGNUM) * 4 |
| 734 | - (FP_REGISTER_BYTES); |
| 735 | #ifdef GDB_TARGET_IS_SPARC64 |
| 736 | else if (regnum >= FP0_REGNUM + 32 && regnum < FP_MAX_REGNUM) |
| 737 | addr = frame1->frame + 32 * 4 + (regnum - FP0_REGNUM - 32) * 8 |
| 738 | - (FP_REGISTER_BYTES); |
| 739 | #endif |
| 740 | #endif /* FP0_REGNUM */ |
| 741 | else if (regnum >= Y_REGNUM && regnum < NUM_REGS) |
| 742 | addr = frame1->frame + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE |
| 743 | - (FP_REGISTER_BYTES + 24 * SPARC_INTREG_SIZE); |
| 744 | } |
| 745 | else if (frame1->flat) |
| 746 | { |
| 747 | |
| 748 | if (regnum == RP_REGNUM) |
| 749 | addr = frame1->pc_addr; |
| 750 | else if (regnum == I7_REGNUM) |
| 751 | addr = frame1->fp_addr; |
| 752 | else |
| 753 | { |
| 754 | CORE_ADDR func_start; |
| 755 | struct frame_saved_regs regs; |
| 756 | memset (®s, 0, sizeof (regs)); |
| 757 | |
| 758 | find_pc_partial_function (frame1->pc, NULL, &func_start, NULL); |
| 759 | examine_prologue (func_start, 0, frame1, ®s); |
| 760 | addr = regs.regs[regnum]; |
| 761 | } |
| 762 | } |
| 763 | else |
| 764 | { |
| 765 | /* Normal frame. Local and In registers are saved on stack. */ |
| 766 | if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8) |
| 767 | addr = (frame1->prev->bottom |
| 768 | + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
| 769 | + FRAME_SAVED_I0); |
| 770 | else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8) |
| 771 | addr = (frame1->prev->bottom |
| 772 | + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE |
| 773 | + FRAME_SAVED_L0); |
| 774 | else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8) |
| 775 | { |
| 776 | /* Outs become ins. */ |
| 777 | get_saved_register (raw_buffer, optimized, addrp, frame1, |
| 778 | (regnum - O0_REGNUM + I0_REGNUM), lval); |
| 779 | return; |
| 780 | } |
| 781 | } |
| 782 | if (addr != 0) |
| 783 | break; |
| 784 | frame1 = frame1->next; |
| 785 | } |
| 786 | if (addr != 0) |
| 787 | { |
| 788 | if (lval != NULL) |
| 789 | *lval = lval_memory; |
| 790 | if (regnum == SP_REGNUM) |
| 791 | { |
| 792 | if (raw_buffer != NULL) |
| 793 | { |
| 794 | /* Put it back in target format. */ |
| 795 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), addr); |
| 796 | } |
| 797 | if (addrp != NULL) |
| 798 | *addrp = 0; |
| 799 | return; |
| 800 | } |
| 801 | if (raw_buffer != NULL) |
| 802 | read_memory (addr, raw_buffer, REGISTER_RAW_SIZE (regnum)); |
| 803 | } |
| 804 | else |
| 805 | { |
| 806 | if (lval != NULL) |
| 807 | *lval = lval_register; |
| 808 | addr = REGISTER_BYTE (regnum); |
| 809 | if (raw_buffer != NULL) |
| 810 | read_register_gen (regnum, raw_buffer); |
| 811 | } |
| 812 | if (addrp != NULL) |
| 813 | *addrp = addr; |
| 814 | } |
| 815 | |
| 816 | /* Push an empty stack frame, and record in it the current PC, regs, etc. |
| 817 | |
| 818 | We save the non-windowed registers and the ins. The locals and outs |
| 819 | are new; they don't need to be saved. The i's and l's of |
| 820 | the last frame were already saved on the stack. */ |
| 821 | |
| 822 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ |
| 823 | |
| 824 | #ifdef GDB_TARGET_IS_SPARC64 |
| 825 | #define DUMMY_REG_SAVE_OFFSET (128 + 16) |
| 826 | #else |
| 827 | #define DUMMY_REG_SAVE_OFFSET 0x60 |
| 828 | #endif |
| 829 | |
| 830 | /* See tm-sparc.h for how this is calculated. */ |
| 831 | #ifdef FP0_REGNUM |
| 832 | #define DUMMY_STACK_REG_BUF_SIZE \ |
| 833 | (((8+8+8) * SPARC_INTREG_SIZE) + FP_REGISTER_BYTES) |
| 834 | #else |
| 835 | #define DUMMY_STACK_REG_BUF_SIZE \ |
| 836 | (((8+8+8) * SPARC_INTREG_SIZE) ) |
| 837 | #endif /* FP0_REGNUM */ |
| 838 | #define DUMMY_STACK_SIZE (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET) |
| 839 | |
| 840 | void |
| 841 | sparc_push_dummy_frame () |
| 842 | { |
| 843 | CORE_ADDR sp, old_sp; |
| 844 | char register_temp[DUMMY_STACK_SIZE]; |
| 845 | |
| 846 | old_sp = sp = read_sp (); |
| 847 | |
| 848 | #ifdef GDB_TARGET_IS_SPARC64 |
| 849 | /* PC, NPC, CCR, FSR, FPRS, Y, ASI */ |
| 850 | read_register_bytes (REGISTER_BYTE (PC_REGNUM), ®ister_temp[0], |
| 851 | REGISTER_RAW_SIZE (PC_REGNUM) * 7); |
| 852 | read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM), ®ister_temp[8], |
| 853 | REGISTER_RAW_SIZE (PSTATE_REGNUM)); |
| 854 | /* FIXME: not sure what needs to be saved here. */ |
| 855 | #else |
| 856 | /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */ |
| 857 | read_register_bytes (REGISTER_BYTE (Y_REGNUM), ®ister_temp[0], |
| 858 | REGISTER_RAW_SIZE (Y_REGNUM) * 8); |
| 859 | #endif |
| 860 | |
| 861 | read_register_bytes (REGISTER_BYTE (O0_REGNUM), |
| 862 | ®ister_temp[8 * SPARC_INTREG_SIZE], |
| 863 | SPARC_INTREG_SIZE * 8); |
| 864 | |
| 865 | read_register_bytes (REGISTER_BYTE (G0_REGNUM), |
| 866 | ®ister_temp[16 * SPARC_INTREG_SIZE], |
| 867 | SPARC_INTREG_SIZE * 8); |
| 868 | |
| 869 | #ifdef FP0_REGNUM |
| 870 | read_register_bytes (REGISTER_BYTE (FP0_REGNUM), |
| 871 | ®ister_temp[24 * SPARC_INTREG_SIZE], |
| 872 | FP_REGISTER_BYTES); |
| 873 | #endif /* FP0_REGNUM */ |
| 874 | |
| 875 | sp -= DUMMY_STACK_SIZE; |
| 876 | |
| 877 | write_sp (sp); |
| 878 | |
| 879 | write_memory (sp + DUMMY_REG_SAVE_OFFSET, ®ister_temp[0], |
| 880 | DUMMY_STACK_REG_BUF_SIZE); |
| 881 | |
| 882 | if (strcmp (target_shortname, "sim") != 0) |
| 883 | { |
| 884 | write_fp (old_sp); |
| 885 | |
| 886 | /* Set return address register for the call dummy to the current PC. */ |
| 887 | write_register (I7_REGNUM, read_pc() - 8); |
| 888 | } |
| 889 | else |
| 890 | { |
| 891 | /* The call dummy will write this value to FP before executing |
| 892 | the 'save'. This ensures that register window flushes work |
| 893 | correctly in the simulator. */ |
| 894 | write_register (G0_REGNUM+1, read_register (FP_REGNUM)); |
| 895 | |
| 896 | /* The call dummy will write this value to FP after executing |
| 897 | the 'save'. */ |
| 898 | write_register (G0_REGNUM+2, old_sp); |
| 899 | |
| 900 | /* The call dummy will write this value to the return address (%i7) after |
| 901 | executing the 'save'. */ |
| 902 | write_register (G0_REGNUM+3, read_pc() - 8); |
| 903 | |
| 904 | /* Set the FP that the call dummy will be using after the 'save'. |
| 905 | This makes backtraces from an inferior function call work properly. */ |
| 906 | write_register (FP_REGNUM, old_sp); |
| 907 | } |
| 908 | } |
| 909 | |
| 910 | /* sparc_frame_find_saved_regs (). This function is here only because |
| 911 | pop_frame uses it. Note there is an interesting corner case which |
| 912 | I think few ports of GDB get right--if you are popping a frame |
| 913 | which does not save some register that *is* saved by a more inner |
| 914 | frame (such a frame will never be a dummy frame because dummy |
| 915 | frames save all registers). Rewriting pop_frame to use |
| 916 | get_saved_register would solve this problem and also get rid of the |
| 917 | ugly duplication between sparc_frame_find_saved_regs and |
| 918 | get_saved_register. |
| 919 | |
| 920 | Stores, into a struct frame_saved_regs, |
| 921 | the addresses of the saved registers of frame described by FRAME_INFO. |
| 922 | This includes special registers such as pc and fp saved in special |
| 923 | ways in the stack frame. sp is even more special: |
| 924 | the address we return for it IS the sp for the next frame. |
| 925 | |
| 926 | Note that on register window machines, we are currently making the |
| 927 | assumption that window registers are being saved somewhere in the |
| 928 | frame in which they are being used. If they are stored in an |
| 929 | inferior frame, find_saved_register will break. |
| 930 | |
| 931 | On the Sun 4, the only time all registers are saved is when |
| 932 | a dummy frame is involved. Otherwise, the only saved registers |
| 933 | are the LOCAL and IN registers which are saved as a result |
| 934 | of the "save/restore" opcodes. This condition is determined |
| 935 | by address rather than by value. |
| 936 | |
| 937 | The "pc" is not stored in a frame on the SPARC. (What is stored |
| 938 | is a return address minus 8.) sparc_pop_frame knows how to |
| 939 | deal with that. Other routines might or might not. |
| 940 | |
| 941 | See tm-sparc.h (PUSH_DUMMY_FRAME and friends) for CRITICAL information |
| 942 | about how this works. */ |
| 943 | |
| 944 | static void sparc_frame_find_saved_regs PARAMS ((struct frame_info *, |
| 945 | struct frame_saved_regs *)); |
| 946 | |
| 947 | static void |
| 948 | sparc_frame_find_saved_regs (fi, saved_regs_addr) |
| 949 | struct frame_info *fi; |
| 950 | struct frame_saved_regs *saved_regs_addr; |
| 951 | { |
| 952 | register int regnum; |
| 953 | CORE_ADDR frame_addr = FRAME_FP (fi); |
| 954 | |
| 955 | if (!fi) |
| 956 | fatal ("Bad frame info struct in FRAME_FIND_SAVED_REGS"); |
| 957 | |
| 958 | memset (saved_regs_addr, 0, sizeof (*saved_regs_addr)); |
| 959 | |
| 960 | if (fi->pc >= (fi->bottom ? fi->bottom : |
| 961 | read_sp ()) |
| 962 | && fi->pc <= FRAME_FP(fi)) |
| 963 | { |
| 964 | /* Dummy frame. All but the window regs are in there somewhere. */ |
| 965 | for (regnum = G1_REGNUM; regnum < G1_REGNUM+7; regnum++) |
| 966 | saved_regs_addr->regs[regnum] = |
| 967 | frame_addr + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE |
| 968 | - DUMMY_STACK_REG_BUF_SIZE + 16 * SPARC_INTREG_SIZE; |
| 969 | for (regnum = I0_REGNUM; regnum < I0_REGNUM+8; regnum++) |
| 970 | saved_regs_addr->regs[regnum] = |
| 971 | frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
| 972 | - DUMMY_STACK_REG_BUF_SIZE + 8 * SPARC_INTREG_SIZE; |
| 973 | #ifdef FP0_REGNUM |
| 974 | for (regnum = FP0_REGNUM; regnum < FP0_REGNUM + 32; regnum++) |
| 975 | saved_regs_addr->regs[regnum] = |
| 976 | frame_addr + (regnum - FP0_REGNUM) * 4 |
| 977 | - DUMMY_STACK_REG_BUF_SIZE + 24 * SPARC_INTREG_SIZE; |
| 978 | #ifdef GDB_TARGET_IS_SPARC64 |
| 979 | for (regnum = FP0_REGNUM + 32; regnum < FP_MAX_REGNUM; regnum++) |
| 980 | saved_regs_addr->regs[regnum] = |
| 981 | frame_addr + 32 * 4 + (regnum - FP0_REGNUM - 32) * 4 |
| 982 | - DUMMY_STACK_REG_BUF_SIZE + 24 * SPARC_INTREG_SIZE; |
| 983 | #endif |
| 984 | #endif /* FP0_REGNUM */ |
| 985 | #ifdef GDB_TARGET_IS_SPARC64 |
| 986 | for (regnum = PC_REGNUM; regnum < PC_REGNUM + 7; regnum++) |
| 987 | { |
| 988 | saved_regs_addr->regs[regnum] = |
| 989 | frame_addr + (regnum - PC_REGNUM) * SPARC_INTREG_SIZE |
| 990 | - DUMMY_STACK_REG_BUF_SIZE; |
| 991 | } |
| 992 | saved_regs_addr->regs[PSTATE_REGNUM] = |
| 993 | frame_addr + 8 * SPARC_INTREG_SIZE - DUMMY_STACK_REG_BUF_SIZE; |
| 994 | #else |
| 995 | for (regnum = Y_REGNUM; regnum < NUM_REGS; regnum++) |
| 996 | saved_regs_addr->regs[regnum] = |
| 997 | frame_addr + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE |
| 998 | - DUMMY_STACK_REG_BUF_SIZE; |
| 999 | #endif |
| 1000 | frame_addr = fi->bottom ? |
| 1001 | fi->bottom : read_sp (); |
| 1002 | } |
| 1003 | else if (fi->flat) |
| 1004 | { |
| 1005 | CORE_ADDR func_start; |
| 1006 | find_pc_partial_function (fi->pc, NULL, &func_start, NULL); |
| 1007 | examine_prologue (func_start, 0, fi, saved_regs_addr); |
| 1008 | |
| 1009 | /* Flat register window frame. */ |
| 1010 | saved_regs_addr->regs[RP_REGNUM] = fi->pc_addr; |
| 1011 | saved_regs_addr->regs[I7_REGNUM] = fi->fp_addr; |
| 1012 | } |
| 1013 | else |
| 1014 | { |
| 1015 | /* Normal frame. Just Local and In registers */ |
| 1016 | frame_addr = fi->bottom ? |
| 1017 | fi->bottom : read_sp (); |
| 1018 | for (regnum = L0_REGNUM; regnum < L0_REGNUM+8; regnum++) |
| 1019 | saved_regs_addr->regs[regnum] = |
| 1020 | (frame_addr + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE |
| 1021 | + FRAME_SAVED_L0); |
| 1022 | for (regnum = I0_REGNUM; regnum < I0_REGNUM+8; regnum++) |
| 1023 | saved_regs_addr->regs[regnum] = |
| 1024 | (frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
| 1025 | + FRAME_SAVED_I0); |
| 1026 | } |
| 1027 | if (fi->next) |
| 1028 | { |
| 1029 | if (fi->flat) |
| 1030 | { |
| 1031 | saved_regs_addr->regs[O7_REGNUM] = fi->pc_addr; |
| 1032 | } |
| 1033 | else |
| 1034 | { |
| 1035 | /* Pull off either the next frame pointer or the stack pointer */ |
| 1036 | CORE_ADDR next_next_frame_addr = |
| 1037 | (fi->next->bottom ? |
| 1038 | fi->next->bottom : |
| 1039 | read_sp ()); |
| 1040 | for (regnum = O0_REGNUM; regnum < O0_REGNUM+8; regnum++) |
| 1041 | saved_regs_addr->regs[regnum] = |
| 1042 | (next_next_frame_addr |
| 1043 | + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE |
| 1044 | + FRAME_SAVED_I0); |
| 1045 | } |
| 1046 | } |
| 1047 | /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */ |
| 1048 | /* FIXME -- should this adjust for the sparc64 offset? */ |
| 1049 | saved_regs_addr->regs[SP_REGNUM] = FRAME_FP (fi); |
| 1050 | } |
| 1051 | |
| 1052 | /* Discard from the stack the innermost frame, restoring all saved registers. |
| 1053 | |
| 1054 | Note that the values stored in fsr by get_frame_saved_regs are *in |
| 1055 | the context of the called frame*. What this means is that the i |
| 1056 | regs of fsr must be restored into the o regs of the (calling) frame that |
| 1057 | we pop into. We don't care about the output regs of the calling frame, |
| 1058 | since unless it's a dummy frame, it won't have any output regs in it. |
| 1059 | |
| 1060 | We never have to bother with %l (local) regs, since the called routine's |
| 1061 | locals get tossed, and the calling routine's locals are already saved |
| 1062 | on its stack. */ |
| 1063 | |
| 1064 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ |
| 1065 | |
| 1066 | void |
| 1067 | sparc_pop_frame () |
| 1068 | { |
| 1069 | register struct frame_info *frame = get_current_frame (); |
| 1070 | register CORE_ADDR pc; |
| 1071 | struct frame_saved_regs fsr; |
| 1072 | char raw_buffer[REGISTER_BYTES]; |
| 1073 | int regnum; |
| 1074 | |
| 1075 | sparc_frame_find_saved_regs (frame, &fsr); |
| 1076 | #ifdef FP0_REGNUM |
| 1077 | if (fsr.regs[FP0_REGNUM]) |
| 1078 | { |
| 1079 | read_memory (fsr.regs[FP0_REGNUM], raw_buffer, FP_REGISTER_BYTES); |
| 1080 | write_register_bytes (REGISTER_BYTE (FP0_REGNUM), |
| 1081 | raw_buffer, FP_REGISTER_BYTES); |
| 1082 | } |
| 1083 | #ifndef GDB_TARGET_IS_SPARC64 |
| 1084 | if (fsr.regs[FPS_REGNUM]) |
| 1085 | { |
| 1086 | read_memory (fsr.regs[FPS_REGNUM], raw_buffer, 4); |
| 1087 | write_register_bytes (REGISTER_BYTE (FPS_REGNUM), raw_buffer, 4); |
| 1088 | } |
| 1089 | if (fsr.regs[CPS_REGNUM]) |
| 1090 | { |
| 1091 | read_memory (fsr.regs[CPS_REGNUM], raw_buffer, 4); |
| 1092 | write_register_bytes (REGISTER_BYTE (CPS_REGNUM), raw_buffer, 4); |
| 1093 | } |
| 1094 | #endif |
| 1095 | #endif /* FP0_REGNUM */ |
| 1096 | if (fsr.regs[G1_REGNUM]) |
| 1097 | { |
| 1098 | read_memory (fsr.regs[G1_REGNUM], raw_buffer, 7 * SPARC_INTREG_SIZE); |
| 1099 | write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer, |
| 1100 | 7 * SPARC_INTREG_SIZE); |
| 1101 | } |
| 1102 | |
| 1103 | if (frame->flat) |
| 1104 | { |
| 1105 | /* Each register might or might not have been saved, need to test |
| 1106 | individually. */ |
| 1107 | for (regnum = L0_REGNUM; regnum < L0_REGNUM + 8; ++regnum) |
| 1108 | if (fsr.regs[regnum]) |
| 1109 | write_register (regnum, read_memory_integer (fsr.regs[regnum], |
| 1110 | SPARC_INTREG_SIZE)); |
| 1111 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; ++regnum) |
| 1112 | if (fsr.regs[regnum]) |
| 1113 | write_register (regnum, read_memory_integer (fsr.regs[regnum], |
| 1114 | SPARC_INTREG_SIZE)); |
| 1115 | |
| 1116 | /* Handle all outs except stack pointer (o0-o5; o7). */ |
| 1117 | for (regnum = O0_REGNUM; regnum < O0_REGNUM + 6; ++regnum) |
| 1118 | if (fsr.regs[regnum]) |
| 1119 | write_register (regnum, read_memory_integer (fsr.regs[regnum], |
| 1120 | SPARC_INTREG_SIZE)); |
| 1121 | if (fsr.regs[O0_REGNUM + 7]) |
| 1122 | write_register (O0_REGNUM + 7, |
| 1123 | read_memory_integer (fsr.regs[O0_REGNUM + 7], |
| 1124 | SPARC_INTREG_SIZE)); |
| 1125 | |
| 1126 | write_sp (frame->frame); |
| 1127 | } |
| 1128 | else if (fsr.regs[I0_REGNUM]) |
| 1129 | { |
| 1130 | CORE_ADDR sp; |
| 1131 | |
| 1132 | char reg_temp[REGISTER_BYTES]; |
| 1133 | |
| 1134 | read_memory (fsr.regs[I0_REGNUM], raw_buffer, 8 * SPARC_INTREG_SIZE); |
| 1135 | |
| 1136 | /* Get the ins and locals which we are about to restore. Just |
| 1137 | moving the stack pointer is all that is really needed, except |
| 1138 | store_inferior_registers is then going to write the ins and |
| 1139 | locals from the registers array, so we need to muck with the |
| 1140 | registers array. */ |
| 1141 | sp = fsr.regs[SP_REGNUM]; |
| 1142 | #ifdef GDB_TARGET_IS_SPARC64 |
| 1143 | if (sp & 1) |
| 1144 | sp += 2047; |
| 1145 | #endif |
| 1146 | read_memory (sp, reg_temp, SPARC_INTREG_SIZE * 16); |
| 1147 | |
| 1148 | /* Restore the out registers. |
| 1149 | Among other things this writes the new stack pointer. */ |
| 1150 | write_register_bytes (REGISTER_BYTE (O0_REGNUM), raw_buffer, |
| 1151 | SPARC_INTREG_SIZE * 8); |
| 1152 | |
| 1153 | write_register_bytes (REGISTER_BYTE (L0_REGNUM), reg_temp, |
| 1154 | SPARC_INTREG_SIZE * 16); |
| 1155 | } |
| 1156 | #ifndef GDB_TARGET_IS_SPARC64 |
| 1157 | if (fsr.regs[PS_REGNUM]) |
| 1158 | write_register (PS_REGNUM, read_memory_integer (fsr.regs[PS_REGNUM], 4)); |
| 1159 | #endif |
| 1160 | if (fsr.regs[Y_REGNUM]) |
| 1161 | write_register (Y_REGNUM, read_memory_integer (fsr.regs[Y_REGNUM], REGISTER_RAW_SIZE (Y_REGNUM))); |
| 1162 | if (fsr.regs[PC_REGNUM]) |
| 1163 | { |
| 1164 | /* Explicitly specified PC (and maybe NPC) -- just restore them. */ |
| 1165 | write_register (PC_REGNUM, read_memory_integer (fsr.regs[PC_REGNUM], |
| 1166 | REGISTER_RAW_SIZE (PC_REGNUM))); |
| 1167 | if (fsr.regs[NPC_REGNUM]) |
| 1168 | write_register (NPC_REGNUM, |
| 1169 | read_memory_integer (fsr.regs[NPC_REGNUM], |
| 1170 | REGISTER_RAW_SIZE (NPC_REGNUM))); |
| 1171 | } |
| 1172 | else if (frame->flat) |
| 1173 | { |
| 1174 | if (frame->pc_addr) |
| 1175 | pc = PC_ADJUST ((CORE_ADDR) |
| 1176 | read_memory_integer (frame->pc_addr, |
| 1177 | REGISTER_RAW_SIZE (PC_REGNUM))); |
| 1178 | else |
| 1179 | { |
| 1180 | /* I think this happens only in the innermost frame, if so then |
| 1181 | it is a complicated way of saying |
| 1182 | "pc = read_register (O7_REGNUM);". */ |
| 1183 | char buf[MAX_REGISTER_RAW_SIZE]; |
| 1184 | get_saved_register (buf, 0, 0, frame, O7_REGNUM, 0); |
| 1185 | pc = PC_ADJUST (extract_address |
| 1186 | (buf, REGISTER_RAW_SIZE (O7_REGNUM))); |
| 1187 | } |
| 1188 | |
| 1189 | write_register (PC_REGNUM, pc); |
| 1190 | write_register (NPC_REGNUM, pc + 4); |
| 1191 | } |
| 1192 | else if (fsr.regs[I7_REGNUM]) |
| 1193 | { |
| 1194 | /* Return address in %i7 -- adjust it, then restore PC and NPC from it */ |
| 1195 | pc = PC_ADJUST ((CORE_ADDR) read_memory_integer (fsr.regs[I7_REGNUM], |
| 1196 | SPARC_INTREG_SIZE)); |
| 1197 | write_register (PC_REGNUM, pc); |
| 1198 | write_register (NPC_REGNUM, pc + 4); |
| 1199 | } |
| 1200 | flush_cached_frames (); |
| 1201 | } |
| 1202 | |
| 1203 | /* On the Sun 4 under SunOS, the compile will leave a fake insn which |
| 1204 | encodes the structure size being returned. If we detect such |
| 1205 | a fake insn, step past it. */ |
| 1206 | |
| 1207 | CORE_ADDR |
| 1208 | sparc_pc_adjust(pc) |
| 1209 | CORE_ADDR pc; |
| 1210 | { |
| 1211 | unsigned long insn; |
| 1212 | char buf[4]; |
| 1213 | int err; |
| 1214 | |
| 1215 | err = target_read_memory (pc + 8, buf, 4); |
| 1216 | insn = extract_unsigned_integer (buf, 4); |
| 1217 | if ((err == 0) && (insn & 0xffc00000) == 0) |
| 1218 | return pc+12; |
| 1219 | else |
| 1220 | return pc+8; |
| 1221 | } |
| 1222 | |
| 1223 | /* If pc is in a shared library trampoline, return its target. |
| 1224 | The SunOs 4.x linker rewrites the jump table entries for PIC |
| 1225 | compiled modules in the main executable to bypass the dynamic linker |
| 1226 | with jumps of the form |
| 1227 | sethi %hi(addr),%g1 |
| 1228 | jmp %g1+%lo(addr) |
| 1229 | and removes the corresponding jump table relocation entry in the |
| 1230 | dynamic relocations. |
| 1231 | find_solib_trampoline_target relies on the presence of the jump |
| 1232 | table relocation entry, so we have to detect these jump instructions |
| 1233 | by hand. */ |
| 1234 | |
| 1235 | CORE_ADDR |
| 1236 | sunos4_skip_trampoline_code (pc) |
| 1237 | CORE_ADDR pc; |
| 1238 | { |
| 1239 | unsigned long insn1; |
| 1240 | char buf[4]; |
| 1241 | int err; |
| 1242 | |
| 1243 | err = target_read_memory (pc, buf, 4); |
| 1244 | insn1 = extract_unsigned_integer (buf, 4); |
| 1245 | if (err == 0 && (insn1 & 0xffc00000) == 0x03000000) |
| 1246 | { |
| 1247 | unsigned long insn2; |
| 1248 | |
| 1249 | err = target_read_memory (pc + 4, buf, 4); |
| 1250 | insn2 = extract_unsigned_integer (buf, 4); |
| 1251 | if (err == 0 && (insn2 & 0xffffe000) == 0x81c06000) |
| 1252 | { |
| 1253 | CORE_ADDR target_pc = (insn1 & 0x3fffff) << 10; |
| 1254 | int delta = insn2 & 0x1fff; |
| 1255 | |
| 1256 | /* Sign extend the displacement. */ |
| 1257 | if (delta & 0x1000) |
| 1258 | delta |= ~0x1fff; |
| 1259 | return target_pc + delta; |
| 1260 | } |
| 1261 | } |
| 1262 | return find_solib_trampoline_target (pc); |
| 1263 | } |
| 1264 | \f |
| 1265 | #ifdef USE_PROC_FS /* Target dependent support for /proc */ |
| 1266 | |
| 1267 | /* The /proc interface divides the target machine's register set up into |
| 1268 | two different sets, the general register set (gregset) and the floating |
| 1269 | point register set (fpregset). For each set, there is an ioctl to get |
| 1270 | the current register set and another ioctl to set the current values. |
| 1271 | |
| 1272 | The actual structure passed through the ioctl interface is, of course, |
| 1273 | naturally machine dependent, and is different for each set of registers. |
| 1274 | For the sparc for example, the general register set is typically defined |
| 1275 | by: |
| 1276 | |
| 1277 | typedef int gregset_t[38]; |
| 1278 | |
| 1279 | #define R_G0 0 |
| 1280 | ... |
| 1281 | #define R_TBR 37 |
| 1282 | |
| 1283 | and the floating point set by: |
| 1284 | |
| 1285 | typedef struct prfpregset { |
| 1286 | union { |
| 1287 | u_long pr_regs[32]; |
| 1288 | double pr_dregs[16]; |
| 1289 | } pr_fr; |
| 1290 | void * pr_filler; |
| 1291 | u_long pr_fsr; |
| 1292 | u_char pr_qcnt; |
| 1293 | u_char pr_q_entrysize; |
| 1294 | u_char pr_en; |
| 1295 | u_long pr_q[64]; |
| 1296 | } prfpregset_t; |
| 1297 | |
| 1298 | These routines provide the packing and unpacking of gregset_t and |
| 1299 | fpregset_t formatted data. |
| 1300 | |
| 1301 | */ |
| 1302 | |
| 1303 | /* Given a pointer to a general register set in /proc format (gregset_t *), |
| 1304 | unpack the register contents and supply them as gdb's idea of the current |
| 1305 | register values. */ |
| 1306 | |
| 1307 | void |
| 1308 | supply_gregset (gregsetp) |
| 1309 | prgregset_t *gregsetp; |
| 1310 | { |
| 1311 | register int regi; |
| 1312 | register prgreg_t *regp = (prgreg_t *) gregsetp; |
| 1313 | static char zerobuf[MAX_REGISTER_RAW_SIZE] = {0}; |
| 1314 | |
| 1315 | /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */ |
| 1316 | for (regi = G0_REGNUM ; regi <= I7_REGNUM ; regi++) |
| 1317 | { |
| 1318 | supply_register (regi, (char *) (regp + regi)); |
| 1319 | } |
| 1320 | |
| 1321 | /* These require a bit more care. */ |
| 1322 | supply_register (PS_REGNUM, (char *) (regp + R_PS)); |
| 1323 | supply_register (PC_REGNUM, (char *) (regp + R_PC)); |
| 1324 | supply_register (NPC_REGNUM,(char *) (regp + R_nPC)); |
| 1325 | supply_register (Y_REGNUM, (char *) (regp + R_Y)); |
| 1326 | |
| 1327 | /* Fill inaccessible registers with zero. */ |
| 1328 | supply_register (WIM_REGNUM, zerobuf); |
| 1329 | supply_register (TBR_REGNUM, zerobuf); |
| 1330 | supply_register (CPS_REGNUM, zerobuf); |
| 1331 | } |
| 1332 | |
| 1333 | void |
| 1334 | fill_gregset (gregsetp, regno) |
| 1335 | prgregset_t *gregsetp; |
| 1336 | int regno; |
| 1337 | { |
| 1338 | int regi; |
| 1339 | register prgreg_t *regp = (prgreg_t *) gregsetp; |
| 1340 | |
| 1341 | for (regi = 0 ; regi <= R_I7 ; regi++) |
| 1342 | { |
| 1343 | if ((regno == -1) || (regno == regi)) |
| 1344 | { |
| 1345 | *(regp + regi) = *(int *) ®isters[REGISTER_BYTE (regi)]; |
| 1346 | } |
| 1347 | } |
| 1348 | if ((regno == -1) || (regno == PS_REGNUM)) |
| 1349 | { |
| 1350 | *(regp + R_PS) = *(int *) ®isters[REGISTER_BYTE (PS_REGNUM)]; |
| 1351 | } |
| 1352 | if ((regno == -1) || (regno == PC_REGNUM)) |
| 1353 | { |
| 1354 | *(regp + R_PC) = *(int *) ®isters[REGISTER_BYTE (PC_REGNUM)]; |
| 1355 | } |
| 1356 | if ((regno == -1) || (regno == NPC_REGNUM)) |
| 1357 | { |
| 1358 | *(regp + R_nPC) = *(int *) ®isters[REGISTER_BYTE (NPC_REGNUM)]; |
| 1359 | } |
| 1360 | if ((regno == -1) || (regno == Y_REGNUM)) |
| 1361 | { |
| 1362 | *(regp + R_Y) = *(int *) ®isters[REGISTER_BYTE (Y_REGNUM)]; |
| 1363 | } |
| 1364 | } |
| 1365 | |
| 1366 | #if defined (FP0_REGNUM) |
| 1367 | |
| 1368 | /* Given a pointer to a floating point register set in /proc format |
| 1369 | (fpregset_t *), unpack the register contents and supply them as gdb's |
| 1370 | idea of the current floating point register values. */ |
| 1371 | |
| 1372 | void |
| 1373 | supply_fpregset (fpregsetp) |
| 1374 | prfpregset_t *fpregsetp; |
| 1375 | { |
| 1376 | register int regi; |
| 1377 | char *from; |
| 1378 | |
| 1379 | for (regi = FP0_REGNUM ; regi < FP_MAX_REGNUM ; regi++) |
| 1380 | { |
| 1381 | from = (char *) &fpregsetp->pr_fr.pr_regs[regi-FP0_REGNUM]; |
| 1382 | supply_register (regi, from); |
| 1383 | } |
| 1384 | supply_register (FPS_REGNUM, (char *) &(fpregsetp->pr_fsr)); |
| 1385 | } |
| 1386 | |
| 1387 | /* Given a pointer to a floating point register set in /proc format |
| 1388 | (fpregset_t *), update the register specified by REGNO from gdb's idea |
| 1389 | of the current floating point register set. If REGNO is -1, update |
| 1390 | them all. */ |
| 1391 | /* ??? This will probably need some changes for sparc64. */ |
| 1392 | |
| 1393 | void |
| 1394 | fill_fpregset (fpregsetp, regno) |
| 1395 | prfpregset_t *fpregsetp; |
| 1396 | int regno; |
| 1397 | { |
| 1398 | int regi; |
| 1399 | char *to; |
| 1400 | char *from; |
| 1401 | |
| 1402 | for (regi = FP0_REGNUM ; regi < FP_MAX_REGNUM ; regi++) |
| 1403 | { |
| 1404 | if ((regno == -1) || (regno == regi)) |
| 1405 | { |
| 1406 | from = (char *) ®isters[REGISTER_BYTE (regi)]; |
| 1407 | to = (char *) &fpregsetp->pr_fr.pr_regs[regi-FP0_REGNUM]; |
| 1408 | memcpy (to, from, REGISTER_RAW_SIZE (regi)); |
| 1409 | } |
| 1410 | } |
| 1411 | if ((regno == -1) || (regno == FPS_REGNUM)) |
| 1412 | { |
| 1413 | fpregsetp->pr_fsr = *(int *) ®isters[REGISTER_BYTE (FPS_REGNUM)]; |
| 1414 | } |
| 1415 | } |
| 1416 | |
| 1417 | #endif /* defined (FP0_REGNUM) */ |
| 1418 | |
| 1419 | #endif /* USE_PROC_FS */ |
| 1420 | |
| 1421 | |
| 1422 | #ifdef GET_LONGJMP_TARGET |
| 1423 | |
| 1424 | /* Figure out where the longjmp will land. We expect that we have just entered |
| 1425 | longjmp and haven't yet setup the stack frame, so the args are still in the |
| 1426 | output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we |
| 1427 | extract the pc (JB_PC) that we will land at. The pc is copied into ADDR. |
| 1428 | This routine returns true on success */ |
| 1429 | |
| 1430 | int |
| 1431 | get_longjmp_target (pc) |
| 1432 | CORE_ADDR *pc; |
| 1433 | { |
| 1434 | CORE_ADDR jb_addr; |
| 1435 | #define LONGJMP_TARGET_SIZE 4 |
| 1436 | char buf[LONGJMP_TARGET_SIZE]; |
| 1437 | |
| 1438 | jb_addr = read_register (O0_REGNUM); |
| 1439 | |
| 1440 | if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf, |
| 1441 | LONGJMP_TARGET_SIZE)) |
| 1442 | return 0; |
| 1443 | |
| 1444 | *pc = extract_address (buf, LONGJMP_TARGET_SIZE); |
| 1445 | |
| 1446 | return 1; |
| 1447 | } |
| 1448 | #endif /* GET_LONGJMP_TARGET */ |
| 1449 | \f |
| 1450 | #ifdef STATIC_TRANSFORM_NAME |
| 1451 | /* SunPRO (3.0 at least), encodes the static variables. This is not |
| 1452 | related to C++ mangling, it is done for C too. */ |
| 1453 | |
| 1454 | char * |
| 1455 | sunpro_static_transform_name (name) |
| 1456 | char *name; |
| 1457 | { |
| 1458 | char *p; |
| 1459 | if (name[0] == '$') |
| 1460 | { |
| 1461 | /* For file-local statics there will be a dollar sign, a bunch |
| 1462 | of junk (the contents of which match a string given in the |
| 1463 | N_OPT), a period and the name. For function-local statics |
| 1464 | there will be a bunch of junk (which seems to change the |
| 1465 | second character from 'A' to 'B'), a period, the name of the |
| 1466 | function, and the name. So just skip everything before the |
| 1467 | last period. */ |
| 1468 | p = strrchr (name, '.'); |
| 1469 | if (p != NULL) |
| 1470 | name = p + 1; |
| 1471 | } |
| 1472 | return name; |
| 1473 | } |
| 1474 | #endif /* STATIC_TRANSFORM_NAME */ |
| 1475 | \f |
| 1476 | |
| 1477 | /* Utilities for printing registers. |
| 1478 | Page numbers refer to the SPARC Architecture Manual. */ |
| 1479 | |
| 1480 | static void dump_ccreg PARAMS ((char *, int)); |
| 1481 | |
| 1482 | static void |
| 1483 | dump_ccreg (reg, val) |
| 1484 | char *reg; |
| 1485 | int val; |
| 1486 | { |
| 1487 | /* page 41 */ |
| 1488 | printf_unfiltered ("%s:%s,%s,%s,%s", reg, |
| 1489 | val & 8 ? "N" : "NN", |
| 1490 | val & 4 ? "Z" : "NZ", |
| 1491 | val & 2 ? "O" : "NO", |
| 1492 | val & 1 ? "C" : "NC" |
| 1493 | ); |
| 1494 | } |
| 1495 | |
| 1496 | static char * |
| 1497 | decode_asi (val) |
| 1498 | int val; |
| 1499 | { |
| 1500 | /* page 72 */ |
| 1501 | switch (val) |
| 1502 | { |
| 1503 | case 4 : return "ASI_NUCLEUS"; |
| 1504 | case 0x0c : return "ASI_NUCLEUS_LITTLE"; |
| 1505 | case 0x10 : return "ASI_AS_IF_USER_PRIMARY"; |
| 1506 | case 0x11 : return "ASI_AS_IF_USER_SECONDARY"; |
| 1507 | case 0x18 : return "ASI_AS_IF_USER_PRIMARY_LITTLE"; |
| 1508 | case 0x19 : return "ASI_AS_IF_USER_SECONDARY_LITTLE"; |
| 1509 | case 0x80 : return "ASI_PRIMARY"; |
| 1510 | case 0x81 : return "ASI_SECONDARY"; |
| 1511 | case 0x82 : return "ASI_PRIMARY_NOFAULT"; |
| 1512 | case 0x83 : return "ASI_SECONDARY_NOFAULT"; |
| 1513 | case 0x88 : return "ASI_PRIMARY_LITTLE"; |
| 1514 | case 0x89 : return "ASI_SECONDARY_LITTLE"; |
| 1515 | case 0x8a : return "ASI_PRIMARY_NOFAULT_LITTLE"; |
| 1516 | case 0x8b : return "ASI_SECONDARY_NOFAULT_LITTLE"; |
| 1517 | default : return NULL; |
| 1518 | } |
| 1519 | } |
| 1520 | |
| 1521 | /* PRINT_REGISTER_HOOK routine. |
| 1522 | Pretty print various registers. */ |
| 1523 | /* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */ |
| 1524 | |
| 1525 | void |
| 1526 | sparc_print_register_hook (regno) |
| 1527 | int regno; |
| 1528 | { |
| 1529 | ULONGEST val; |
| 1530 | |
| 1531 | /* Handle double/quad versions of lower 32 fp regs. */ |
| 1532 | if (regno >= FP0_REGNUM && regno < FP0_REGNUM + 32 |
| 1533 | && (regno & 1) == 0) |
| 1534 | { |
| 1535 | char value[16]; |
| 1536 | |
| 1537 | if (!read_relative_register_raw_bytes (regno, value) |
| 1538 | && !read_relative_register_raw_bytes (regno + 1, value + 4)) |
| 1539 | { |
| 1540 | printf_unfiltered ("\t"); |
| 1541 | print_floating (value, builtin_type_double, gdb_stdout); |
| 1542 | } |
| 1543 | #if 0 /* FIXME: gdb doesn't handle long doubles */ |
| 1544 | if ((regno & 3) == 0) |
| 1545 | { |
| 1546 | if (!read_relative_register_raw_bytes (regno + 2, value + 8) |
| 1547 | && !read_relative_register_raw_bytes (regno + 3, value + 12)) |
| 1548 | { |
| 1549 | printf_unfiltered ("\t"); |
| 1550 | print_floating (value, builtin_type_long_double, gdb_stdout); |
| 1551 | } |
| 1552 | } |
| 1553 | #endif |
| 1554 | return; |
| 1555 | } |
| 1556 | |
| 1557 | #if 0 /* FIXME: gdb doesn't handle long doubles */ |
| 1558 | /* Print upper fp regs as long double if appropriate. */ |
| 1559 | if (regno >= FP0_REGNUM + 32 && regno < FP_MAX_REGNUM |
| 1560 | /* We test for even numbered regs and not a multiple of 4 because |
| 1561 | the upper fp regs are recorded as doubles. */ |
| 1562 | && (regno & 1) == 0) |
| 1563 | { |
| 1564 | char value[16]; |
| 1565 | |
| 1566 | if (!read_relative_register_raw_bytes (regno, value) |
| 1567 | && !read_relative_register_raw_bytes (regno + 1, value + 8)) |
| 1568 | { |
| 1569 | printf_unfiltered ("\t"); |
| 1570 | print_floating (value, builtin_type_long_double, gdb_stdout); |
| 1571 | } |
| 1572 | return; |
| 1573 | } |
| 1574 | #endif |
| 1575 | |
| 1576 | /* FIXME: Some of these are priviledged registers. |
| 1577 | Not sure how they should be handled. */ |
| 1578 | |
| 1579 | #define BITS(n, mask) ((int) (((val) >> (n)) & (mask))) |
| 1580 | |
| 1581 | val = read_register (regno); |
| 1582 | |
| 1583 | /* pages 40 - 60 */ |
| 1584 | switch (regno) |
| 1585 | { |
| 1586 | #ifdef GDB_TARGET_IS_SPARC64 |
| 1587 | case CCR_REGNUM : |
| 1588 | printf_unfiltered("\t"); |
| 1589 | dump_ccreg ("xcc", val >> 4); |
| 1590 | printf_unfiltered(", "); |
| 1591 | dump_ccreg ("icc", val & 15); |
| 1592 | break; |
| 1593 | case FPRS_REGNUM : |
| 1594 | printf ("\tfef:%d, du:%d, dl:%d", |
| 1595 | BITS (2, 1), BITS (1, 1), BITS (0, 1)); |
| 1596 | break; |
| 1597 | case FSR_REGNUM : |
| 1598 | { |
| 1599 | static char *fcc[4] = { "=", "<", ">", "?" }; |
| 1600 | static char *rd[4] = { "N", "0", "+", "-" }; |
| 1601 | /* Long, yes, but I'd rather leave it as is and use a wide screen. */ |
| 1602 | printf ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d", |
| 1603 | fcc[BITS (10, 3)], fcc[BITS (32, 3)], |
| 1604 | fcc[BITS (34, 3)], fcc[BITS (36, 3)], |
| 1605 | rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7), |
| 1606 | BITS (14, 7), BITS (13, 1), BITS (5, 31), BITS (0, 31)); |
| 1607 | break; |
| 1608 | } |
| 1609 | case ASI_REGNUM : |
| 1610 | { |
| 1611 | char *asi = decode_asi (val); |
| 1612 | if (asi != NULL) |
| 1613 | printf ("\t%s", asi); |
| 1614 | break; |
| 1615 | } |
| 1616 | case VER_REGNUM : |
| 1617 | printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d", |
| 1618 | BITS (48, 0xffff), BITS (32, 0xffff), |
| 1619 | BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31)); |
| 1620 | break; |
| 1621 | case PSTATE_REGNUM : |
| 1622 | { |
| 1623 | static char *mm[4] = { "tso", "pso", "rso", "?" }; |
| 1624 | printf ("\tcle:%d, tle:%d, mm:%s, red:%d, pef:%d, am:%d, priv:%d, ie:%d, ag:%d", |
| 1625 | BITS (9, 1), BITS (8, 1), mm[BITS (6, 3)], BITS (5, 1), |
| 1626 | BITS (4, 1), BITS (3, 1), BITS (2, 1), BITS (1, 1), |
| 1627 | BITS (0, 1)); |
| 1628 | break; |
| 1629 | } |
| 1630 | case TSTATE_REGNUM : |
| 1631 | /* FIXME: print all 4? */ |
| 1632 | break; |
| 1633 | case TT_REGNUM : |
| 1634 | /* FIXME: print all 4? */ |
| 1635 | break; |
| 1636 | case TPC_REGNUM : |
| 1637 | /* FIXME: print all 4? */ |
| 1638 | break; |
| 1639 | case TNPC_REGNUM : |
| 1640 | /* FIXME: print all 4? */ |
| 1641 | break; |
| 1642 | case WSTATE_REGNUM : |
| 1643 | printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7)); |
| 1644 | break; |
| 1645 | case CWP_REGNUM : |
| 1646 | printf ("\t%d", BITS (0, 31)); |
| 1647 | break; |
| 1648 | case CANSAVE_REGNUM : |
| 1649 | printf ("\t%-2d before spill", BITS (0, 31)); |
| 1650 | break; |
| 1651 | case CANRESTORE_REGNUM : |
| 1652 | printf ("\t%-2d before fill", BITS (0, 31)); |
| 1653 | break; |
| 1654 | case CLEANWIN_REGNUM : |
| 1655 | printf ("\t%-2d before clean", BITS (0, 31)); |
| 1656 | break; |
| 1657 | case OTHERWIN_REGNUM : |
| 1658 | printf ("\t%d", BITS (0, 31)); |
| 1659 | break; |
| 1660 | #else |
| 1661 | case PS_REGNUM: |
| 1662 | printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d", |
| 1663 | BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-', |
| 1664 | BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-', |
| 1665 | BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1), |
| 1666 | BITS (0, 31)); |
| 1667 | break; |
| 1668 | case FPS_REGNUM: |
| 1669 | { |
| 1670 | static char *fcc[4] = { "=", "<", ">", "?" }; |
| 1671 | static char *rd[4] = { "N", "0", "+", "-" }; |
| 1672 | /* Long, yes, but I'd rather leave it as is and use a wide screen. */ |
| 1673 | printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, " |
| 1674 | "fcc:%s, aexc:%d, cexc:%d", |
| 1675 | rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7), |
| 1676 | BITS (14, 7), BITS (13, 1), fcc[BITS (10, 3)], BITS (5, 31), |
| 1677 | BITS (0, 31)); |
| 1678 | break; |
| 1679 | } |
| 1680 | |
| 1681 | #endif /* GDB_TARGET_IS_SPARC64 */ |
| 1682 | } |
| 1683 | |
| 1684 | #undef BITS |
| 1685 | } |
| 1686 | \f |
| 1687 | int |
| 1688 | gdb_print_insn_sparc (memaddr, info) |
| 1689 | bfd_vma memaddr; |
| 1690 | disassemble_info *info; |
| 1691 | { |
| 1692 | /* It's necessary to override mach again because print_insn messes it up. */ |
| 1693 | info->mach = TM_PRINT_INSN_MACH; |
| 1694 | return print_insn_sparc (memaddr, info); |
| 1695 | } |
| 1696 | \f |
| 1697 | /* The SPARC passes the arguments on the stack; arguments smaller |
| 1698 | than an int are promoted to an int. */ |
| 1699 | |
| 1700 | CORE_ADDR |
| 1701 | sparc_push_arguments (nargs, args, sp, struct_return, struct_addr) |
| 1702 | int nargs; |
| 1703 | value_ptr *args; |
| 1704 | CORE_ADDR sp; |
| 1705 | int struct_return; |
| 1706 | CORE_ADDR struct_addr; |
| 1707 | { |
| 1708 | int i; |
| 1709 | int accumulate_size = 0; |
| 1710 | struct sparc_arg |
| 1711 | { |
| 1712 | char *contents; |
| 1713 | int len; |
| 1714 | int offset; |
| 1715 | }; |
| 1716 | struct sparc_arg *sparc_args = |
| 1717 | (struct sparc_arg*)alloca (nargs * sizeof (struct sparc_arg)); |
| 1718 | struct sparc_arg *m_arg; |
| 1719 | |
| 1720 | /* Promote arguments if necessary, and calculate their stack offsets |
| 1721 | and sizes. */ |
| 1722 | for (i = 0, m_arg = sparc_args; i < nargs; i++, m_arg++) |
| 1723 | { |
| 1724 | value_ptr arg = args[i]; |
| 1725 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
| 1726 | /* Cast argument to long if necessary as the compiler does it too. */ |
| 1727 | switch (TYPE_CODE (arg_type)) |
| 1728 | { |
| 1729 | case TYPE_CODE_INT: |
| 1730 | case TYPE_CODE_BOOL: |
| 1731 | case TYPE_CODE_CHAR: |
| 1732 | case TYPE_CODE_RANGE: |
| 1733 | case TYPE_CODE_ENUM: |
| 1734 | if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long)) |
| 1735 | { |
| 1736 | arg_type = builtin_type_long; |
| 1737 | arg = value_cast (arg_type, arg); |
| 1738 | } |
| 1739 | break; |
| 1740 | default: |
| 1741 | break; |
| 1742 | } |
| 1743 | m_arg->len = TYPE_LENGTH (arg_type); |
| 1744 | m_arg->offset = accumulate_size; |
| 1745 | accumulate_size = (accumulate_size + m_arg->len + 3) & ~3; |
| 1746 | m_arg->contents = VALUE_CONTENTS(arg); |
| 1747 | } |
| 1748 | |
| 1749 | /* Make room for the arguments on the stack. */ |
| 1750 | accumulate_size += CALL_DUMMY_STACK_ADJUST; |
| 1751 | sp = ((sp - accumulate_size) & ~7) + CALL_DUMMY_STACK_ADJUST; |
| 1752 | |
| 1753 | /* `Push' arguments on the stack. */ |
| 1754 | for (i = nargs; m_arg--, --i >= 0; ) |
| 1755 | write_memory(sp + m_arg->offset, m_arg->contents, m_arg->len); |
| 1756 | |
| 1757 | return sp; |
| 1758 | } |
| 1759 | |
| 1760 | |
| 1761 | /* Extract from an array REGBUF containing the (raw) register state |
| 1762 | a function return value of type TYPE, and copy that, in virtual format, |
| 1763 | into VALBUF. */ |
| 1764 | |
| 1765 | void |
| 1766 | sparc_extract_return_value (type, regbuf, valbuf) |
| 1767 | struct type *type; |
| 1768 | char *regbuf; |
| 1769 | char *valbuf; |
| 1770 | { |
| 1771 | int typelen = TYPE_LENGTH (type); |
| 1772 | int regsize = REGISTER_RAW_SIZE (O0_REGNUM); |
| 1773 | |
| 1774 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) |
| 1775 | memcpy (valbuf, ®buf [REGISTER_BYTE (FP0_REGNUM)], typelen); |
| 1776 | else |
| 1777 | memcpy (valbuf, |
| 1778 | ®buf [O0_REGNUM * regsize + |
| 1779 | (typelen >= regsize ? 0 : regsize - typelen)], |
| 1780 | typelen); |
| 1781 | } |
| 1782 | |
| 1783 | |
| 1784 | /* Write into appropriate registers a function return value |
| 1785 | of type TYPE, given in virtual format. On SPARCs with FPUs, |
| 1786 | float values are returned in %f0 (and %f1). In all other cases, |
| 1787 | values are returned in register %o0. */ |
| 1788 | |
| 1789 | void |
| 1790 | sparc_store_return_value (type, valbuf) |
| 1791 | struct type *type; |
| 1792 | char *valbuf; |
| 1793 | { |
| 1794 | int regno; |
| 1795 | char buffer[MAX_REGISTER_RAW_SIZE]; |
| 1796 | |
| 1797 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) |
| 1798 | /* Floating-point values are returned in the register pair */ |
| 1799 | /* formed by %f0 and %f1 (doubles are, anyway). */ |
| 1800 | regno = FP0_REGNUM; |
| 1801 | else |
| 1802 | /* Other values are returned in register %o0. */ |
| 1803 | regno = O0_REGNUM; |
| 1804 | |
| 1805 | /* Add leading zeros to the value. */ |
| 1806 | if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE(regno)) |
| 1807 | { |
| 1808 | bzero (buffer, REGISTER_RAW_SIZE(regno)); |
| 1809 | memcpy (buffer + REGISTER_RAW_SIZE(regno) - TYPE_LENGTH (type), valbuf, |
| 1810 | TYPE_LENGTH (type)); |
| 1811 | write_register_bytes (REGISTER_BYTE (regno), buffer, |
| 1812 | REGISTER_RAW_SIZE(regno)); |
| 1813 | } |
| 1814 | else |
| 1815 | write_register_bytes (REGISTER_BYTE (regno), valbuf, TYPE_LENGTH (type)); |
| 1816 | } |
| 1817 | |
| 1818 | |
| 1819 | /* Insert the function address into a call dummy instsruction sequence |
| 1820 | stored at DUMMY. |
| 1821 | |
| 1822 | For structs and unions, if the function was compiled with Sun cc, |
| 1823 | it expects 'unimp' after the call. But gcc doesn't use that |
| 1824 | (twisted) convention. So leave a nop there for gcc (FIX_CALL_DUMMY |
| 1825 | can assume it is operating on a pristine CALL_DUMMY, not one that |
| 1826 | has already been customized for a different function). */ |
| 1827 | |
| 1828 | void |
| 1829 | sparc_fix_call_dummy (dummy, pc, fun, value_type, using_gcc) |
| 1830 | char *dummy; |
| 1831 | CORE_ADDR pc; |
| 1832 | CORE_ADDR fun; |
| 1833 | struct type *value_type; |
| 1834 | int using_gcc; |
| 1835 | { |
| 1836 | int i; |
| 1837 | |
| 1838 | /* Store the relative adddress of the target function into the |
| 1839 | 'call' instruction. */ |
| 1840 | store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET, 4, |
| 1841 | (0x40000000 |
| 1842 | | (((fun - (pc + CALL_DUMMY_CALL_OFFSET)) >> 2) |
| 1843 | & 0x3fffffff))); |
| 1844 | |
| 1845 | /* Comply with strange Sun cc calling convention for struct-returning |
| 1846 | functions. */ |
| 1847 | if (!using_gcc |
| 1848 | && (TYPE_CODE (value_type) == TYPE_CODE_STRUCT |
| 1849 | || TYPE_CODE (value_type) == TYPE_CODE_UNION)) |
| 1850 | store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET + 8, 4, |
| 1851 | TYPE_LENGTH (value_type) & 0x1fff); |
| 1852 | |
| 1853 | #ifndef GDB_TARGET_IS_SPARC64 |
| 1854 | /* If this is not a simulator target, change the first four instructions |
| 1855 | of the call dummy to NOPs. Those instructions include a 'save' |
| 1856 | instruction and are designed to work around problems with register |
| 1857 | window flushing in the simulator. */ |
| 1858 | if (strcmp (target_shortname, "sim") != 0) |
| 1859 | { |
| 1860 | for (i = 0; i < 4; i++) |
| 1861 | store_unsigned_integer (dummy + (i * 4), 4, 0x01000000); |
| 1862 | } |
| 1863 | #endif |
| 1864 | } |
| 1865 | |
| 1866 | |
| 1867 | /* Set target byte order based on machine type. */ |
| 1868 | |
| 1869 | static int |
| 1870 | sparc_target_architecture_hook (ap) |
| 1871 | const bfd_arch_info_type *ap; |
| 1872 | { |
| 1873 | int i, j; |
| 1874 | |
| 1875 | #ifdef TARGET_BYTE_ORDER_SELECTABLE |
| 1876 | if (ap->mach == bfd_mach_sparc_sparclite_le) |
| 1877 | target_byte_order = LITTLE_ENDIAN; |
| 1878 | #endif |
| 1879 | return 1; |
| 1880 | } |
| 1881 | |
| 1882 | \f |
| 1883 | void |
| 1884 | _initialize_sparc_tdep () |
| 1885 | { |
| 1886 | tm_print_insn = gdb_print_insn_sparc; |
| 1887 | tm_print_insn_info.mach = TM_PRINT_INSN_MACH; /* Selects sparc/sparclite */ |
| 1888 | target_architecture_hook = sparc_target_architecture_hook; |
| 1889 | } |
| 1890 | |
| 1891 | |
| 1892 | #ifdef GDB_TARGET_IS_SPARC64 |
| 1893 | |
| 1894 | /* Compensate for stack bias. Note that we currently don't handle mixed |
| 1895 | 32/64 bit code. */ |
| 1896 | CORE_ADDR |
| 1897 | sparc64_read_sp () |
| 1898 | { |
| 1899 | CORE_ADDR sp = read_register (SP_REGNUM); |
| 1900 | |
| 1901 | if (sp & 1) |
| 1902 | sp += 2047; |
| 1903 | return sp; |
| 1904 | } |
| 1905 | |
| 1906 | CORE_ADDR |
| 1907 | sparc64_read_fp () |
| 1908 | { |
| 1909 | CORE_ADDR fp = read_register (FP_REGNUM); |
| 1910 | |
| 1911 | if (fp & 1) |
| 1912 | fp += 2047; |
| 1913 | return fp; |
| 1914 | } |
| 1915 | |
| 1916 | void |
| 1917 | sparc64_write_sp (val) |
| 1918 | CORE_ADDR val; |
| 1919 | { |
| 1920 | CORE_ADDR oldsp = read_register (SP_REGNUM); |
| 1921 | if (oldsp & 1) |
| 1922 | write_register (SP_REGNUM, val - 2047); |
| 1923 | else |
| 1924 | write_register (SP_REGNUM, val); |
| 1925 | } |
| 1926 | |
| 1927 | void |
| 1928 | sparc64_write_fp (val) |
| 1929 | CORE_ADDR val; |
| 1930 | { |
| 1931 | CORE_ADDR oldfp = read_register (FP_REGNUM); |
| 1932 | if (oldfp & 1) |
| 1933 | write_register (FP_REGNUM, val - 2047); |
| 1934 | else |
| 1935 | write_register (FP_REGNUM, val); |
| 1936 | } |
| 1937 | |
| 1938 | /* The SPARC 64 ABI passes floating-point arguments in FP0-31. They are |
| 1939 | also copied onto the stack in the correct places. */ |
| 1940 | |
| 1941 | CORE_ADDR |
| 1942 | sp64_push_arguments (nargs, args, sp, struct_return, struct_retaddr) |
| 1943 | int nargs; |
| 1944 | value_ptr *args; |
| 1945 | CORE_ADDR sp; |
| 1946 | unsigned char struct_return; |
| 1947 | CORE_ADDR struct_retaddr; |
| 1948 | { |
| 1949 | int x; |
| 1950 | int regnum = 0; |
| 1951 | CORE_ADDR tempsp; |
| 1952 | |
| 1953 | sp = (sp & ~(((unsigned long)TYPE_LENGTH (builtin_type_long)) - 1UL)); |
| 1954 | |
| 1955 | /* Figure out how much space we'll need. */ |
| 1956 | for (x = nargs - 1; x >= 0; x--) |
| 1957 | { |
| 1958 | int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[x]))); |
| 1959 | value_ptr copyarg = args[x]; |
| 1960 | int copylen = len; |
| 1961 | |
| 1962 | /* This code is, of course, no longer correct. */ |
| 1963 | if (copylen < TYPE_LENGTH (builtin_type_long)) |
| 1964 | { |
| 1965 | copyarg = value_cast(builtin_type_long, copyarg); |
| 1966 | copylen = TYPE_LENGTH (builtin_type_long); |
| 1967 | } |
| 1968 | sp -= copylen; |
| 1969 | } |
| 1970 | |
| 1971 | /* Round down. */ |
| 1972 | sp = sp & ~7; |
| 1973 | tempsp = sp; |
| 1974 | |
| 1975 | /* Now write the arguments onto the stack, while writing FP arguments |
| 1976 | into the FP registers. */ |
| 1977 | for (x = 0; x < nargs; x++) |
| 1978 | { |
| 1979 | int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[x]))); |
| 1980 | value_ptr copyarg = args[x]; |
| 1981 | int copylen = len; |
| 1982 | |
| 1983 | /* This code is, of course, no longer correct. */ |
| 1984 | if (copylen < TYPE_LENGTH (builtin_type_long)) |
| 1985 | { |
| 1986 | copyarg = value_cast(builtin_type_long, copyarg); |
| 1987 | copylen = TYPE_LENGTH (builtin_type_long); |
| 1988 | } |
| 1989 | write_memory (tempsp, VALUE_CONTENTS (copyarg), copylen); |
| 1990 | tempsp += copylen; |
| 1991 | if (TYPE_CODE (VALUE_TYPE (args[x])) == TYPE_CODE_FLT && regnum < 32) |
| 1992 | { |
| 1993 | /* This gets copied into a FP register. */ |
| 1994 | int nextreg = regnum + 2; |
| 1995 | char *data = VALUE_CONTENTS (args[x]); |
| 1996 | /* Floats go into the lower half of a FP register pair; quads |
| 1997 | use 2 pairs. */ |
| 1998 | |
| 1999 | if (len == 16) |
| 2000 | nextreg += 2; |
| 2001 | else if (len == 4) |
| 2002 | regnum++; |
| 2003 | |
| 2004 | write_register_bytes (REGISTER_BYTE (FP0_REGNUM + regnum), |
| 2005 | data, |
| 2006 | len); |
| 2007 | regnum = nextreg; |
| 2008 | } |
| 2009 | } |
| 2010 | return sp; |
| 2011 | } |
| 2012 | |
| 2013 | /* Values <= 32 bytes are returned in o0-o3 (floating-point values are |
| 2014 | returned in f0-f3). */ |
| 2015 | void |
| 2016 | sparc64_extract_return_value (type, regbuf, valbuf, bitoffset) |
| 2017 | struct type *type; |
| 2018 | char *regbuf; |
| 2019 | char *valbuf; |
| 2020 | int bitoffset; |
| 2021 | { |
| 2022 | int typelen = TYPE_LENGTH (type); |
| 2023 | int regsize = REGISTER_RAW_SIZE (O0_REGNUM); |
| 2024 | |
| 2025 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) |
| 2026 | { |
| 2027 | memcpy (valbuf, ®buf [REGISTER_BYTE (FP0_REGNUM)], typelen); |
| 2028 | return; |
| 2029 | } |
| 2030 | |
| 2031 | if (TYPE_CODE (type) != TYPE_CODE_STRUCT |
| 2032 | || (TYPE_LENGTH (type) > 32)) |
| 2033 | { |
| 2034 | memcpy (valbuf, |
| 2035 | ®buf [O0_REGNUM * regsize + |
| 2036 | (typelen >= regsize ? 0 : regsize - typelen)], |
| 2037 | typelen); |
| 2038 | return; |
| 2039 | } |
| 2040 | else |
| 2041 | { |
| 2042 | char *o0 = ®buf[O0_REGNUM * regsize]; |
| 2043 | char *f0 = ®buf[FP0_REGNUM * regsize]; |
| 2044 | int x; |
| 2045 | |
| 2046 | for (x = 0; x < TYPE_NFIELDS (type); x++) |
| 2047 | { |
| 2048 | struct field *f = &TYPE_FIELDS(type)[x]; |
| 2049 | /* FIXME: We may need to handle static fields here. */ |
| 2050 | int whichreg = (f->loc.bitpos + bitoffset) / 32; |
| 2051 | int remainder = ((f->loc.bitpos + bitoffset) % 32) / 8; |
| 2052 | int where = (f->loc.bitpos + bitoffset) / 8; |
| 2053 | int size = TYPE_LENGTH (f->type); |
| 2054 | int typecode = TYPE_CODE (f->type); |
| 2055 | |
| 2056 | if (typecode == TYPE_CODE_STRUCT) |
| 2057 | { |
| 2058 | sparc64_extract_return_value (f->type, |
| 2059 | regbuf, |
| 2060 | valbuf, |
| 2061 | bitoffset + f->loc.bitpos); |
| 2062 | } |
| 2063 | else if (typecode == TYPE_CODE_FLT) |
| 2064 | { |
| 2065 | memcpy (valbuf + where, &f0[whichreg * 4] + remainder, size); |
| 2066 | } |
| 2067 | else |
| 2068 | { |
| 2069 | memcpy (valbuf + where, &o0[whichreg * 4] + remainder, size); |
| 2070 | } |
| 2071 | } |
| 2072 | } |
| 2073 | } |
| 2074 | #endif |