| 1 | /* Target-dependent code for the SPARC for GDB, the GNU debugger. |
| 2 | Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997 |
| 3 | Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program; if not, write to the Free Software |
| 19 | Foundation, Inc., 59 Temple Place - Suite 330, |
| 20 | Boston, MA 02111-1307, USA. */ |
| 21 | |
| 22 | /* ??? Support for calling functions from gdb in sparc64 is unfinished. */ |
| 23 | |
| 24 | #include "defs.h" |
| 25 | #include "arch-utils.h" |
| 26 | #include "frame.h" |
| 27 | #include "inferior.h" |
| 28 | #include "obstack.h" |
| 29 | #include "target.h" |
| 30 | #include "value.h" |
| 31 | #include "bfd.h" |
| 32 | #include "gdb_string.h" |
| 33 | |
| 34 | #ifdef USE_PROC_FS |
| 35 | #include <sys/procfs.h> |
| 36 | /* Prototypes for supply_gregset etc. */ |
| 37 | #include "gregset.h" |
| 38 | #endif |
| 39 | |
| 40 | #include "gdbcore.h" |
| 41 | |
| 42 | #include "symfile.h" /* for 'entry_point_address' */ |
| 43 | |
| 44 | /* |
| 45 | * Some local macros that have multi-arch and non-multi-arch versions: |
| 46 | */ |
| 47 | |
| 48 | #if (GDB_MULTI_ARCH > 0) |
| 49 | |
| 50 | /* Does the target have Floating Point registers? */ |
| 51 | #define SPARC_HAS_FPU (gdbarch_tdep (current_gdbarch)->has_fpu) |
| 52 | /* Number of bytes devoted to Floating Point registers: */ |
| 53 | #define FP_REGISTER_BYTES (gdbarch_tdep (current_gdbarch)->fp_register_bytes) |
| 54 | /* Highest numbered Floating Point register. */ |
| 55 | #define FP_MAX_REGNUM (gdbarch_tdep (current_gdbarch)->fp_max_regnum) |
| 56 | /* Size of a general (integer) register: */ |
| 57 | #define SPARC_INTREG_SIZE (gdbarch_tdep (current_gdbarch)->intreg_size) |
| 58 | /* Offset within the call dummy stack of the saved registers. */ |
| 59 | #define DUMMY_REG_SAVE_OFFSET (gdbarch_tdep (current_gdbarch)->reg_save_offset) |
| 60 | |
| 61 | #else /* non-multi-arch */ |
| 62 | |
| 63 | |
| 64 | /* Does the target have Floating Point registers? */ |
| 65 | #if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE) |
| 66 | #define SPARC_HAS_FPU 0 |
| 67 | #else |
| 68 | #define SPARC_HAS_FPU 1 |
| 69 | #endif |
| 70 | |
| 71 | /* Number of bytes devoted to Floating Point registers: */ |
| 72 | #if (GDB_TARGET_IS_SPARC64) |
| 73 | #define FP_REGISTER_BYTES (64 * 4) |
| 74 | #else |
| 75 | #if (SPARC_HAS_FPU) |
| 76 | #define FP_REGISTER_BYTES (32 * 4) |
| 77 | #else |
| 78 | #define FP_REGISTER_BYTES 0 |
| 79 | #endif |
| 80 | #endif |
| 81 | |
| 82 | /* Highest numbered Floating Point register. */ |
| 83 | #if (GDB_TARGET_IS_SPARC64) |
| 84 | #define FP_MAX_REGNUM (FP0_REGNUM + 48) |
| 85 | #else |
| 86 | #define FP_MAX_REGNUM (FP0_REGNUM + 32) |
| 87 | #endif |
| 88 | |
| 89 | /* Size of a general (integer) register: */ |
| 90 | #define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM)) |
| 91 | |
| 92 | /* Offset within the call dummy stack of the saved registers. */ |
| 93 | #if (GDB_TARGET_IS_SPARC64) |
| 94 | #define DUMMY_REG_SAVE_OFFSET (128 + 16) |
| 95 | #else |
| 96 | #define DUMMY_REG_SAVE_OFFSET 0x60 |
| 97 | #endif |
| 98 | |
| 99 | #endif /* GDB_MULTI_ARCH */ |
| 100 | |
| 101 | struct gdbarch_tdep |
| 102 | { |
| 103 | int has_fpu; |
| 104 | int fp_register_bytes; |
| 105 | int y_regnum; |
| 106 | int fp_max_regnum; |
| 107 | int intreg_size; |
| 108 | int reg_save_offset; |
| 109 | int call_dummy_call_offset; |
| 110 | int print_insn_mach; |
| 111 | }; |
| 112 | |
| 113 | /* Now make GDB_TARGET_IS_SPARC64 a runtime test. */ |
| 114 | /* FIXME MVS: or try testing bfd_arch_info.arch and bfd_arch_info.mach ... |
| 115 | * define GDB_TARGET_IS_SPARC64 \ |
| 116 | * (TARGET_ARCHITECTURE->arch == bfd_arch_sparc && \ |
| 117 | * (TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9 || \ |
| 118 | * TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9a)) |
| 119 | */ |
| 120 | |
| 121 | /* From infrun.c */ |
| 122 | extern int stop_after_trap; |
| 123 | |
| 124 | /* We don't store all registers immediately when requested, since they |
| 125 | get sent over in large chunks anyway. Instead, we accumulate most |
| 126 | of the changes and send them over once. "deferred_stores" keeps |
| 127 | track of which sets of registers we have locally-changed copies of, |
| 128 | so we only need send the groups that have changed. */ |
| 129 | |
| 130 | int deferred_stores = 0; /* Accumulated stores we want to do eventually. */ |
| 131 | |
| 132 | |
| 133 | /* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode |
| 134 | where instructions are big-endian and data are little-endian. |
| 135 | This flag is set when we detect that the target is of this type. */ |
| 136 | |
| 137 | int bi_endian = 0; |
| 138 | |
| 139 | |
| 140 | /* Fetch a single instruction. Even on bi-endian machines |
| 141 | such as sparc86x, instructions are always big-endian. */ |
| 142 | |
| 143 | static unsigned long |
| 144 | fetch_instruction (CORE_ADDR pc) |
| 145 | { |
| 146 | unsigned long retval; |
| 147 | int i; |
| 148 | unsigned char buf[4]; |
| 149 | |
| 150 | read_memory (pc, buf, sizeof (buf)); |
| 151 | |
| 152 | /* Start at the most significant end of the integer, and work towards |
| 153 | the least significant. */ |
| 154 | retval = 0; |
| 155 | for (i = 0; i < sizeof (buf); ++i) |
| 156 | retval = (retval << 8) | buf[i]; |
| 157 | return retval; |
| 158 | } |
| 159 | |
| 160 | |
| 161 | /* Branches with prediction are treated like their non-predicting cousins. */ |
| 162 | /* FIXME: What about floating point branches? */ |
| 163 | |
| 164 | /* Macros to extract fields from sparc instructions. */ |
| 165 | #define X_OP(i) (((i) >> 30) & 0x3) |
| 166 | #define X_RD(i) (((i) >> 25) & 0x1f) |
| 167 | #define X_A(i) (((i) >> 29) & 1) |
| 168 | #define X_COND(i) (((i) >> 25) & 0xf) |
| 169 | #define X_OP2(i) (((i) >> 22) & 0x7) |
| 170 | #define X_IMM22(i) ((i) & 0x3fffff) |
| 171 | #define X_OP3(i) (((i) >> 19) & 0x3f) |
| 172 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
| 173 | #define X_I(i) (((i) >> 13) & 1) |
| 174 | #define X_IMM13(i) ((i) & 0x1fff) |
| 175 | /* Sign extension macros. */ |
| 176 | #define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000) |
| 177 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
| 178 | #define X_CC(i) (((i) >> 20) & 3) |
| 179 | #define X_P(i) (((i) >> 19) & 1) |
| 180 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
| 181 | #define X_RCOND(i) (((i) >> 25) & 7) |
| 182 | #define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000) |
| 183 | #define X_FCN(i) (((i) >> 25) & 31) |
| 184 | |
| 185 | typedef enum |
| 186 | { |
| 187 | Error, not_branch, bicc, bicca, ba, baa, ticc, ta, done_retry |
| 188 | } branch_type; |
| 189 | |
| 190 | /* Simulate single-step ptrace call for sun4. Code written by Gary |
| 191 | Beihl (beihl@mcc.com). */ |
| 192 | |
| 193 | /* npc4 and next_pc describe the situation at the time that the |
| 194 | step-breakpoint was set, not necessary the current value of NPC_REGNUM. */ |
| 195 | static CORE_ADDR next_pc, npc4, target; |
| 196 | static int brknpc4, brktrg; |
| 197 | typedef char binsn_quantum[BREAKPOINT_MAX]; |
| 198 | static binsn_quantum break_mem[3]; |
| 199 | |
| 200 | static branch_type isbranch (long, CORE_ADDR, CORE_ADDR *); |
| 201 | |
| 202 | /* single_step() is called just before we want to resume the inferior, |
| 203 | if we want to single-step it but there is no hardware or kernel single-step |
| 204 | support (as on all SPARCs). We find all the possible targets of the |
| 205 | coming instruction and breakpoint them. |
| 206 | |
| 207 | single_step is also called just after the inferior stops. If we had |
| 208 | set up a simulated single-step, we undo our damage. */ |
| 209 | |
| 210 | void |
| 211 | sparc_software_single_step (enum target_signal ignore, /* pid, but we don't need it */ |
| 212 | int insert_breakpoints_p) |
| 213 | { |
| 214 | branch_type br; |
| 215 | CORE_ADDR pc; |
| 216 | long pc_instruction; |
| 217 | |
| 218 | if (insert_breakpoints_p) |
| 219 | { |
| 220 | /* Always set breakpoint for NPC. */ |
| 221 | next_pc = read_register (NPC_REGNUM); |
| 222 | npc4 = next_pc + 4; /* branch not taken */ |
| 223 | |
| 224 | target_insert_breakpoint (next_pc, break_mem[0]); |
| 225 | /* printf_unfiltered ("set break at %x\n",next_pc); */ |
| 226 | |
| 227 | pc = read_register (PC_REGNUM); |
| 228 | pc_instruction = fetch_instruction (pc); |
| 229 | br = isbranch (pc_instruction, pc, &target); |
| 230 | brknpc4 = brktrg = 0; |
| 231 | |
| 232 | if (br == bicca) |
| 233 | { |
| 234 | /* Conditional annulled branch will either end up at |
| 235 | npc (if taken) or at npc+4 (if not taken). |
| 236 | Trap npc+4. */ |
| 237 | brknpc4 = 1; |
| 238 | target_insert_breakpoint (npc4, break_mem[1]); |
| 239 | } |
| 240 | else if (br == baa && target != next_pc) |
| 241 | { |
| 242 | /* Unconditional annulled branch will always end up at |
| 243 | the target. */ |
| 244 | brktrg = 1; |
| 245 | target_insert_breakpoint (target, break_mem[2]); |
| 246 | } |
| 247 | else if (GDB_TARGET_IS_SPARC64 && br == done_retry) |
| 248 | { |
| 249 | brktrg = 1; |
| 250 | target_insert_breakpoint (target, break_mem[2]); |
| 251 | } |
| 252 | } |
| 253 | else |
| 254 | { |
| 255 | /* Remove breakpoints */ |
| 256 | target_remove_breakpoint (next_pc, break_mem[0]); |
| 257 | |
| 258 | if (brknpc4) |
| 259 | target_remove_breakpoint (npc4, break_mem[1]); |
| 260 | |
| 261 | if (brktrg) |
| 262 | target_remove_breakpoint (target, break_mem[2]); |
| 263 | } |
| 264 | } |
| 265 | \f |
| 266 | struct frame_extra_info |
| 267 | { |
| 268 | CORE_ADDR bottom; |
| 269 | int in_prologue; |
| 270 | int flat; |
| 271 | /* Following fields only relevant for flat frames. */ |
| 272 | CORE_ADDR pc_addr; |
| 273 | CORE_ADDR fp_addr; |
| 274 | /* Add this to ->frame to get the value of the stack pointer at the |
| 275 | time of the register saves. */ |
| 276 | int sp_offset; |
| 277 | }; |
| 278 | |
| 279 | /* Call this for each newly created frame. For SPARC, we need to |
| 280 | calculate the bottom of the frame, and do some extra work if the |
| 281 | prologue has been generated via the -mflat option to GCC. In |
| 282 | particular, we need to know where the previous fp and the pc have |
| 283 | been stashed, since their exact position within the frame may vary. */ |
| 284 | |
| 285 | void |
| 286 | sparc_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
| 287 | { |
| 288 | char *name; |
| 289 | CORE_ADDR prologue_start, prologue_end; |
| 290 | int insn; |
| 291 | |
| 292 | fi->extra_info = (struct frame_extra_info *) |
| 293 | frame_obstack_alloc (sizeof (struct frame_extra_info)); |
| 294 | frame_saved_regs_zalloc (fi); |
| 295 | |
| 296 | fi->extra_info->bottom = |
| 297 | (fi->next ? |
| 298 | (fi->frame == fi->next->frame ? fi->next->extra_info->bottom : |
| 299 | fi->next->frame) : read_sp ()); |
| 300 | |
| 301 | /* If fi->next is NULL, then we already set ->frame by passing read_fp() |
| 302 | to create_new_frame. */ |
| 303 | if (fi->next) |
| 304 | { |
| 305 | char *buf; |
| 306 | |
| 307 | buf = alloca (MAX_REGISTER_RAW_SIZE); |
| 308 | |
| 309 | /* Compute ->frame as if not flat. If it is flat, we'll change |
| 310 | it later. */ |
| 311 | if (fi->next->next != NULL |
| 312 | && (fi->next->next->signal_handler_caller |
| 313 | || frame_in_dummy (fi->next->next)) |
| 314 | && frameless_look_for_prologue (fi->next)) |
| 315 | { |
| 316 | /* A frameless function interrupted by a signal did not change |
| 317 | the frame pointer, fix up frame pointer accordingly. */ |
| 318 | fi->frame = FRAME_FP (fi->next); |
| 319 | fi->extra_info->bottom = fi->next->extra_info->bottom; |
| 320 | } |
| 321 | else |
| 322 | { |
| 323 | /* Should we adjust for stack bias here? */ |
| 324 | get_saved_register (buf, 0, 0, fi, FP_REGNUM, 0); |
| 325 | fi->frame = extract_address (buf, REGISTER_RAW_SIZE (FP_REGNUM)); |
| 326 | |
| 327 | if (GDB_TARGET_IS_SPARC64 && (fi->frame & 1)) |
| 328 | fi->frame += 2047; |
| 329 | } |
| 330 | } |
| 331 | |
| 332 | /* Decide whether this is a function with a ``flat register window'' |
| 333 | frame. For such functions, the frame pointer is actually in %i7. */ |
| 334 | fi->extra_info->flat = 0; |
| 335 | fi->extra_info->in_prologue = 0; |
| 336 | if (find_pc_partial_function (fi->pc, &name, &prologue_start, &prologue_end)) |
| 337 | { |
| 338 | /* See if the function starts with an add (which will be of a |
| 339 | negative number if a flat frame) to the sp. FIXME: Does not |
| 340 | handle large frames which will need more than one instruction |
| 341 | to adjust the sp. */ |
| 342 | insn = fetch_instruction (prologue_start); |
| 343 | if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0 |
| 344 | && X_I (insn) && X_SIMM13 (insn) < 0) |
| 345 | { |
| 346 | int offset = X_SIMM13 (insn); |
| 347 | |
| 348 | /* Then look for a save of %i7 into the frame. */ |
| 349 | insn = fetch_instruction (prologue_start + 4); |
| 350 | if (X_OP (insn) == 3 |
| 351 | && X_RD (insn) == 31 |
| 352 | && X_OP3 (insn) == 4 |
| 353 | && X_RS1 (insn) == 14) |
| 354 | { |
| 355 | char *buf; |
| 356 | |
| 357 | buf = alloca (MAX_REGISTER_RAW_SIZE); |
| 358 | |
| 359 | /* We definitely have a flat frame now. */ |
| 360 | fi->extra_info->flat = 1; |
| 361 | |
| 362 | fi->extra_info->sp_offset = offset; |
| 363 | |
| 364 | /* Overwrite the frame's address with the value in %i7. */ |
| 365 | get_saved_register (buf, 0, 0, fi, I7_REGNUM, 0); |
| 366 | fi->frame = extract_address (buf, REGISTER_RAW_SIZE (I7_REGNUM)); |
| 367 | |
| 368 | if (GDB_TARGET_IS_SPARC64 && (fi->frame & 1)) |
| 369 | fi->frame += 2047; |
| 370 | |
| 371 | /* Record where the fp got saved. */ |
| 372 | fi->extra_info->fp_addr = |
| 373 | fi->frame + fi->extra_info->sp_offset + X_SIMM13 (insn); |
| 374 | |
| 375 | /* Also try to collect where the pc got saved to. */ |
| 376 | fi->extra_info->pc_addr = 0; |
| 377 | insn = fetch_instruction (prologue_start + 12); |
| 378 | if (X_OP (insn) == 3 |
| 379 | && X_RD (insn) == 15 |
| 380 | && X_OP3 (insn) == 4 |
| 381 | && X_RS1 (insn) == 14) |
| 382 | fi->extra_info->pc_addr = |
| 383 | fi->frame + fi->extra_info->sp_offset + X_SIMM13 (insn); |
| 384 | } |
| 385 | } |
| 386 | else |
| 387 | { |
| 388 | /* Check if the PC is in the function prologue before a SAVE |
| 389 | instruction has been executed yet. If so, set the frame |
| 390 | to the current value of the stack pointer and set |
| 391 | the in_prologue flag. */ |
| 392 | CORE_ADDR addr; |
| 393 | struct symtab_and_line sal; |
| 394 | |
| 395 | sal = find_pc_line (prologue_start, 0); |
| 396 | if (sal.line == 0) /* no line info, use PC */ |
| 397 | prologue_end = fi->pc; |
| 398 | else if (sal.end < prologue_end) |
| 399 | prologue_end = sal.end; |
| 400 | if (fi->pc < prologue_end) |
| 401 | { |
| 402 | for (addr = prologue_start; addr < fi->pc; addr += 4) |
| 403 | { |
| 404 | insn = read_memory_integer (addr, 4); |
| 405 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) |
| 406 | break; /* SAVE seen, stop searching */ |
| 407 | } |
| 408 | if (addr >= fi->pc) |
| 409 | { |
| 410 | fi->extra_info->in_prologue = 1; |
| 411 | fi->frame = read_register (SP_REGNUM); |
| 412 | } |
| 413 | } |
| 414 | } |
| 415 | } |
| 416 | if (fi->next && fi->frame == 0) |
| 417 | { |
| 418 | /* Kludge to cause init_prev_frame_info to destroy the new frame. */ |
| 419 | fi->frame = fi->next->frame; |
| 420 | fi->pc = fi->next->pc; |
| 421 | } |
| 422 | } |
| 423 | |
| 424 | CORE_ADDR |
| 425 | sparc_frame_chain (struct frame_info *frame) |
| 426 | { |
| 427 | /* Value that will cause FRAME_CHAIN_VALID to not worry about the chain |
| 428 | value. If it realy is zero, we detect it later in |
| 429 | sparc_init_prev_frame. */ |
| 430 | return (CORE_ADDR) 1; |
| 431 | } |
| 432 | |
| 433 | CORE_ADDR |
| 434 | sparc_extract_struct_value_address (char *regbuf) |
| 435 | { |
| 436 | return extract_address (regbuf + REGISTER_BYTE (O0_REGNUM), |
| 437 | REGISTER_RAW_SIZE (O0_REGNUM)); |
| 438 | } |
| 439 | |
| 440 | /* Find the pc saved in frame FRAME. */ |
| 441 | |
| 442 | CORE_ADDR |
| 443 | sparc_frame_saved_pc (struct frame_info *frame) |
| 444 | { |
| 445 | char *buf; |
| 446 | CORE_ADDR addr; |
| 447 | |
| 448 | buf = alloca (MAX_REGISTER_RAW_SIZE); |
| 449 | if (frame->signal_handler_caller) |
| 450 | { |
| 451 | /* This is the signal trampoline frame. |
| 452 | Get the saved PC from the sigcontext structure. */ |
| 453 | |
| 454 | #ifndef SIGCONTEXT_PC_OFFSET |
| 455 | #define SIGCONTEXT_PC_OFFSET 12 |
| 456 | #endif |
| 457 | |
| 458 | CORE_ADDR sigcontext_addr; |
| 459 | char *scbuf; |
| 460 | int saved_pc_offset = SIGCONTEXT_PC_OFFSET; |
| 461 | char *name = NULL; |
| 462 | |
| 463 | scbuf = alloca (TARGET_PTR_BIT / HOST_CHAR_BIT); |
| 464 | |
| 465 | /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext |
| 466 | as the third parameter. The offset to the saved pc is 12. */ |
| 467 | find_pc_partial_function (frame->pc, &name, |
| 468 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
| 469 | if (name && STREQ (name, "ucbsigvechandler")) |
| 470 | saved_pc_offset = 12; |
| 471 | |
| 472 | /* The sigcontext address is contained in register O2. */ |
| 473 | get_saved_register (buf, (int *) NULL, (CORE_ADDR *) NULL, |
| 474 | frame, O0_REGNUM + 2, (enum lval_type *) NULL); |
| 475 | sigcontext_addr = extract_address (buf, REGISTER_RAW_SIZE (O0_REGNUM + 2)); |
| 476 | |
| 477 | /* Don't cause a memory_error when accessing sigcontext in case the |
| 478 | stack layout has changed or the stack is corrupt. */ |
| 479 | target_read_memory (sigcontext_addr + saved_pc_offset, |
| 480 | scbuf, sizeof (scbuf)); |
| 481 | return extract_address (scbuf, sizeof (scbuf)); |
| 482 | } |
| 483 | else if (frame->extra_info->in_prologue || |
| 484 | (frame->next != NULL && |
| 485 | (frame->next->signal_handler_caller || |
| 486 | frame_in_dummy (frame->next)) && |
| 487 | frameless_look_for_prologue (frame))) |
| 488 | { |
| 489 | /* A frameless function interrupted by a signal did not save |
| 490 | the PC, it is still in %o7. */ |
| 491 | get_saved_register (buf, (int *) NULL, (CORE_ADDR *) NULL, |
| 492 | frame, O7_REGNUM, (enum lval_type *) NULL); |
| 493 | return PC_ADJUST (extract_address (buf, SPARC_INTREG_SIZE)); |
| 494 | } |
| 495 | if (frame->extra_info->flat) |
| 496 | addr = frame->extra_info->pc_addr; |
| 497 | else |
| 498 | addr = frame->extra_info->bottom + FRAME_SAVED_I0 + |
| 499 | SPARC_INTREG_SIZE * (I7_REGNUM - I0_REGNUM); |
| 500 | |
| 501 | if (addr == 0) |
| 502 | /* A flat frame leaf function might not save the PC anywhere, |
| 503 | just leave it in %o7. */ |
| 504 | return PC_ADJUST (read_register (O7_REGNUM)); |
| 505 | |
| 506 | read_memory (addr, buf, SPARC_INTREG_SIZE); |
| 507 | return PC_ADJUST (extract_address (buf, SPARC_INTREG_SIZE)); |
| 508 | } |
| 509 | |
| 510 | /* Since an individual frame in the frame cache is defined by two |
| 511 | arguments (a frame pointer and a stack pointer), we need two |
| 512 | arguments to get info for an arbitrary stack frame. This routine |
| 513 | takes two arguments and makes the cached frames look as if these |
| 514 | two arguments defined a frame on the cache. This allows the rest |
| 515 | of info frame to extract the important arguments without |
| 516 | difficulty. */ |
| 517 | |
| 518 | struct frame_info * |
| 519 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
| 520 | { |
| 521 | struct frame_info *frame; |
| 522 | |
| 523 | if (argc != 2) |
| 524 | error ("Sparc frame specifications require two arguments: fp and sp"); |
| 525 | |
| 526 | frame = create_new_frame (argv[0], 0); |
| 527 | |
| 528 | if (!frame) |
| 529 | internal_error ("create_new_frame returned invalid frame"); |
| 530 | |
| 531 | frame->extra_info->bottom = argv[1]; |
| 532 | frame->pc = FRAME_SAVED_PC (frame); |
| 533 | return frame; |
| 534 | } |
| 535 | |
| 536 | /* Given a pc value, skip it forward past the function prologue by |
| 537 | disassembling instructions that appear to be a prologue. |
| 538 | |
| 539 | If FRAMELESS_P is set, we are only testing to see if the function |
| 540 | is frameless. This allows a quicker answer. |
| 541 | |
| 542 | This routine should be more specific in its actions; making sure |
| 543 | that it uses the same register in the initial prologue section. */ |
| 544 | |
| 545 | static CORE_ADDR examine_prologue (CORE_ADDR, int, struct frame_info *, |
| 546 | CORE_ADDR *); |
| 547 | |
| 548 | static CORE_ADDR |
| 549 | examine_prologue (CORE_ADDR start_pc, int frameless_p, struct frame_info *fi, |
| 550 | CORE_ADDR *saved_regs) |
| 551 | { |
| 552 | int insn; |
| 553 | int dest = -1; |
| 554 | CORE_ADDR pc = start_pc; |
| 555 | int is_flat = 0; |
| 556 | |
| 557 | insn = fetch_instruction (pc); |
| 558 | |
| 559 | /* Recognize the `sethi' insn and record its destination. */ |
| 560 | if (X_OP (insn) == 0 && X_OP2 (insn) == 4) |
| 561 | { |
| 562 | dest = X_RD (insn); |
| 563 | pc += 4; |
| 564 | insn = fetch_instruction (pc); |
| 565 | } |
| 566 | |
| 567 | /* Recognize an add immediate value to register to either %g1 or |
| 568 | the destination register recorded above. Actually, this might |
| 569 | well recognize several different arithmetic operations. |
| 570 | It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1" |
| 571 | followed by "save %sp, %g1, %sp" is a valid prologue (Not that |
| 572 | I imagine any compiler really does that, however). */ |
| 573 | if (X_OP (insn) == 2 |
| 574 | && X_I (insn) |
| 575 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
| 576 | { |
| 577 | pc += 4; |
| 578 | insn = fetch_instruction (pc); |
| 579 | } |
| 580 | |
| 581 | /* Recognize any SAVE insn. */ |
| 582 | if (X_OP (insn) == 2 && X_OP3 (insn) == 60) |
| 583 | { |
| 584 | pc += 4; |
| 585 | if (frameless_p) /* If the save is all we care about, */ |
| 586 | return pc; /* return before doing more work */ |
| 587 | insn = fetch_instruction (pc); |
| 588 | } |
| 589 | /* Recognize add to %sp. */ |
| 590 | else if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0) |
| 591 | { |
| 592 | pc += 4; |
| 593 | if (frameless_p) /* If the add is all we care about, */ |
| 594 | return pc; /* return before doing more work */ |
| 595 | is_flat = 1; |
| 596 | insn = fetch_instruction (pc); |
| 597 | /* Recognize store of frame pointer (i7). */ |
| 598 | if (X_OP (insn) == 3 |
| 599 | && X_RD (insn) == 31 |
| 600 | && X_OP3 (insn) == 4 |
| 601 | && X_RS1 (insn) == 14) |
| 602 | { |
| 603 | pc += 4; |
| 604 | insn = fetch_instruction (pc); |
| 605 | |
| 606 | /* Recognize sub %sp, <anything>, %i7. */ |
| 607 | if (X_OP (insn) == 2 |
| 608 | && X_OP3 (insn) == 4 |
| 609 | && X_RS1 (insn) == 14 |
| 610 | && X_RD (insn) == 31) |
| 611 | { |
| 612 | pc += 4; |
| 613 | insn = fetch_instruction (pc); |
| 614 | } |
| 615 | else |
| 616 | return pc; |
| 617 | } |
| 618 | else |
| 619 | return pc; |
| 620 | } |
| 621 | else |
| 622 | /* Without a save or add instruction, it's not a prologue. */ |
| 623 | return start_pc; |
| 624 | |
| 625 | while (1) |
| 626 | { |
| 627 | /* Recognize stores into the frame from the input registers. |
| 628 | This recognizes all non alternate stores of an input register, |
| 629 | into a location offset from the frame pointer between |
| 630 | +68 and +92. */ |
| 631 | |
| 632 | /* The above will fail for arguments that are promoted |
| 633 | (eg. shorts to ints or floats to doubles), because the compiler |
| 634 | will pass them in positive-offset frame space, but the prologue |
| 635 | will save them (after conversion) in negative frame space at an |
| 636 | unpredictable offset. Therefore I am going to remove the |
| 637 | restriction on the target-address of the save, on the theory |
| 638 | that any unbroken sequence of saves from input registers must |
| 639 | be part of the prologue. In un-optimized code (at least), I'm |
| 640 | fairly sure that the compiler would emit SOME other instruction |
| 641 | (eg. a move or add) before emitting another save that is actually |
| 642 | a part of the function body. |
| 643 | |
| 644 | Besides, the reserved stack space is different for SPARC64 anyway. |
| 645 | |
| 646 | MVS 4/23/2000 */ |
| 647 | |
| 648 | if (X_OP (insn) == 3 |
| 649 | && (X_OP3 (insn) & 0x3c) == 4 /* Store, non-alternate. */ |
| 650 | && (X_RD (insn) & 0x18) == 0x18 /* Input register. */ |
| 651 | && X_I (insn) /* Immediate mode. */ |
| 652 | && X_RS1 (insn) == 30) /* Off of frame pointer. */ |
| 653 | ; /* empty statement -- fall thru to end of loop */ |
| 654 | else if (GDB_TARGET_IS_SPARC64 |
| 655 | && X_OP (insn) == 3 |
| 656 | && (X_OP3 (insn) & 0x3c) == 12 /* store, extended (64-bit) */ |
| 657 | && (X_RD (insn) & 0x18) == 0x18 /* input register */ |
| 658 | && X_I (insn) /* immediate mode */ |
| 659 | && X_RS1 (insn) == 30) /* off of frame pointer */ |
| 660 | ; /* empty statement -- fall thru to end of loop */ |
| 661 | else if (X_OP (insn) == 3 |
| 662 | && (X_OP3 (insn) & 0x3c) == 36 /* store, floating-point */ |
| 663 | && X_I (insn) /* immediate mode */ |
| 664 | && X_RS1 (insn) == 30) /* off of frame pointer */ |
| 665 | ; /* empty statement -- fall thru to end of loop */ |
| 666 | else if (is_flat |
| 667 | && X_OP (insn) == 3 |
| 668 | && X_OP3 (insn) == 4 /* store? */ |
| 669 | && X_RS1 (insn) == 14) /* off of frame pointer */ |
| 670 | { |
| 671 | if (saved_regs && X_I (insn)) |
| 672 | saved_regs[X_RD (insn)] = |
| 673 | fi->frame + fi->extra_info->sp_offset + X_SIMM13 (insn); |
| 674 | } |
| 675 | else |
| 676 | break; |
| 677 | pc += 4; |
| 678 | insn = fetch_instruction (pc); |
| 679 | } |
| 680 | |
| 681 | return pc; |
| 682 | } |
| 683 | |
| 684 | CORE_ADDR |
| 685 | sparc_skip_prologue (CORE_ADDR start_pc, int frameless_p) |
| 686 | { |
| 687 | return examine_prologue (start_pc, frameless_p, NULL, NULL); |
| 688 | } |
| 689 | |
| 690 | /* Check instruction at ADDR to see if it is a branch. |
| 691 | All non-annulled instructions will go to NPC or will trap. |
| 692 | Set *TARGET if we find a candidate branch; set to zero if not. |
| 693 | |
| 694 | This isn't static as it's used by remote-sa.sparc.c. */ |
| 695 | |
| 696 | static branch_type |
| 697 | isbranch (long instruction, CORE_ADDR addr, CORE_ADDR *target) |
| 698 | { |
| 699 | branch_type val = not_branch; |
| 700 | long int offset = 0; /* Must be signed for sign-extend. */ |
| 701 | |
| 702 | *target = 0; |
| 703 | |
| 704 | if (X_OP (instruction) == 0 |
| 705 | && (X_OP2 (instruction) == 2 |
| 706 | || X_OP2 (instruction) == 6 |
| 707 | || X_OP2 (instruction) == 1 |
| 708 | || X_OP2 (instruction) == 3 |
| 709 | || X_OP2 (instruction) == 5 |
| 710 | || (GDB_TARGET_IS_SPARC64 && X_OP2 (instruction) == 7))) |
| 711 | { |
| 712 | if (X_COND (instruction) == 8) |
| 713 | val = X_A (instruction) ? baa : ba; |
| 714 | else |
| 715 | val = X_A (instruction) ? bicca : bicc; |
| 716 | switch (X_OP2 (instruction)) |
| 717 | { |
| 718 | case 7: |
| 719 | if (!GDB_TARGET_IS_SPARC64) |
| 720 | break; |
| 721 | /* else fall thru */ |
| 722 | case 2: |
| 723 | case 6: |
| 724 | offset = 4 * X_DISP22 (instruction); |
| 725 | break; |
| 726 | case 1: |
| 727 | case 5: |
| 728 | offset = 4 * X_DISP19 (instruction); |
| 729 | break; |
| 730 | case 3: |
| 731 | offset = 4 * X_DISP16 (instruction); |
| 732 | break; |
| 733 | } |
| 734 | *target = addr + offset; |
| 735 | } |
| 736 | else if (GDB_TARGET_IS_SPARC64 |
| 737 | && X_OP (instruction) == 2 |
| 738 | && X_OP3 (instruction) == 62) |
| 739 | { |
| 740 | if (X_FCN (instruction) == 0) |
| 741 | { |
| 742 | /* done */ |
| 743 | *target = read_register (TNPC_REGNUM); |
| 744 | val = done_retry; |
| 745 | } |
| 746 | else if (X_FCN (instruction) == 1) |
| 747 | { |
| 748 | /* retry */ |
| 749 | *target = read_register (TPC_REGNUM); |
| 750 | val = done_retry; |
| 751 | } |
| 752 | } |
| 753 | |
| 754 | return val; |
| 755 | } |
| 756 | \f |
| 757 | /* Find register number REGNUM relative to FRAME and put its |
| 758 | (raw) contents in *RAW_BUFFER. Set *OPTIMIZED if the variable |
| 759 | was optimized out (and thus can't be fetched). If the variable |
| 760 | was fetched from memory, set *ADDRP to where it was fetched from, |
| 761 | otherwise it was fetched from a register. |
| 762 | |
| 763 | The argument RAW_BUFFER must point to aligned memory. */ |
| 764 | |
| 765 | void |
| 766 | sparc_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp, |
| 767 | struct frame_info *frame, int regnum, |
| 768 | enum lval_type *lval) |
| 769 | { |
| 770 | struct frame_info *frame1; |
| 771 | CORE_ADDR addr; |
| 772 | |
| 773 | if (!target_has_registers) |
| 774 | error ("No registers."); |
| 775 | |
| 776 | if (optimized) |
| 777 | *optimized = 0; |
| 778 | |
| 779 | addr = 0; |
| 780 | |
| 781 | /* FIXME This code extracted from infcmd.c; should put elsewhere! */ |
| 782 | if (frame == NULL) |
| 783 | { |
| 784 | /* error ("No selected frame."); */ |
| 785 | if (!target_has_registers) |
| 786 | error ("The program has no registers now."); |
| 787 | if (selected_frame == NULL) |
| 788 | error ("No selected frame."); |
| 789 | /* Try to use selected frame */ |
| 790 | frame = get_prev_frame (selected_frame); |
| 791 | if (frame == 0) |
| 792 | error ("Cmd not meaningful in the outermost frame."); |
| 793 | } |
| 794 | |
| 795 | |
| 796 | frame1 = frame->next; |
| 797 | |
| 798 | /* Get saved PC from the frame info if not in innermost frame. */ |
| 799 | if (regnum == PC_REGNUM && frame1 != NULL) |
| 800 | { |
| 801 | if (lval != NULL) |
| 802 | *lval = not_lval; |
| 803 | if (raw_buffer != NULL) |
| 804 | { |
| 805 | /* Put it back in target format. */ |
| 806 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), frame->pc); |
| 807 | } |
| 808 | if (addrp != NULL) |
| 809 | *addrp = 0; |
| 810 | return; |
| 811 | } |
| 812 | |
| 813 | while (frame1 != NULL) |
| 814 | { |
| 815 | /* FIXME MVS: wrong test for dummy frame at entry. */ |
| 816 | |
| 817 | if (frame1->pc >= (frame1->extra_info->bottom ? |
| 818 | frame1->extra_info->bottom : read_sp ()) |
| 819 | && frame1->pc <= FRAME_FP (frame1)) |
| 820 | { |
| 821 | /* Dummy frame. All but the window regs are in there somewhere. |
| 822 | The window registers are saved on the stack, just like in a |
| 823 | normal frame. */ |
| 824 | if (regnum >= G1_REGNUM && regnum < G1_REGNUM + 7) |
| 825 | addr = frame1->frame + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE |
| 826 | - (FP_REGISTER_BYTES + 8 * SPARC_INTREG_SIZE); |
| 827 | else if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8) |
| 828 | addr = (frame1->prev->extra_info->bottom |
| 829 | + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
| 830 | + FRAME_SAVED_I0); |
| 831 | else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8) |
| 832 | addr = (frame1->prev->extra_info->bottom |
| 833 | + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE |
| 834 | + FRAME_SAVED_L0); |
| 835 | else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8) |
| 836 | addr = frame1->frame + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE |
| 837 | - (FP_REGISTER_BYTES + 16 * SPARC_INTREG_SIZE); |
| 838 | else if (SPARC_HAS_FPU && |
| 839 | regnum >= FP0_REGNUM && regnum < FP0_REGNUM + 32) |
| 840 | addr = frame1->frame + (regnum - FP0_REGNUM) * 4 |
| 841 | - (FP_REGISTER_BYTES); |
| 842 | else if (GDB_TARGET_IS_SPARC64 && SPARC_HAS_FPU && |
| 843 | regnum >= FP0_REGNUM + 32 && regnum < FP_MAX_REGNUM) |
| 844 | addr = frame1->frame + 32 * 4 + (regnum - FP0_REGNUM - 32) * 8 |
| 845 | - (FP_REGISTER_BYTES); |
| 846 | else if (regnum >= Y_REGNUM && regnum < NUM_REGS) |
| 847 | addr = frame1->frame + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE |
| 848 | - (FP_REGISTER_BYTES + 24 * SPARC_INTREG_SIZE); |
| 849 | } |
| 850 | else if (frame1->extra_info->flat) |
| 851 | { |
| 852 | |
| 853 | if (regnum == RP_REGNUM) |
| 854 | addr = frame1->extra_info->pc_addr; |
| 855 | else if (regnum == I7_REGNUM) |
| 856 | addr = frame1->extra_info->fp_addr; |
| 857 | else |
| 858 | { |
| 859 | CORE_ADDR func_start; |
| 860 | CORE_ADDR *regs; |
| 861 | |
| 862 | regs = alloca (NUM_REGS * sizeof (CORE_ADDR)); |
| 863 | memset (regs, 0, NUM_REGS * sizeof (CORE_ADDR)); |
| 864 | |
| 865 | find_pc_partial_function (frame1->pc, NULL, &func_start, NULL); |
| 866 | examine_prologue (func_start, 0, frame1, regs); |
| 867 | addr = regs[regnum]; |
| 868 | } |
| 869 | } |
| 870 | else |
| 871 | { |
| 872 | /* Normal frame. Local and In registers are saved on stack. */ |
| 873 | if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8) |
| 874 | addr = (frame1->prev->extra_info->bottom |
| 875 | + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
| 876 | + FRAME_SAVED_I0); |
| 877 | else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8) |
| 878 | addr = (frame1->prev->extra_info->bottom |
| 879 | + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE |
| 880 | + FRAME_SAVED_L0); |
| 881 | else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8) |
| 882 | { |
| 883 | /* Outs become ins. */ |
| 884 | get_saved_register (raw_buffer, optimized, addrp, frame1, |
| 885 | (regnum - O0_REGNUM + I0_REGNUM), lval); |
| 886 | return; |
| 887 | } |
| 888 | } |
| 889 | if (addr != 0) |
| 890 | break; |
| 891 | frame1 = frame1->next; |
| 892 | } |
| 893 | if (addr != 0) |
| 894 | { |
| 895 | if (lval != NULL) |
| 896 | *lval = lval_memory; |
| 897 | if (regnum == SP_REGNUM) |
| 898 | { |
| 899 | if (raw_buffer != NULL) |
| 900 | { |
| 901 | /* Put it back in target format. */ |
| 902 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), addr); |
| 903 | } |
| 904 | if (addrp != NULL) |
| 905 | *addrp = 0; |
| 906 | return; |
| 907 | } |
| 908 | if (raw_buffer != NULL) |
| 909 | read_memory (addr, raw_buffer, REGISTER_RAW_SIZE (regnum)); |
| 910 | } |
| 911 | else |
| 912 | { |
| 913 | if (lval != NULL) |
| 914 | *lval = lval_register; |
| 915 | addr = REGISTER_BYTE (regnum); |
| 916 | if (raw_buffer != NULL) |
| 917 | read_register_gen (regnum, raw_buffer); |
| 918 | } |
| 919 | if (addrp != NULL) |
| 920 | *addrp = addr; |
| 921 | } |
| 922 | |
| 923 | /* Push an empty stack frame, and record in it the current PC, regs, etc. |
| 924 | |
| 925 | We save the non-windowed registers and the ins. The locals and outs |
| 926 | are new; they don't need to be saved. The i's and l's of |
| 927 | the last frame were already saved on the stack. */ |
| 928 | |
| 929 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ |
| 930 | |
| 931 | /* See tm-sparc.h for how this is calculated. */ |
| 932 | |
| 933 | #define DUMMY_STACK_REG_BUF_SIZE \ |
| 934 | (((8+8+8) * SPARC_INTREG_SIZE) + FP_REGISTER_BYTES) |
| 935 | #define DUMMY_STACK_SIZE \ |
| 936 | (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET) |
| 937 | |
| 938 | void |
| 939 | sparc_push_dummy_frame (void) |
| 940 | { |
| 941 | CORE_ADDR sp, old_sp; |
| 942 | char *register_temp; |
| 943 | |
| 944 | register_temp = alloca (DUMMY_STACK_SIZE); |
| 945 | |
| 946 | old_sp = sp = read_sp (); |
| 947 | |
| 948 | if (GDB_TARGET_IS_SPARC64) |
| 949 | { |
| 950 | /* PC, NPC, CCR, FSR, FPRS, Y, ASI */ |
| 951 | read_register_bytes (REGISTER_BYTE (PC_REGNUM), ®ister_temp[0], |
| 952 | REGISTER_RAW_SIZE (PC_REGNUM) * 7); |
| 953 | read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM), |
| 954 | ®ister_temp[7 * SPARC_INTREG_SIZE], |
| 955 | REGISTER_RAW_SIZE (PSTATE_REGNUM)); |
| 956 | /* FIXME: not sure what needs to be saved here. */ |
| 957 | } |
| 958 | else |
| 959 | { |
| 960 | /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */ |
| 961 | read_register_bytes (REGISTER_BYTE (Y_REGNUM), ®ister_temp[0], |
| 962 | REGISTER_RAW_SIZE (Y_REGNUM) * 8); |
| 963 | } |
| 964 | |
| 965 | read_register_bytes (REGISTER_BYTE (O0_REGNUM), |
| 966 | ®ister_temp[8 * SPARC_INTREG_SIZE], |
| 967 | SPARC_INTREG_SIZE * 8); |
| 968 | |
| 969 | read_register_bytes (REGISTER_BYTE (G0_REGNUM), |
| 970 | ®ister_temp[16 * SPARC_INTREG_SIZE], |
| 971 | SPARC_INTREG_SIZE * 8); |
| 972 | |
| 973 | if (SPARC_HAS_FPU) |
| 974 | read_register_bytes (REGISTER_BYTE (FP0_REGNUM), |
| 975 | ®ister_temp[24 * SPARC_INTREG_SIZE], |
| 976 | FP_REGISTER_BYTES); |
| 977 | |
| 978 | sp -= DUMMY_STACK_SIZE; |
| 979 | |
| 980 | write_sp (sp); |
| 981 | |
| 982 | write_memory (sp + DUMMY_REG_SAVE_OFFSET, ®ister_temp[0], |
| 983 | DUMMY_STACK_REG_BUF_SIZE); |
| 984 | |
| 985 | if (strcmp (target_shortname, "sim") != 0) |
| 986 | { |
| 987 | write_fp (old_sp); |
| 988 | |
| 989 | /* Set return address register for the call dummy to the current PC. */ |
| 990 | write_register (I7_REGNUM, read_pc () - 8); |
| 991 | } |
| 992 | else |
| 993 | { |
| 994 | /* The call dummy will write this value to FP before executing |
| 995 | the 'save'. This ensures that register window flushes work |
| 996 | correctly in the simulator. */ |
| 997 | write_register (G0_REGNUM + 1, read_register (FP_REGNUM)); |
| 998 | |
| 999 | /* The call dummy will write this value to FP after executing |
| 1000 | the 'save'. */ |
| 1001 | write_register (G0_REGNUM + 2, old_sp); |
| 1002 | |
| 1003 | /* The call dummy will write this value to the return address (%i7) after |
| 1004 | executing the 'save'. */ |
| 1005 | write_register (G0_REGNUM + 3, read_pc () - 8); |
| 1006 | |
| 1007 | /* Set the FP that the call dummy will be using after the 'save'. |
| 1008 | This makes backtraces from an inferior function call work properly. */ |
| 1009 | write_register (FP_REGNUM, old_sp); |
| 1010 | } |
| 1011 | } |
| 1012 | |
| 1013 | /* sparc_frame_find_saved_regs (). This function is here only because |
| 1014 | pop_frame uses it. Note there is an interesting corner case which |
| 1015 | I think few ports of GDB get right--if you are popping a frame |
| 1016 | which does not save some register that *is* saved by a more inner |
| 1017 | frame (such a frame will never be a dummy frame because dummy |
| 1018 | frames save all registers). Rewriting pop_frame to use |
| 1019 | get_saved_register would solve this problem and also get rid of the |
| 1020 | ugly duplication between sparc_frame_find_saved_regs and |
| 1021 | get_saved_register. |
| 1022 | |
| 1023 | Stores, into an array of CORE_ADDR, |
| 1024 | the addresses of the saved registers of frame described by FRAME_INFO. |
| 1025 | This includes special registers such as pc and fp saved in special |
| 1026 | ways in the stack frame. sp is even more special: |
| 1027 | the address we return for it IS the sp for the next frame. |
| 1028 | |
| 1029 | Note that on register window machines, we are currently making the |
| 1030 | assumption that window registers are being saved somewhere in the |
| 1031 | frame in which they are being used. If they are stored in an |
| 1032 | inferior frame, find_saved_register will break. |
| 1033 | |
| 1034 | On the Sun 4, the only time all registers are saved is when |
| 1035 | a dummy frame is involved. Otherwise, the only saved registers |
| 1036 | are the LOCAL and IN registers which are saved as a result |
| 1037 | of the "save/restore" opcodes. This condition is determined |
| 1038 | by address rather than by value. |
| 1039 | |
| 1040 | The "pc" is not stored in a frame on the SPARC. (What is stored |
| 1041 | is a return address minus 8.) sparc_pop_frame knows how to |
| 1042 | deal with that. Other routines might or might not. |
| 1043 | |
| 1044 | See tm-sparc.h (PUSH_DUMMY_FRAME and friends) for CRITICAL information |
| 1045 | about how this works. */ |
| 1046 | |
| 1047 | static void sparc_frame_find_saved_regs (struct frame_info *, CORE_ADDR *); |
| 1048 | |
| 1049 | static void |
| 1050 | sparc_frame_find_saved_regs (struct frame_info *fi, CORE_ADDR *saved_regs_addr) |
| 1051 | { |
| 1052 | register int regnum; |
| 1053 | CORE_ADDR frame_addr = FRAME_FP (fi); |
| 1054 | |
| 1055 | if (!fi) |
| 1056 | internal_error ("Bad frame info struct in FRAME_FIND_SAVED_REGS"); |
| 1057 | |
| 1058 | memset (saved_regs_addr, 0, NUM_REGS * sizeof (CORE_ADDR)); |
| 1059 | |
| 1060 | if (fi->pc >= (fi->extra_info->bottom ? |
| 1061 | fi->extra_info->bottom : read_sp ()) |
| 1062 | && fi->pc <= FRAME_FP (fi)) |
| 1063 | { |
| 1064 | /* Dummy frame. All but the window regs are in there somewhere. */ |
| 1065 | for (regnum = G1_REGNUM; regnum < G1_REGNUM + 7; regnum++) |
| 1066 | saved_regs_addr[regnum] = |
| 1067 | frame_addr + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE |
| 1068 | - DUMMY_STACK_REG_BUF_SIZE + 16 * SPARC_INTREG_SIZE; |
| 1069 | |
| 1070 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; regnum++) |
| 1071 | saved_regs_addr[regnum] = |
| 1072 | frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
| 1073 | - DUMMY_STACK_REG_BUF_SIZE + 8 * SPARC_INTREG_SIZE; |
| 1074 | |
| 1075 | if (SPARC_HAS_FPU) |
| 1076 | for (regnum = FP0_REGNUM; regnum < FP_MAX_REGNUM; regnum++) |
| 1077 | saved_regs_addr[regnum] = frame_addr + (regnum - FP0_REGNUM) * 4 |
| 1078 | - DUMMY_STACK_REG_BUF_SIZE + 24 * SPARC_INTREG_SIZE; |
| 1079 | |
| 1080 | if (GDB_TARGET_IS_SPARC64) |
| 1081 | { |
| 1082 | for (regnum = PC_REGNUM; regnum < PC_REGNUM + 7; regnum++) |
| 1083 | { |
| 1084 | saved_regs_addr[regnum] = |
| 1085 | frame_addr + (regnum - PC_REGNUM) * SPARC_INTREG_SIZE |
| 1086 | - DUMMY_STACK_REG_BUF_SIZE; |
| 1087 | } |
| 1088 | saved_regs_addr[PSTATE_REGNUM] = |
| 1089 | frame_addr + 8 * SPARC_INTREG_SIZE - DUMMY_STACK_REG_BUF_SIZE; |
| 1090 | } |
| 1091 | else |
| 1092 | for (regnum = Y_REGNUM; regnum < NUM_REGS; regnum++) |
| 1093 | saved_regs_addr[regnum] = |
| 1094 | frame_addr + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE |
| 1095 | - DUMMY_STACK_REG_BUF_SIZE; |
| 1096 | |
| 1097 | frame_addr = fi->extra_info->bottom ? |
| 1098 | fi->extra_info->bottom : read_sp (); |
| 1099 | } |
| 1100 | else if (fi->extra_info->flat) |
| 1101 | { |
| 1102 | CORE_ADDR func_start; |
| 1103 | find_pc_partial_function (fi->pc, NULL, &func_start, NULL); |
| 1104 | examine_prologue (func_start, 0, fi, saved_regs_addr); |
| 1105 | |
| 1106 | /* Flat register window frame. */ |
| 1107 | saved_regs_addr[RP_REGNUM] = fi->extra_info->pc_addr; |
| 1108 | saved_regs_addr[I7_REGNUM] = fi->extra_info->fp_addr; |
| 1109 | } |
| 1110 | else |
| 1111 | { |
| 1112 | /* Normal frame. Just Local and In registers */ |
| 1113 | frame_addr = fi->extra_info->bottom ? |
| 1114 | fi->extra_info->bottom : read_sp (); |
| 1115 | for (regnum = L0_REGNUM; regnum < L0_REGNUM + 8; regnum++) |
| 1116 | saved_regs_addr[regnum] = |
| 1117 | (frame_addr + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE |
| 1118 | + FRAME_SAVED_L0); |
| 1119 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; regnum++) |
| 1120 | saved_regs_addr[regnum] = |
| 1121 | (frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
| 1122 | + FRAME_SAVED_I0); |
| 1123 | } |
| 1124 | if (fi->next) |
| 1125 | { |
| 1126 | if (fi->extra_info->flat) |
| 1127 | { |
| 1128 | saved_regs_addr[O7_REGNUM] = fi->extra_info->pc_addr; |
| 1129 | } |
| 1130 | else |
| 1131 | { |
| 1132 | /* Pull off either the next frame pointer or the stack pointer */ |
| 1133 | CORE_ADDR next_next_frame_addr = |
| 1134 | (fi->next->extra_info->bottom ? |
| 1135 | fi->next->extra_info->bottom : read_sp ()); |
| 1136 | for (regnum = O0_REGNUM; regnum < O0_REGNUM + 8; regnum++) |
| 1137 | saved_regs_addr[regnum] = |
| 1138 | (next_next_frame_addr |
| 1139 | + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE |
| 1140 | + FRAME_SAVED_I0); |
| 1141 | } |
| 1142 | } |
| 1143 | /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */ |
| 1144 | /* FIXME -- should this adjust for the sparc64 offset? */ |
| 1145 | saved_regs_addr[SP_REGNUM] = FRAME_FP (fi); |
| 1146 | } |
| 1147 | |
| 1148 | /* Discard from the stack the innermost frame, restoring all saved registers. |
| 1149 | |
| 1150 | Note that the values stored in fsr by get_frame_saved_regs are *in |
| 1151 | the context of the called frame*. What this means is that the i |
| 1152 | regs of fsr must be restored into the o regs of the (calling) frame that |
| 1153 | we pop into. We don't care about the output regs of the calling frame, |
| 1154 | since unless it's a dummy frame, it won't have any output regs in it. |
| 1155 | |
| 1156 | We never have to bother with %l (local) regs, since the called routine's |
| 1157 | locals get tossed, and the calling routine's locals are already saved |
| 1158 | on its stack. */ |
| 1159 | |
| 1160 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ |
| 1161 | |
| 1162 | void |
| 1163 | sparc_pop_frame (void) |
| 1164 | { |
| 1165 | register struct frame_info *frame = get_current_frame (); |
| 1166 | register CORE_ADDR pc; |
| 1167 | CORE_ADDR *fsr; |
| 1168 | char *raw_buffer; |
| 1169 | int regnum; |
| 1170 | |
| 1171 | fsr = alloca (NUM_REGS * sizeof (CORE_ADDR)); |
| 1172 | raw_buffer = alloca (REGISTER_BYTES); |
| 1173 | sparc_frame_find_saved_regs (frame, &fsr[0]); |
| 1174 | if (SPARC_HAS_FPU) |
| 1175 | { |
| 1176 | if (fsr[FP0_REGNUM]) |
| 1177 | { |
| 1178 | read_memory (fsr[FP0_REGNUM], raw_buffer, FP_REGISTER_BYTES); |
| 1179 | write_register_bytes (REGISTER_BYTE (FP0_REGNUM), |
| 1180 | raw_buffer, FP_REGISTER_BYTES); |
| 1181 | } |
| 1182 | if (!(GDB_TARGET_IS_SPARC64)) |
| 1183 | { |
| 1184 | if (fsr[FPS_REGNUM]) |
| 1185 | { |
| 1186 | read_memory (fsr[FPS_REGNUM], raw_buffer, SPARC_INTREG_SIZE); |
| 1187 | write_register_gen (FPS_REGNUM, raw_buffer); |
| 1188 | } |
| 1189 | if (fsr[CPS_REGNUM]) |
| 1190 | { |
| 1191 | read_memory (fsr[CPS_REGNUM], raw_buffer, SPARC_INTREG_SIZE); |
| 1192 | write_register_gen (CPS_REGNUM, raw_buffer); |
| 1193 | } |
| 1194 | } |
| 1195 | } |
| 1196 | if (fsr[G1_REGNUM]) |
| 1197 | { |
| 1198 | read_memory (fsr[G1_REGNUM], raw_buffer, 7 * SPARC_INTREG_SIZE); |
| 1199 | write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer, |
| 1200 | 7 * SPARC_INTREG_SIZE); |
| 1201 | } |
| 1202 | |
| 1203 | if (frame->extra_info->flat) |
| 1204 | { |
| 1205 | /* Each register might or might not have been saved, need to test |
| 1206 | individually. */ |
| 1207 | for (regnum = L0_REGNUM; regnum < L0_REGNUM + 8; ++regnum) |
| 1208 | if (fsr[regnum]) |
| 1209 | write_register (regnum, read_memory_integer (fsr[regnum], |
| 1210 | SPARC_INTREG_SIZE)); |
| 1211 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; ++regnum) |
| 1212 | if (fsr[regnum]) |
| 1213 | write_register (regnum, read_memory_integer (fsr[regnum], |
| 1214 | SPARC_INTREG_SIZE)); |
| 1215 | |
| 1216 | /* Handle all outs except stack pointer (o0-o5; o7). */ |
| 1217 | for (regnum = O0_REGNUM; regnum < O0_REGNUM + 6; ++regnum) |
| 1218 | if (fsr[regnum]) |
| 1219 | write_register (regnum, read_memory_integer (fsr[regnum], |
| 1220 | SPARC_INTREG_SIZE)); |
| 1221 | if (fsr[O0_REGNUM + 7]) |
| 1222 | write_register (O0_REGNUM + 7, |
| 1223 | read_memory_integer (fsr[O0_REGNUM + 7], |
| 1224 | SPARC_INTREG_SIZE)); |
| 1225 | |
| 1226 | write_sp (frame->frame); |
| 1227 | } |
| 1228 | else if (fsr[I0_REGNUM]) |
| 1229 | { |
| 1230 | CORE_ADDR sp; |
| 1231 | |
| 1232 | char *reg_temp; |
| 1233 | |
| 1234 | reg_temp = alloca (REGISTER_BYTES); |
| 1235 | |
| 1236 | read_memory (fsr[I0_REGNUM], raw_buffer, 8 * SPARC_INTREG_SIZE); |
| 1237 | |
| 1238 | /* Get the ins and locals which we are about to restore. Just |
| 1239 | moving the stack pointer is all that is really needed, except |
| 1240 | store_inferior_registers is then going to write the ins and |
| 1241 | locals from the registers array, so we need to muck with the |
| 1242 | registers array. */ |
| 1243 | sp = fsr[SP_REGNUM]; |
| 1244 | |
| 1245 | if (GDB_TARGET_IS_SPARC64 && (sp & 1)) |
| 1246 | sp += 2047; |
| 1247 | |
| 1248 | read_memory (sp, reg_temp, SPARC_INTREG_SIZE * 16); |
| 1249 | |
| 1250 | /* Restore the out registers. |
| 1251 | Among other things this writes the new stack pointer. */ |
| 1252 | write_register_bytes (REGISTER_BYTE (O0_REGNUM), raw_buffer, |
| 1253 | SPARC_INTREG_SIZE * 8); |
| 1254 | |
| 1255 | write_register_bytes (REGISTER_BYTE (L0_REGNUM), reg_temp, |
| 1256 | SPARC_INTREG_SIZE * 16); |
| 1257 | } |
| 1258 | |
| 1259 | if (!(GDB_TARGET_IS_SPARC64)) |
| 1260 | if (fsr[PS_REGNUM]) |
| 1261 | write_register (PS_REGNUM, |
| 1262 | read_memory_integer (fsr[PS_REGNUM], |
| 1263 | REGISTER_RAW_SIZE (PS_REGNUM))); |
| 1264 | |
| 1265 | if (fsr[Y_REGNUM]) |
| 1266 | write_register (Y_REGNUM, |
| 1267 | read_memory_integer (fsr[Y_REGNUM], |
| 1268 | REGISTER_RAW_SIZE (Y_REGNUM))); |
| 1269 | if (fsr[PC_REGNUM]) |
| 1270 | { |
| 1271 | /* Explicitly specified PC (and maybe NPC) -- just restore them. */ |
| 1272 | write_register (PC_REGNUM, |
| 1273 | read_memory_integer (fsr[PC_REGNUM], |
| 1274 | REGISTER_RAW_SIZE (PC_REGNUM))); |
| 1275 | if (fsr[NPC_REGNUM]) |
| 1276 | write_register (NPC_REGNUM, |
| 1277 | read_memory_integer (fsr[NPC_REGNUM], |
| 1278 | REGISTER_RAW_SIZE (NPC_REGNUM))); |
| 1279 | } |
| 1280 | else if (frame->extra_info->flat) |
| 1281 | { |
| 1282 | if (frame->extra_info->pc_addr) |
| 1283 | pc = PC_ADJUST ((CORE_ADDR) |
| 1284 | read_memory_integer (frame->extra_info->pc_addr, |
| 1285 | REGISTER_RAW_SIZE (PC_REGNUM))); |
| 1286 | else |
| 1287 | { |
| 1288 | /* I think this happens only in the innermost frame, if so then |
| 1289 | it is a complicated way of saying |
| 1290 | "pc = read_register (O7_REGNUM);". */ |
| 1291 | char *buf; |
| 1292 | |
| 1293 | buf = alloca (MAX_REGISTER_RAW_SIZE); |
| 1294 | get_saved_register (buf, 0, 0, frame, O7_REGNUM, 0); |
| 1295 | pc = PC_ADJUST (extract_address |
| 1296 | (buf, REGISTER_RAW_SIZE (O7_REGNUM))); |
| 1297 | } |
| 1298 | |
| 1299 | write_register (PC_REGNUM, pc); |
| 1300 | write_register (NPC_REGNUM, pc + 4); |
| 1301 | } |
| 1302 | else if (fsr[I7_REGNUM]) |
| 1303 | { |
| 1304 | /* Return address in %i7 -- adjust it, then restore PC and NPC from it */ |
| 1305 | pc = PC_ADJUST ((CORE_ADDR) read_memory_integer (fsr[I7_REGNUM], |
| 1306 | SPARC_INTREG_SIZE)); |
| 1307 | write_register (PC_REGNUM, pc); |
| 1308 | write_register (NPC_REGNUM, pc + 4); |
| 1309 | } |
| 1310 | flush_cached_frames (); |
| 1311 | } |
| 1312 | |
| 1313 | /* On the Sun 4 under SunOS, the compile will leave a fake insn which |
| 1314 | encodes the structure size being returned. If we detect such |
| 1315 | a fake insn, step past it. */ |
| 1316 | |
| 1317 | CORE_ADDR |
| 1318 | sparc_pc_adjust (CORE_ADDR pc) |
| 1319 | { |
| 1320 | unsigned long insn; |
| 1321 | char buf[4]; |
| 1322 | int err; |
| 1323 | |
| 1324 | err = target_read_memory (pc + 8, buf, 4); |
| 1325 | insn = extract_unsigned_integer (buf, 4); |
| 1326 | if ((err == 0) && (insn & 0xffc00000) == 0) |
| 1327 | return pc + 12; |
| 1328 | else |
| 1329 | return pc + 8; |
| 1330 | } |
| 1331 | |
| 1332 | /* If pc is in a shared library trampoline, return its target. |
| 1333 | The SunOs 4.x linker rewrites the jump table entries for PIC |
| 1334 | compiled modules in the main executable to bypass the dynamic linker |
| 1335 | with jumps of the form |
| 1336 | sethi %hi(addr),%g1 |
| 1337 | jmp %g1+%lo(addr) |
| 1338 | and removes the corresponding jump table relocation entry in the |
| 1339 | dynamic relocations. |
| 1340 | find_solib_trampoline_target relies on the presence of the jump |
| 1341 | table relocation entry, so we have to detect these jump instructions |
| 1342 | by hand. */ |
| 1343 | |
| 1344 | CORE_ADDR |
| 1345 | sunos4_skip_trampoline_code (CORE_ADDR pc) |
| 1346 | { |
| 1347 | unsigned long insn1; |
| 1348 | char buf[4]; |
| 1349 | int err; |
| 1350 | |
| 1351 | err = target_read_memory (pc, buf, 4); |
| 1352 | insn1 = extract_unsigned_integer (buf, 4); |
| 1353 | if (err == 0 && (insn1 & 0xffc00000) == 0x03000000) |
| 1354 | { |
| 1355 | unsigned long insn2; |
| 1356 | |
| 1357 | err = target_read_memory (pc + 4, buf, 4); |
| 1358 | insn2 = extract_unsigned_integer (buf, 4); |
| 1359 | if (err == 0 && (insn2 & 0xffffe000) == 0x81c06000) |
| 1360 | { |
| 1361 | CORE_ADDR target_pc = (insn1 & 0x3fffff) << 10; |
| 1362 | int delta = insn2 & 0x1fff; |
| 1363 | |
| 1364 | /* Sign extend the displacement. */ |
| 1365 | if (delta & 0x1000) |
| 1366 | delta |= ~0x1fff; |
| 1367 | return target_pc + delta; |
| 1368 | } |
| 1369 | } |
| 1370 | return find_solib_trampoline_target (pc); |
| 1371 | } |
| 1372 | \f |
| 1373 | #ifdef USE_PROC_FS /* Target dependent support for /proc */ |
| 1374 | /* *INDENT-OFF* */ |
| 1375 | /* The /proc interface divides the target machine's register set up into |
| 1376 | two different sets, the general register set (gregset) and the floating |
| 1377 | point register set (fpregset). For each set, there is an ioctl to get |
| 1378 | the current register set and another ioctl to set the current values. |
| 1379 | |
| 1380 | The actual structure passed through the ioctl interface is, of course, |
| 1381 | naturally machine dependent, and is different for each set of registers. |
| 1382 | For the sparc for example, the general register set is typically defined |
| 1383 | by: |
| 1384 | |
| 1385 | typedef int gregset_t[38]; |
| 1386 | |
| 1387 | #define R_G0 0 |
| 1388 | ... |
| 1389 | #define R_TBR 37 |
| 1390 | |
| 1391 | and the floating point set by: |
| 1392 | |
| 1393 | typedef struct prfpregset { |
| 1394 | union { |
| 1395 | u_long pr_regs[32]; |
| 1396 | double pr_dregs[16]; |
| 1397 | } pr_fr; |
| 1398 | void * pr_filler; |
| 1399 | u_long pr_fsr; |
| 1400 | u_char pr_qcnt; |
| 1401 | u_char pr_q_entrysize; |
| 1402 | u_char pr_en; |
| 1403 | u_long pr_q[64]; |
| 1404 | } prfpregset_t; |
| 1405 | |
| 1406 | These routines provide the packing and unpacking of gregset_t and |
| 1407 | fpregset_t formatted data. |
| 1408 | |
| 1409 | */ |
| 1410 | /* *INDENT-ON* */ |
| 1411 | |
| 1412 | /* Given a pointer to a general register set in /proc format (gregset_t *), |
| 1413 | unpack the register contents and supply them as gdb's idea of the current |
| 1414 | register values. */ |
| 1415 | |
| 1416 | void |
| 1417 | supply_gregset (gdb_gregset_t *gregsetp) |
| 1418 | { |
| 1419 | prgreg_t *regp = (prgreg_t *) gregsetp; |
| 1420 | int regi, offset = 0; |
| 1421 | |
| 1422 | /* If the host is 64-bit sparc, but the target is 32-bit sparc, |
| 1423 | then the gregset may contain 64-bit ints while supply_register |
| 1424 | is expecting 32-bit ints. Compensate. */ |
| 1425 | if (sizeof (regp[0]) == 8 && SPARC_INTREG_SIZE == 4) |
| 1426 | offset = 4; |
| 1427 | |
| 1428 | /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */ |
| 1429 | /* FIXME MVS: assumes the order of the first 32 elements... */ |
| 1430 | for (regi = G0_REGNUM; regi <= I7_REGNUM; regi++) |
| 1431 | { |
| 1432 | supply_register (regi, ((char *) (regp + regi)) + offset); |
| 1433 | } |
| 1434 | |
| 1435 | /* These require a bit more care. */ |
| 1436 | supply_register (PC_REGNUM, ((char *) (regp + R_PC)) + offset); |
| 1437 | supply_register (NPC_REGNUM, ((char *) (regp + R_nPC)) + offset); |
| 1438 | supply_register (Y_REGNUM, ((char *) (regp + R_Y)) + offset); |
| 1439 | |
| 1440 | if (GDB_TARGET_IS_SPARC64) |
| 1441 | { |
| 1442 | #ifdef R_CCR |
| 1443 | supply_register (CCR_REGNUM, ((char *) (regp + R_CCR)) + offset); |
| 1444 | #else |
| 1445 | supply_register (CCR_REGNUM, NULL); |
| 1446 | #endif |
| 1447 | #ifdef R_FPRS |
| 1448 | supply_register (FPRS_REGNUM, ((char *) (regp + R_FPRS)) + offset); |
| 1449 | #else |
| 1450 | supply_register (FPRS_REGNUM, NULL); |
| 1451 | #endif |
| 1452 | #ifdef R_ASI |
| 1453 | supply_register (ASI_REGNUM, ((char *) (regp + R_ASI)) + offset); |
| 1454 | #else |
| 1455 | supply_register (ASI_REGNUM, NULL); |
| 1456 | #endif |
| 1457 | } |
| 1458 | else /* sparc32 */ |
| 1459 | { |
| 1460 | #ifdef R_PS |
| 1461 | supply_register (PS_REGNUM, ((char *) (regp + R_PS)) + offset); |
| 1462 | #else |
| 1463 | supply_register (PS_REGNUM, NULL); |
| 1464 | #endif |
| 1465 | |
| 1466 | /* For 64-bit hosts, R_WIM and R_TBR may not be defined. |
| 1467 | Steal R_ASI and R_FPRS, and hope for the best! */ |
| 1468 | |
| 1469 | #if !defined (R_WIM) && defined (R_ASI) |
| 1470 | #define R_WIM R_ASI |
| 1471 | #endif |
| 1472 | |
| 1473 | #if !defined (R_TBR) && defined (R_FPRS) |
| 1474 | #define R_TBR R_FPRS |
| 1475 | #endif |
| 1476 | |
| 1477 | #if defined (R_WIM) |
| 1478 | supply_register (WIM_REGNUM, ((char *) (regp + R_WIM)) + offset); |
| 1479 | #else |
| 1480 | supply_register (WIM_REGNUM, NULL); |
| 1481 | #endif |
| 1482 | |
| 1483 | #if defined (R_TBR) |
| 1484 | supply_register (TBR_REGNUM, ((char *) (regp + R_TBR)) + offset); |
| 1485 | #else |
| 1486 | supply_register (TBR_REGNUM, NULL); |
| 1487 | #endif |
| 1488 | } |
| 1489 | |
| 1490 | /* Fill inaccessible registers with zero. */ |
| 1491 | if (GDB_TARGET_IS_SPARC64) |
| 1492 | { |
| 1493 | /* |
| 1494 | * don't know how to get value of any of the following: |
| 1495 | */ |
| 1496 | supply_register (VER_REGNUM, NULL); |
| 1497 | supply_register (TICK_REGNUM, NULL); |
| 1498 | supply_register (PIL_REGNUM, NULL); |
| 1499 | supply_register (PSTATE_REGNUM, NULL); |
| 1500 | supply_register (TSTATE_REGNUM, NULL); |
| 1501 | supply_register (TBA_REGNUM, NULL); |
| 1502 | supply_register (TL_REGNUM, NULL); |
| 1503 | supply_register (TT_REGNUM, NULL); |
| 1504 | supply_register (TPC_REGNUM, NULL); |
| 1505 | supply_register (TNPC_REGNUM, NULL); |
| 1506 | supply_register (WSTATE_REGNUM, NULL); |
| 1507 | supply_register (CWP_REGNUM, NULL); |
| 1508 | supply_register (CANSAVE_REGNUM, NULL); |
| 1509 | supply_register (CANRESTORE_REGNUM, NULL); |
| 1510 | supply_register (CLEANWIN_REGNUM, NULL); |
| 1511 | supply_register (OTHERWIN_REGNUM, NULL); |
| 1512 | supply_register (ASR16_REGNUM, NULL); |
| 1513 | supply_register (ASR17_REGNUM, NULL); |
| 1514 | supply_register (ASR18_REGNUM, NULL); |
| 1515 | supply_register (ASR19_REGNUM, NULL); |
| 1516 | supply_register (ASR20_REGNUM, NULL); |
| 1517 | supply_register (ASR21_REGNUM, NULL); |
| 1518 | supply_register (ASR22_REGNUM, NULL); |
| 1519 | supply_register (ASR23_REGNUM, NULL); |
| 1520 | supply_register (ASR24_REGNUM, NULL); |
| 1521 | supply_register (ASR25_REGNUM, NULL); |
| 1522 | supply_register (ASR26_REGNUM, NULL); |
| 1523 | supply_register (ASR27_REGNUM, NULL); |
| 1524 | supply_register (ASR28_REGNUM, NULL); |
| 1525 | supply_register (ASR29_REGNUM, NULL); |
| 1526 | supply_register (ASR30_REGNUM, NULL); |
| 1527 | supply_register (ASR31_REGNUM, NULL); |
| 1528 | supply_register (ICC_REGNUM, NULL); |
| 1529 | supply_register (XCC_REGNUM, NULL); |
| 1530 | } |
| 1531 | else |
| 1532 | { |
| 1533 | supply_register (CPS_REGNUM, NULL); |
| 1534 | } |
| 1535 | } |
| 1536 | |
| 1537 | void |
| 1538 | fill_gregset (gdb_gregset_t *gregsetp, int regno) |
| 1539 | { |
| 1540 | prgreg_t *regp = (prgreg_t *) gregsetp; |
| 1541 | int regi, offset = 0; |
| 1542 | |
| 1543 | /* If the host is 64-bit sparc, but the target is 32-bit sparc, |
| 1544 | then the gregset may contain 64-bit ints while supply_register |
| 1545 | is expecting 32-bit ints. Compensate. */ |
| 1546 | if (sizeof (regp[0]) == 8 && SPARC_INTREG_SIZE == 4) |
| 1547 | offset = 4; |
| 1548 | |
| 1549 | for (regi = 0; regi <= R_I7; regi++) |
| 1550 | if ((regno == -1) || (regno == regi)) |
| 1551 | read_register_gen (regi, (char *) (regp + regi) + offset); |
| 1552 | |
| 1553 | if ((regno == -1) || (regno == PC_REGNUM)) |
| 1554 | read_register_gen (PC_REGNUM, (char *) (regp + R_PC) + offset); |
| 1555 | |
| 1556 | if ((regno == -1) || (regno == NPC_REGNUM)) |
| 1557 | read_register_gen (NPC_REGNUM, (char *) (regp + R_nPC) + offset); |
| 1558 | |
| 1559 | if ((regno == -1) || (regno == Y_REGNUM)) |
| 1560 | read_register_gen (Y_REGNUM, (char *) (regp + R_Y) + offset); |
| 1561 | |
| 1562 | if (GDB_TARGET_IS_SPARC64) |
| 1563 | { |
| 1564 | #ifdef R_CCR |
| 1565 | if (regno == -1 || regno == CCR_REGNUM) |
| 1566 | read_register_gen (CCR_REGNUM, ((char *) (regp + R_CCR)) + offset); |
| 1567 | #endif |
| 1568 | #ifdef R_FPRS |
| 1569 | if (regno == -1 || regno == FPRS_REGNUM) |
| 1570 | read_register_gen (FPRS_REGNUM, ((char *) (regp + R_FPRS)) + offset); |
| 1571 | #endif |
| 1572 | #ifdef R_ASI |
| 1573 | if (regno == -1 || regno == ASI_REGNUM) |
| 1574 | read_register_gen (ASI_REGNUM, ((char *) (regp + R_ASI)) + offset); |
| 1575 | #endif |
| 1576 | } |
| 1577 | else /* sparc32 */ |
| 1578 | { |
| 1579 | #ifdef R_PS |
| 1580 | if (regno == -1 || regno == PS_REGNUM) |
| 1581 | read_register_gen (PS_REGNUM, ((char *) (regp + R_PS)) + offset); |
| 1582 | #endif |
| 1583 | |
| 1584 | /* For 64-bit hosts, R_WIM and R_TBR may not be defined. |
| 1585 | Steal R_ASI and R_FPRS, and hope for the best! */ |
| 1586 | |
| 1587 | #if !defined (R_WIM) && defined (R_ASI) |
| 1588 | #define R_WIM R_ASI |
| 1589 | #endif |
| 1590 | |
| 1591 | #if !defined (R_TBR) && defined (R_FPRS) |
| 1592 | #define R_TBR R_FPRS |
| 1593 | #endif |
| 1594 | |
| 1595 | #if defined (R_WIM) |
| 1596 | if (regno == -1 || regno == WIM_REGNUM) |
| 1597 | read_register_gen (WIM_REGNUM, ((char *) (regp + R_WIM)) + offset); |
| 1598 | #else |
| 1599 | if (regno == -1 || regno == WIM_REGNUM) |
| 1600 | read_register_gen (WIM_REGNUM, NULL); |
| 1601 | #endif |
| 1602 | |
| 1603 | #if defined (R_TBR) |
| 1604 | if (regno == -1 || regno == TBR_REGNUM) |
| 1605 | read_register_gen (TBR_REGNUM, ((char *) (regp + R_TBR)) + offset); |
| 1606 | #else |
| 1607 | if (regno == -1 || regno == TBR_REGNUM) |
| 1608 | read_register_gen (TBR_REGNUM, NULL); |
| 1609 | #endif |
| 1610 | } |
| 1611 | } |
| 1612 | |
| 1613 | /* Given a pointer to a floating point register set in /proc format |
| 1614 | (fpregset_t *), unpack the register contents and supply them as gdb's |
| 1615 | idea of the current floating point register values. */ |
| 1616 | |
| 1617 | void |
| 1618 | supply_fpregset (gdb_fpregset_t *fpregsetp) |
| 1619 | { |
| 1620 | register int regi; |
| 1621 | char *from; |
| 1622 | |
| 1623 | if (!SPARC_HAS_FPU) |
| 1624 | return; |
| 1625 | |
| 1626 | for (regi = FP0_REGNUM; regi < FP_MAX_REGNUM; regi++) |
| 1627 | { |
| 1628 | from = (char *) &fpregsetp->pr_fr.pr_regs[regi - FP0_REGNUM]; |
| 1629 | supply_register (regi, from); |
| 1630 | } |
| 1631 | |
| 1632 | if (GDB_TARGET_IS_SPARC64) |
| 1633 | { |
| 1634 | /* |
| 1635 | * don't know how to get value of the following. |
| 1636 | */ |
| 1637 | supply_register (FSR_REGNUM, NULL); /* zero it out for now */ |
| 1638 | supply_register (FCC0_REGNUM, NULL); |
| 1639 | supply_register (FCC1_REGNUM, NULL); /* don't know how to get value */ |
| 1640 | supply_register (FCC2_REGNUM, NULL); /* don't know how to get value */ |
| 1641 | supply_register (FCC3_REGNUM, NULL); /* don't know how to get value */ |
| 1642 | } |
| 1643 | else |
| 1644 | { |
| 1645 | supply_register (FPS_REGNUM, (char *) &(fpregsetp->pr_fsr)); |
| 1646 | } |
| 1647 | } |
| 1648 | |
| 1649 | /* Given a pointer to a floating point register set in /proc format |
| 1650 | (fpregset_t *), update the register specified by REGNO from gdb's idea |
| 1651 | of the current floating point register set. If REGNO is -1, update |
| 1652 | them all. */ |
| 1653 | /* This will probably need some changes for sparc64. */ |
| 1654 | |
| 1655 | void |
| 1656 | fill_fpregset (gdb_fpregset_t *fpregsetp, int regno) |
| 1657 | { |
| 1658 | int regi; |
| 1659 | char *to; |
| 1660 | char *from; |
| 1661 | |
| 1662 | if (!SPARC_HAS_FPU) |
| 1663 | return; |
| 1664 | |
| 1665 | for (regi = FP0_REGNUM; regi < FP_MAX_REGNUM; regi++) |
| 1666 | { |
| 1667 | if ((regno == -1) || (regno == regi)) |
| 1668 | { |
| 1669 | from = (char *) ®isters[REGISTER_BYTE (regi)]; |
| 1670 | to = (char *) &fpregsetp->pr_fr.pr_regs[regi - FP0_REGNUM]; |
| 1671 | memcpy (to, from, REGISTER_RAW_SIZE (regi)); |
| 1672 | } |
| 1673 | } |
| 1674 | |
| 1675 | if (!(GDB_TARGET_IS_SPARC64)) /* FIXME: does Sparc64 have this register? */ |
| 1676 | if ((regno == -1) || (regno == FPS_REGNUM)) |
| 1677 | { |
| 1678 | from = (char *)®isters[REGISTER_BYTE (FPS_REGNUM)]; |
| 1679 | to = (char *) &fpregsetp->pr_fsr; |
| 1680 | memcpy (to, from, REGISTER_RAW_SIZE (FPS_REGNUM)); |
| 1681 | } |
| 1682 | } |
| 1683 | |
| 1684 | #endif /* USE_PROC_FS */ |
| 1685 | |
| 1686 | |
| 1687 | #ifdef GET_LONGJMP_TARGET |
| 1688 | |
| 1689 | /* Figure out where the longjmp will land. We expect that we have just entered |
| 1690 | longjmp and haven't yet setup the stack frame, so the args are still in the |
| 1691 | output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we |
| 1692 | extract the pc (JB_PC) that we will land at. The pc is copied into ADDR. |
| 1693 | This routine returns true on success */ |
| 1694 | |
| 1695 | int |
| 1696 | get_longjmp_target (CORE_ADDR *pc) |
| 1697 | { |
| 1698 | CORE_ADDR jb_addr; |
| 1699 | #define LONGJMP_TARGET_SIZE 4 |
| 1700 | char buf[LONGJMP_TARGET_SIZE]; |
| 1701 | |
| 1702 | jb_addr = read_register (O0_REGNUM); |
| 1703 | |
| 1704 | if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf, |
| 1705 | LONGJMP_TARGET_SIZE)) |
| 1706 | return 0; |
| 1707 | |
| 1708 | *pc = extract_address (buf, LONGJMP_TARGET_SIZE); |
| 1709 | |
| 1710 | return 1; |
| 1711 | } |
| 1712 | #endif /* GET_LONGJMP_TARGET */ |
| 1713 | \f |
| 1714 | #ifdef STATIC_TRANSFORM_NAME |
| 1715 | /* SunPRO (3.0 at least), encodes the static variables. This is not |
| 1716 | related to C++ mangling, it is done for C too. */ |
| 1717 | |
| 1718 | char * |
| 1719 | sunpro_static_transform_name (char *name) |
| 1720 | { |
| 1721 | char *p; |
| 1722 | if (name[0] == '$') |
| 1723 | { |
| 1724 | /* For file-local statics there will be a dollar sign, a bunch |
| 1725 | of junk (the contents of which match a string given in the |
| 1726 | N_OPT), a period and the name. For function-local statics |
| 1727 | there will be a bunch of junk (which seems to change the |
| 1728 | second character from 'A' to 'B'), a period, the name of the |
| 1729 | function, and the name. So just skip everything before the |
| 1730 | last period. */ |
| 1731 | p = strrchr (name, '.'); |
| 1732 | if (p != NULL) |
| 1733 | name = p + 1; |
| 1734 | } |
| 1735 | return name; |
| 1736 | } |
| 1737 | #endif /* STATIC_TRANSFORM_NAME */ |
| 1738 | \f |
| 1739 | |
| 1740 | /* Utilities for printing registers. |
| 1741 | Page numbers refer to the SPARC Architecture Manual. */ |
| 1742 | |
| 1743 | static void dump_ccreg (char *, int); |
| 1744 | |
| 1745 | static void |
| 1746 | dump_ccreg (char *reg, int val) |
| 1747 | { |
| 1748 | /* page 41 */ |
| 1749 | printf_unfiltered ("%s:%s,%s,%s,%s", reg, |
| 1750 | val & 8 ? "N" : "NN", |
| 1751 | val & 4 ? "Z" : "NZ", |
| 1752 | val & 2 ? "O" : "NO", |
| 1753 | val & 1 ? "C" : "NC"); |
| 1754 | } |
| 1755 | |
| 1756 | static char * |
| 1757 | decode_asi (int val) |
| 1758 | { |
| 1759 | /* page 72 */ |
| 1760 | switch (val) |
| 1761 | { |
| 1762 | case 4: |
| 1763 | return "ASI_NUCLEUS"; |
| 1764 | case 0x0c: |
| 1765 | return "ASI_NUCLEUS_LITTLE"; |
| 1766 | case 0x10: |
| 1767 | return "ASI_AS_IF_USER_PRIMARY"; |
| 1768 | case 0x11: |
| 1769 | return "ASI_AS_IF_USER_SECONDARY"; |
| 1770 | case 0x18: |
| 1771 | return "ASI_AS_IF_USER_PRIMARY_LITTLE"; |
| 1772 | case 0x19: |
| 1773 | return "ASI_AS_IF_USER_SECONDARY_LITTLE"; |
| 1774 | case 0x80: |
| 1775 | return "ASI_PRIMARY"; |
| 1776 | case 0x81: |
| 1777 | return "ASI_SECONDARY"; |
| 1778 | case 0x82: |
| 1779 | return "ASI_PRIMARY_NOFAULT"; |
| 1780 | case 0x83: |
| 1781 | return "ASI_SECONDARY_NOFAULT"; |
| 1782 | case 0x88: |
| 1783 | return "ASI_PRIMARY_LITTLE"; |
| 1784 | case 0x89: |
| 1785 | return "ASI_SECONDARY_LITTLE"; |
| 1786 | case 0x8a: |
| 1787 | return "ASI_PRIMARY_NOFAULT_LITTLE"; |
| 1788 | case 0x8b: |
| 1789 | return "ASI_SECONDARY_NOFAULT_LITTLE"; |
| 1790 | default: |
| 1791 | return NULL; |
| 1792 | } |
| 1793 | } |
| 1794 | |
| 1795 | /* PRINT_REGISTER_HOOK routine. |
| 1796 | Pretty print various registers. */ |
| 1797 | /* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */ |
| 1798 | |
| 1799 | void |
| 1800 | sparc_print_register_hook (int regno) |
| 1801 | { |
| 1802 | ULONGEST val; |
| 1803 | |
| 1804 | /* Handle double/quad versions of lower 32 fp regs. */ |
| 1805 | if (regno >= FP0_REGNUM && regno < FP0_REGNUM + 32 |
| 1806 | && (regno & 1) == 0) |
| 1807 | { |
| 1808 | char value[16]; |
| 1809 | |
| 1810 | if (!read_relative_register_raw_bytes (regno, value) |
| 1811 | && !read_relative_register_raw_bytes (regno + 1, value + 4)) |
| 1812 | { |
| 1813 | printf_unfiltered ("\t"); |
| 1814 | print_floating (value, builtin_type_double, gdb_stdout); |
| 1815 | } |
| 1816 | #if 0 /* FIXME: gdb doesn't handle long doubles */ |
| 1817 | if ((regno & 3) == 0) |
| 1818 | { |
| 1819 | if (!read_relative_register_raw_bytes (regno + 2, value + 8) |
| 1820 | && !read_relative_register_raw_bytes (regno + 3, value + 12)) |
| 1821 | { |
| 1822 | printf_unfiltered ("\t"); |
| 1823 | print_floating (value, builtin_type_long_double, gdb_stdout); |
| 1824 | } |
| 1825 | } |
| 1826 | #endif |
| 1827 | return; |
| 1828 | } |
| 1829 | |
| 1830 | #if 0 /* FIXME: gdb doesn't handle long doubles */ |
| 1831 | /* Print upper fp regs as long double if appropriate. */ |
| 1832 | if (regno >= FP0_REGNUM + 32 && regno < FP_MAX_REGNUM |
| 1833 | /* We test for even numbered regs and not a multiple of 4 because |
| 1834 | the upper fp regs are recorded as doubles. */ |
| 1835 | && (regno & 1) == 0) |
| 1836 | { |
| 1837 | char value[16]; |
| 1838 | |
| 1839 | if (!read_relative_register_raw_bytes (regno, value) |
| 1840 | && !read_relative_register_raw_bytes (regno + 1, value + 8)) |
| 1841 | { |
| 1842 | printf_unfiltered ("\t"); |
| 1843 | print_floating (value, builtin_type_long_double, gdb_stdout); |
| 1844 | } |
| 1845 | return; |
| 1846 | } |
| 1847 | #endif |
| 1848 | |
| 1849 | /* FIXME: Some of these are priviledged registers. |
| 1850 | Not sure how they should be handled. */ |
| 1851 | |
| 1852 | #define BITS(n, mask) ((int) (((val) >> (n)) & (mask))) |
| 1853 | |
| 1854 | val = read_register (regno); |
| 1855 | |
| 1856 | /* pages 40 - 60 */ |
| 1857 | if (GDB_TARGET_IS_SPARC64) |
| 1858 | switch (regno) |
| 1859 | { |
| 1860 | case CCR_REGNUM: |
| 1861 | printf_unfiltered ("\t"); |
| 1862 | dump_ccreg ("xcc", val >> 4); |
| 1863 | printf_unfiltered (", "); |
| 1864 | dump_ccreg ("icc", val & 15); |
| 1865 | break; |
| 1866 | case FPRS_REGNUM: |
| 1867 | printf ("\tfef:%d, du:%d, dl:%d", |
| 1868 | BITS (2, 1), BITS (1, 1), BITS (0, 1)); |
| 1869 | break; |
| 1870 | case FSR_REGNUM: |
| 1871 | { |
| 1872 | static char *fcc[4] = |
| 1873 | {"=", "<", ">", "?"}; |
| 1874 | static char *rd[4] = |
| 1875 | {"N", "0", "+", "-"}; |
| 1876 | /* Long, but I'd rather leave it as is and use a wide screen. */ |
| 1877 | printf_filtered ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ", |
| 1878 | fcc[BITS (10, 3)], fcc[BITS (32, 3)], |
| 1879 | fcc[BITS (34, 3)], fcc[BITS (36, 3)], |
| 1880 | rd[BITS (30, 3)], BITS (23, 31)); |
| 1881 | printf_filtered ("ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d", |
| 1882 | BITS (22, 1), BITS (17, 7), BITS (14, 7), |
| 1883 | BITS (13, 1), BITS (5, 31), BITS (0, 31)); |
| 1884 | break; |
| 1885 | } |
| 1886 | case ASI_REGNUM: |
| 1887 | { |
| 1888 | char *asi = decode_asi (val); |
| 1889 | if (asi != NULL) |
| 1890 | printf ("\t%s", asi); |
| 1891 | break; |
| 1892 | } |
| 1893 | case VER_REGNUM: |
| 1894 | printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d", |
| 1895 | BITS (48, 0xffff), BITS (32, 0xffff), |
| 1896 | BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31)); |
| 1897 | break; |
| 1898 | case PSTATE_REGNUM: |
| 1899 | { |
| 1900 | static char *mm[4] = |
| 1901 | {"tso", "pso", "rso", "?"}; |
| 1902 | printf_filtered ("\tcle:%d, tle:%d, mm:%s, red:%d, ", |
| 1903 | BITS (9, 1), BITS (8, 1), |
| 1904 | mm[BITS (6, 3)], BITS (5, 1)); |
| 1905 | printf_filtered ("pef:%d, am:%d, priv:%d, ie:%d, ag:%d", |
| 1906 | BITS (4, 1), BITS (3, 1), BITS (2, 1), |
| 1907 | BITS (1, 1), BITS (0, 1)); |
| 1908 | break; |
| 1909 | } |
| 1910 | case TSTATE_REGNUM: |
| 1911 | /* FIXME: print all 4? */ |
| 1912 | break; |
| 1913 | case TT_REGNUM: |
| 1914 | /* FIXME: print all 4? */ |
| 1915 | break; |
| 1916 | case TPC_REGNUM: |
| 1917 | /* FIXME: print all 4? */ |
| 1918 | break; |
| 1919 | case TNPC_REGNUM: |
| 1920 | /* FIXME: print all 4? */ |
| 1921 | break; |
| 1922 | case WSTATE_REGNUM: |
| 1923 | printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7)); |
| 1924 | break; |
| 1925 | case CWP_REGNUM: |
| 1926 | printf ("\t%d", BITS (0, 31)); |
| 1927 | break; |
| 1928 | case CANSAVE_REGNUM: |
| 1929 | printf ("\t%-2d before spill", BITS (0, 31)); |
| 1930 | break; |
| 1931 | case CANRESTORE_REGNUM: |
| 1932 | printf ("\t%-2d before fill", BITS (0, 31)); |
| 1933 | break; |
| 1934 | case CLEANWIN_REGNUM: |
| 1935 | printf ("\t%-2d before clean", BITS (0, 31)); |
| 1936 | break; |
| 1937 | case OTHERWIN_REGNUM: |
| 1938 | printf ("\t%d", BITS (0, 31)); |
| 1939 | break; |
| 1940 | } |
| 1941 | else /* Sparc32 */ |
| 1942 | switch (regno) |
| 1943 | { |
| 1944 | case PS_REGNUM: |
| 1945 | printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d", |
| 1946 | BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-', |
| 1947 | BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-', |
| 1948 | BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1), |
| 1949 | BITS (0, 31)); |
| 1950 | break; |
| 1951 | case FPS_REGNUM: |
| 1952 | { |
| 1953 | static char *fcc[4] = |
| 1954 | {"=", "<", ">", "?"}; |
| 1955 | static char *rd[4] = |
| 1956 | {"N", "0", "+", "-"}; |
| 1957 | /* Long, but I'd rather leave it as is and use a wide screen. */ |
| 1958 | printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, " |
| 1959 | "fcc:%s, aexc:%d, cexc:%d", |
| 1960 | rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7), |
| 1961 | BITS (14, 7), BITS (13, 1), fcc[BITS (10, 3)], BITS (5, 31), |
| 1962 | BITS (0, 31)); |
| 1963 | break; |
| 1964 | } |
| 1965 | } |
| 1966 | |
| 1967 | #undef BITS |
| 1968 | } |
| 1969 | \f |
| 1970 | int |
| 1971 | gdb_print_insn_sparc (bfd_vma memaddr, disassemble_info *info) |
| 1972 | { |
| 1973 | /* It's necessary to override mach again because print_insn messes it up. */ |
| 1974 | info->mach = TARGET_ARCHITECTURE->mach; |
| 1975 | return print_insn_sparc (memaddr, info); |
| 1976 | } |
| 1977 | \f |
| 1978 | /* The SPARC passes the arguments on the stack; arguments smaller |
| 1979 | than an int are promoted to an int. The first 6 words worth of |
| 1980 | args are also passed in registers o0 - o5. */ |
| 1981 | |
| 1982 | CORE_ADDR |
| 1983 | sparc32_push_arguments (int nargs, value_ptr *args, CORE_ADDR sp, |
| 1984 | int struct_return, CORE_ADDR struct_addr) |
| 1985 | { |
| 1986 | int i, j, oregnum; |
| 1987 | int accumulate_size = 0; |
| 1988 | struct sparc_arg |
| 1989 | { |
| 1990 | char *contents; |
| 1991 | int len; |
| 1992 | int offset; |
| 1993 | }; |
| 1994 | struct sparc_arg *sparc_args = |
| 1995 | (struct sparc_arg *) alloca (nargs * sizeof (struct sparc_arg)); |
| 1996 | struct sparc_arg *m_arg; |
| 1997 | |
| 1998 | /* Promote arguments if necessary, and calculate their stack offsets |
| 1999 | and sizes. */ |
| 2000 | for (i = 0, m_arg = sparc_args; i < nargs; i++, m_arg++) |
| 2001 | { |
| 2002 | value_ptr arg = args[i]; |
| 2003 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
| 2004 | /* Cast argument to long if necessary as the compiler does it too. */ |
| 2005 | switch (TYPE_CODE (arg_type)) |
| 2006 | { |
| 2007 | case TYPE_CODE_INT: |
| 2008 | case TYPE_CODE_BOOL: |
| 2009 | case TYPE_CODE_CHAR: |
| 2010 | case TYPE_CODE_RANGE: |
| 2011 | case TYPE_CODE_ENUM: |
| 2012 | if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long)) |
| 2013 | { |
| 2014 | arg_type = builtin_type_long; |
| 2015 | arg = value_cast (arg_type, arg); |
| 2016 | } |
| 2017 | break; |
| 2018 | default: |
| 2019 | break; |
| 2020 | } |
| 2021 | m_arg->len = TYPE_LENGTH (arg_type); |
| 2022 | m_arg->offset = accumulate_size; |
| 2023 | accumulate_size = (accumulate_size + m_arg->len + 3) & ~3; |
| 2024 | m_arg->contents = VALUE_CONTENTS (arg); |
| 2025 | } |
| 2026 | |
| 2027 | /* Make room for the arguments on the stack. */ |
| 2028 | accumulate_size += CALL_DUMMY_STACK_ADJUST; |
| 2029 | sp = ((sp - accumulate_size) & ~7) + CALL_DUMMY_STACK_ADJUST; |
| 2030 | |
| 2031 | /* `Push' arguments on the stack. */ |
| 2032 | for (i = 0, oregnum = 0, m_arg = sparc_args; |
| 2033 | i < nargs; |
| 2034 | i++, m_arg++) |
| 2035 | { |
| 2036 | write_memory (sp + m_arg->offset, m_arg->contents, m_arg->len); |
| 2037 | for (j = 0; |
| 2038 | j < m_arg->len && oregnum < 6; |
| 2039 | j += SPARC_INTREG_SIZE, oregnum++) |
| 2040 | write_register_gen (O0_REGNUM + oregnum, m_arg->contents + j); |
| 2041 | } |
| 2042 | |
| 2043 | return sp; |
| 2044 | } |
| 2045 | |
| 2046 | |
| 2047 | /* Extract from an array REGBUF containing the (raw) register state |
| 2048 | a function return value of type TYPE, and copy that, in virtual format, |
| 2049 | into VALBUF. */ |
| 2050 | |
| 2051 | void |
| 2052 | sparc32_extract_return_value (struct type *type, char *regbuf, char *valbuf) |
| 2053 | { |
| 2054 | int typelen = TYPE_LENGTH (type); |
| 2055 | int regsize = REGISTER_RAW_SIZE (O0_REGNUM); |
| 2056 | |
| 2057 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) |
| 2058 | memcpy (valbuf, ®buf[REGISTER_BYTE (FP0_REGNUM)], typelen); |
| 2059 | else |
| 2060 | memcpy (valbuf, |
| 2061 | ®buf[O0_REGNUM * regsize + |
| 2062 | (typelen >= regsize |
| 2063 | || TARGET_BYTE_ORDER == LITTLE_ENDIAN ? 0 |
| 2064 | : regsize - typelen)], |
| 2065 | typelen); |
| 2066 | } |
| 2067 | |
| 2068 | |
| 2069 | /* Write into appropriate registers a function return value |
| 2070 | of type TYPE, given in virtual format. On SPARCs with FPUs, |
| 2071 | float values are returned in %f0 (and %f1). In all other cases, |
| 2072 | values are returned in register %o0. */ |
| 2073 | |
| 2074 | void |
| 2075 | sparc_store_return_value (struct type *type, char *valbuf) |
| 2076 | { |
| 2077 | int regno; |
| 2078 | char *buffer; |
| 2079 | |
| 2080 | buffer = alloca(MAX_REGISTER_RAW_SIZE); |
| 2081 | |
| 2082 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) |
| 2083 | /* Floating-point values are returned in the register pair */ |
| 2084 | /* formed by %f0 and %f1 (doubles are, anyway). */ |
| 2085 | regno = FP0_REGNUM; |
| 2086 | else |
| 2087 | /* Other values are returned in register %o0. */ |
| 2088 | regno = O0_REGNUM; |
| 2089 | |
| 2090 | /* Add leading zeros to the value. */ |
| 2091 | if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (regno)) |
| 2092 | { |
| 2093 | memset (buffer, 0, REGISTER_RAW_SIZE (regno)); |
| 2094 | memcpy (buffer + REGISTER_RAW_SIZE (regno) - TYPE_LENGTH (type), valbuf, |
| 2095 | TYPE_LENGTH (type)); |
| 2096 | write_register_gen (regno, buffer); |
| 2097 | } |
| 2098 | else |
| 2099 | write_register_bytes (REGISTER_BYTE (regno), valbuf, TYPE_LENGTH (type)); |
| 2100 | } |
| 2101 | |
| 2102 | extern void |
| 2103 | sparclet_store_return_value (struct type *type, char *valbuf) |
| 2104 | { |
| 2105 | /* Other values are returned in register %o0. */ |
| 2106 | write_register_bytes (REGISTER_BYTE (O0_REGNUM), valbuf, |
| 2107 | TYPE_LENGTH (type)); |
| 2108 | } |
| 2109 | |
| 2110 | |
| 2111 | #ifndef CALL_DUMMY_CALL_OFFSET |
| 2112 | #define CALL_DUMMY_CALL_OFFSET \ |
| 2113 | (gdbarch_tdep (current_gdbarch)->call_dummy_call_offset) |
| 2114 | #endif /* CALL_DUMMY_CALL_OFFSET */ |
| 2115 | |
| 2116 | /* Insert the function address into a call dummy instruction sequence |
| 2117 | stored at DUMMY. |
| 2118 | |
| 2119 | For structs and unions, if the function was compiled with Sun cc, |
| 2120 | it expects 'unimp' after the call. But gcc doesn't use that |
| 2121 | (twisted) convention. So leave a nop there for gcc (FIX_CALL_DUMMY |
| 2122 | can assume it is operating on a pristine CALL_DUMMY, not one that |
| 2123 | has already been customized for a different function). */ |
| 2124 | |
| 2125 | void |
| 2126 | sparc_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, |
| 2127 | struct type *value_type, int using_gcc) |
| 2128 | { |
| 2129 | int i; |
| 2130 | |
| 2131 | /* Store the relative adddress of the target function into the |
| 2132 | 'call' instruction. */ |
| 2133 | store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET, 4, |
| 2134 | (0x40000000 |
| 2135 | | (((fun - (pc + CALL_DUMMY_CALL_OFFSET)) >> 2) |
| 2136 | & 0x3fffffff))); |
| 2137 | |
| 2138 | /* If the called function returns an aggregate value, fill in the UNIMP |
| 2139 | instruction containing the size of the returned aggregate return value, |
| 2140 | which follows the call instruction. |
| 2141 | For details see the SPARC Architecture Manual Version 8, Appendix D.3. |
| 2142 | |
| 2143 | Adjust the call_dummy_breakpoint_offset for the bp_call_dummy breakpoint |
| 2144 | to the proper address in the call dummy, so that `finish' after a stop |
| 2145 | in a call dummy works. |
| 2146 | Tweeking current_gdbarch is not an optimal solution, but the call to |
| 2147 | sparc_fix_call_dummy is immediately followed by a call to run_stack_dummy, |
| 2148 | which is the only function where dummy_breakpoint_offset is actually |
| 2149 | used, if it is non-zero. */ |
| 2150 | if (TYPE_CODE (value_type) == TYPE_CODE_STRUCT |
| 2151 | || TYPE_CODE (value_type) == TYPE_CODE_UNION) |
| 2152 | { |
| 2153 | store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET + 8, 4, |
| 2154 | TYPE_LENGTH (value_type) & 0x1fff); |
| 2155 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 0x30); |
| 2156 | } |
| 2157 | else |
| 2158 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 0x2c); |
| 2159 | |
| 2160 | if (!(GDB_TARGET_IS_SPARC64)) |
| 2161 | { |
| 2162 | /* If this is not a simulator target, change the first four |
| 2163 | instructions of the call dummy to NOPs. Those instructions |
| 2164 | include a 'save' instruction and are designed to work around |
| 2165 | problems with register window flushing in the simulator. */ |
| 2166 | |
| 2167 | if (strcmp (target_shortname, "sim") != 0) |
| 2168 | { |
| 2169 | for (i = 0; i < 4; i++) |
| 2170 | store_unsigned_integer (dummy + (i * 4), 4, 0x01000000); |
| 2171 | } |
| 2172 | } |
| 2173 | |
| 2174 | /* If this is a bi-endian target, GDB has written the call dummy |
| 2175 | in little-endian order. We must byte-swap it back to big-endian. */ |
| 2176 | if (bi_endian) |
| 2177 | { |
| 2178 | for (i = 0; i < CALL_DUMMY_LENGTH; i += 4) |
| 2179 | { |
| 2180 | char tmp = dummy[i]; |
| 2181 | dummy[i] = dummy[i + 3]; |
| 2182 | dummy[i + 3] = tmp; |
| 2183 | tmp = dummy[i + 1]; |
| 2184 | dummy[i + 1] = dummy[i + 2]; |
| 2185 | dummy[i + 2] = tmp; |
| 2186 | } |
| 2187 | } |
| 2188 | } |
| 2189 | |
| 2190 | |
| 2191 | /* Set target byte order based on machine type. */ |
| 2192 | |
| 2193 | static int |
| 2194 | sparc_target_architecture_hook (const bfd_arch_info_type *ap) |
| 2195 | { |
| 2196 | int i, j; |
| 2197 | |
| 2198 | if (ap->mach == bfd_mach_sparc_sparclite_le) |
| 2199 | { |
| 2200 | if (TARGET_BYTE_ORDER_SELECTABLE_P) |
| 2201 | { |
| 2202 | target_byte_order = LITTLE_ENDIAN; |
| 2203 | bi_endian = 1; |
| 2204 | } |
| 2205 | else |
| 2206 | { |
| 2207 | warning ("This GDB does not support little endian sparclite."); |
| 2208 | } |
| 2209 | } |
| 2210 | else |
| 2211 | bi_endian = 0; |
| 2212 | return 1; |
| 2213 | } |
| 2214 | \f |
| 2215 | |
| 2216 | /* |
| 2217 | * Module "constructor" function. |
| 2218 | */ |
| 2219 | |
| 2220 | static struct gdbarch * sparc_gdbarch_init (struct gdbarch_info info, |
| 2221 | struct gdbarch_list *arches); |
| 2222 | |
| 2223 | void |
| 2224 | _initialize_sparc_tdep (void) |
| 2225 | { |
| 2226 | /* Hook us into the gdbarch mechanism. */ |
| 2227 | register_gdbarch_init (bfd_arch_sparc, sparc_gdbarch_init); |
| 2228 | |
| 2229 | tm_print_insn = gdb_print_insn_sparc; |
| 2230 | tm_print_insn_info.mach = TM_PRINT_INSN_MACH; /* Selects sparc/sparclite */ |
| 2231 | target_architecture_hook = sparc_target_architecture_hook; |
| 2232 | } |
| 2233 | |
| 2234 | /* Compensate for stack bias. Note that we currently don't handle |
| 2235 | mixed 32/64 bit code. */ |
| 2236 | |
| 2237 | CORE_ADDR |
| 2238 | sparc64_read_sp (void) |
| 2239 | { |
| 2240 | CORE_ADDR sp = read_register (SP_REGNUM); |
| 2241 | |
| 2242 | if (sp & 1) |
| 2243 | sp += 2047; |
| 2244 | return sp; |
| 2245 | } |
| 2246 | |
| 2247 | CORE_ADDR |
| 2248 | sparc64_read_fp (void) |
| 2249 | { |
| 2250 | CORE_ADDR fp = read_register (FP_REGNUM); |
| 2251 | |
| 2252 | if (fp & 1) |
| 2253 | fp += 2047; |
| 2254 | return fp; |
| 2255 | } |
| 2256 | |
| 2257 | void |
| 2258 | sparc64_write_sp (CORE_ADDR val) |
| 2259 | { |
| 2260 | CORE_ADDR oldsp = read_register (SP_REGNUM); |
| 2261 | if (oldsp & 1) |
| 2262 | write_register (SP_REGNUM, val - 2047); |
| 2263 | else |
| 2264 | write_register (SP_REGNUM, val); |
| 2265 | } |
| 2266 | |
| 2267 | void |
| 2268 | sparc64_write_fp (CORE_ADDR val) |
| 2269 | { |
| 2270 | CORE_ADDR oldfp = read_register (FP_REGNUM); |
| 2271 | if (oldfp & 1) |
| 2272 | write_register (FP_REGNUM, val - 2047); |
| 2273 | else |
| 2274 | write_register (FP_REGNUM, val); |
| 2275 | } |
| 2276 | |
| 2277 | /* The SPARC 64 ABI passes floating-point arguments in FP0 to FP31, |
| 2278 | and all other arguments in O0 to O5. They are also copied onto |
| 2279 | the stack in the correct places. Apparently (empirically), |
| 2280 | structs of less than 16 bytes are passed member-by-member in |
| 2281 | separate registers, but I am unable to figure out the algorithm. |
| 2282 | Some members go in floating point regs, but I don't know which. |
| 2283 | |
| 2284 | FIXME: Handle small structs (less than 16 bytes containing floats). |
| 2285 | |
| 2286 | The counting regimen for using both integer and FP registers |
| 2287 | for argument passing is rather odd -- a single counter is used |
| 2288 | for both; this means that if the arguments alternate between |
| 2289 | int and float, we will waste every other register of both types. */ |
| 2290 | |
| 2291 | CORE_ADDR |
| 2292 | sparc64_push_arguments (int nargs, value_ptr *args, CORE_ADDR sp, |
| 2293 | int struct_return, CORE_ADDR struct_retaddr) |
| 2294 | { |
| 2295 | int i, j, register_counter = 0; |
| 2296 | CORE_ADDR tempsp; |
| 2297 | struct type *sparc_intreg_type = |
| 2298 | TYPE_LENGTH (builtin_type_long) == SPARC_INTREG_SIZE ? |
| 2299 | builtin_type_long : builtin_type_long_long; |
| 2300 | |
| 2301 | sp = (sp & ~(((unsigned long) SPARC_INTREG_SIZE) - 1UL)); |
| 2302 | |
| 2303 | /* Figure out how much space we'll need. */ |
| 2304 | for (i = nargs - 1; i >= 0; i--) |
| 2305 | { |
| 2306 | int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[i]))); |
| 2307 | value_ptr copyarg = args[i]; |
| 2308 | int copylen = len; |
| 2309 | |
| 2310 | if (copylen < SPARC_INTREG_SIZE) |
| 2311 | { |
| 2312 | copyarg = value_cast (sparc_intreg_type, copyarg); |
| 2313 | copylen = SPARC_INTREG_SIZE; |
| 2314 | } |
| 2315 | sp -= copylen; |
| 2316 | } |
| 2317 | |
| 2318 | /* Round down. */ |
| 2319 | sp = sp & ~7; |
| 2320 | tempsp = sp; |
| 2321 | |
| 2322 | /* if STRUCT_RETURN, then first argument is the struct return location. */ |
| 2323 | if (struct_return) |
| 2324 | write_register (O0_REGNUM + register_counter++, struct_retaddr); |
| 2325 | |
| 2326 | /* Now write the arguments onto the stack, while writing FP |
| 2327 | arguments into the FP registers, and other arguments into the |
| 2328 | first six 'O' registers. */ |
| 2329 | |
| 2330 | for (i = 0; i < nargs; i++) |
| 2331 | { |
| 2332 | int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[i]))); |
| 2333 | value_ptr copyarg = args[i]; |
| 2334 | enum type_code typecode = TYPE_CODE (VALUE_TYPE (args[i])); |
| 2335 | int copylen = len; |
| 2336 | |
| 2337 | if (typecode == TYPE_CODE_INT || |
| 2338 | typecode == TYPE_CODE_BOOL || |
| 2339 | typecode == TYPE_CODE_CHAR || |
| 2340 | typecode == TYPE_CODE_RANGE || |
| 2341 | typecode == TYPE_CODE_ENUM) |
| 2342 | if (len < SPARC_INTREG_SIZE) |
| 2343 | { |
| 2344 | /* Small ints will all take up the size of one intreg on |
| 2345 | the stack. */ |
| 2346 | copyarg = value_cast (sparc_intreg_type, copyarg); |
| 2347 | copylen = SPARC_INTREG_SIZE; |
| 2348 | } |
| 2349 | |
| 2350 | write_memory (tempsp, VALUE_CONTENTS (copyarg), copylen); |
| 2351 | tempsp += copylen; |
| 2352 | |
| 2353 | /* Corner case: Structs consisting of a single float member are floats. |
| 2354 | * FIXME! I don't know about structs containing multiple floats! |
| 2355 | * Structs containing mixed floats and ints are even more weird. |
| 2356 | */ |
| 2357 | |
| 2358 | |
| 2359 | |
| 2360 | /* Separate float args from all other args. */ |
| 2361 | if (typecode == TYPE_CODE_FLT && SPARC_HAS_FPU) |
| 2362 | { |
| 2363 | if (register_counter < 16) |
| 2364 | { |
| 2365 | /* This arg gets copied into a FP register. */ |
| 2366 | int fpreg; |
| 2367 | |
| 2368 | switch (len) { |
| 2369 | case 4: /* Single-precision (float) */ |
| 2370 | fpreg = FP0_REGNUM + 2 * register_counter + 1; |
| 2371 | register_counter += 1; |
| 2372 | break; |
| 2373 | case 8: /* Double-precision (double) */ |
| 2374 | fpreg = FP0_REGNUM + 2 * register_counter; |
| 2375 | register_counter += 1; |
| 2376 | break; |
| 2377 | case 16: /* Quad-precision (long double) */ |
| 2378 | fpreg = FP0_REGNUM + 2 * register_counter; |
| 2379 | register_counter += 2; |
| 2380 | break; |
| 2381 | } |
| 2382 | write_register_bytes (REGISTER_BYTE (fpreg), |
| 2383 | VALUE_CONTENTS (args[i]), |
| 2384 | len); |
| 2385 | } |
| 2386 | } |
| 2387 | else /* all other args go into the first six 'o' registers */ |
| 2388 | { |
| 2389 | for (j = 0; |
| 2390 | j < len && register_counter < 6; |
| 2391 | j += SPARC_INTREG_SIZE) |
| 2392 | { |
| 2393 | int oreg = O0_REGNUM + register_counter; |
| 2394 | |
| 2395 | write_register_gen (oreg, VALUE_CONTENTS (copyarg) + j); |
| 2396 | register_counter += 1; |
| 2397 | } |
| 2398 | } |
| 2399 | } |
| 2400 | return sp; |
| 2401 | } |
| 2402 | |
| 2403 | /* Values <= 32 bytes are returned in o0-o3 (floating-point values are |
| 2404 | returned in f0-f3). */ |
| 2405 | |
| 2406 | void |
| 2407 | sp64_extract_return_value (struct type *type, char *regbuf, char *valbuf, |
| 2408 | int bitoffset) |
| 2409 | { |
| 2410 | int typelen = TYPE_LENGTH (type); |
| 2411 | int regsize = REGISTER_RAW_SIZE (O0_REGNUM); |
| 2412 | |
| 2413 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) |
| 2414 | { |
| 2415 | memcpy (valbuf, ®buf[REGISTER_BYTE (FP0_REGNUM)], typelen); |
| 2416 | return; |
| 2417 | } |
| 2418 | |
| 2419 | if (TYPE_CODE (type) != TYPE_CODE_STRUCT |
| 2420 | || (TYPE_LENGTH (type) > 32)) |
| 2421 | { |
| 2422 | memcpy (valbuf, |
| 2423 | ®buf[O0_REGNUM * regsize + |
| 2424 | (typelen >= regsize ? 0 : regsize - typelen)], |
| 2425 | typelen); |
| 2426 | return; |
| 2427 | } |
| 2428 | else |
| 2429 | { |
| 2430 | char *o0 = ®buf[O0_REGNUM * regsize]; |
| 2431 | char *f0 = ®buf[FP0_REGNUM * regsize]; |
| 2432 | int x; |
| 2433 | |
| 2434 | for (x = 0; x < TYPE_NFIELDS (type); x++) |
| 2435 | { |
| 2436 | struct field *f = &TYPE_FIELDS (type)[x]; |
| 2437 | /* FIXME: We may need to handle static fields here. */ |
| 2438 | int whichreg = (f->loc.bitpos + bitoffset) / 32; |
| 2439 | int remainder = ((f->loc.bitpos + bitoffset) % 32) / 8; |
| 2440 | int where = (f->loc.bitpos + bitoffset) / 8; |
| 2441 | int size = TYPE_LENGTH (f->type); |
| 2442 | int typecode = TYPE_CODE (f->type); |
| 2443 | |
| 2444 | if (typecode == TYPE_CODE_STRUCT) |
| 2445 | { |
| 2446 | sp64_extract_return_value (f->type, |
| 2447 | regbuf, |
| 2448 | valbuf, |
| 2449 | bitoffset + f->loc.bitpos); |
| 2450 | } |
| 2451 | else if (typecode == TYPE_CODE_FLT && SPARC_HAS_FPU) |
| 2452 | { |
| 2453 | memcpy (valbuf + where, &f0[whichreg * 4] + remainder, size); |
| 2454 | } |
| 2455 | else |
| 2456 | { |
| 2457 | memcpy (valbuf + where, &o0[whichreg * 4] + remainder, size); |
| 2458 | } |
| 2459 | } |
| 2460 | } |
| 2461 | } |
| 2462 | |
| 2463 | extern void |
| 2464 | sparc64_extract_return_value (struct type *type, char *regbuf, char *valbuf) |
| 2465 | { |
| 2466 | sp64_extract_return_value (type, regbuf, valbuf, 0); |
| 2467 | } |
| 2468 | |
| 2469 | extern void |
| 2470 | sparclet_extract_return_value (struct type *type, |
| 2471 | char *regbuf, |
| 2472 | char *valbuf) |
| 2473 | { |
| 2474 | regbuf += REGISTER_RAW_SIZE (O0_REGNUM) * 8; |
| 2475 | if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (O0_REGNUM)) |
| 2476 | regbuf += REGISTER_RAW_SIZE (O0_REGNUM) - TYPE_LENGTH (type); |
| 2477 | |
| 2478 | memcpy ((void *) valbuf, regbuf, TYPE_LENGTH (type)); |
| 2479 | } |
| 2480 | |
| 2481 | |
| 2482 | extern CORE_ADDR |
| 2483 | sparc32_stack_align (CORE_ADDR addr) |
| 2484 | { |
| 2485 | return ((addr + 7) & -8); |
| 2486 | } |
| 2487 | |
| 2488 | extern CORE_ADDR |
| 2489 | sparc64_stack_align (CORE_ADDR addr) |
| 2490 | { |
| 2491 | return ((addr + 15) & -16); |
| 2492 | } |
| 2493 | |
| 2494 | extern void |
| 2495 | sparc_print_extra_frame_info (struct frame_info *fi) |
| 2496 | { |
| 2497 | if (fi && fi->extra_info && fi->extra_info->flat) |
| 2498 | printf_filtered (" flat, pc saved at 0x%s, fp saved at 0x%s\n", |
| 2499 | paddr_nz (fi->extra_info->pc_addr), |
| 2500 | paddr_nz (fi->extra_info->fp_addr)); |
| 2501 | } |
| 2502 | |
| 2503 | /* MULTI_ARCH support */ |
| 2504 | |
| 2505 | static char * |
| 2506 | sparc32_register_name (int regno) |
| 2507 | { |
| 2508 | static char *register_names[] = |
| 2509 | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
| 2510 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", |
| 2511 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", |
| 2512 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", |
| 2513 | |
| 2514 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 2515 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 2516 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 2517 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 2518 | |
| 2519 | "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" |
| 2520 | }; |
| 2521 | |
| 2522 | if (regno < 0 || |
| 2523 | regno >= (sizeof (register_names) / sizeof (register_names[0]))) |
| 2524 | return NULL; |
| 2525 | else |
| 2526 | return register_names[regno]; |
| 2527 | } |
| 2528 | |
| 2529 | static char * |
| 2530 | sparc64_register_name (int regno) |
| 2531 | { |
| 2532 | static char *register_names[] = |
| 2533 | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
| 2534 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", |
| 2535 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", |
| 2536 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", |
| 2537 | |
| 2538 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 2539 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 2540 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 2541 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 2542 | "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46", |
| 2543 | "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62", |
| 2544 | |
| 2545 | "pc", "npc", "ccr", "fsr", "fprs", "y", "asi", "ver", |
| 2546 | "tick", "pil", "pstate", "tstate", "tba", "tl", "tt", "tpc", |
| 2547 | "tnpc", "wstate", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", |
| 2548 | "asr16", "asr17", "asr18", "asr19", "asr20", "asr21", "asr22", "asr23", |
| 2549 | "asr24", "asr25", "asr26", "asr27", "asr28", "asr29", "asr30", "asr31", |
| 2550 | /* These are here at the end to simplify removing them if we have to. */ |
| 2551 | "icc", "xcc", "fcc0", "fcc1", "fcc2", "fcc3" |
| 2552 | }; |
| 2553 | |
| 2554 | if (regno < 0 || |
| 2555 | regno >= (sizeof (register_names) / sizeof (register_names[0]))) |
| 2556 | return NULL; |
| 2557 | else |
| 2558 | return register_names[regno]; |
| 2559 | } |
| 2560 | |
| 2561 | static char * |
| 2562 | sparclite_register_name (int regno) |
| 2563 | { |
| 2564 | static char *register_names[] = |
| 2565 | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
| 2566 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", |
| 2567 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", |
| 2568 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", |
| 2569 | |
| 2570 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 2571 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 2572 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 2573 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 2574 | |
| 2575 | "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr", |
| 2576 | "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr" |
| 2577 | }; |
| 2578 | |
| 2579 | if (regno < 0 || |
| 2580 | regno >= (sizeof (register_names) / sizeof (register_names[0]))) |
| 2581 | return NULL; |
| 2582 | else |
| 2583 | return register_names[regno]; |
| 2584 | } |
| 2585 | |
| 2586 | static char * |
| 2587 | sparclet_register_name (int regno) |
| 2588 | { |
| 2589 | static char *register_names[] = |
| 2590 | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
| 2591 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", |
| 2592 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", |
| 2593 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", |
| 2594 | |
| 2595 | "", "", "", "", "", "", "", "", /* no floating point registers */ |
| 2596 | "", "", "", "", "", "", "", "", |
| 2597 | "", "", "", "", "", "", "", "", |
| 2598 | "", "", "", "", "", "", "", "", |
| 2599 | |
| 2600 | "y", "psr", "wim", "tbr", "pc", "npc", "", "", /* no FPSR or CPSR */ |
| 2601 | "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "", |
| 2602 | |
| 2603 | /* ASR15 ASR19 (don't display them) */ |
| 2604 | "asr1", "", "asr17", "asr18", "", "asr20", "asr21", "asr22" |
| 2605 | /* None of the rest get displayed */ |
| 2606 | #if 0 |
| 2607 | "awr0", "awr1", "awr2", "awr3", "awr4", "awr5", "awr6", "awr7", |
| 2608 | "awr8", "awr9", "awr10", "awr11", "awr12", "awr13", "awr14", "awr15", |
| 2609 | "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23", |
| 2610 | "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31", |
| 2611 | "apsr" |
| 2612 | #endif /* 0 */ |
| 2613 | }; |
| 2614 | |
| 2615 | if (regno < 0 || |
| 2616 | regno >= (sizeof (register_names) / sizeof (register_names[0]))) |
| 2617 | return NULL; |
| 2618 | else |
| 2619 | return register_names[regno]; |
| 2620 | } |
| 2621 | |
| 2622 | CORE_ADDR |
| 2623 | sparc_push_return_address (CORE_ADDR pc_unused, CORE_ADDR sp) |
| 2624 | { |
| 2625 | if (CALL_DUMMY_LOCATION == AT_ENTRY_POINT) |
| 2626 | { |
| 2627 | /* The return PC of the dummy_frame is the former 'current' PC |
| 2628 | (where we were before we made the target function call). |
| 2629 | This is saved in %i7 by push_dummy_frame. |
| 2630 | |
| 2631 | We will save the 'call dummy location' (ie. the address |
| 2632 | to which the target function will return) in %o7. |
| 2633 | This address will actually be the program's entry point. |
| 2634 | There will be a special call_dummy breakpoint there. */ |
| 2635 | |
| 2636 | write_register (O7_REGNUM, |
| 2637 | CALL_DUMMY_ADDRESS () - 8); |
| 2638 | } |
| 2639 | |
| 2640 | return sp; |
| 2641 | } |
| 2642 | |
| 2643 | /* Should call_function allocate stack space for a struct return? */ |
| 2644 | |
| 2645 | static int |
| 2646 | sparc64_use_struct_convention (int gcc_p, struct type *type) |
| 2647 | { |
| 2648 | return (TYPE_LENGTH (type) > 32); |
| 2649 | } |
| 2650 | |
| 2651 | /* Store the address of the place in which to copy the structure the |
| 2652 | subroutine will return. This is called from call_function_by_hand. |
| 2653 | The ultimate mystery is, tho, what is the value "16"? |
| 2654 | |
| 2655 | MVS: That's the offset from where the sp is now, to where the |
| 2656 | subroutine is gonna expect to find the struct return address. */ |
| 2657 | |
| 2658 | static void |
| 2659 | sparc32_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
| 2660 | { |
| 2661 | char *val; |
| 2662 | CORE_ADDR o7; |
| 2663 | |
| 2664 | val = alloca (SPARC_INTREG_SIZE); |
| 2665 | store_unsigned_integer (val, SPARC_INTREG_SIZE, addr); |
| 2666 | write_memory (sp + (16 * SPARC_INTREG_SIZE), val, SPARC_INTREG_SIZE); |
| 2667 | |
| 2668 | if (CALL_DUMMY_LOCATION == AT_ENTRY_POINT) |
| 2669 | { |
| 2670 | /* Now adjust the value of the link register, which was previously |
| 2671 | stored by push_return_address. Functions that return structs are |
| 2672 | peculiar in that they return to link register + 12, rather than |
| 2673 | link register + 8. */ |
| 2674 | |
| 2675 | o7 = read_register (O7_REGNUM); |
| 2676 | write_register (O7_REGNUM, o7 - 4); |
| 2677 | } |
| 2678 | } |
| 2679 | |
| 2680 | static void |
| 2681 | sparc64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
| 2682 | { |
| 2683 | /* FIXME: V9 uses %o0 for this. */ |
| 2684 | /* FIXME MVS: Only for small enough structs!!! */ |
| 2685 | |
| 2686 | target_write_memory (sp + (16 * SPARC_INTREG_SIZE), |
| 2687 | (char *) &addr, SPARC_INTREG_SIZE); |
| 2688 | #if 0 |
| 2689 | if (CALL_DUMMY_LOCATION == AT_ENTRY_POINT) |
| 2690 | { |
| 2691 | /* Now adjust the value of the link register, which was previously |
| 2692 | stored by push_return_address. Functions that return structs are |
| 2693 | peculiar in that they return to link register + 12, rather than |
| 2694 | link register + 8. */ |
| 2695 | |
| 2696 | write_register (O7_REGNUM, read_register (O7_REGNUM) - 4); |
| 2697 | } |
| 2698 | #endif |
| 2699 | } |
| 2700 | |
| 2701 | /* Default target data type for register REGNO. */ |
| 2702 | |
| 2703 | static struct type * |
| 2704 | sparc32_register_virtual_type (int regno) |
| 2705 | { |
| 2706 | if (regno == PC_REGNUM || |
| 2707 | regno == FP_REGNUM || |
| 2708 | regno == SP_REGNUM) |
| 2709 | return builtin_type_unsigned_int; |
| 2710 | if (regno < 32) |
| 2711 | return builtin_type_int; |
| 2712 | if (regno < 64) |
| 2713 | return builtin_type_float; |
| 2714 | return builtin_type_int; |
| 2715 | } |
| 2716 | |
| 2717 | static struct type * |
| 2718 | sparc64_register_virtual_type (int regno) |
| 2719 | { |
| 2720 | if (regno == PC_REGNUM || |
| 2721 | regno == FP_REGNUM || |
| 2722 | regno == SP_REGNUM) |
| 2723 | return builtin_type_unsigned_long_long; |
| 2724 | if (regno < 32) |
| 2725 | return builtin_type_long_long; |
| 2726 | if (regno < 64) |
| 2727 | return builtin_type_float; |
| 2728 | if (regno < 80) |
| 2729 | return builtin_type_double; |
| 2730 | return builtin_type_long_long; |
| 2731 | } |
| 2732 | |
| 2733 | /* Number of bytes of storage in the actual machine representation for |
| 2734 | register REGNO. */ |
| 2735 | |
| 2736 | static int |
| 2737 | sparc32_register_size (int regno) |
| 2738 | { |
| 2739 | return 4; |
| 2740 | } |
| 2741 | |
| 2742 | static int |
| 2743 | sparc64_register_size (int regno) |
| 2744 | { |
| 2745 | return (regno < 32 ? 8 : regno < 64 ? 4 : 8); |
| 2746 | } |
| 2747 | |
| 2748 | /* Index within the `registers' buffer of the first byte of the space |
| 2749 | for register REGNO. */ |
| 2750 | |
| 2751 | static int |
| 2752 | sparc32_register_byte (int regno) |
| 2753 | { |
| 2754 | return (regno * 4); |
| 2755 | } |
| 2756 | |
| 2757 | static int |
| 2758 | sparc64_register_byte (int regno) |
| 2759 | { |
| 2760 | if (regno < 32) |
| 2761 | return regno * 8; |
| 2762 | else if (regno < 64) |
| 2763 | return 32 * 8 + (regno - 32) * 4; |
| 2764 | else if (regno < 80) |
| 2765 | return 32 * 8 + 32 * 4 + (regno - 64) * 8; |
| 2766 | else |
| 2767 | return 64 * 8 + (regno - 80) * 8; |
| 2768 | } |
| 2769 | |
| 2770 | /* Advance PC across any function entry prologue instructions to reach |
| 2771 | some "real" code. SKIP_PROLOGUE_FRAMELESS_P advances the PC past |
| 2772 | some of the prologue, but stops as soon as it knows that the |
| 2773 | function has a frame. Its result is equal to its input PC if the |
| 2774 | function is frameless, unequal otherwise. */ |
| 2775 | |
| 2776 | static CORE_ADDR |
| 2777 | sparc_gdbarch_skip_prologue (CORE_ADDR ip) |
| 2778 | { |
| 2779 | return examine_prologue (ip, 0, NULL, NULL); |
| 2780 | } |
| 2781 | |
| 2782 | /* Immediately after a function call, return the saved pc. |
| 2783 | Can't go through the frames for this because on some machines |
| 2784 | the new frame is not set up until the new function executes |
| 2785 | some instructions. */ |
| 2786 | |
| 2787 | static CORE_ADDR |
| 2788 | sparc_saved_pc_after_call (struct frame_info *fi) |
| 2789 | { |
| 2790 | return sparc_pc_adjust (read_register (RP_REGNUM)); |
| 2791 | } |
| 2792 | |
| 2793 | /* Convert registers between 'raw' and 'virtual' formats. |
| 2794 | They are the same on sparc, so there's nothing to do. */ |
| 2795 | |
| 2796 | static void |
| 2797 | sparc_convert_to_virtual (int regnum, struct type *type, char *from, char *to) |
| 2798 | { /* do nothing (should never be called) */ |
| 2799 | } |
| 2800 | |
| 2801 | static void |
| 2802 | sparc_convert_to_raw (struct type *type, int regnum, char *from, char *to) |
| 2803 | { /* do nothing (should never be called) */ |
| 2804 | } |
| 2805 | |
| 2806 | /* Init saved regs: nothing to do, just a place-holder function. */ |
| 2807 | |
| 2808 | static void |
| 2809 | sparc_frame_init_saved_regs (struct frame_info *fi_ignored) |
| 2810 | { /* no-op */ |
| 2811 | } |
| 2812 | |
| 2813 | /* The frame address: stored in the 'frame' field of the frame_info. */ |
| 2814 | |
| 2815 | static CORE_ADDR |
| 2816 | sparc_frame_address (struct frame_info *fi) |
| 2817 | { |
| 2818 | return fi->frame; |
| 2819 | } |
| 2820 | |
| 2821 | /* gdbarch fix call dummy: |
| 2822 | All this function does is rearrange the arguments before calling |
| 2823 | sparc_fix_call_dummy (which does the real work). */ |
| 2824 | |
| 2825 | static void |
| 2826 | sparc_gdbarch_fix_call_dummy (char *dummy, |
| 2827 | CORE_ADDR pc, |
| 2828 | CORE_ADDR fun, |
| 2829 | int nargs, |
| 2830 | struct value **args, |
| 2831 | struct type *type, |
| 2832 | int gcc_p) |
| 2833 | { |
| 2834 | if (CALL_DUMMY_LOCATION == ON_STACK) |
| 2835 | sparc_fix_call_dummy (dummy, pc, fun, type, gcc_p); |
| 2836 | } |
| 2837 | |
| 2838 | /* Coerce float to double: a no-op. */ |
| 2839 | |
| 2840 | static int |
| 2841 | sparc_coerce_float_to_double (struct type *formal, struct type *actual) |
| 2842 | { |
| 2843 | return 1; |
| 2844 | } |
| 2845 | |
| 2846 | /* CALL_DUMMY_ADDRESS: fetch the breakpoint address for a call dummy. */ |
| 2847 | |
| 2848 | static CORE_ADDR |
| 2849 | sparc_call_dummy_address (void) |
| 2850 | { |
| 2851 | return (CALL_DUMMY_START_OFFSET) + CALL_DUMMY_BREAKPOINT_OFFSET; |
| 2852 | } |
| 2853 | |
| 2854 | /* Supply the Y register number to those that need it. */ |
| 2855 | |
| 2856 | int |
| 2857 | sparc_y_regnum (void) |
| 2858 | { |
| 2859 | return gdbarch_tdep (current_gdbarch)->y_regnum; |
| 2860 | } |
| 2861 | |
| 2862 | int |
| 2863 | sparc_reg_struct_has_addr (int gcc_p, struct type *type) |
| 2864 | { |
| 2865 | if (GDB_TARGET_IS_SPARC64) |
| 2866 | return (TYPE_LENGTH (type) > 32); |
| 2867 | else |
| 2868 | return (gcc_p != 1); |
| 2869 | } |
| 2870 | |
| 2871 | int |
| 2872 | sparc_intreg_size (void) |
| 2873 | { |
| 2874 | return SPARC_INTREG_SIZE; |
| 2875 | } |
| 2876 | |
| 2877 | static int |
| 2878 | sparc_return_value_on_stack (struct type *type) |
| 2879 | { |
| 2880 | if (TYPE_CODE (type) == TYPE_CODE_FLT && |
| 2881 | TYPE_LENGTH (type) > 8) |
| 2882 | return 1; |
| 2883 | else |
| 2884 | return 0; |
| 2885 | } |
| 2886 | |
| 2887 | /* |
| 2888 | * Gdbarch "constructor" function. |
| 2889 | */ |
| 2890 | |
| 2891 | #define SPARC32_CALL_DUMMY_ON_STACK |
| 2892 | |
| 2893 | #define SPARC_SP_REGNUM 14 |
| 2894 | #define SPARC_FP_REGNUM 30 |
| 2895 | #define SPARC_FP0_REGNUM 32 |
| 2896 | #define SPARC32_NPC_REGNUM 69 |
| 2897 | #define SPARC32_PC_REGNUM 68 |
| 2898 | #define SPARC32_Y_REGNUM 64 |
| 2899 | #define SPARC64_PC_REGNUM 80 |
| 2900 | #define SPARC64_NPC_REGNUM 81 |
| 2901 | #define SPARC64_Y_REGNUM 85 |
| 2902 | |
| 2903 | static struct gdbarch * |
| 2904 | sparc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 2905 | { |
| 2906 | struct gdbarch *gdbarch; |
| 2907 | struct gdbarch_tdep *tdep; |
| 2908 | |
| 2909 | static LONGEST call_dummy_32[] = |
| 2910 | { 0xbc100001, 0x9de38000, 0xbc100002, 0xbe100003, |
| 2911 | 0xda03a058, 0xd803a054, 0xd603a050, 0xd403a04c, |
| 2912 | 0xd203a048, 0x40000000, 0xd003a044, 0x01000000, |
| 2913 | 0x91d02001, 0x01000000 |
| 2914 | }; |
| 2915 | static LONGEST call_dummy_64[] = |
| 2916 | { 0x9de3bec0fd3fa7f7LL, 0xf93fa7eff53fa7e7LL, |
| 2917 | 0xf13fa7dfed3fa7d7LL, 0xe93fa7cfe53fa7c7LL, |
| 2918 | 0xe13fa7bfdd3fa7b7LL, 0xd93fa7afd53fa7a7LL, |
| 2919 | 0xd13fa79fcd3fa797LL, 0xc93fa78fc53fa787LL, |
| 2920 | 0xc13fa77fcc3fa777LL, 0xc83fa76fc43fa767LL, |
| 2921 | 0xc03fa75ffc3fa757LL, 0xf83fa74ff43fa747LL, |
| 2922 | 0xf03fa73f01000000LL, 0x0100000001000000LL, |
| 2923 | 0x0100000091580000LL, 0xd027a72b93500000LL, |
| 2924 | 0xd027a72791480000LL, 0xd027a72391400000LL, |
| 2925 | 0xd027a71fda5ba8a7LL, 0xd85ba89fd65ba897LL, |
| 2926 | 0xd45ba88fd25ba887LL, 0x9fc02000d05ba87fLL, |
| 2927 | 0x0100000091d02001LL, 0x0100000001000000LL |
| 2928 | }; |
| 2929 | static LONGEST call_dummy_nil[] = {0}; |
| 2930 | |
| 2931 | /* First see if there is already a gdbarch that can satisfy the request. */ |
| 2932 | arches = gdbarch_list_lookup_by_info (arches, &info); |
| 2933 | if (arches != NULL) |
| 2934 | return arches->gdbarch; |
| 2935 | |
| 2936 | /* None found: is the request for a sparc architecture? */ |
| 2937 | if (info.bfd_architecture != bfd_arch_sparc) |
| 2938 | return NULL; /* No; then it's not for us. */ |
| 2939 | |
| 2940 | /* Yes: create a new gdbarch for the specified machine type. */ |
| 2941 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
| 2942 | gdbarch = gdbarch_alloc (&info, tdep); |
| 2943 | |
| 2944 | /* First set settings that are common for all sparc architectures. */ |
| 2945 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
| 2946 | set_gdbarch_breakpoint_from_pc (gdbarch, memory_breakpoint_from_pc); |
| 2947 | set_gdbarch_coerce_float_to_double (gdbarch, |
| 2948 | sparc_coerce_float_to_double); |
| 2949 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); |
| 2950 | set_gdbarch_call_dummy_p (gdbarch, 1); |
| 2951 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 1); |
| 2952 | set_gdbarch_decr_pc_after_break (gdbarch, 0); |
| 2953 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 2954 | set_gdbarch_extract_struct_value_address (gdbarch, |
| 2955 | sparc_extract_struct_value_address); |
| 2956 | set_gdbarch_fix_call_dummy (gdbarch, sparc_gdbarch_fix_call_dummy); |
| 2957 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 2958 | set_gdbarch_fp_regnum (gdbarch, SPARC_FP_REGNUM); |
| 2959 | set_gdbarch_fp0_regnum (gdbarch, SPARC_FP0_REGNUM); |
| 2960 | set_gdbarch_frame_args_address (gdbarch, sparc_frame_address); |
| 2961 | set_gdbarch_frame_chain (gdbarch, sparc_frame_chain); |
| 2962 | set_gdbarch_frame_init_saved_regs (gdbarch, sparc_frame_init_saved_regs); |
| 2963 | set_gdbarch_frame_locals_address (gdbarch, sparc_frame_address); |
| 2964 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); |
| 2965 | set_gdbarch_frame_saved_pc (gdbarch, sparc_frame_saved_pc); |
| 2966 | set_gdbarch_frameless_function_invocation (gdbarch, |
| 2967 | frameless_look_for_prologue); |
| 2968 | set_gdbarch_get_saved_register (gdbarch, sparc_get_saved_register); |
| 2969 | set_gdbarch_ieee_float (gdbarch, 1); |
| 2970 | set_gdbarch_init_extra_frame_info (gdbarch, sparc_init_extra_frame_info); |
| 2971 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 2972 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 2973 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); |
| 2974 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 2975 | set_gdbarch_max_register_raw_size (gdbarch, 8); |
| 2976 | set_gdbarch_max_register_virtual_size (gdbarch, 8); |
| 2977 | set_gdbarch_pop_frame (gdbarch, sparc_pop_frame); |
| 2978 | set_gdbarch_push_return_address (gdbarch, sparc_push_return_address); |
| 2979 | set_gdbarch_push_dummy_frame (gdbarch, sparc_push_dummy_frame); |
| 2980 | set_gdbarch_read_pc (gdbarch, generic_target_read_pc); |
| 2981 | set_gdbarch_register_convert_to_raw (gdbarch, sparc_convert_to_raw); |
| 2982 | set_gdbarch_register_convert_to_virtual (gdbarch, |
| 2983 | sparc_convert_to_virtual); |
| 2984 | set_gdbarch_register_convertible (gdbarch, |
| 2985 | generic_register_convertible_not); |
| 2986 | set_gdbarch_reg_struct_has_addr (gdbarch, sparc_reg_struct_has_addr); |
| 2987 | set_gdbarch_return_value_on_stack (gdbarch, sparc_return_value_on_stack); |
| 2988 | set_gdbarch_saved_pc_after_call (gdbarch, sparc_saved_pc_after_call); |
| 2989 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
| 2990 | set_gdbarch_skip_prologue (gdbarch, sparc_gdbarch_skip_prologue); |
| 2991 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); |
| 2992 | set_gdbarch_use_generic_dummy_frames (gdbarch, 0); |
| 2993 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
| 2994 | |
| 2995 | /* |
| 2996 | * Settings that depend only on 32/64 bit word size |
| 2997 | */ |
| 2998 | |
| 2999 | switch (info.bfd_arch_info->mach) |
| 3000 | { |
| 3001 | case bfd_mach_sparc: |
| 3002 | case bfd_mach_sparc_sparclet: |
| 3003 | case bfd_mach_sparc_sparclite: |
| 3004 | case bfd_mach_sparc_v8plus: |
| 3005 | case bfd_mach_sparc_v8plusa: |
| 3006 | case bfd_mach_sparc_sparclite_le: |
| 3007 | /* 32-bit machine types: */ |
| 3008 | |
| 3009 | #ifdef SPARC32_CALL_DUMMY_ON_STACK |
| 3010 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_on_stack); |
| 3011 | set_gdbarch_call_dummy_address (gdbarch, sparc_call_dummy_address); |
| 3012 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0x30); |
| 3013 | set_gdbarch_call_dummy_length (gdbarch, 0x38); |
| 3014 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
| 3015 | set_gdbarch_call_dummy_words (gdbarch, call_dummy_32); |
| 3016 | #else |
| 3017 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point); |
| 3018 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); |
| 3019 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); |
| 3020 | set_gdbarch_call_dummy_length (gdbarch, 0); |
| 3021 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); |
| 3022 | set_gdbarch_call_dummy_words (gdbarch, call_dummy_nil); |
| 3023 | #endif |
| 3024 | set_gdbarch_call_dummy_stack_adjust (gdbarch, 68); |
| 3025 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); |
| 3026 | set_gdbarch_frame_args_skip (gdbarch, 68); |
| 3027 | set_gdbarch_function_start_offset (gdbarch, 0); |
| 3028 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 3029 | set_gdbarch_npc_regnum (gdbarch, SPARC32_NPC_REGNUM); |
| 3030 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); |
| 3031 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 3032 | set_gdbarch_push_arguments (gdbarch, sparc32_push_arguments); |
| 3033 | set_gdbarch_read_fp (gdbarch, generic_target_read_fp); |
| 3034 | set_gdbarch_read_sp (gdbarch, generic_target_read_sp); |
| 3035 | |
| 3036 | set_gdbarch_register_byte (gdbarch, sparc32_register_byte); |
| 3037 | set_gdbarch_register_raw_size (gdbarch, sparc32_register_size); |
| 3038 | set_gdbarch_register_size (gdbarch, 4); |
| 3039 | set_gdbarch_register_virtual_size (gdbarch, sparc32_register_size); |
| 3040 | set_gdbarch_register_virtual_type (gdbarch, |
| 3041 | sparc32_register_virtual_type); |
| 3042 | #ifdef SPARC32_CALL_DUMMY_ON_STACK |
| 3043 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (call_dummy_32)); |
| 3044 | #else |
| 3045 | set_gdbarch_sizeof_call_dummy_words (gdbarch, 0); |
| 3046 | #endif |
| 3047 | set_gdbarch_stack_align (gdbarch, sparc32_stack_align); |
| 3048 | set_gdbarch_store_struct_return (gdbarch, sparc32_store_struct_return); |
| 3049 | set_gdbarch_use_struct_convention (gdbarch, |
| 3050 | generic_use_struct_convention); |
| 3051 | set_gdbarch_write_fp (gdbarch, generic_target_write_fp); |
| 3052 | set_gdbarch_write_sp (gdbarch, generic_target_write_sp); |
| 3053 | tdep->y_regnum = SPARC32_Y_REGNUM; |
| 3054 | tdep->fp_max_regnum = SPARC_FP0_REGNUM + 32; |
| 3055 | tdep->intreg_size = 4; |
| 3056 | tdep->reg_save_offset = 0x60; |
| 3057 | tdep->call_dummy_call_offset = 0x24; |
| 3058 | break; |
| 3059 | |
| 3060 | case bfd_mach_sparc_v9: |
| 3061 | case bfd_mach_sparc_v9a: |
| 3062 | /* 64-bit machine types: */ |
| 3063 | default: /* Any new machine type is likely to be 64-bit. */ |
| 3064 | |
| 3065 | #ifdef SPARC64_CALL_DUMMY_ON_STACK |
| 3066 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_on_stack); |
| 3067 | set_gdbarch_call_dummy_address (gdbarch, sparc_call_dummy_address); |
| 3068 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 8 * 4); |
| 3069 | set_gdbarch_call_dummy_length (gdbarch, 192); |
| 3070 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
| 3071 | set_gdbarch_call_dummy_start_offset (gdbarch, 148); |
| 3072 | set_gdbarch_call_dummy_words (gdbarch, call_dummy_64); |
| 3073 | #else |
| 3074 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point); |
| 3075 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); |
| 3076 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); |
| 3077 | set_gdbarch_call_dummy_length (gdbarch, 0); |
| 3078 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); |
| 3079 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); |
| 3080 | set_gdbarch_call_dummy_words (gdbarch, call_dummy_nil); |
| 3081 | #endif |
| 3082 | set_gdbarch_call_dummy_stack_adjust (gdbarch, 128); |
| 3083 | set_gdbarch_frame_args_skip (gdbarch, 136); |
| 3084 | set_gdbarch_function_start_offset (gdbarch, 0); |
| 3085 | set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 3086 | set_gdbarch_npc_regnum (gdbarch, SPARC64_NPC_REGNUM); |
| 3087 | set_gdbarch_pc_regnum (gdbarch, SPARC64_PC_REGNUM); |
| 3088 | set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 3089 | set_gdbarch_push_arguments (gdbarch, sparc64_push_arguments); |
| 3090 | /* NOTE different for at_entry */ |
| 3091 | set_gdbarch_read_fp (gdbarch, sparc64_read_fp); |
| 3092 | set_gdbarch_read_sp (gdbarch, sparc64_read_sp); |
| 3093 | /* Some of the registers aren't 64 bits, but it's a lot simpler just |
| 3094 | to assume they all are (since most of them are). */ |
| 3095 | set_gdbarch_register_byte (gdbarch, sparc64_register_byte); |
| 3096 | set_gdbarch_register_raw_size (gdbarch, sparc64_register_size); |
| 3097 | set_gdbarch_register_size (gdbarch, 8); |
| 3098 | set_gdbarch_register_virtual_size (gdbarch, sparc64_register_size); |
| 3099 | set_gdbarch_register_virtual_type (gdbarch, |
| 3100 | sparc64_register_virtual_type); |
| 3101 | #ifdef SPARC64_CALL_DUMMY_ON_STACK |
| 3102 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (call_dummy_64)); |
| 3103 | #else |
| 3104 | set_gdbarch_sizeof_call_dummy_words (gdbarch, 0); |
| 3105 | #endif |
| 3106 | set_gdbarch_stack_align (gdbarch, sparc64_stack_align); |
| 3107 | set_gdbarch_store_struct_return (gdbarch, sparc64_store_struct_return); |
| 3108 | set_gdbarch_use_struct_convention (gdbarch, |
| 3109 | sparc64_use_struct_convention); |
| 3110 | set_gdbarch_write_fp (gdbarch, sparc64_write_fp); |
| 3111 | set_gdbarch_write_sp (gdbarch, sparc64_write_sp); |
| 3112 | tdep->y_regnum = SPARC64_Y_REGNUM; |
| 3113 | tdep->fp_max_regnum = SPARC_FP0_REGNUM + 48; |
| 3114 | tdep->intreg_size = 8; |
| 3115 | tdep->reg_save_offset = 0x90; |
| 3116 | tdep->call_dummy_call_offset = 148 + 4 * 5; |
| 3117 | break; |
| 3118 | } |
| 3119 | |
| 3120 | /* |
| 3121 | * Settings that vary per-architecture: |
| 3122 | */ |
| 3123 | |
| 3124 | switch (info.bfd_arch_info->mach) |
| 3125 | { |
| 3126 | case bfd_mach_sparc: |
| 3127 | set_gdbarch_extract_return_value (gdbarch, sparc32_extract_return_value); |
| 3128 | set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid); |
| 3129 | set_gdbarch_num_regs (gdbarch, 72); |
| 3130 | set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4); |
| 3131 | set_gdbarch_register_name (gdbarch, sparc32_register_name); |
| 3132 | set_gdbarch_store_return_value (gdbarch, sparc_store_return_value); |
| 3133 | tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ |
| 3134 | tdep->fp_register_bytes = 32 * 4; |
| 3135 | tdep->print_insn_mach = bfd_mach_sparc; |
| 3136 | break; |
| 3137 | case bfd_mach_sparc_sparclet: |
| 3138 | set_gdbarch_extract_return_value (gdbarch, |
| 3139 | sparclet_extract_return_value); |
| 3140 | set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid); |
| 3141 | set_gdbarch_num_regs (gdbarch, 32 + 32 + 8 + 8 + 8); |
| 3142 | set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4 + 8*4); |
| 3143 | set_gdbarch_register_name (gdbarch, sparclet_register_name); |
| 3144 | set_gdbarch_store_return_value (gdbarch, sparclet_store_return_value); |
| 3145 | tdep->has_fpu = 0; /* (all but sparclet and sparclite) */ |
| 3146 | tdep->fp_register_bytes = 0; |
| 3147 | tdep->print_insn_mach = bfd_mach_sparc_sparclet; |
| 3148 | break; |
| 3149 | case bfd_mach_sparc_sparclite: |
| 3150 | set_gdbarch_extract_return_value (gdbarch, sparc32_extract_return_value); |
| 3151 | set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid); |
| 3152 | set_gdbarch_num_regs (gdbarch, 80); |
| 3153 | set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4); |
| 3154 | set_gdbarch_register_name (gdbarch, sparclite_register_name); |
| 3155 | set_gdbarch_store_return_value (gdbarch, sparc_store_return_value); |
| 3156 | tdep->has_fpu = 0; /* (all but sparclet and sparclite) */ |
| 3157 | tdep->fp_register_bytes = 0; |
| 3158 | tdep->print_insn_mach = bfd_mach_sparc_sparclite; |
| 3159 | break; |
| 3160 | case bfd_mach_sparc_v8plus: |
| 3161 | set_gdbarch_extract_return_value (gdbarch, sparc32_extract_return_value); |
| 3162 | set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid); |
| 3163 | set_gdbarch_num_regs (gdbarch, 72); |
| 3164 | set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4); |
| 3165 | set_gdbarch_register_name (gdbarch, sparc32_register_name); |
| 3166 | set_gdbarch_store_return_value (gdbarch, sparc_store_return_value); |
| 3167 | tdep->print_insn_mach = bfd_mach_sparc; |
| 3168 | tdep->fp_register_bytes = 32 * 4; |
| 3169 | tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ |
| 3170 | break; |
| 3171 | case bfd_mach_sparc_v8plusa: |
| 3172 | set_gdbarch_extract_return_value (gdbarch, sparc32_extract_return_value); |
| 3173 | set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid); |
| 3174 | set_gdbarch_num_regs (gdbarch, 72); |
| 3175 | set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4); |
| 3176 | set_gdbarch_register_name (gdbarch, sparc32_register_name); |
| 3177 | set_gdbarch_store_return_value (gdbarch, sparc_store_return_value); |
| 3178 | tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ |
| 3179 | tdep->fp_register_bytes = 32 * 4; |
| 3180 | tdep->print_insn_mach = bfd_mach_sparc; |
| 3181 | break; |
| 3182 | case bfd_mach_sparc_sparclite_le: |
| 3183 | set_gdbarch_extract_return_value (gdbarch, sparc32_extract_return_value); |
| 3184 | set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid); |
| 3185 | set_gdbarch_num_regs (gdbarch, 80); |
| 3186 | set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4); |
| 3187 | set_gdbarch_register_name (gdbarch, sparclite_register_name); |
| 3188 | set_gdbarch_store_return_value (gdbarch, sparc_store_return_value); |
| 3189 | tdep->has_fpu = 0; /* (all but sparclet and sparclite) */ |
| 3190 | tdep->fp_register_bytes = 0; |
| 3191 | tdep->print_insn_mach = bfd_mach_sparc_sparclite; |
| 3192 | break; |
| 3193 | case bfd_mach_sparc_v9: |
| 3194 | set_gdbarch_extract_return_value (gdbarch, sparc64_extract_return_value); |
| 3195 | set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid); |
| 3196 | set_gdbarch_num_regs (gdbarch, 125); |
| 3197 | set_gdbarch_register_bytes (gdbarch, 32*8 + 32*8 + 45*8); |
| 3198 | set_gdbarch_register_name (gdbarch, sparc64_register_name); |
| 3199 | set_gdbarch_store_return_value (gdbarch, sparc_store_return_value); |
| 3200 | tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ |
| 3201 | tdep->fp_register_bytes = 64 * 4; |
| 3202 | tdep->print_insn_mach = bfd_mach_sparc_v9a; |
| 3203 | break; |
| 3204 | case bfd_mach_sparc_v9a: |
| 3205 | set_gdbarch_extract_return_value (gdbarch, sparc64_extract_return_value); |
| 3206 | set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid); |
| 3207 | set_gdbarch_num_regs (gdbarch, 125); |
| 3208 | set_gdbarch_register_bytes (gdbarch, 32*8 + 32*8 + 45*8); |
| 3209 | set_gdbarch_register_name (gdbarch, sparc64_register_name); |
| 3210 | set_gdbarch_store_return_value (gdbarch, sparc_store_return_value); |
| 3211 | tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ |
| 3212 | tdep->fp_register_bytes = 64 * 4; |
| 3213 | tdep->print_insn_mach = bfd_mach_sparc_v9a; |
| 3214 | break; |
| 3215 | } |
| 3216 | |
| 3217 | return gdbarch; |
| 3218 | } |
| 3219 | |