| 1 | /* Target-dependent code for SPARC. |
| 2 | |
| 3 | Copyright 2003, 2004 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program; if not, write to the Free Software |
| 19 | Foundation, Inc., 59 Temple Place - Suite 330, |
| 20 | Boston, MA 02111-1307, USA. */ |
| 21 | |
| 22 | #include "defs.h" |
| 23 | #include "arch-utils.h" |
| 24 | #include "dis-asm.h" |
| 25 | #include "floatformat.h" |
| 26 | #include "frame.h" |
| 27 | #include "frame-base.h" |
| 28 | #include "frame-unwind.h" |
| 29 | #include "gdbcore.h" |
| 30 | #include "gdbtypes.h" |
| 31 | #include "inferior.h" |
| 32 | #include "symtab.h" |
| 33 | #include "objfiles.h" |
| 34 | #include "osabi.h" |
| 35 | #include "regcache.h" |
| 36 | #include "target.h" |
| 37 | #include "value.h" |
| 38 | |
| 39 | #include "gdb_assert.h" |
| 40 | #include "gdb_string.h" |
| 41 | |
| 42 | #include "sparc-tdep.h" |
| 43 | |
| 44 | struct regset; |
| 45 | |
| 46 | /* This file implements the The SPARC 32-bit ABI as defined by the |
| 47 | section "Low-Level System Information" of the SPARC Compliance |
| 48 | Definition (SCD) 2.4.1, which is the 32-bit System V psABI for |
| 49 | SPARC. The SCD lists changes with respect to the origional 32-bit |
| 50 | psABI as defined in the "System V ABI, SPARC Processor |
| 51 | Supplement". |
| 52 | |
| 53 | Note that if we talk about SunOS, we mean SunOS 4.x, which was |
| 54 | BSD-based, which is sometimes (retroactively?) referred to as |
| 55 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and |
| 56 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 |
| 57 | suffering from severe version number inflation). Solaris 2.x is |
| 58 | also known as SunOS 5.x, since that's what uname(1) says. Solaris |
| 59 | 2.x is SVR4-based. */ |
| 60 | |
| 61 | /* Please use the sparc32_-prefix for 32-bit specific code, the |
| 62 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for |
| 63 | code that can handle both. The 64-bit specific code lives in |
| 64 | sparc64-tdep.c; don't add any here. */ |
| 65 | |
| 66 | /* The SPARC Floating-Point Quad-Precision format is similar to |
| 67 | big-endian IA-64 Quad-recision format. */ |
| 68 | #define floatformat_sparc_quad floatformat_ia64_quad_big |
| 69 | |
| 70 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 |
| 71 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC |
| 72 | hosts, so undefine it first. */ |
| 73 | #undef BIAS |
| 74 | #define BIAS 2047 |
| 75 | |
| 76 | /* Macros to extract fields from SPARC instructions. */ |
| 77 | #define X_OP(i) (((i) >> 30) & 0x3) |
| 78 | #define X_RD(i) (((i) >> 25) & 0x1f) |
| 79 | #define X_A(i) (((i) >> 29) & 1) |
| 80 | #define X_COND(i) (((i) >> 25) & 0xf) |
| 81 | #define X_OP2(i) (((i) >> 22) & 0x7) |
| 82 | #define X_IMM22(i) ((i) & 0x3fffff) |
| 83 | #define X_OP3(i) (((i) >> 19) & 0x3f) |
| 84 | #define X_I(i) (((i) >> 13) & 1) |
| 85 | /* Sign extension macros. */ |
| 86 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
| 87 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
| 88 | |
| 89 | /* Fetch the instruction at PC. Instructions are always big-endian |
| 90 | even if the processor operates in little-endian mode. */ |
| 91 | |
| 92 | unsigned long |
| 93 | sparc_fetch_instruction (CORE_ADDR pc) |
| 94 | { |
| 95 | unsigned char buf[4]; |
| 96 | unsigned long insn; |
| 97 | int i; |
| 98 | |
| 99 | read_memory (pc, buf, sizeof (buf)); |
| 100 | |
| 101 | insn = 0; |
| 102 | for (i = 0; i < sizeof (buf); i++) |
| 103 | insn = (insn << 8) | buf[i]; |
| 104 | return insn; |
| 105 | } |
| 106 | \f |
| 107 | /* Return the contents if register REGNUM as an address. */ |
| 108 | |
| 109 | static CORE_ADDR |
| 110 | sparc_address_from_register (int regnum) |
| 111 | { |
| 112 | ULONGEST addr; |
| 113 | |
| 114 | regcache_cooked_read_unsigned (current_regcache, regnum, &addr); |
| 115 | return addr; |
| 116 | } |
| 117 | \f |
| 118 | |
| 119 | /* The functions on this page are intended to be used to classify |
| 120 | function arguments. */ |
| 121 | |
| 122 | /* Check whether TYPE is "Integral or Pointer". */ |
| 123 | |
| 124 | static int |
| 125 | sparc_integral_or_pointer_p (const struct type *type) |
| 126 | { |
| 127 | switch (TYPE_CODE (type)) |
| 128 | { |
| 129 | case TYPE_CODE_INT: |
| 130 | case TYPE_CODE_BOOL: |
| 131 | case TYPE_CODE_CHAR: |
| 132 | case TYPE_CODE_ENUM: |
| 133 | case TYPE_CODE_RANGE: |
| 134 | { |
| 135 | /* We have byte, half-word, word and extended-word/doubleword |
| 136 | integral types. The doubleword is an extension to the |
| 137 | origional 32-bit ABI by the SCD 2.4.x. */ |
| 138 | int len = TYPE_LENGTH (type); |
| 139 | return (len == 1 || len == 2 || len == 4 || len == 8); |
| 140 | } |
| 141 | return 1; |
| 142 | case TYPE_CODE_PTR: |
| 143 | case TYPE_CODE_REF: |
| 144 | { |
| 145 | /* Allow either 32-bit or 64-bit pointers. */ |
| 146 | int len = TYPE_LENGTH (type); |
| 147 | return (len == 4 || len == 8); |
| 148 | } |
| 149 | return 1; |
| 150 | default: |
| 151 | break; |
| 152 | } |
| 153 | |
| 154 | return 0; |
| 155 | } |
| 156 | |
| 157 | /* Check whether TYPE is "Floating". */ |
| 158 | |
| 159 | static int |
| 160 | sparc_floating_p (const struct type *type) |
| 161 | { |
| 162 | switch (TYPE_CODE (type)) |
| 163 | { |
| 164 | case TYPE_CODE_FLT: |
| 165 | { |
| 166 | int len = TYPE_LENGTH (type); |
| 167 | return (len == 4 || len == 8 || len == 16); |
| 168 | } |
| 169 | default: |
| 170 | break; |
| 171 | } |
| 172 | |
| 173 | return 0; |
| 174 | } |
| 175 | |
| 176 | /* Check whether TYPE is "Structure or Union". */ |
| 177 | |
| 178 | static int |
| 179 | sparc_structure_or_union_p (const struct type *type) |
| 180 | { |
| 181 | switch (TYPE_CODE (type)) |
| 182 | { |
| 183 | case TYPE_CODE_STRUCT: |
| 184 | case TYPE_CODE_UNION: |
| 185 | return 1; |
| 186 | default: |
| 187 | break; |
| 188 | } |
| 189 | |
| 190 | return 0; |
| 191 | } |
| 192 | |
| 193 | /* Register information. */ |
| 194 | |
| 195 | static const char *sparc32_register_names[] = |
| 196 | { |
| 197 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
| 198 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", |
| 199 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", |
| 200 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", |
| 201 | |
| 202 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 203 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 204 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 205 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 206 | |
| 207 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" |
| 208 | }; |
| 209 | |
| 210 | /* Total number of registers. */ |
| 211 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) |
| 212 | |
| 213 | /* We provide the aliases %d0..%d30 for the floating registers as |
| 214 | "psuedo" registers. */ |
| 215 | |
| 216 | static const char *sparc32_pseudo_register_names[] = |
| 217 | { |
| 218 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", |
| 219 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" |
| 220 | }; |
| 221 | |
| 222 | /* Total number of pseudo registers. */ |
| 223 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) |
| 224 | |
| 225 | /* Return the name of register REGNUM. */ |
| 226 | |
| 227 | static const char * |
| 228 | sparc32_register_name (int regnum) |
| 229 | { |
| 230 | if (regnum >= 0 && regnum < SPARC32_NUM_REGS) |
| 231 | return sparc32_register_names[regnum]; |
| 232 | |
| 233 | if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS) |
| 234 | return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS]; |
| 235 | |
| 236 | return NULL; |
| 237 | } |
| 238 | |
| 239 | /* Return the GDB type object for the "standard" data type of data in |
| 240 | register REGNUM. */ |
| 241 | |
| 242 | static struct type * |
| 243 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) |
| 244 | { |
| 245 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) |
| 246 | return builtin_type_float; |
| 247 | |
| 248 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) |
| 249 | return builtin_type_double; |
| 250 | |
| 251 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) |
| 252 | return builtin_type_void_data_ptr; |
| 253 | |
| 254 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
| 255 | return builtin_type_void_func_ptr; |
| 256 | |
| 257 | return builtin_type_int32; |
| 258 | } |
| 259 | |
| 260 | static void |
| 261 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, |
| 262 | struct regcache *regcache, |
| 263 | int regnum, void *buf) |
| 264 | { |
| 265 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
| 266 | |
| 267 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); |
| 268 | regcache_raw_read (regcache, regnum, buf); |
| 269 | regcache_raw_read (regcache, regnum + 1, ((char *)buf) + 4); |
| 270 | } |
| 271 | |
| 272 | static void |
| 273 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, |
| 274 | struct regcache *regcache, |
| 275 | int regnum, const void *buf) |
| 276 | { |
| 277 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
| 278 | |
| 279 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); |
| 280 | regcache_raw_write (regcache, regnum, buf); |
| 281 | regcache_raw_write (regcache, regnum + 1, ((const char *)buf) + 4); |
| 282 | } |
| 283 | \f |
| 284 | |
| 285 | static CORE_ADDR |
| 286 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, |
| 287 | CORE_ADDR funcaddr, int using_gcc, |
| 288 | struct value **args, int nargs, |
| 289 | struct type *value_type, |
| 290 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr) |
| 291 | { |
| 292 | *bp_addr = sp - 4; |
| 293 | *real_pc = funcaddr; |
| 294 | |
| 295 | if (using_struct_return (value_type, using_gcc)) |
| 296 | { |
| 297 | char buf[4]; |
| 298 | |
| 299 | /* This is an UNIMP instruction. */ |
| 300 | store_unsigned_integer (buf, 4, TYPE_LENGTH (value_type) & 0x1fff); |
| 301 | write_memory (sp - 8, buf, 4); |
| 302 | return sp - 8; |
| 303 | } |
| 304 | |
| 305 | return sp - 4; |
| 306 | } |
| 307 | |
| 308 | static CORE_ADDR |
| 309 | sparc32_store_arguments (struct regcache *regcache, int nargs, |
| 310 | struct value **args, CORE_ADDR sp, |
| 311 | int struct_return, CORE_ADDR struct_addr) |
| 312 | { |
| 313 | /* Number of words in the "parameter array". */ |
| 314 | int num_elements = 0; |
| 315 | int element = 0; |
| 316 | int i; |
| 317 | |
| 318 | for (i = 0; i < nargs; i++) |
| 319 | { |
| 320 | struct type *type = VALUE_TYPE (args[i]); |
| 321 | int len = TYPE_LENGTH (type); |
| 322 | |
| 323 | if (sparc_structure_or_union_p (type) |
| 324 | || (sparc_floating_p (type) && len == 16)) |
| 325 | { |
| 326 | /* Structure, Union and Quad-Precision Arguments. */ |
| 327 | sp -= len; |
| 328 | |
| 329 | /* Use doubleword alignment for these values. That's always |
| 330 | correct, and wasting a few bytes shouldn't be a problem. */ |
| 331 | sp &= ~0x7; |
| 332 | |
| 333 | write_memory (sp, VALUE_CONTENTS (args[i]), len); |
| 334 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
| 335 | num_elements++; |
| 336 | } |
| 337 | else if (sparc_floating_p (type)) |
| 338 | { |
| 339 | /* Floating arguments. */ |
| 340 | gdb_assert (len == 4 || len == 8); |
| 341 | num_elements += (len / 4); |
| 342 | } |
| 343 | else |
| 344 | { |
| 345 | /* Integral and pointer arguments. */ |
| 346 | gdb_assert (sparc_integral_or_pointer_p (type)); |
| 347 | |
| 348 | if (len < 4) |
| 349 | args[i] = value_cast (builtin_type_int32, args[i]); |
| 350 | num_elements += ((len + 3) / 4); |
| 351 | } |
| 352 | } |
| 353 | |
| 354 | /* Always allocate at least six words. */ |
| 355 | sp -= max (6, num_elements) * 4; |
| 356 | |
| 357 | /* The psABI says that "Software convention requires space for the |
| 358 | struct/union return value pointer, even if the word is unused." */ |
| 359 | sp -= 4; |
| 360 | |
| 361 | /* The psABI says that "Although software convention and the |
| 362 | operating system require every stack frame to be doubleword |
| 363 | aligned." */ |
| 364 | sp &= ~0x7; |
| 365 | |
| 366 | for (i = 0; i < nargs; i++) |
| 367 | { |
| 368 | char *valbuf = VALUE_CONTENTS (args[i]); |
| 369 | struct type *type = VALUE_TYPE (args[i]); |
| 370 | int len = TYPE_LENGTH (type); |
| 371 | |
| 372 | gdb_assert (len == 4 || len == 8); |
| 373 | |
| 374 | if (element < 6) |
| 375 | { |
| 376 | int regnum = SPARC_O0_REGNUM + element; |
| 377 | |
| 378 | regcache_cooked_write (regcache, regnum, valbuf); |
| 379 | if (len > 4 && element < 5) |
| 380 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); |
| 381 | } |
| 382 | |
| 383 | /* Always store the argument in memory. */ |
| 384 | write_memory (sp + 4 + element * 4, valbuf, len); |
| 385 | element += len / 4; |
| 386 | } |
| 387 | |
| 388 | gdb_assert (element == num_elements); |
| 389 | |
| 390 | if (struct_return) |
| 391 | { |
| 392 | char buf[4]; |
| 393 | |
| 394 | store_unsigned_integer (buf, 4, struct_addr); |
| 395 | write_memory (sp, buf, 4); |
| 396 | } |
| 397 | |
| 398 | return sp; |
| 399 | } |
| 400 | |
| 401 | static CORE_ADDR |
| 402 | sparc32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
| 403 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 404 | int nargs, struct value **args, CORE_ADDR sp, |
| 405 | int struct_return, CORE_ADDR struct_addr) |
| 406 | { |
| 407 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
| 408 | |
| 409 | /* Set return address. */ |
| 410 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); |
| 411 | |
| 412 | /* Set up function arguments. */ |
| 413 | sp = sparc32_store_arguments (regcache, nargs, args, sp, |
| 414 | struct_return, struct_addr); |
| 415 | |
| 416 | /* Allocate the 16-word window save area. */ |
| 417 | sp -= 16 * 4; |
| 418 | |
| 419 | /* Stack should be doubleword aligned at this point. */ |
| 420 | gdb_assert (sp % 8 == 0); |
| 421 | |
| 422 | /* Finally, update the stack pointer. */ |
| 423 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); |
| 424 | |
| 425 | return sp; |
| 426 | } |
| 427 | \f |
| 428 | |
| 429 | /* Use the program counter to determine the contents and size of a |
| 430 | breakpoint instruction. Return a pointer to a string of bytes that |
| 431 | encode a breakpoint instruction, store the length of the string in |
| 432 | *LEN and optionally adjust *PC to point to the correct memory |
| 433 | location for inserting the breakpoint. */ |
| 434 | |
| 435 | static const unsigned char * |
| 436 | sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len) |
| 437 | { |
| 438 | static unsigned char break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
| 439 | |
| 440 | *len = sizeof (break_insn); |
| 441 | return break_insn; |
| 442 | } |
| 443 | \f |
| 444 | |
| 445 | /* Allocate and initialize a frame cache. */ |
| 446 | |
| 447 | static struct sparc_frame_cache * |
| 448 | sparc_alloc_frame_cache (void) |
| 449 | { |
| 450 | struct sparc_frame_cache *cache; |
| 451 | int i; |
| 452 | |
| 453 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
| 454 | |
| 455 | /* Base address. */ |
| 456 | cache->base = 0; |
| 457 | cache->pc = 0; |
| 458 | |
| 459 | /* Frameless until proven otherwise. */ |
| 460 | cache->frameless_p = 1; |
| 461 | |
| 462 | cache->struct_return_p = 0; |
| 463 | |
| 464 | return cache; |
| 465 | } |
| 466 | |
| 467 | CORE_ADDR |
| 468 | sparc_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, |
| 469 | struct sparc_frame_cache *cache) |
| 470 | { |
| 471 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 472 | unsigned long insn; |
| 473 | int offset = 0; |
| 474 | int dest = -1; |
| 475 | |
| 476 | if (current_pc <= pc) |
| 477 | return current_pc; |
| 478 | |
| 479 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On |
| 480 | SPARC the linker usually defines a symbol (typically |
| 481 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. |
| 482 | This symbol makes us end up here with PC pointing at the start of |
| 483 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we |
| 484 | would do our normal prologue analysis, we would probably conclude |
| 485 | that we've got a frame when in reality we don't, since the |
| 486 | dynamic linker patches up the first PLT with some code that |
| 487 | starts with a SAVE instruction. Patch up PC such that it points |
| 488 | at the start of our PLT entry. */ |
| 489 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL)) |
| 490 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); |
| 491 | |
| 492 | insn = sparc_fetch_instruction (pc); |
| 493 | |
| 494 | /* Recognize a SETHI insn and record its destination. */ |
| 495 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) |
| 496 | { |
| 497 | dest = X_RD (insn); |
| 498 | offset += 4; |
| 499 | |
| 500 | insn = sparc_fetch_instruction (pc + 4); |
| 501 | } |
| 502 | |
| 503 | /* Allow for an arithmetic operation on DEST or %g1. */ |
| 504 | if (X_OP (insn) == 2 && X_I (insn) |
| 505 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
| 506 | { |
| 507 | offset += 4; |
| 508 | |
| 509 | insn = sparc_fetch_instruction (pc + 8); |
| 510 | } |
| 511 | |
| 512 | /* Check for the SAVE instruction that sets up the frame. */ |
| 513 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) |
| 514 | { |
| 515 | cache->frameless_p = 0; |
| 516 | return pc + offset + 4; |
| 517 | } |
| 518 | |
| 519 | return pc; |
| 520 | } |
| 521 | |
| 522 | static CORE_ADDR |
| 523 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 524 | { |
| 525 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 526 | return frame_unwind_register_unsigned (next_frame, tdep->pc_regnum); |
| 527 | } |
| 528 | |
| 529 | /* Return PC of first real instruction of the function starting at |
| 530 | START_PC. */ |
| 531 | |
| 532 | static CORE_ADDR |
| 533 | sparc32_skip_prologue (CORE_ADDR start_pc) |
| 534 | { |
| 535 | struct symtab_and_line sal; |
| 536 | CORE_ADDR func_start, func_end; |
| 537 | struct sparc_frame_cache cache; |
| 538 | |
| 539 | /* This is the preferred method, find the end of the prologue by |
| 540 | using the debugging information. */ |
| 541 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) |
| 542 | { |
| 543 | sal = find_pc_line (func_start, 0); |
| 544 | |
| 545 | if (sal.end < func_end |
| 546 | && start_pc <= sal.end) |
| 547 | return sal.end; |
| 548 | } |
| 549 | |
| 550 | return sparc_analyze_prologue (start_pc, 0xffffffffUL, &cache); |
| 551 | } |
| 552 | |
| 553 | /* Normal frames. */ |
| 554 | |
| 555 | struct sparc_frame_cache * |
| 556 | sparc_frame_cache (struct frame_info *next_frame, void **this_cache) |
| 557 | { |
| 558 | struct sparc_frame_cache *cache; |
| 559 | |
| 560 | if (*this_cache) |
| 561 | return *this_cache; |
| 562 | |
| 563 | cache = sparc_alloc_frame_cache (); |
| 564 | *this_cache = cache; |
| 565 | |
| 566 | /* In priciple, for normal frames, %fp (%i6) holds the frame |
| 567 | pointer, which holds the base address for the current stack |
| 568 | frame. */ |
| 569 | |
| 570 | cache->base = frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM); |
| 571 | if (cache->base == 0) |
| 572 | return cache; |
| 573 | |
| 574 | cache->pc = frame_func_unwind (next_frame); |
| 575 | if (cache->pc != 0) |
| 576 | { |
| 577 | CORE_ADDR addr_in_block = frame_unwind_address_in_block (next_frame); |
| 578 | sparc_analyze_prologue (cache->pc, addr_in_block, cache); |
| 579 | } |
| 580 | |
| 581 | if (cache->frameless_p) |
| 582 | { |
| 583 | /* We didn't find a valid frame, which means that CACHE->base |
| 584 | currently holds the frame pointer for our calling frame. */ |
| 585 | cache->base = frame_unwind_register_unsigned (next_frame, |
| 586 | SPARC_SP_REGNUM); |
| 587 | } |
| 588 | |
| 589 | return cache; |
| 590 | } |
| 591 | |
| 592 | struct sparc_frame_cache * |
| 593 | sparc32_frame_cache (struct frame_info *next_frame, void **this_cache) |
| 594 | { |
| 595 | struct sparc_frame_cache *cache; |
| 596 | struct symbol *sym; |
| 597 | |
| 598 | if (*this_cache) |
| 599 | return *this_cache; |
| 600 | |
| 601 | cache = sparc_frame_cache (next_frame, this_cache); |
| 602 | |
| 603 | sym = find_pc_function (cache->pc); |
| 604 | if (sym) |
| 605 | { |
| 606 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); |
| 607 | enum type_code code = TYPE_CODE (type); |
| 608 | |
| 609 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) |
| 610 | { |
| 611 | type = check_typedef (TYPE_TARGET_TYPE (type)); |
| 612 | if (sparc_structure_or_union_p (type) |
| 613 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) |
| 614 | cache->struct_return_p = 1; |
| 615 | } |
| 616 | } |
| 617 | |
| 618 | return cache; |
| 619 | } |
| 620 | |
| 621 | static void |
| 622 | sparc32_frame_this_id (struct frame_info *next_frame, void **this_cache, |
| 623 | struct frame_id *this_id) |
| 624 | { |
| 625 | struct sparc_frame_cache *cache = |
| 626 | sparc32_frame_cache (next_frame, this_cache); |
| 627 | |
| 628 | /* This marks the outermost frame. */ |
| 629 | if (cache->base == 0) |
| 630 | return; |
| 631 | |
| 632 | (*this_id) = frame_id_build (cache->base, cache->pc); |
| 633 | } |
| 634 | |
| 635 | static void |
| 636 | sparc32_frame_prev_register (struct frame_info *next_frame, void **this_cache, |
| 637 | int regnum, int *optimizedp, |
| 638 | enum lval_type *lvalp, CORE_ADDR *addrp, |
| 639 | int *realnump, void *valuep) |
| 640 | { |
| 641 | struct sparc_frame_cache *cache = |
| 642 | sparc32_frame_cache (next_frame, this_cache); |
| 643 | |
| 644 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
| 645 | { |
| 646 | *optimizedp = 0; |
| 647 | *lvalp = not_lval; |
| 648 | *addrp = 0; |
| 649 | *realnump = -1; |
| 650 | if (valuep) |
| 651 | { |
| 652 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
| 653 | |
| 654 | /* If this functions has a Structure, Union or |
| 655 | Quad-Precision return value, we have to skip the UNIMP |
| 656 | instruction that encodes the size of the structure. */ |
| 657 | if (cache->struct_return_p) |
| 658 | pc += 4; |
| 659 | |
| 660 | regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM; |
| 661 | pc += frame_unwind_register_unsigned (next_frame, regnum) + 8; |
| 662 | store_unsigned_integer (valuep, 4, pc); |
| 663 | } |
| 664 | return; |
| 665 | } |
| 666 | |
| 667 | /* The previous frame's `local' and `in' registers have been saved |
| 668 | in the register save area. */ |
| 669 | if (!cache->frameless_p |
| 670 | && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) |
| 671 | { |
| 672 | *optimizedp = 0; |
| 673 | *lvalp = lval_memory; |
| 674 | *addrp = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
| 675 | *realnump = -1; |
| 676 | if (valuep) |
| 677 | { |
| 678 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
| 679 | |
| 680 | /* Read the value in from memory. */ |
| 681 | read_memory (*addrp, valuep, register_size (gdbarch, regnum)); |
| 682 | } |
| 683 | return; |
| 684 | } |
| 685 | |
| 686 | /* The previous frame's `out' registers are accessable as the |
| 687 | current frame's `in' registers. */ |
| 688 | if (!cache->frameless_p |
| 689 | && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM) |
| 690 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); |
| 691 | |
| 692 | frame_register_unwind (next_frame, regnum, |
| 693 | optimizedp, lvalp, addrp, realnump, valuep); |
| 694 | } |
| 695 | |
| 696 | static const struct frame_unwind sparc32_frame_unwind = |
| 697 | { |
| 698 | NORMAL_FRAME, |
| 699 | sparc32_frame_this_id, |
| 700 | sparc32_frame_prev_register |
| 701 | }; |
| 702 | |
| 703 | static const struct frame_unwind * |
| 704 | sparc32_frame_sniffer (struct frame_info *next_frame) |
| 705 | { |
| 706 | return &sparc32_frame_unwind; |
| 707 | } |
| 708 | \f |
| 709 | |
| 710 | static CORE_ADDR |
| 711 | sparc32_frame_base_address (struct frame_info *next_frame, void **this_cache) |
| 712 | { |
| 713 | struct sparc_frame_cache *cache = |
| 714 | sparc32_frame_cache (next_frame, this_cache); |
| 715 | |
| 716 | return cache->base; |
| 717 | } |
| 718 | |
| 719 | static const struct frame_base sparc32_frame_base = |
| 720 | { |
| 721 | &sparc32_frame_unwind, |
| 722 | sparc32_frame_base_address, |
| 723 | sparc32_frame_base_address, |
| 724 | sparc32_frame_base_address |
| 725 | }; |
| 726 | |
| 727 | static struct frame_id |
| 728 | sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 729 | { |
| 730 | CORE_ADDR sp; |
| 731 | |
| 732 | sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM); |
| 733 | return frame_id_build (sp, frame_pc_unwind (next_frame)); |
| 734 | } |
| 735 | \f |
| 736 | |
| 737 | /* Extract from an array REGBUF containing the (raw) register state, a |
| 738 | function return value of TYPE, and copy that into VALBUF. */ |
| 739 | |
| 740 | static void |
| 741 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, |
| 742 | void *valbuf) |
| 743 | { |
| 744 | int len = TYPE_LENGTH (type); |
| 745 | char buf[8]; |
| 746 | |
| 747 | gdb_assert (!sparc_structure_or_union_p (type)); |
| 748 | gdb_assert (!(sparc_floating_p (type) && len == 16)); |
| 749 | |
| 750 | if (sparc_floating_p (type)) |
| 751 | { |
| 752 | /* Floating return values. */ |
| 753 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); |
| 754 | if (len > 4) |
| 755 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); |
| 756 | memcpy (valbuf, buf, len); |
| 757 | } |
| 758 | else |
| 759 | { |
| 760 | /* Integral and pointer return values. */ |
| 761 | gdb_assert (sparc_integral_or_pointer_p (type)); |
| 762 | |
| 763 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
| 764 | if (len > 4) |
| 765 | { |
| 766 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); |
| 767 | gdb_assert (len == 8); |
| 768 | memcpy (valbuf, buf, 8); |
| 769 | } |
| 770 | else |
| 771 | { |
| 772 | /* Just stripping off any unused bytes should preserve the |
| 773 | signed-ness just fine. */ |
| 774 | memcpy (valbuf, buf + 4 - len, len); |
| 775 | } |
| 776 | } |
| 777 | } |
| 778 | |
| 779 | /* Write into the appropriate registers a function return value stored |
| 780 | in VALBUF of type TYPE. */ |
| 781 | |
| 782 | static void |
| 783 | sparc32_store_return_value (struct type *type, struct regcache *regcache, |
| 784 | const void *valbuf) |
| 785 | { |
| 786 | int len = TYPE_LENGTH (type); |
| 787 | char buf[8]; |
| 788 | |
| 789 | gdb_assert (!sparc_structure_or_union_p (type)); |
| 790 | gdb_assert (!(sparc_floating_p (type) && len == 16)); |
| 791 | |
| 792 | if (sparc_floating_p (type)) |
| 793 | { |
| 794 | /* Floating return values. */ |
| 795 | memcpy (buf, valbuf, len); |
| 796 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); |
| 797 | if (len > 4) |
| 798 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); |
| 799 | } |
| 800 | else |
| 801 | { |
| 802 | /* Integral and pointer return values. */ |
| 803 | gdb_assert (sparc_integral_or_pointer_p (type)); |
| 804 | |
| 805 | if (len > 4) |
| 806 | { |
| 807 | gdb_assert (len == 8); |
| 808 | memcpy (buf, valbuf, 8); |
| 809 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); |
| 810 | } |
| 811 | else |
| 812 | { |
| 813 | /* ??? Do we need to do any sign-extension here? */ |
| 814 | memcpy (buf + 4 - len, valbuf, len); |
| 815 | } |
| 816 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
| 817 | } |
| 818 | } |
| 819 | |
| 820 | static enum return_value_convention |
| 821 | sparc32_return_value (struct gdbarch *gdbarch, struct type *type, |
| 822 | struct regcache *regcache, void *readbuf, |
| 823 | const void *writebuf) |
| 824 | { |
| 825 | if (sparc_structure_or_union_p (type) |
| 826 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) |
| 827 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 828 | |
| 829 | if (readbuf) |
| 830 | sparc32_extract_return_value (type, regcache, readbuf); |
| 831 | if (writebuf) |
| 832 | sparc32_store_return_value (type, regcache, writebuf); |
| 833 | |
| 834 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 835 | } |
| 836 | |
| 837 | #if 0 |
| 838 | /* NOTE: cagney/2004-01-17: For the moment disable this method. The |
| 839 | architecture and CORE-gdb will need new code (and a replacement for |
| 840 | EXTRACT_STRUCT_VALUE_ADDRESS) before this can be made to work |
| 841 | robustly. Here is a possible function signature: */ |
| 842 | /* NOTE: cagney/2004-01-17: So far only the 32-bit SPARC ABI has been |
| 843 | identifed as having a way to robustly recover the address of a |
| 844 | struct-convention return-value (after the function has returned). |
| 845 | For all other ABIs so far examined, the calling convention makes no |
| 846 | guarenteed that the register containing the return-value will be |
| 847 | preserved and hence that the return-value's address can be |
| 848 | recovered. */ |
| 849 | /* Extract from REGCACHE, which contains the (raw) register state, the |
| 850 | address in which a function should return its structure value, as a |
| 851 | CORE_ADDR. */ |
| 852 | |
| 853 | static CORE_ADDR |
| 854 | sparc32_extract_struct_value_address (struct regcache *regcache) |
| 855 | { |
| 856 | ULONGEST sp; |
| 857 | |
| 858 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); |
| 859 | return read_memory_unsigned_integer (sp + 64, 4); |
| 860 | } |
| 861 | #endif |
| 862 | |
| 863 | static int |
| 864 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) |
| 865 | { |
| 866 | return (sparc_structure_or_union_p (type) |
| 867 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)); |
| 868 | } |
| 869 | |
| 870 | \f |
| 871 | /* The SPARC Architecture doesn't have hardware single-step support, |
| 872 | and most operating systems don't implement it either, so we provide |
| 873 | software single-step mechanism. */ |
| 874 | |
| 875 | static CORE_ADDR |
| 876 | sparc_analyze_control_transfer (CORE_ADDR pc, CORE_ADDR *npc) |
| 877 | { |
| 878 | unsigned long insn = sparc_fetch_instruction (pc); |
| 879 | int conditional_p = X_COND (insn) & 0x7; |
| 880 | int branch_p = 0; |
| 881 | long offset = 0; /* Must be signed for sign-extend. */ |
| 882 | |
| 883 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0) |
| 884 | { |
| 885 | /* Branch on Integer Register with Prediction (BPr). */ |
| 886 | branch_p = 1; |
| 887 | conditional_p = 1; |
| 888 | } |
| 889 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
| 890 | { |
| 891 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
| 892 | branch_p = 1; |
| 893 | offset = 4 * X_DISP22 (insn); |
| 894 | } |
| 895 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
| 896 | { |
| 897 | /* Branch on Floating-Point Condition Codes with Prediction |
| 898 | (FBPfcc). */ |
| 899 | branch_p = 1; |
| 900 | offset = 4 * X_DISP19 (insn); |
| 901 | } |
| 902 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) |
| 903 | { |
| 904 | /* Branch on Integer Condition Codes (Bicc). */ |
| 905 | branch_p = 1; |
| 906 | offset = 4 * X_DISP22 (insn); |
| 907 | } |
| 908 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) |
| 909 | { |
| 910 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
| 911 | branch_p = 1; |
| 912 | offset = 4 * X_DISP19 (insn); |
| 913 | } |
| 914 | |
| 915 | /* FIXME: Handle DONE and RETRY instructions. */ |
| 916 | |
| 917 | /* FIXME: Handle the Trap instruction. */ |
| 918 | |
| 919 | if (branch_p) |
| 920 | { |
| 921 | if (conditional_p) |
| 922 | { |
| 923 | /* For conditional branches, return nPC + 4 iff the annul |
| 924 | bit is 1. */ |
| 925 | return (X_A (insn) ? *npc + 4 : 0); |
| 926 | } |
| 927 | else |
| 928 | { |
| 929 | /* For unconditional branches, return the target if its |
| 930 | specified condition is "always" and return nPC + 4 if the |
| 931 | condition is "never". If the annul bit is 1, set *NPC to |
| 932 | zero. */ |
| 933 | if (X_COND (insn) == 0x0) |
| 934 | pc = *npc, offset = 4; |
| 935 | if (X_A (insn)) |
| 936 | *npc = 0; |
| 937 | |
| 938 | gdb_assert (offset != 0); |
| 939 | return pc + offset; |
| 940 | } |
| 941 | } |
| 942 | |
| 943 | return 0; |
| 944 | } |
| 945 | |
| 946 | void |
| 947 | sparc_software_single_step (enum target_signal sig, int insert_breakpoints_p) |
| 948 | { |
| 949 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 950 | static CORE_ADDR npc, nnpc; |
| 951 | static char npc_save[4], nnpc_save[4]; |
| 952 | |
| 953 | if (insert_breakpoints_p) |
| 954 | { |
| 955 | CORE_ADDR pc; |
| 956 | |
| 957 | pc = sparc_address_from_register (tdep->pc_regnum); |
| 958 | npc = sparc_address_from_register (tdep->npc_regnum); |
| 959 | |
| 960 | /* Analyze the instruction at PC. */ |
| 961 | nnpc = sparc_analyze_control_transfer (pc, &npc); |
| 962 | if (npc != 0) |
| 963 | target_insert_breakpoint (npc, npc_save); |
| 964 | if (nnpc != 0) |
| 965 | target_insert_breakpoint (nnpc, nnpc_save); |
| 966 | |
| 967 | /* Assert that we have set at least one breakpoint, and that |
| 968 | they're not set at the same spot. */ |
| 969 | gdb_assert (npc != 0 || nnpc != 0); |
| 970 | gdb_assert (nnpc != npc); |
| 971 | } |
| 972 | else |
| 973 | { |
| 974 | if (npc != 0) |
| 975 | target_remove_breakpoint (npc, npc_save); |
| 976 | if (nnpc != 0) |
| 977 | target_remove_breakpoint (nnpc, nnpc_save); |
| 978 | } |
| 979 | } |
| 980 | |
| 981 | static void |
| 982 | sparc_write_pc (CORE_ADDR pc, ptid_t ptid) |
| 983 | { |
| 984 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 985 | |
| 986 | write_register_pid (tdep->pc_regnum, pc, ptid); |
| 987 | write_register_pid (tdep->npc_regnum, pc + 4, ptid); |
| 988 | } |
| 989 | \f |
| 990 | /* Unglobalize NAME. */ |
| 991 | |
| 992 | char * |
| 993 | sparc_stabs_unglobalize_name (char *name) |
| 994 | { |
| 995 | /* The Sun compilers (Sun ONE Studio, Forte Developer, Sun WorkShop, |
| 996 | SunPRO) convert file static variables into global values, a |
| 997 | process known as globalization. In order to do this, the |
| 998 | compiler will create a unique prefix and prepend it to each file |
| 999 | static variable. For static variables within a function, this |
| 1000 | globalization prefix is followed by the function name (nested |
| 1001 | static variables within a function are supposed to generate a |
| 1002 | warning message, and are left alone). The procedure is |
| 1003 | documented in the Stabs Interface Manual, which is distrubuted |
| 1004 | with the compilers, although version 4.0 of the manual seems to |
| 1005 | be incorrect in some places, at least for SPARC. The |
| 1006 | globalization prefix is encoded into an N_OPT stab, with the form |
| 1007 | "G=<prefix>". The globalization prefix always seems to start |
| 1008 | with a dollar sign '$'; a dot '.' is used as a seperator. So we |
| 1009 | simply strip everything up until the last dot. */ |
| 1010 | |
| 1011 | if (name[0] == '$') |
| 1012 | { |
| 1013 | char *p = strrchr (name, '.'); |
| 1014 | if (p) |
| 1015 | return p + 1; |
| 1016 | } |
| 1017 | |
| 1018 | return name; |
| 1019 | } |
| 1020 | \f |
| 1021 | |
| 1022 | /* Return the appropriate register set for the core section identified |
| 1023 | by SECT_NAME and SECT_SIZE. */ |
| 1024 | |
| 1025 | const struct regset * |
| 1026 | sparc_regset_from_core_section (struct gdbarch *gdbarch, |
| 1027 | const char *sect_name, size_t sect_size) |
| 1028 | { |
| 1029 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1030 | |
| 1031 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) |
| 1032 | return tdep->gregset; |
| 1033 | |
| 1034 | if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
| 1035 | return tdep->fpregset; |
| 1036 | |
| 1037 | return NULL; |
| 1038 | } |
| 1039 | \f |
| 1040 | |
| 1041 | static struct gdbarch * |
| 1042 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 1043 | { |
| 1044 | struct gdbarch_tdep *tdep; |
| 1045 | struct gdbarch *gdbarch; |
| 1046 | |
| 1047 | /* If there is already a candidate, use it. */ |
| 1048 | arches = gdbarch_list_lookup_by_info (arches, &info); |
| 1049 | if (arches != NULL) |
| 1050 | return arches->gdbarch; |
| 1051 | |
| 1052 | /* Allocate space for the new architecture. */ |
| 1053 | tdep = XMALLOC (struct gdbarch_tdep); |
| 1054 | gdbarch = gdbarch_alloc (&info, tdep); |
| 1055 | |
| 1056 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
| 1057 | tdep->npc_regnum = SPARC32_NPC_REGNUM; |
| 1058 | tdep->gregset = NULL; |
| 1059 | tdep->sizeof_gregset = 20 * 4; |
| 1060 | tdep->fpregset = NULL; |
| 1061 | tdep->sizeof_fpregset = 33 * 4; |
| 1062 | tdep->plt_entry_size = 0; |
| 1063 | |
| 1064 | set_gdbarch_long_double_bit (gdbarch, 128); |
| 1065 | set_gdbarch_long_double_format (gdbarch, &floatformat_sparc_quad); |
| 1066 | |
| 1067 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); |
| 1068 | set_gdbarch_register_name (gdbarch, sparc32_register_name); |
| 1069 | set_gdbarch_register_type (gdbarch, sparc32_register_type); |
| 1070 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); |
| 1071 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); |
| 1072 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); |
| 1073 | |
| 1074 | /* Register numbers of various important registers. */ |
| 1075 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ |
| 1076 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ |
| 1077 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ |
| 1078 | |
| 1079 | /* Call dummy code. */ |
| 1080 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
| 1081 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); |
| 1082 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); |
| 1083 | |
| 1084 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
| 1085 | set_gdbarch_stabs_argument_has_addr |
| 1086 | (gdbarch, sparc32_stabs_argument_has_addr); |
| 1087 | |
| 1088 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); |
| 1089 | |
| 1090 | /* Stack grows downward. */ |
| 1091 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 1092 | |
| 1093 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); |
| 1094 | |
| 1095 | set_gdbarch_frame_args_skip (gdbarch, 8); |
| 1096 | |
| 1097 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
| 1098 | |
| 1099 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
| 1100 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); |
| 1101 | |
| 1102 | set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id); |
| 1103 | |
| 1104 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
| 1105 | |
| 1106 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
| 1107 | |
| 1108 | /* Hook in ABI-specific overrides, if they have been registered. */ |
| 1109 | gdbarch_init_osabi (info, gdbarch); |
| 1110 | |
| 1111 | frame_unwind_append_sniffer (gdbarch, sparc32_frame_sniffer); |
| 1112 | |
| 1113 | /* If we have register sets, enable the generic core file support. */ |
| 1114 | if (tdep->gregset && tdep->fpregset) |
| 1115 | set_gdbarch_regset_from_core_section (gdbarch, |
| 1116 | sparc_regset_from_core_section); |
| 1117 | |
| 1118 | return gdbarch; |
| 1119 | } |
| 1120 | \f |
| 1121 | /* Helper functions for dealing with register windows. */ |
| 1122 | |
| 1123 | void |
| 1124 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) |
| 1125 | { |
| 1126 | int offset = 0; |
| 1127 | char buf[8]; |
| 1128 | int i; |
| 1129 | |
| 1130 | if (sp & 1) |
| 1131 | { |
| 1132 | /* Registers are 64-bit. */ |
| 1133 | sp += BIAS; |
| 1134 | |
| 1135 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
| 1136 | { |
| 1137 | if (regnum == i || regnum == -1) |
| 1138 | { |
| 1139 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
| 1140 | regcache_raw_supply (regcache, i, buf); |
| 1141 | } |
| 1142 | } |
| 1143 | } |
| 1144 | else |
| 1145 | { |
| 1146 | /* Registers are 32-bit. Toss any sign-extension of the stack |
| 1147 | pointer. */ |
| 1148 | sp &= 0xffffffffUL; |
| 1149 | |
| 1150 | /* Clear out the top half of the temporary buffer, and put the |
| 1151 | register value in the bottom half if we're in 64-bit mode. */ |
| 1152 | if (gdbarch_ptr_bit (current_gdbarch) == 64) |
| 1153 | { |
| 1154 | memset (buf, 0, 4); |
| 1155 | offset = 4; |
| 1156 | } |
| 1157 | |
| 1158 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
| 1159 | { |
| 1160 | if (regnum == i || regnum == -1) |
| 1161 | { |
| 1162 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
| 1163 | buf + offset, 4); |
| 1164 | regcache_raw_supply (regcache, i, buf); |
| 1165 | } |
| 1166 | } |
| 1167 | } |
| 1168 | } |
| 1169 | |
| 1170 | void |
| 1171 | sparc_collect_rwindow (const struct regcache *regcache, |
| 1172 | CORE_ADDR sp, int regnum) |
| 1173 | { |
| 1174 | int offset = 0; |
| 1175 | char buf[8]; |
| 1176 | int i; |
| 1177 | |
| 1178 | if (sp & 1) |
| 1179 | { |
| 1180 | /* Registers are 64-bit. */ |
| 1181 | sp += BIAS; |
| 1182 | |
| 1183 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
| 1184 | { |
| 1185 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) |
| 1186 | { |
| 1187 | regcache_raw_collect (regcache, i, buf); |
| 1188 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
| 1189 | } |
| 1190 | } |
| 1191 | } |
| 1192 | else |
| 1193 | { |
| 1194 | /* Registers are 32-bit. Toss any sign-extension of the stack |
| 1195 | pointer. */ |
| 1196 | sp &= 0xffffffffUL; |
| 1197 | |
| 1198 | /* Only use the bottom half if we're in 64-bit mode. */ |
| 1199 | if (gdbarch_ptr_bit (current_gdbarch) == 64) |
| 1200 | offset = 4; |
| 1201 | |
| 1202 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
| 1203 | { |
| 1204 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) |
| 1205 | { |
| 1206 | regcache_raw_collect (regcache, i, buf); |
| 1207 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
| 1208 | buf + offset, 4); |
| 1209 | } |
| 1210 | } |
| 1211 | } |
| 1212 | } |
| 1213 | |
| 1214 | /* Helper functions for dealing with register sets. */ |
| 1215 | |
| 1216 | void |
| 1217 | sparc32_supply_gregset (const struct sparc_gregset *gregset, |
| 1218 | struct regcache *regcache, |
| 1219 | int regnum, const void *gregs) |
| 1220 | { |
| 1221 | const char *regs = gregs; |
| 1222 | int i; |
| 1223 | |
| 1224 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
| 1225 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, |
| 1226 | regs + gregset->r_psr_offset); |
| 1227 | |
| 1228 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
| 1229 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, |
| 1230 | regs + gregset->r_pc_offset); |
| 1231 | |
| 1232 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
| 1233 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, |
| 1234 | regs + gregset->r_npc_offset); |
| 1235 | |
| 1236 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
| 1237 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, |
| 1238 | regs + gregset->r_y_offset); |
| 1239 | |
| 1240 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
| 1241 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL); |
| 1242 | |
| 1243 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
| 1244 | { |
| 1245 | int offset = gregset->r_g1_offset; |
| 1246 | |
| 1247 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) |
| 1248 | { |
| 1249 | if (regnum == i || regnum == -1) |
| 1250 | regcache_raw_supply (regcache, i, regs + offset); |
| 1251 | offset += 4; |
| 1252 | } |
| 1253 | } |
| 1254 | |
| 1255 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) |
| 1256 | { |
| 1257 | /* Not all of the register set variants include Locals and |
| 1258 | Inputs. For those that don't, we read them off the stack. */ |
| 1259 | if (gregset->r_l0_offset == -1) |
| 1260 | { |
| 1261 | ULONGEST sp; |
| 1262 | |
| 1263 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); |
| 1264 | sparc_supply_rwindow (regcache, sp, regnum); |
| 1265 | } |
| 1266 | else |
| 1267 | { |
| 1268 | int offset = gregset->r_l0_offset; |
| 1269 | |
| 1270 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
| 1271 | { |
| 1272 | if (regnum == i || regnum == -1) |
| 1273 | regcache_raw_supply (regcache, i, regs + offset); |
| 1274 | offset += 4; |
| 1275 | } |
| 1276 | } |
| 1277 | } |
| 1278 | } |
| 1279 | |
| 1280 | void |
| 1281 | sparc32_collect_gregset (const struct sparc_gregset *gregset, |
| 1282 | const struct regcache *regcache, |
| 1283 | int regnum, void *gregs) |
| 1284 | { |
| 1285 | char *regs = gregs; |
| 1286 | int i; |
| 1287 | |
| 1288 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
| 1289 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, |
| 1290 | regs + gregset->r_psr_offset); |
| 1291 | |
| 1292 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
| 1293 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, |
| 1294 | regs + gregset->r_pc_offset); |
| 1295 | |
| 1296 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
| 1297 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, |
| 1298 | regs + gregset->r_npc_offset); |
| 1299 | |
| 1300 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
| 1301 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, |
| 1302 | regs + gregset->r_y_offset); |
| 1303 | |
| 1304 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
| 1305 | { |
| 1306 | int offset = gregset->r_g1_offset; |
| 1307 | |
| 1308 | /* %g0 is always zero. */ |
| 1309 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) |
| 1310 | { |
| 1311 | if (regnum == i || regnum == -1) |
| 1312 | regcache_raw_collect (regcache, i, regs + offset); |
| 1313 | offset += 4; |
| 1314 | } |
| 1315 | } |
| 1316 | |
| 1317 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) |
| 1318 | { |
| 1319 | /* Not all of the register set variants include Locals and |
| 1320 | Inputs. For those that don't, we read them off the stack. */ |
| 1321 | if (gregset->r_l0_offset != -1) |
| 1322 | { |
| 1323 | int offset = gregset->r_l0_offset; |
| 1324 | |
| 1325 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
| 1326 | { |
| 1327 | if (regnum == i || regnum == -1) |
| 1328 | regcache_raw_collect (regcache, i, regs + offset); |
| 1329 | offset += 4; |
| 1330 | } |
| 1331 | } |
| 1332 | } |
| 1333 | } |
| 1334 | |
| 1335 | void |
| 1336 | sparc32_supply_fpregset (struct regcache *regcache, |
| 1337 | int regnum, const void *fpregs) |
| 1338 | { |
| 1339 | const char *regs = fpregs; |
| 1340 | int i; |
| 1341 | |
| 1342 | for (i = 0; i < 32; i++) |
| 1343 | { |
| 1344 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
| 1345 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); |
| 1346 | } |
| 1347 | |
| 1348 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
| 1349 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); |
| 1350 | } |
| 1351 | |
| 1352 | void |
| 1353 | sparc32_collect_fpregset (const struct regcache *regcache, |
| 1354 | int regnum, void *fpregs) |
| 1355 | { |
| 1356 | char *regs = fpregs; |
| 1357 | int i; |
| 1358 | |
| 1359 | for (i = 0; i < 32; i++) |
| 1360 | { |
| 1361 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
| 1362 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); |
| 1363 | } |
| 1364 | |
| 1365 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
| 1366 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); |
| 1367 | } |
| 1368 | \f |
| 1369 | |
| 1370 | /* SunOS 4. */ |
| 1371 | |
| 1372 | /* From <machine/reg.h>. */ |
| 1373 | const struct sparc_gregset sparc32_sunos4_gregset = |
| 1374 | { |
| 1375 | 0 * 4, /* %psr */ |
| 1376 | 1 * 4, /* %pc */ |
| 1377 | 2 * 4, /* %npc */ |
| 1378 | 3 * 4, /* %y */ |
| 1379 | -1, /* %wim */ |
| 1380 | -1, /* %tbr */ |
| 1381 | 4 * 4, /* %g1 */ |
| 1382 | -1 /* %l0 */ |
| 1383 | }; |
| 1384 | \f |
| 1385 | |
| 1386 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
| 1387 | void _initialize_sparc_tdep (void); |
| 1388 | |
| 1389 | void |
| 1390 | _initialize_sparc_tdep (void) |
| 1391 | { |
| 1392 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
| 1393 | } |