| 1 | /* SPU target-dependent code for GDB, the GNU debugger. |
| 2 | Copyright (C) 2006-2018 Free Software Foundation, Inc. |
| 3 | |
| 4 | Contributed by Ulrich Weigand <uweigand@de.ibm.com>. |
| 5 | Based on a port by Sid Manning <sid@us.ibm.com>. |
| 6 | |
| 7 | This file is part of GDB. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3 of the License, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 21 | |
| 22 | #include "defs.h" |
| 23 | #include "arch-utils.h" |
| 24 | #include "gdbtypes.h" |
| 25 | #include "gdbcmd.h" |
| 26 | #include "gdbcore.h" |
| 27 | #include "frame.h" |
| 28 | #include "frame-unwind.h" |
| 29 | #include "frame-base.h" |
| 30 | #include "trad-frame.h" |
| 31 | #include "symtab.h" |
| 32 | #include "symfile.h" |
| 33 | #include "value.h" |
| 34 | #include "inferior.h" |
| 35 | #include "dis-asm.h" |
| 36 | #include "disasm.h" |
| 37 | #include "objfiles.h" |
| 38 | #include "language.h" |
| 39 | #include "regcache.h" |
| 40 | #include "reggroups.h" |
| 41 | #include "block.h" |
| 42 | #include "observable.h" |
| 43 | #include "infcall.h" |
| 44 | #include "dwarf2.h" |
| 45 | #include "dwarf2-frame.h" |
| 46 | #include "ax.h" |
| 47 | #include "spu-tdep.h" |
| 48 | #include "location.h" |
| 49 | |
| 50 | /* The list of available "set spu " and "show spu " commands. */ |
| 51 | static struct cmd_list_element *setspucmdlist = NULL; |
| 52 | static struct cmd_list_element *showspucmdlist = NULL; |
| 53 | |
| 54 | /* Whether to stop for new SPE contexts. */ |
| 55 | static int spu_stop_on_load_p = 0; |
| 56 | /* Whether to automatically flush the SW-managed cache. */ |
| 57 | static int spu_auto_flush_cache_p = 1; |
| 58 | |
| 59 | |
| 60 | /* The tdep structure. */ |
| 61 | struct gdbarch_tdep |
| 62 | { |
| 63 | /* The spufs ID identifying our address space. */ |
| 64 | int id; |
| 65 | |
| 66 | /* SPU-specific vector type. */ |
| 67 | struct type *spu_builtin_type_vec128; |
| 68 | }; |
| 69 | |
| 70 | |
| 71 | /* SPU-specific vector type. */ |
| 72 | static struct type * |
| 73 | spu_builtin_type_vec128 (struct gdbarch *gdbarch) |
| 74 | { |
| 75 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 76 | |
| 77 | if (!tdep->spu_builtin_type_vec128) |
| 78 | { |
| 79 | const struct builtin_type *bt = builtin_type (gdbarch); |
| 80 | struct type *t; |
| 81 | |
| 82 | t = arch_composite_type (gdbarch, |
| 83 | "__spu_builtin_type_vec128", TYPE_CODE_UNION); |
| 84 | append_composite_type_field (t, "uint128", bt->builtin_int128); |
| 85 | append_composite_type_field (t, "v2_int64", |
| 86 | init_vector_type (bt->builtin_int64, 2)); |
| 87 | append_composite_type_field (t, "v4_int32", |
| 88 | init_vector_type (bt->builtin_int32, 4)); |
| 89 | append_composite_type_field (t, "v8_int16", |
| 90 | init_vector_type (bt->builtin_int16, 8)); |
| 91 | append_composite_type_field (t, "v16_int8", |
| 92 | init_vector_type (bt->builtin_int8, 16)); |
| 93 | append_composite_type_field (t, "v2_double", |
| 94 | init_vector_type (bt->builtin_double, 2)); |
| 95 | append_composite_type_field (t, "v4_float", |
| 96 | init_vector_type (bt->builtin_float, 4)); |
| 97 | |
| 98 | TYPE_VECTOR (t) = 1; |
| 99 | TYPE_NAME (t) = "spu_builtin_type_vec128"; |
| 100 | |
| 101 | tdep->spu_builtin_type_vec128 = t; |
| 102 | } |
| 103 | |
| 104 | return tdep->spu_builtin_type_vec128; |
| 105 | } |
| 106 | |
| 107 | |
| 108 | /* The list of available "info spu " commands. */ |
| 109 | static struct cmd_list_element *infospucmdlist = NULL; |
| 110 | |
| 111 | /* Registers. */ |
| 112 | |
| 113 | static const char * |
| 114 | spu_register_name (struct gdbarch *gdbarch, int reg_nr) |
| 115 | { |
| 116 | static const char *register_names[] = |
| 117 | { |
| 118 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 119 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 120 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
| 121 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
| 122 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", |
| 123 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", |
| 124 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", |
| 125 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", |
| 126 | "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71", |
| 127 | "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79", |
| 128 | "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", |
| 129 | "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95", |
| 130 | "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103", |
| 131 | "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111", |
| 132 | "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119", |
| 133 | "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127", |
| 134 | "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status" |
| 135 | }; |
| 136 | |
| 137 | if (reg_nr < 0) |
| 138 | return NULL; |
| 139 | if (reg_nr >= sizeof register_names / sizeof *register_names) |
| 140 | return NULL; |
| 141 | |
| 142 | return register_names[reg_nr]; |
| 143 | } |
| 144 | |
| 145 | static struct type * |
| 146 | spu_register_type (struct gdbarch *gdbarch, int reg_nr) |
| 147 | { |
| 148 | if (reg_nr < SPU_NUM_GPRS) |
| 149 | return spu_builtin_type_vec128 (gdbarch); |
| 150 | |
| 151 | switch (reg_nr) |
| 152 | { |
| 153 | case SPU_ID_REGNUM: |
| 154 | return builtin_type (gdbarch)->builtin_uint32; |
| 155 | |
| 156 | case SPU_PC_REGNUM: |
| 157 | return builtin_type (gdbarch)->builtin_func_ptr; |
| 158 | |
| 159 | case SPU_SP_REGNUM: |
| 160 | return builtin_type (gdbarch)->builtin_data_ptr; |
| 161 | |
| 162 | case SPU_FPSCR_REGNUM: |
| 163 | return builtin_type (gdbarch)->builtin_uint128; |
| 164 | |
| 165 | case SPU_SRR0_REGNUM: |
| 166 | return builtin_type (gdbarch)->builtin_uint32; |
| 167 | |
| 168 | case SPU_LSLR_REGNUM: |
| 169 | return builtin_type (gdbarch)->builtin_uint32; |
| 170 | |
| 171 | case SPU_DECR_REGNUM: |
| 172 | return builtin_type (gdbarch)->builtin_uint32; |
| 173 | |
| 174 | case SPU_DECR_STATUS_REGNUM: |
| 175 | return builtin_type (gdbarch)->builtin_uint32; |
| 176 | |
| 177 | default: |
| 178 | internal_error (__FILE__, __LINE__, _("invalid regnum")); |
| 179 | } |
| 180 | } |
| 181 | |
| 182 | /* Pseudo registers for preferred slots - stack pointer. */ |
| 183 | |
| 184 | static enum register_status |
| 185 | spu_pseudo_register_read_spu (readable_regcache *regcache, const char *regname, |
| 186 | gdb_byte *buf) |
| 187 | { |
| 188 | struct gdbarch *gdbarch = regcache->arch (); |
| 189 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 190 | enum register_status status; |
| 191 | gdb_byte reg[32]; |
| 192 | char annex[32]; |
| 193 | ULONGEST id; |
| 194 | ULONGEST ul; |
| 195 | |
| 196 | status = regcache->raw_read (SPU_ID_REGNUM, &id); |
| 197 | if (status != REG_VALID) |
| 198 | return status; |
| 199 | xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname); |
| 200 | memset (reg, 0, sizeof reg); |
| 201 | target_read (current_top_target (), TARGET_OBJECT_SPU, annex, |
| 202 | reg, 0, sizeof reg); |
| 203 | |
| 204 | ul = strtoulst ((char *) reg, NULL, 16); |
| 205 | store_unsigned_integer (buf, 4, byte_order, ul); |
| 206 | return REG_VALID; |
| 207 | } |
| 208 | |
| 209 | static enum register_status |
| 210 | spu_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
| 211 | int regnum, gdb_byte *buf) |
| 212 | { |
| 213 | gdb_byte reg[16]; |
| 214 | char annex[32]; |
| 215 | ULONGEST id; |
| 216 | enum register_status status; |
| 217 | |
| 218 | switch (regnum) |
| 219 | { |
| 220 | case SPU_SP_REGNUM: |
| 221 | status = regcache->raw_read (SPU_RAW_SP_REGNUM, reg); |
| 222 | if (status != REG_VALID) |
| 223 | return status; |
| 224 | memcpy (buf, reg, 4); |
| 225 | return status; |
| 226 | |
| 227 | case SPU_FPSCR_REGNUM: |
| 228 | status = regcache->raw_read (SPU_ID_REGNUM, &id); |
| 229 | if (status != REG_VALID) |
| 230 | return status; |
| 231 | xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id); |
| 232 | target_read (current_top_target (), TARGET_OBJECT_SPU, annex, buf, 0, 16); |
| 233 | return status; |
| 234 | |
| 235 | case SPU_SRR0_REGNUM: |
| 236 | return spu_pseudo_register_read_spu (regcache, "srr0", buf); |
| 237 | |
| 238 | case SPU_LSLR_REGNUM: |
| 239 | return spu_pseudo_register_read_spu (regcache, "lslr", buf); |
| 240 | |
| 241 | case SPU_DECR_REGNUM: |
| 242 | return spu_pseudo_register_read_spu (regcache, "decr", buf); |
| 243 | |
| 244 | case SPU_DECR_STATUS_REGNUM: |
| 245 | return spu_pseudo_register_read_spu (regcache, "decr_status", buf); |
| 246 | |
| 247 | default: |
| 248 | internal_error (__FILE__, __LINE__, _("invalid regnum")); |
| 249 | } |
| 250 | } |
| 251 | |
| 252 | static void |
| 253 | spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname, |
| 254 | const gdb_byte *buf) |
| 255 | { |
| 256 | struct gdbarch *gdbarch = regcache->arch (); |
| 257 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 258 | char reg[32]; |
| 259 | char annex[32]; |
| 260 | ULONGEST id; |
| 261 | |
| 262 | regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id); |
| 263 | xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname); |
| 264 | xsnprintf (reg, sizeof reg, "0x%s", |
| 265 | phex_nz (extract_unsigned_integer (buf, 4, byte_order), 4)); |
| 266 | target_write (current_top_target (), TARGET_OBJECT_SPU, annex, |
| 267 | (gdb_byte *) reg, 0, strlen (reg)); |
| 268 | } |
| 269 | |
| 270 | static void |
| 271 | spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
| 272 | int regnum, const gdb_byte *buf) |
| 273 | { |
| 274 | gdb_byte reg[16]; |
| 275 | char annex[32]; |
| 276 | ULONGEST id; |
| 277 | |
| 278 | switch (regnum) |
| 279 | { |
| 280 | case SPU_SP_REGNUM: |
| 281 | regcache->raw_read (SPU_RAW_SP_REGNUM, reg); |
| 282 | memcpy (reg, buf, 4); |
| 283 | regcache->raw_write (SPU_RAW_SP_REGNUM, reg); |
| 284 | break; |
| 285 | |
| 286 | case SPU_FPSCR_REGNUM: |
| 287 | regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id); |
| 288 | xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id); |
| 289 | target_write (current_top_target (), TARGET_OBJECT_SPU, annex, buf, 0, 16); |
| 290 | break; |
| 291 | |
| 292 | case SPU_SRR0_REGNUM: |
| 293 | spu_pseudo_register_write_spu (regcache, "srr0", buf); |
| 294 | break; |
| 295 | |
| 296 | case SPU_LSLR_REGNUM: |
| 297 | spu_pseudo_register_write_spu (regcache, "lslr", buf); |
| 298 | break; |
| 299 | |
| 300 | case SPU_DECR_REGNUM: |
| 301 | spu_pseudo_register_write_spu (regcache, "decr", buf); |
| 302 | break; |
| 303 | |
| 304 | case SPU_DECR_STATUS_REGNUM: |
| 305 | spu_pseudo_register_write_spu (regcache, "decr_status", buf); |
| 306 | break; |
| 307 | |
| 308 | default: |
| 309 | internal_error (__FILE__, __LINE__, _("invalid regnum")); |
| 310 | } |
| 311 | } |
| 312 | |
| 313 | static int |
| 314 | spu_ax_pseudo_register_collect (struct gdbarch *gdbarch, |
| 315 | struct agent_expr *ax, int regnum) |
| 316 | { |
| 317 | switch (regnum) |
| 318 | { |
| 319 | case SPU_SP_REGNUM: |
| 320 | ax_reg_mask (ax, SPU_RAW_SP_REGNUM); |
| 321 | return 0; |
| 322 | |
| 323 | case SPU_FPSCR_REGNUM: |
| 324 | case SPU_SRR0_REGNUM: |
| 325 | case SPU_LSLR_REGNUM: |
| 326 | case SPU_DECR_REGNUM: |
| 327 | case SPU_DECR_STATUS_REGNUM: |
| 328 | return -1; |
| 329 | |
| 330 | default: |
| 331 | internal_error (__FILE__, __LINE__, _("invalid regnum")); |
| 332 | } |
| 333 | } |
| 334 | |
| 335 | static int |
| 336 | spu_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, |
| 337 | struct agent_expr *ax, int regnum) |
| 338 | { |
| 339 | switch (regnum) |
| 340 | { |
| 341 | case SPU_SP_REGNUM: |
| 342 | ax_reg (ax, SPU_RAW_SP_REGNUM); |
| 343 | return 0; |
| 344 | |
| 345 | case SPU_FPSCR_REGNUM: |
| 346 | case SPU_SRR0_REGNUM: |
| 347 | case SPU_LSLR_REGNUM: |
| 348 | case SPU_DECR_REGNUM: |
| 349 | case SPU_DECR_STATUS_REGNUM: |
| 350 | return -1; |
| 351 | |
| 352 | default: |
| 353 | internal_error (__FILE__, __LINE__, _("invalid regnum")); |
| 354 | } |
| 355 | } |
| 356 | |
| 357 | |
| 358 | /* Value conversion -- access scalar values at the preferred slot. */ |
| 359 | |
| 360 | static struct value * |
| 361 | spu_value_from_register (struct gdbarch *gdbarch, struct type *type, |
| 362 | int regnum, struct frame_id frame_id) |
| 363 | { |
| 364 | struct value *value = default_value_from_register (gdbarch, type, |
| 365 | regnum, frame_id); |
| 366 | LONGEST len = TYPE_LENGTH (type); |
| 367 | |
| 368 | if (regnum < SPU_NUM_GPRS && len < 16) |
| 369 | { |
| 370 | int preferred_slot = len < 4 ? 4 - len : 0; |
| 371 | set_value_offset (value, preferred_slot); |
| 372 | } |
| 373 | |
| 374 | return value; |
| 375 | } |
| 376 | |
| 377 | /* Register groups. */ |
| 378 | |
| 379 | static int |
| 380 | spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
| 381 | struct reggroup *group) |
| 382 | { |
| 383 | /* Registers displayed via 'info regs'. */ |
| 384 | if (group == general_reggroup) |
| 385 | return 1; |
| 386 | |
| 387 | /* Registers displayed via 'info float'. */ |
| 388 | if (group == float_reggroup) |
| 389 | return 0; |
| 390 | |
| 391 | /* Registers that need to be saved/restored in order to |
| 392 | push or pop frames. */ |
| 393 | if (group == save_reggroup || group == restore_reggroup) |
| 394 | return 1; |
| 395 | |
| 396 | return default_register_reggroup_p (gdbarch, regnum, group); |
| 397 | } |
| 398 | |
| 399 | /* DWARF-2 register numbers. */ |
| 400 | |
| 401 | static int |
| 402 | spu_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
| 403 | { |
| 404 | /* Use cooked instead of raw SP. */ |
| 405 | return (reg == SPU_RAW_SP_REGNUM)? SPU_SP_REGNUM : reg; |
| 406 | } |
| 407 | |
| 408 | |
| 409 | /* Address handling. */ |
| 410 | |
| 411 | static int |
| 412 | spu_gdbarch_id (struct gdbarch *gdbarch) |
| 413 | { |
| 414 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 415 | int id = tdep->id; |
| 416 | |
| 417 | /* The objfile architecture of a standalone SPU executable does not |
| 418 | provide an SPU ID. Retrieve it from the objfile's relocated |
| 419 | address range in this special case. */ |
| 420 | if (id == -1 |
| 421 | && symfile_objfile && symfile_objfile->obfd |
| 422 | && bfd_get_arch (symfile_objfile->obfd) == bfd_arch_spu |
| 423 | && symfile_objfile->sections != symfile_objfile->sections_end) |
| 424 | id = SPUADDR_SPU (obj_section_addr (symfile_objfile->sections)); |
| 425 | |
| 426 | return id; |
| 427 | } |
| 428 | |
| 429 | static int |
| 430 | spu_address_class_type_flags (int byte_size, int dwarf2_addr_class) |
| 431 | { |
| 432 | if (dwarf2_addr_class == 1) |
| 433 | return TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1; |
| 434 | else |
| 435 | return 0; |
| 436 | } |
| 437 | |
| 438 | static const char * |
| 439 | spu_address_class_type_flags_to_name (struct gdbarch *gdbarch, int type_flags) |
| 440 | { |
| 441 | if (type_flags & TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1) |
| 442 | return "__ea"; |
| 443 | else |
| 444 | return NULL; |
| 445 | } |
| 446 | |
| 447 | static int |
| 448 | spu_address_class_name_to_type_flags (struct gdbarch *gdbarch, |
| 449 | const char *name, int *type_flags_ptr) |
| 450 | { |
| 451 | if (strcmp (name, "__ea") == 0) |
| 452 | { |
| 453 | *type_flags_ptr = TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1; |
| 454 | return 1; |
| 455 | } |
| 456 | else |
| 457 | return 0; |
| 458 | } |
| 459 | |
| 460 | static void |
| 461 | spu_address_to_pointer (struct gdbarch *gdbarch, |
| 462 | struct type *type, gdb_byte *buf, CORE_ADDR addr) |
| 463 | { |
| 464 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 465 | store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, |
| 466 | SPUADDR_ADDR (addr)); |
| 467 | } |
| 468 | |
| 469 | static CORE_ADDR |
| 470 | spu_pointer_to_address (struct gdbarch *gdbarch, |
| 471 | struct type *type, const gdb_byte *buf) |
| 472 | { |
| 473 | int id = spu_gdbarch_id (gdbarch); |
| 474 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 475 | ULONGEST addr |
| 476 | = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order); |
| 477 | |
| 478 | /* Do not convert __ea pointers. */ |
| 479 | if (TYPE_ADDRESS_CLASS_1 (type)) |
| 480 | return addr; |
| 481 | |
| 482 | return addr? SPUADDR (id, addr) : 0; |
| 483 | } |
| 484 | |
| 485 | static CORE_ADDR |
| 486 | spu_integer_to_address (struct gdbarch *gdbarch, |
| 487 | struct type *type, const gdb_byte *buf) |
| 488 | { |
| 489 | int id = spu_gdbarch_id (gdbarch); |
| 490 | ULONGEST addr = unpack_long (type, buf); |
| 491 | |
| 492 | return SPUADDR (id, addr); |
| 493 | } |
| 494 | |
| 495 | |
| 496 | /* Decoding SPU instructions. */ |
| 497 | |
| 498 | enum |
| 499 | { |
| 500 | op_lqd = 0x34, |
| 501 | op_lqx = 0x3c4, |
| 502 | op_lqa = 0x61, |
| 503 | op_lqr = 0x67, |
| 504 | op_stqd = 0x24, |
| 505 | op_stqx = 0x144, |
| 506 | op_stqa = 0x41, |
| 507 | op_stqr = 0x47, |
| 508 | |
| 509 | op_il = 0x081, |
| 510 | op_ila = 0x21, |
| 511 | op_a = 0x0c0, |
| 512 | op_ai = 0x1c, |
| 513 | |
| 514 | op_selb = 0x8, |
| 515 | |
| 516 | op_br = 0x64, |
| 517 | op_bra = 0x60, |
| 518 | op_brsl = 0x66, |
| 519 | op_brasl = 0x62, |
| 520 | op_brnz = 0x42, |
| 521 | op_brz = 0x40, |
| 522 | op_brhnz = 0x46, |
| 523 | op_brhz = 0x44, |
| 524 | op_bi = 0x1a8, |
| 525 | op_bisl = 0x1a9, |
| 526 | op_biz = 0x128, |
| 527 | op_binz = 0x129, |
| 528 | op_bihz = 0x12a, |
| 529 | op_bihnz = 0x12b, |
| 530 | }; |
| 531 | |
| 532 | static int |
| 533 | is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb) |
| 534 | { |
| 535 | if ((insn >> 21) == op) |
| 536 | { |
| 537 | *rt = insn & 127; |
| 538 | *ra = (insn >> 7) & 127; |
| 539 | *rb = (insn >> 14) & 127; |
| 540 | return 1; |
| 541 | } |
| 542 | |
| 543 | return 0; |
| 544 | } |
| 545 | |
| 546 | static int |
| 547 | is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc) |
| 548 | { |
| 549 | if ((insn >> 28) == op) |
| 550 | { |
| 551 | *rt = (insn >> 21) & 127; |
| 552 | *ra = (insn >> 7) & 127; |
| 553 | *rb = (insn >> 14) & 127; |
| 554 | *rc = insn & 127; |
| 555 | return 1; |
| 556 | } |
| 557 | |
| 558 | return 0; |
| 559 | } |
| 560 | |
| 561 | static int |
| 562 | is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7) |
| 563 | { |
| 564 | if ((insn >> 21) == op) |
| 565 | { |
| 566 | *rt = insn & 127; |
| 567 | *ra = (insn >> 7) & 127; |
| 568 | *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40; |
| 569 | return 1; |
| 570 | } |
| 571 | |
| 572 | return 0; |
| 573 | } |
| 574 | |
| 575 | static int |
| 576 | is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10) |
| 577 | { |
| 578 | if ((insn >> 24) == op) |
| 579 | { |
| 580 | *rt = insn & 127; |
| 581 | *ra = (insn >> 7) & 127; |
| 582 | *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200; |
| 583 | return 1; |
| 584 | } |
| 585 | |
| 586 | return 0; |
| 587 | } |
| 588 | |
| 589 | static int |
| 590 | is_ri16 (unsigned int insn, int op, int *rt, int *i16) |
| 591 | { |
| 592 | if ((insn >> 23) == op) |
| 593 | { |
| 594 | *rt = insn & 127; |
| 595 | *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000; |
| 596 | return 1; |
| 597 | } |
| 598 | |
| 599 | return 0; |
| 600 | } |
| 601 | |
| 602 | static int |
| 603 | is_ri18 (unsigned int insn, int op, int *rt, int *i18) |
| 604 | { |
| 605 | if ((insn >> 25) == op) |
| 606 | { |
| 607 | *rt = insn & 127; |
| 608 | *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000; |
| 609 | return 1; |
| 610 | } |
| 611 | |
| 612 | return 0; |
| 613 | } |
| 614 | |
| 615 | static int |
| 616 | is_branch (unsigned int insn, int *offset, int *reg) |
| 617 | { |
| 618 | int rt, i7, i16; |
| 619 | |
| 620 | if (is_ri16 (insn, op_br, &rt, &i16) |
| 621 | || is_ri16 (insn, op_brsl, &rt, &i16) |
| 622 | || is_ri16 (insn, op_brnz, &rt, &i16) |
| 623 | || is_ri16 (insn, op_brz, &rt, &i16) |
| 624 | || is_ri16 (insn, op_brhnz, &rt, &i16) |
| 625 | || is_ri16 (insn, op_brhz, &rt, &i16)) |
| 626 | { |
| 627 | *reg = SPU_PC_REGNUM; |
| 628 | *offset = i16 << 2; |
| 629 | return 1; |
| 630 | } |
| 631 | |
| 632 | if (is_ri16 (insn, op_bra, &rt, &i16) |
| 633 | || is_ri16 (insn, op_brasl, &rt, &i16)) |
| 634 | { |
| 635 | *reg = -1; |
| 636 | *offset = i16 << 2; |
| 637 | return 1; |
| 638 | } |
| 639 | |
| 640 | if (is_ri7 (insn, op_bi, &rt, reg, &i7) |
| 641 | || is_ri7 (insn, op_bisl, &rt, reg, &i7) |
| 642 | || is_ri7 (insn, op_biz, &rt, reg, &i7) |
| 643 | || is_ri7 (insn, op_binz, &rt, reg, &i7) |
| 644 | || is_ri7 (insn, op_bihz, &rt, reg, &i7) |
| 645 | || is_ri7 (insn, op_bihnz, &rt, reg, &i7)) |
| 646 | { |
| 647 | *offset = 0; |
| 648 | return 1; |
| 649 | } |
| 650 | |
| 651 | return 0; |
| 652 | } |
| 653 | |
| 654 | |
| 655 | /* Prolog parsing. */ |
| 656 | |
| 657 | struct spu_prologue_data |
| 658 | { |
| 659 | /* Stack frame size. -1 if analysis was unsuccessful. */ |
| 660 | int size; |
| 661 | |
| 662 | /* How to find the CFA. The CFA is equal to SP at function entry. */ |
| 663 | int cfa_reg; |
| 664 | int cfa_offset; |
| 665 | |
| 666 | /* Offset relative to CFA where a register is saved. -1 if invalid. */ |
| 667 | int reg_offset[SPU_NUM_GPRS]; |
| 668 | }; |
| 669 | |
| 670 | static CORE_ADDR |
| 671 | spu_analyze_prologue (struct gdbarch *gdbarch, |
| 672 | CORE_ADDR start_pc, CORE_ADDR end_pc, |
| 673 | struct spu_prologue_data *data) |
| 674 | { |
| 675 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 676 | int found_sp = 0; |
| 677 | int found_fp = 0; |
| 678 | int found_lr = 0; |
| 679 | int found_bc = 0; |
| 680 | int reg_immed[SPU_NUM_GPRS]; |
| 681 | gdb_byte buf[16]; |
| 682 | CORE_ADDR prolog_pc = start_pc; |
| 683 | CORE_ADDR pc; |
| 684 | int i; |
| 685 | |
| 686 | |
| 687 | /* Initialize DATA to default values. */ |
| 688 | data->size = -1; |
| 689 | |
| 690 | data->cfa_reg = SPU_RAW_SP_REGNUM; |
| 691 | data->cfa_offset = 0; |
| 692 | |
| 693 | for (i = 0; i < SPU_NUM_GPRS; i++) |
| 694 | data->reg_offset[i] = -1; |
| 695 | |
| 696 | /* Set up REG_IMMED array. This is non-zero for a register if we know its |
| 697 | preferred slot currently holds this immediate value. */ |
| 698 | for (i = 0; i < SPU_NUM_GPRS; i++) |
| 699 | reg_immed[i] = 0; |
| 700 | |
| 701 | /* Scan instructions until the first branch. |
| 702 | |
| 703 | The following instructions are important prolog components: |
| 704 | |
| 705 | - The first instruction to set up the stack pointer. |
| 706 | - The first instruction to set up the frame pointer. |
| 707 | - The first instruction to save the link register. |
| 708 | - The first instruction to save the backchain. |
| 709 | |
| 710 | We return the instruction after the latest of these four, |
| 711 | or the incoming PC if none is found. The first instruction |
| 712 | to set up the stack pointer also defines the frame size. |
| 713 | |
| 714 | Note that instructions saving incoming arguments to their stack |
| 715 | slots are not counted as important, because they are hard to |
| 716 | identify with certainty. This should not matter much, because |
| 717 | arguments are relevant only in code compiled with debug data, |
| 718 | and in such code the GDB core will advance until the first source |
| 719 | line anyway, using SAL data. |
| 720 | |
| 721 | For purposes of stack unwinding, we analyze the following types |
| 722 | of instructions in addition: |
| 723 | |
| 724 | - Any instruction adding to the current frame pointer. |
| 725 | - Any instruction loading an immediate constant into a register. |
| 726 | - Any instruction storing a register onto the stack. |
| 727 | |
| 728 | These are used to compute the CFA and REG_OFFSET output. */ |
| 729 | |
| 730 | for (pc = start_pc; pc < end_pc; pc += 4) |
| 731 | { |
| 732 | unsigned int insn; |
| 733 | int rt, ra, rb, rc, immed; |
| 734 | |
| 735 | if (target_read_memory (pc, buf, 4)) |
| 736 | break; |
| 737 | insn = extract_unsigned_integer (buf, 4, byte_order); |
| 738 | |
| 739 | /* AI is the typical instruction to set up a stack frame. |
| 740 | It is also used to initialize the frame pointer. */ |
| 741 | if (is_ri10 (insn, op_ai, &rt, &ra, &immed)) |
| 742 | { |
| 743 | if (rt == data->cfa_reg && ra == data->cfa_reg) |
| 744 | data->cfa_offset -= immed; |
| 745 | |
| 746 | if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM |
| 747 | && !found_sp) |
| 748 | { |
| 749 | found_sp = 1; |
| 750 | prolog_pc = pc + 4; |
| 751 | |
| 752 | data->size = -immed; |
| 753 | } |
| 754 | else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM |
| 755 | && !found_fp) |
| 756 | { |
| 757 | found_fp = 1; |
| 758 | prolog_pc = pc + 4; |
| 759 | |
| 760 | data->cfa_reg = SPU_FP_REGNUM; |
| 761 | data->cfa_offset -= immed; |
| 762 | } |
| 763 | } |
| 764 | |
| 765 | /* A is used to set up stack frames of size >= 512 bytes. |
| 766 | If we have tracked the contents of the addend register, |
| 767 | we can handle this as well. */ |
| 768 | else if (is_rr (insn, op_a, &rt, &ra, &rb)) |
| 769 | { |
| 770 | if (rt == data->cfa_reg && ra == data->cfa_reg) |
| 771 | { |
| 772 | if (reg_immed[rb] != 0) |
| 773 | data->cfa_offset -= reg_immed[rb]; |
| 774 | else |
| 775 | data->cfa_reg = -1; /* We don't know the CFA any more. */ |
| 776 | } |
| 777 | |
| 778 | if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM |
| 779 | && !found_sp) |
| 780 | { |
| 781 | found_sp = 1; |
| 782 | prolog_pc = pc + 4; |
| 783 | |
| 784 | if (reg_immed[rb] != 0) |
| 785 | data->size = -reg_immed[rb]; |
| 786 | } |
| 787 | } |
| 788 | |
| 789 | /* We need to track IL and ILA used to load immediate constants |
| 790 | in case they are later used as input to an A instruction. */ |
| 791 | else if (is_ri16 (insn, op_il, &rt, &immed)) |
| 792 | { |
| 793 | reg_immed[rt] = immed; |
| 794 | |
| 795 | if (rt == SPU_RAW_SP_REGNUM && !found_sp) |
| 796 | found_sp = 1; |
| 797 | } |
| 798 | |
| 799 | else if (is_ri18 (insn, op_ila, &rt, &immed)) |
| 800 | { |
| 801 | reg_immed[rt] = immed & 0x3ffff; |
| 802 | |
| 803 | if (rt == SPU_RAW_SP_REGNUM && !found_sp) |
| 804 | found_sp = 1; |
| 805 | } |
| 806 | |
| 807 | /* STQD is used to save registers to the stack. */ |
| 808 | else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed)) |
| 809 | { |
| 810 | if (ra == data->cfa_reg) |
| 811 | data->reg_offset[rt] = data->cfa_offset - (immed << 4); |
| 812 | |
| 813 | if (ra == data->cfa_reg && rt == SPU_LR_REGNUM |
| 814 | && !found_lr) |
| 815 | { |
| 816 | found_lr = 1; |
| 817 | prolog_pc = pc + 4; |
| 818 | } |
| 819 | |
| 820 | if (ra == SPU_RAW_SP_REGNUM |
| 821 | && (found_sp? immed == 0 : rt == SPU_RAW_SP_REGNUM) |
| 822 | && !found_bc) |
| 823 | { |
| 824 | found_bc = 1; |
| 825 | prolog_pc = pc + 4; |
| 826 | } |
| 827 | } |
| 828 | |
| 829 | /* _start uses SELB to set up the stack pointer. */ |
| 830 | else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc)) |
| 831 | { |
| 832 | if (rt == SPU_RAW_SP_REGNUM && !found_sp) |
| 833 | found_sp = 1; |
| 834 | } |
| 835 | |
| 836 | /* We terminate if we find a branch. */ |
| 837 | else if (is_branch (insn, &immed, &ra)) |
| 838 | break; |
| 839 | } |
| 840 | |
| 841 | |
| 842 | /* If we successfully parsed until here, and didn't find any instruction |
| 843 | modifying SP, we assume we have a frameless function. */ |
| 844 | if (!found_sp) |
| 845 | data->size = 0; |
| 846 | |
| 847 | /* Return cooked instead of raw SP. */ |
| 848 | if (data->cfa_reg == SPU_RAW_SP_REGNUM) |
| 849 | data->cfa_reg = SPU_SP_REGNUM; |
| 850 | |
| 851 | return prolog_pc; |
| 852 | } |
| 853 | |
| 854 | /* Return the first instruction after the prologue starting at PC. */ |
| 855 | static CORE_ADDR |
| 856 | spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 857 | { |
| 858 | struct spu_prologue_data data; |
| 859 | return spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data); |
| 860 | } |
| 861 | |
| 862 | /* Return the frame pointer in use at address PC. */ |
| 863 | static void |
| 864 | spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc, |
| 865 | int *reg, LONGEST *offset) |
| 866 | { |
| 867 | struct spu_prologue_data data; |
| 868 | spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data); |
| 869 | |
| 870 | if (data.size != -1 && data.cfa_reg != -1) |
| 871 | { |
| 872 | /* The 'frame pointer' address is CFA minus frame size. */ |
| 873 | *reg = data.cfa_reg; |
| 874 | *offset = data.cfa_offset - data.size; |
| 875 | } |
| 876 | else |
| 877 | { |
| 878 | /* ??? We don't really know ... */ |
| 879 | *reg = SPU_SP_REGNUM; |
| 880 | *offset = 0; |
| 881 | } |
| 882 | } |
| 883 | |
| 884 | /* Implement the stack_frame_destroyed_p gdbarch method. |
| 885 | |
| 886 | 1) scan forward from the point of execution: |
| 887 | a) If you find an instruction that modifies the stack pointer |
| 888 | or transfers control (except a return), execution is not in |
| 889 | an epilogue, return. |
| 890 | b) Stop scanning if you find a return instruction or reach the |
| 891 | end of the function or reach the hard limit for the size of |
| 892 | an epilogue. |
| 893 | 2) scan backward from the point of execution: |
| 894 | a) If you find an instruction that modifies the stack pointer, |
| 895 | execution *is* in an epilogue, return. |
| 896 | b) Stop scanning if you reach an instruction that transfers |
| 897 | control or the beginning of the function or reach the hard |
| 898 | limit for the size of an epilogue. */ |
| 899 | |
| 900 | static int |
| 901 | spu_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 902 | { |
| 903 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 904 | CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end; |
| 905 | bfd_byte buf[4]; |
| 906 | unsigned int insn; |
| 907 | int rt, ra, rb, immed; |
| 908 | |
| 909 | /* Find the search limits based on function boundaries and hard limit. |
| 910 | We assume the epilogue can be up to 64 instructions long. */ |
| 911 | |
| 912 | const int spu_max_epilogue_size = 64 * 4; |
| 913 | |
| 914 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) |
| 915 | return 0; |
| 916 | |
| 917 | if (pc - func_start < spu_max_epilogue_size) |
| 918 | epilogue_start = func_start; |
| 919 | else |
| 920 | epilogue_start = pc - spu_max_epilogue_size; |
| 921 | |
| 922 | if (func_end - pc < spu_max_epilogue_size) |
| 923 | epilogue_end = func_end; |
| 924 | else |
| 925 | epilogue_end = pc + spu_max_epilogue_size; |
| 926 | |
| 927 | /* Scan forward until next 'bi $0'. */ |
| 928 | |
| 929 | for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4) |
| 930 | { |
| 931 | if (target_read_memory (scan_pc, buf, 4)) |
| 932 | return 0; |
| 933 | insn = extract_unsigned_integer (buf, 4, byte_order); |
| 934 | |
| 935 | if (is_branch (insn, &immed, &ra)) |
| 936 | { |
| 937 | if (immed == 0 && ra == SPU_LR_REGNUM) |
| 938 | break; |
| 939 | |
| 940 | return 0; |
| 941 | } |
| 942 | |
| 943 | if (is_ri10 (insn, op_ai, &rt, &ra, &immed) |
| 944 | || is_rr (insn, op_a, &rt, &ra, &rb) |
| 945 | || is_ri10 (insn, op_lqd, &rt, &ra, &immed)) |
| 946 | { |
| 947 | if (rt == SPU_RAW_SP_REGNUM) |
| 948 | return 0; |
| 949 | } |
| 950 | } |
| 951 | |
| 952 | if (scan_pc >= epilogue_end) |
| 953 | return 0; |
| 954 | |
| 955 | /* Scan backward until adjustment to stack pointer (R1). */ |
| 956 | |
| 957 | for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4) |
| 958 | { |
| 959 | if (target_read_memory (scan_pc, buf, 4)) |
| 960 | return 0; |
| 961 | insn = extract_unsigned_integer (buf, 4, byte_order); |
| 962 | |
| 963 | if (is_branch (insn, &immed, &ra)) |
| 964 | return 0; |
| 965 | |
| 966 | if (is_ri10 (insn, op_ai, &rt, &ra, &immed) |
| 967 | || is_rr (insn, op_a, &rt, &ra, &rb) |
| 968 | || is_ri10 (insn, op_lqd, &rt, &ra, &immed)) |
| 969 | { |
| 970 | if (rt == SPU_RAW_SP_REGNUM) |
| 971 | return 1; |
| 972 | } |
| 973 | } |
| 974 | |
| 975 | return 0; |
| 976 | } |
| 977 | |
| 978 | |
| 979 | /* Normal stack frames. */ |
| 980 | |
| 981 | struct spu_unwind_cache |
| 982 | { |
| 983 | CORE_ADDR func; |
| 984 | CORE_ADDR frame_base; |
| 985 | CORE_ADDR local_base; |
| 986 | |
| 987 | struct trad_frame_saved_reg *saved_regs; |
| 988 | }; |
| 989 | |
| 990 | static struct spu_unwind_cache * |
| 991 | spu_frame_unwind_cache (struct frame_info *this_frame, |
| 992 | void **this_prologue_cache) |
| 993 | { |
| 994 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 995 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 996 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 997 | struct spu_unwind_cache *info; |
| 998 | struct spu_prologue_data data; |
| 999 | CORE_ADDR id = tdep->id; |
| 1000 | gdb_byte buf[16]; |
| 1001 | |
| 1002 | if (*this_prologue_cache) |
| 1003 | return (struct spu_unwind_cache *) *this_prologue_cache; |
| 1004 | |
| 1005 | info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache); |
| 1006 | *this_prologue_cache = info; |
| 1007 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 1008 | info->frame_base = 0; |
| 1009 | info->local_base = 0; |
| 1010 | |
| 1011 | /* Find the start of the current function, and analyze its prologue. */ |
| 1012 | info->func = get_frame_func (this_frame); |
| 1013 | if (info->func == 0) |
| 1014 | { |
| 1015 | /* Fall back to using the current PC as frame ID. */ |
| 1016 | info->func = get_frame_pc (this_frame); |
| 1017 | data.size = -1; |
| 1018 | } |
| 1019 | else |
| 1020 | spu_analyze_prologue (gdbarch, info->func, get_frame_pc (this_frame), |
| 1021 | &data); |
| 1022 | |
| 1023 | /* If successful, use prologue analysis data. */ |
| 1024 | if (data.size != -1 && data.cfa_reg != -1) |
| 1025 | { |
| 1026 | CORE_ADDR cfa; |
| 1027 | int i; |
| 1028 | |
| 1029 | /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */ |
| 1030 | get_frame_register (this_frame, data.cfa_reg, buf); |
| 1031 | cfa = extract_unsigned_integer (buf, 4, byte_order) + data.cfa_offset; |
| 1032 | cfa = SPUADDR (id, cfa); |
| 1033 | |
| 1034 | /* Call-saved register slots. */ |
| 1035 | for (i = 0; i < SPU_NUM_GPRS; i++) |
| 1036 | if (i == SPU_LR_REGNUM |
| 1037 | || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM)) |
| 1038 | if (data.reg_offset[i] != -1) |
| 1039 | info->saved_regs[i].addr = cfa - data.reg_offset[i]; |
| 1040 | |
| 1041 | /* Frame bases. */ |
| 1042 | info->frame_base = cfa; |
| 1043 | info->local_base = cfa - data.size; |
| 1044 | } |
| 1045 | |
| 1046 | /* Otherwise, fall back to reading the backchain link. */ |
| 1047 | else |
| 1048 | { |
| 1049 | CORE_ADDR reg; |
| 1050 | LONGEST backchain; |
| 1051 | ULONGEST lslr; |
| 1052 | int status; |
| 1053 | |
| 1054 | /* Get local store limit. */ |
| 1055 | lslr = get_frame_register_unsigned (this_frame, SPU_LSLR_REGNUM); |
| 1056 | if (!lslr) |
| 1057 | lslr = (ULONGEST) -1; |
| 1058 | |
| 1059 | /* Get the backchain. */ |
| 1060 | reg = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM); |
| 1061 | status = safe_read_memory_integer (SPUADDR (id, reg), 4, byte_order, |
| 1062 | &backchain); |
| 1063 | |
| 1064 | /* A zero backchain terminates the frame chain. Also, sanity |
| 1065 | check against the local store size limit. */ |
| 1066 | if (status && backchain > 0 && backchain <= lslr) |
| 1067 | { |
| 1068 | /* Assume the link register is saved into its slot. */ |
| 1069 | if (backchain + 16 <= lslr) |
| 1070 | info->saved_regs[SPU_LR_REGNUM].addr = SPUADDR (id, |
| 1071 | backchain + 16); |
| 1072 | |
| 1073 | /* Frame bases. */ |
| 1074 | info->frame_base = SPUADDR (id, backchain); |
| 1075 | info->local_base = SPUADDR (id, reg); |
| 1076 | } |
| 1077 | } |
| 1078 | |
| 1079 | /* If we didn't find a frame, we cannot determine SP / return address. */ |
| 1080 | if (info->frame_base == 0) |
| 1081 | return info; |
| 1082 | |
| 1083 | /* The previous SP is equal to the CFA. */ |
| 1084 | trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM, |
| 1085 | SPUADDR_ADDR (info->frame_base)); |
| 1086 | |
| 1087 | /* Read full contents of the unwound link register in order to |
| 1088 | be able to determine the return address. */ |
| 1089 | if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM)) |
| 1090 | target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16); |
| 1091 | else |
| 1092 | get_frame_register (this_frame, SPU_LR_REGNUM, buf); |
| 1093 | |
| 1094 | /* Normally, the return address is contained in the slot 0 of the |
| 1095 | link register, and slots 1-3 are zero. For an overlay return, |
| 1096 | slot 0 contains the address of the overlay manager return stub, |
| 1097 | slot 1 contains the partition number of the overlay section to |
| 1098 | be returned to, and slot 2 contains the return address within |
| 1099 | that section. Return the latter address in that case. */ |
| 1100 | if (extract_unsigned_integer (buf + 8, 4, byte_order) != 0) |
| 1101 | trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM, |
| 1102 | extract_unsigned_integer (buf + 8, 4, byte_order)); |
| 1103 | else |
| 1104 | trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM, |
| 1105 | extract_unsigned_integer (buf, 4, byte_order)); |
| 1106 | |
| 1107 | return info; |
| 1108 | } |
| 1109 | |
| 1110 | static void |
| 1111 | spu_frame_this_id (struct frame_info *this_frame, |
| 1112 | void **this_prologue_cache, struct frame_id *this_id) |
| 1113 | { |
| 1114 | struct spu_unwind_cache *info = |
| 1115 | spu_frame_unwind_cache (this_frame, this_prologue_cache); |
| 1116 | |
| 1117 | if (info->frame_base == 0) |
| 1118 | return; |
| 1119 | |
| 1120 | *this_id = frame_id_build (info->frame_base, info->func); |
| 1121 | } |
| 1122 | |
| 1123 | static struct value * |
| 1124 | spu_frame_prev_register (struct frame_info *this_frame, |
| 1125 | void **this_prologue_cache, int regnum) |
| 1126 | { |
| 1127 | struct spu_unwind_cache *info |
| 1128 | = spu_frame_unwind_cache (this_frame, this_prologue_cache); |
| 1129 | |
| 1130 | /* Special-case the stack pointer. */ |
| 1131 | if (regnum == SPU_RAW_SP_REGNUM) |
| 1132 | regnum = SPU_SP_REGNUM; |
| 1133 | |
| 1134 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
| 1135 | } |
| 1136 | |
| 1137 | static const struct frame_unwind spu_frame_unwind = { |
| 1138 | NORMAL_FRAME, |
| 1139 | default_frame_unwind_stop_reason, |
| 1140 | spu_frame_this_id, |
| 1141 | spu_frame_prev_register, |
| 1142 | NULL, |
| 1143 | default_frame_sniffer |
| 1144 | }; |
| 1145 | |
| 1146 | static CORE_ADDR |
| 1147 | spu_frame_base_address (struct frame_info *this_frame, void **this_cache) |
| 1148 | { |
| 1149 | struct spu_unwind_cache *info |
| 1150 | = spu_frame_unwind_cache (this_frame, this_cache); |
| 1151 | return info->local_base; |
| 1152 | } |
| 1153 | |
| 1154 | static const struct frame_base spu_frame_base = { |
| 1155 | &spu_frame_unwind, |
| 1156 | spu_frame_base_address, |
| 1157 | spu_frame_base_address, |
| 1158 | spu_frame_base_address |
| 1159 | }; |
| 1160 | |
| 1161 | static CORE_ADDR |
| 1162 | spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1163 | { |
| 1164 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1165 | CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM); |
| 1166 | /* Mask off interrupt enable bit. */ |
| 1167 | return SPUADDR (tdep->id, pc & -4); |
| 1168 | } |
| 1169 | |
| 1170 | static CORE_ADDR |
| 1171 | spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1172 | { |
| 1173 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1174 | CORE_ADDR sp = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM); |
| 1175 | return SPUADDR (tdep->id, sp); |
| 1176 | } |
| 1177 | |
| 1178 | static CORE_ADDR |
| 1179 | spu_read_pc (readable_regcache *regcache) |
| 1180 | { |
| 1181 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
| 1182 | ULONGEST pc; |
| 1183 | |
| 1184 | regcache->cooked_read (SPU_PC_REGNUM, &pc); |
| 1185 | /* Mask off interrupt enable bit. */ |
| 1186 | return SPUADDR (tdep->id, pc & -4); |
| 1187 | } |
| 1188 | |
| 1189 | static void |
| 1190 | spu_write_pc (struct regcache *regcache, CORE_ADDR pc) |
| 1191 | { |
| 1192 | /* Keep interrupt enabled state unchanged. */ |
| 1193 | ULONGEST old_pc; |
| 1194 | |
| 1195 | regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc); |
| 1196 | regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM, |
| 1197 | (SPUADDR_ADDR (pc) & -4) | (old_pc & 3)); |
| 1198 | } |
| 1199 | |
| 1200 | |
| 1201 | /* Cell/B.E. cross-architecture unwinder support. */ |
| 1202 | |
| 1203 | struct spu2ppu_cache |
| 1204 | { |
| 1205 | struct frame_id frame_id; |
| 1206 | readonly_detached_regcache *regcache; |
| 1207 | }; |
| 1208 | |
| 1209 | static struct gdbarch * |
| 1210 | spu2ppu_prev_arch (struct frame_info *this_frame, void **this_cache) |
| 1211 | { |
| 1212 | struct spu2ppu_cache *cache = (struct spu2ppu_cache *) *this_cache; |
| 1213 | return cache->regcache->arch (); |
| 1214 | } |
| 1215 | |
| 1216 | static void |
| 1217 | spu2ppu_this_id (struct frame_info *this_frame, |
| 1218 | void **this_cache, struct frame_id *this_id) |
| 1219 | { |
| 1220 | struct spu2ppu_cache *cache = (struct spu2ppu_cache *) *this_cache; |
| 1221 | *this_id = cache->frame_id; |
| 1222 | } |
| 1223 | |
| 1224 | static struct value * |
| 1225 | spu2ppu_prev_register (struct frame_info *this_frame, |
| 1226 | void **this_cache, int regnum) |
| 1227 | { |
| 1228 | struct spu2ppu_cache *cache = (struct spu2ppu_cache *) *this_cache; |
| 1229 | struct gdbarch *gdbarch = cache->regcache->arch (); |
| 1230 | gdb_byte *buf; |
| 1231 | |
| 1232 | buf = (gdb_byte *) alloca (register_size (gdbarch, regnum)); |
| 1233 | cache->regcache->cooked_read (regnum, buf); |
| 1234 | return frame_unwind_got_bytes (this_frame, regnum, buf); |
| 1235 | } |
| 1236 | |
| 1237 | static int |
| 1238 | spu2ppu_sniffer (const struct frame_unwind *self, |
| 1239 | struct frame_info *this_frame, void **this_prologue_cache) |
| 1240 | { |
| 1241 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1242 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1243 | CORE_ADDR base, func, backchain; |
| 1244 | gdb_byte buf[4]; |
| 1245 | |
| 1246 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_spu) |
| 1247 | return 0; |
| 1248 | |
| 1249 | base = get_frame_sp (this_frame); |
| 1250 | func = get_frame_pc (this_frame); |
| 1251 | if (target_read_memory (base, buf, 4)) |
| 1252 | return 0; |
| 1253 | backchain = extract_unsigned_integer (buf, 4, byte_order); |
| 1254 | |
| 1255 | if (!backchain) |
| 1256 | { |
| 1257 | struct frame_info *fi; |
| 1258 | |
| 1259 | struct spu2ppu_cache *cache |
| 1260 | = FRAME_OBSTACK_CALLOC (1, struct spu2ppu_cache); |
| 1261 | |
| 1262 | cache->frame_id = frame_id_build (base + 16, func); |
| 1263 | |
| 1264 | for (fi = get_next_frame (this_frame); fi; fi = get_next_frame (fi)) |
| 1265 | if (gdbarch_bfd_arch_info (get_frame_arch (fi))->arch != bfd_arch_spu) |
| 1266 | break; |
| 1267 | |
| 1268 | if (fi) |
| 1269 | { |
| 1270 | cache->regcache = frame_save_as_regcache (fi).release (); |
| 1271 | *this_prologue_cache = cache; |
| 1272 | return 1; |
| 1273 | } |
| 1274 | else |
| 1275 | { |
| 1276 | struct regcache *regcache; |
| 1277 | regcache = get_thread_arch_regcache (inferior_ptid, target_gdbarch ()); |
| 1278 | cache->regcache = new readonly_detached_regcache (*regcache); |
| 1279 | *this_prologue_cache = cache; |
| 1280 | return 1; |
| 1281 | } |
| 1282 | } |
| 1283 | |
| 1284 | return 0; |
| 1285 | } |
| 1286 | |
| 1287 | static void |
| 1288 | spu2ppu_dealloc_cache (struct frame_info *self, void *this_cache) |
| 1289 | { |
| 1290 | struct spu2ppu_cache *cache = (struct spu2ppu_cache *) this_cache; |
| 1291 | delete cache->regcache; |
| 1292 | } |
| 1293 | |
| 1294 | static const struct frame_unwind spu2ppu_unwind = { |
| 1295 | ARCH_FRAME, |
| 1296 | default_frame_unwind_stop_reason, |
| 1297 | spu2ppu_this_id, |
| 1298 | spu2ppu_prev_register, |
| 1299 | NULL, |
| 1300 | spu2ppu_sniffer, |
| 1301 | spu2ppu_dealloc_cache, |
| 1302 | spu2ppu_prev_arch, |
| 1303 | }; |
| 1304 | |
| 1305 | |
| 1306 | /* Function calling convention. */ |
| 1307 | |
| 1308 | static CORE_ADDR |
| 1309 | spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
| 1310 | { |
| 1311 | return sp & ~15; |
| 1312 | } |
| 1313 | |
| 1314 | static CORE_ADDR |
| 1315 | spu_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, |
| 1316 | struct value **args, int nargs, struct type *value_type, |
| 1317 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
| 1318 | struct regcache *regcache) |
| 1319 | { |
| 1320 | /* Allocate space sufficient for a breakpoint, keeping the stack aligned. */ |
| 1321 | sp = (sp - 4) & ~15; |
| 1322 | /* Store the address of that breakpoint */ |
| 1323 | *bp_addr = sp; |
| 1324 | /* The call starts at the callee's entry point. */ |
| 1325 | *real_pc = funaddr; |
| 1326 | |
| 1327 | return sp; |
| 1328 | } |
| 1329 | |
| 1330 | static int |
| 1331 | spu_scalar_value_p (struct type *type) |
| 1332 | { |
| 1333 | switch (TYPE_CODE (type)) |
| 1334 | { |
| 1335 | case TYPE_CODE_INT: |
| 1336 | case TYPE_CODE_ENUM: |
| 1337 | case TYPE_CODE_RANGE: |
| 1338 | case TYPE_CODE_CHAR: |
| 1339 | case TYPE_CODE_BOOL: |
| 1340 | case TYPE_CODE_PTR: |
| 1341 | case TYPE_CODE_REF: |
| 1342 | case TYPE_CODE_RVALUE_REF: |
| 1343 | return TYPE_LENGTH (type) <= 16; |
| 1344 | |
| 1345 | default: |
| 1346 | return 0; |
| 1347 | } |
| 1348 | } |
| 1349 | |
| 1350 | static void |
| 1351 | spu_value_to_regcache (struct regcache *regcache, int regnum, |
| 1352 | struct type *type, const gdb_byte *in) |
| 1353 | { |
| 1354 | int len = TYPE_LENGTH (type); |
| 1355 | |
| 1356 | if (spu_scalar_value_p (type)) |
| 1357 | { |
| 1358 | int preferred_slot = len < 4 ? 4 - len : 0; |
| 1359 | regcache->cooked_write_part (regnum, preferred_slot, len, in); |
| 1360 | } |
| 1361 | else |
| 1362 | { |
| 1363 | while (len >= 16) |
| 1364 | { |
| 1365 | regcache->cooked_write (regnum++, in); |
| 1366 | in += 16; |
| 1367 | len -= 16; |
| 1368 | } |
| 1369 | |
| 1370 | if (len > 0) |
| 1371 | regcache->cooked_write_part (regnum, 0, len, in); |
| 1372 | } |
| 1373 | } |
| 1374 | |
| 1375 | static void |
| 1376 | spu_regcache_to_value (struct regcache *regcache, int regnum, |
| 1377 | struct type *type, gdb_byte *out) |
| 1378 | { |
| 1379 | int len = TYPE_LENGTH (type); |
| 1380 | |
| 1381 | if (spu_scalar_value_p (type)) |
| 1382 | { |
| 1383 | int preferred_slot = len < 4 ? 4 - len : 0; |
| 1384 | regcache->cooked_read_part (regnum, preferred_slot, len, out); |
| 1385 | } |
| 1386 | else |
| 1387 | { |
| 1388 | while (len >= 16) |
| 1389 | { |
| 1390 | regcache->cooked_read (regnum++, out); |
| 1391 | out += 16; |
| 1392 | len -= 16; |
| 1393 | } |
| 1394 | |
| 1395 | if (len > 0) |
| 1396 | regcache->cooked_read_part (regnum, 0, len, out); |
| 1397 | } |
| 1398 | } |
| 1399 | |
| 1400 | static CORE_ADDR |
| 1401 | spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 1402 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 1403 | int nargs, struct value **args, CORE_ADDR sp, |
| 1404 | int struct_return, CORE_ADDR struct_addr) |
| 1405 | { |
| 1406 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1407 | CORE_ADDR sp_delta; |
| 1408 | int i; |
| 1409 | int regnum = SPU_ARG1_REGNUM; |
| 1410 | int stack_arg = -1; |
| 1411 | gdb_byte buf[16]; |
| 1412 | |
| 1413 | /* Set the return address. */ |
| 1414 | memset (buf, 0, sizeof buf); |
| 1415 | store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (bp_addr)); |
| 1416 | regcache->cooked_write (SPU_LR_REGNUM, buf); |
| 1417 | |
| 1418 | /* If STRUCT_RETURN is true, then the struct return address (in |
| 1419 | STRUCT_ADDR) will consume the first argument-passing register. |
| 1420 | Both adjust the register count and store that value. */ |
| 1421 | if (struct_return) |
| 1422 | { |
| 1423 | memset (buf, 0, sizeof buf); |
| 1424 | store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (struct_addr)); |
| 1425 | regcache->cooked_write (regnum++, buf); |
| 1426 | } |
| 1427 | |
| 1428 | /* Fill in argument registers. */ |
| 1429 | for (i = 0; i < nargs; i++) |
| 1430 | { |
| 1431 | struct value *arg = args[i]; |
| 1432 | struct type *type = check_typedef (value_type (arg)); |
| 1433 | const gdb_byte *contents = value_contents (arg); |
| 1434 | int n_regs = align_up (TYPE_LENGTH (type), 16) / 16; |
| 1435 | |
| 1436 | /* If the argument doesn't wholly fit into registers, it and |
| 1437 | all subsequent arguments go to the stack. */ |
| 1438 | if (regnum + n_regs - 1 > SPU_ARGN_REGNUM) |
| 1439 | { |
| 1440 | stack_arg = i; |
| 1441 | break; |
| 1442 | } |
| 1443 | |
| 1444 | spu_value_to_regcache (regcache, regnum, type, contents); |
| 1445 | regnum += n_regs; |
| 1446 | } |
| 1447 | |
| 1448 | /* Overflow arguments go to the stack. */ |
| 1449 | if (stack_arg != -1) |
| 1450 | { |
| 1451 | CORE_ADDR ap; |
| 1452 | |
| 1453 | /* Allocate all required stack size. */ |
| 1454 | for (i = stack_arg; i < nargs; i++) |
| 1455 | { |
| 1456 | struct type *type = check_typedef (value_type (args[i])); |
| 1457 | sp -= align_up (TYPE_LENGTH (type), 16); |
| 1458 | } |
| 1459 | |
| 1460 | /* Fill in stack arguments. */ |
| 1461 | ap = sp; |
| 1462 | for (i = stack_arg; i < nargs; i++) |
| 1463 | { |
| 1464 | struct value *arg = args[i]; |
| 1465 | struct type *type = check_typedef (value_type (arg)); |
| 1466 | int len = TYPE_LENGTH (type); |
| 1467 | int preferred_slot; |
| 1468 | |
| 1469 | if (spu_scalar_value_p (type)) |
| 1470 | preferred_slot = len < 4 ? 4 - len : 0; |
| 1471 | else |
| 1472 | preferred_slot = 0; |
| 1473 | |
| 1474 | target_write_memory (ap + preferred_slot, value_contents (arg), len); |
| 1475 | ap += align_up (TYPE_LENGTH (type), 16); |
| 1476 | } |
| 1477 | } |
| 1478 | |
| 1479 | /* Allocate stack frame header. */ |
| 1480 | sp -= 32; |
| 1481 | |
| 1482 | /* Store stack back chain. */ |
| 1483 | regcache->cooked_read (SPU_RAW_SP_REGNUM, buf); |
| 1484 | target_write_memory (sp, buf, 16); |
| 1485 | |
| 1486 | /* Finally, update all slots of the SP register. */ |
| 1487 | sp_delta = sp - extract_unsigned_integer (buf, 4, byte_order); |
| 1488 | for (i = 0; i < 4; i++) |
| 1489 | { |
| 1490 | CORE_ADDR sp_slot = extract_unsigned_integer (buf + 4*i, 4, byte_order); |
| 1491 | store_unsigned_integer (buf + 4*i, 4, byte_order, sp_slot + sp_delta); |
| 1492 | } |
| 1493 | regcache->cooked_write (SPU_RAW_SP_REGNUM, buf); |
| 1494 | |
| 1495 | return sp; |
| 1496 | } |
| 1497 | |
| 1498 | static struct frame_id |
| 1499 | spu_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1500 | { |
| 1501 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1502 | CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM); |
| 1503 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM); |
| 1504 | return frame_id_build (SPUADDR (tdep->id, sp), SPUADDR (tdep->id, pc & -4)); |
| 1505 | } |
| 1506 | |
| 1507 | /* Function return value access. */ |
| 1508 | |
| 1509 | static enum return_value_convention |
| 1510 | spu_return_value (struct gdbarch *gdbarch, struct value *function, |
| 1511 | struct type *type, struct regcache *regcache, |
| 1512 | gdb_byte *out, const gdb_byte *in) |
| 1513 | { |
| 1514 | struct type *func_type = function ? value_type (function) : NULL; |
| 1515 | enum return_value_convention rvc; |
| 1516 | int opencl_vector = 0; |
| 1517 | |
| 1518 | if (func_type) |
| 1519 | { |
| 1520 | func_type = check_typedef (func_type); |
| 1521 | |
| 1522 | if (TYPE_CODE (func_type) == TYPE_CODE_PTR) |
| 1523 | func_type = check_typedef (TYPE_TARGET_TYPE (func_type)); |
| 1524 | |
| 1525 | if (TYPE_CODE (func_type) == TYPE_CODE_FUNC |
| 1526 | && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GDB_IBM_OpenCL |
| 1527 | && TYPE_CODE (type) == TYPE_CODE_ARRAY |
| 1528 | && TYPE_VECTOR (type)) |
| 1529 | opencl_vector = 1; |
| 1530 | } |
| 1531 | |
| 1532 | if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16) |
| 1533 | rvc = RETURN_VALUE_REGISTER_CONVENTION; |
| 1534 | else |
| 1535 | rvc = RETURN_VALUE_STRUCT_CONVENTION; |
| 1536 | |
| 1537 | if (in) |
| 1538 | { |
| 1539 | switch (rvc) |
| 1540 | { |
| 1541 | case RETURN_VALUE_REGISTER_CONVENTION: |
| 1542 | if (opencl_vector && TYPE_LENGTH (type) == 2) |
| 1543 | regcache->cooked_write_part (SPU_ARG1_REGNUM, 2, 2, in); |
| 1544 | else |
| 1545 | spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in); |
| 1546 | break; |
| 1547 | |
| 1548 | case RETURN_VALUE_STRUCT_CONVENTION: |
| 1549 | error (_("Cannot set function return value.")); |
| 1550 | break; |
| 1551 | } |
| 1552 | } |
| 1553 | else if (out) |
| 1554 | { |
| 1555 | switch (rvc) |
| 1556 | { |
| 1557 | case RETURN_VALUE_REGISTER_CONVENTION: |
| 1558 | if (opencl_vector && TYPE_LENGTH (type) == 2) |
| 1559 | regcache->cooked_read_part (SPU_ARG1_REGNUM, 2, 2, out); |
| 1560 | else |
| 1561 | spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out); |
| 1562 | break; |
| 1563 | |
| 1564 | case RETURN_VALUE_STRUCT_CONVENTION: |
| 1565 | error (_("Function return value unknown.")); |
| 1566 | break; |
| 1567 | } |
| 1568 | } |
| 1569 | |
| 1570 | return rvc; |
| 1571 | } |
| 1572 | |
| 1573 | |
| 1574 | /* Breakpoints. */ |
| 1575 | constexpr gdb_byte spu_break_insn[] = { 0x00, 0x00, 0x3f, 0xff }; |
| 1576 | |
| 1577 | typedef BP_MANIPULATION (spu_break_insn) spu_breakpoint; |
| 1578 | |
| 1579 | static int |
| 1580 | spu_memory_remove_breakpoint (struct gdbarch *gdbarch, |
| 1581 | struct bp_target_info *bp_tgt) |
| 1582 | { |
| 1583 | /* We work around a problem in combined Cell/B.E. debugging here. Consider |
| 1584 | that in a combined application, we have some breakpoints inserted in SPU |
| 1585 | code, and now the application forks (on the PPU side). GDB common code |
| 1586 | will assume that the fork system call copied all breakpoints into the new |
| 1587 | process' address space, and that all those copies now need to be removed |
| 1588 | (see breakpoint.c:detach_breakpoints). |
| 1589 | |
| 1590 | While this is certainly true for PPU side breakpoints, it is not true |
| 1591 | for SPU side breakpoints. fork will clone the SPU context file |
| 1592 | descriptors, so that all the existing SPU contexts are in accessible |
| 1593 | in the new process. However, the contents of the SPU contexts themselves |
| 1594 | are *not* cloned. Therefore the effect of detach_breakpoints is to |
| 1595 | remove SPU breakpoints from the *original* SPU context's local store |
| 1596 | -- this is not the correct behaviour. |
| 1597 | |
| 1598 | The workaround is to check whether the PID we are asked to remove this |
| 1599 | breakpoint from (i.e. inferior_ptid.pid ()) is different from the |
| 1600 | PID of the current inferior (i.e. current_inferior ()->pid). This is only |
| 1601 | true in the context of detach_breakpoints. If so, we simply do nothing. |
| 1602 | [ Note that for the fork child process, it does not matter if breakpoints |
| 1603 | remain inserted, because those SPU contexts are not runnable anyway -- |
| 1604 | the Linux kernel allows only the original process to invoke spu_run. */ |
| 1605 | |
| 1606 | if (inferior_ptid.pid () != current_inferior ()->pid) |
| 1607 | return 0; |
| 1608 | |
| 1609 | return default_memory_remove_breakpoint (gdbarch, bp_tgt); |
| 1610 | } |
| 1611 | |
| 1612 | |
| 1613 | /* Software single-stepping support. */ |
| 1614 | |
| 1615 | static std::vector<CORE_ADDR> |
| 1616 | spu_software_single_step (struct regcache *regcache) |
| 1617 | { |
| 1618 | struct gdbarch *gdbarch = regcache->arch (); |
| 1619 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1620 | CORE_ADDR pc, next_pc; |
| 1621 | unsigned int insn; |
| 1622 | int offset, reg; |
| 1623 | gdb_byte buf[4]; |
| 1624 | ULONGEST lslr; |
| 1625 | std::vector<CORE_ADDR> next_pcs; |
| 1626 | |
| 1627 | pc = regcache_read_pc (regcache); |
| 1628 | |
| 1629 | if (target_read_memory (pc, buf, 4)) |
| 1630 | throw_error (MEMORY_ERROR, _("Could not read instruction at %s."), |
| 1631 | paddress (gdbarch, pc)); |
| 1632 | |
| 1633 | insn = extract_unsigned_integer (buf, 4, byte_order); |
| 1634 | |
| 1635 | /* Get local store limit. */ |
| 1636 | if ((regcache_cooked_read_unsigned (regcache, SPU_LSLR_REGNUM, &lslr) |
| 1637 | != REG_VALID) || !lslr) |
| 1638 | lslr = (ULONGEST) -1; |
| 1639 | |
| 1640 | /* Next sequential instruction is at PC + 4, except if the current |
| 1641 | instruction is a PPE-assisted call, in which case it is at PC + 8. |
| 1642 | Wrap around LS limit to be on the safe side. */ |
| 1643 | if ((insn & 0xffffff00) == 0x00002100) |
| 1644 | next_pc = (SPUADDR_ADDR (pc) + 8) & lslr; |
| 1645 | else |
| 1646 | next_pc = (SPUADDR_ADDR (pc) + 4) & lslr; |
| 1647 | |
| 1648 | next_pcs.push_back (SPUADDR (SPUADDR_SPU (pc), next_pc)); |
| 1649 | |
| 1650 | if (is_branch (insn, &offset, ®)) |
| 1651 | { |
| 1652 | CORE_ADDR target = offset; |
| 1653 | |
| 1654 | if (reg == SPU_PC_REGNUM) |
| 1655 | target += SPUADDR_ADDR (pc); |
| 1656 | else if (reg != -1) |
| 1657 | { |
| 1658 | regcache->raw_read_part (reg, 0, 4, buf); |
| 1659 | target += extract_unsigned_integer (buf, 4, byte_order) & -4; |
| 1660 | } |
| 1661 | |
| 1662 | target = target & lslr; |
| 1663 | if (target != next_pc) |
| 1664 | next_pcs.push_back (SPUADDR (SPUADDR_SPU (pc), target)); |
| 1665 | } |
| 1666 | |
| 1667 | return next_pcs; |
| 1668 | } |
| 1669 | |
| 1670 | |
| 1671 | /* Longjmp support. */ |
| 1672 | |
| 1673 | static int |
| 1674 | spu_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
| 1675 | { |
| 1676 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 1677 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1678 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1679 | gdb_byte buf[4]; |
| 1680 | CORE_ADDR jb_addr; |
| 1681 | int optim, unavail; |
| 1682 | |
| 1683 | /* Jump buffer is pointed to by the argument register $r3. */ |
| 1684 | if (!get_frame_register_bytes (frame, SPU_ARG1_REGNUM, 0, 4, buf, |
| 1685 | &optim, &unavail)) |
| 1686 | return 0; |
| 1687 | |
| 1688 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
| 1689 | if (target_read_memory (SPUADDR (tdep->id, jb_addr), buf, 4)) |
| 1690 | return 0; |
| 1691 | |
| 1692 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
| 1693 | *pc = SPUADDR (tdep->id, *pc); |
| 1694 | return 1; |
| 1695 | } |
| 1696 | |
| 1697 | |
| 1698 | /* Disassembler. */ |
| 1699 | |
| 1700 | struct spu_dis_asm_info : disassemble_info |
| 1701 | { |
| 1702 | int id; |
| 1703 | }; |
| 1704 | |
| 1705 | static void |
| 1706 | spu_dis_asm_print_address (bfd_vma addr, struct disassemble_info *info) |
| 1707 | { |
| 1708 | struct spu_dis_asm_info *data = (struct spu_dis_asm_info *) info; |
| 1709 | gdb_disassembler *di |
| 1710 | = static_cast<gdb_disassembler *>(info->application_data); |
| 1711 | |
| 1712 | print_address (di->arch (), SPUADDR (data->id, addr), |
| 1713 | (struct ui_file *) info->stream); |
| 1714 | } |
| 1715 | |
| 1716 | static int |
| 1717 | gdb_print_insn_spu (bfd_vma memaddr, struct disassemble_info *info) |
| 1718 | { |
| 1719 | /* The opcodes disassembler does 18-bit address arithmetic. Make |
| 1720 | sure the SPU ID encoded in the high bits is added back when we |
| 1721 | call print_address. */ |
| 1722 | struct spu_dis_asm_info spu_info; |
| 1723 | |
| 1724 | memcpy (&spu_info, info, sizeof (*info)); |
| 1725 | spu_info.id = SPUADDR_SPU (memaddr); |
| 1726 | spu_info.print_address_func = spu_dis_asm_print_address; |
| 1727 | return default_print_insn (memaddr, &spu_info); |
| 1728 | } |
| 1729 | |
| 1730 | |
| 1731 | /* Target overlays for the SPU overlay manager. |
| 1732 | |
| 1733 | See the documentation of simple_overlay_update for how the |
| 1734 | interface is supposed to work. |
| 1735 | |
| 1736 | Data structures used by the overlay manager: |
| 1737 | |
| 1738 | struct ovly_table |
| 1739 | { |
| 1740 | u32 vma; |
| 1741 | u32 size; |
| 1742 | u32 pos; |
| 1743 | u32 buf; |
| 1744 | } _ovly_table[]; -- one entry per overlay section |
| 1745 | |
| 1746 | struct ovly_buf_table |
| 1747 | { |
| 1748 | u32 mapped; |
| 1749 | } _ovly_buf_table[]; -- one entry per overlay buffer |
| 1750 | |
| 1751 | _ovly_table should never change. |
| 1752 | |
| 1753 | Both tables are aligned to a 16-byte boundary, the symbols |
| 1754 | _ovly_table and _ovly_buf_table are of type STT_OBJECT and their |
| 1755 | size set to the size of the respective array. buf in _ovly_table is |
| 1756 | an index into _ovly_buf_table. |
| 1757 | |
| 1758 | mapped is an index into _ovly_table. Both the mapped and buf indices start |
| 1759 | from one to reference the first entry in their respective tables. */ |
| 1760 | |
| 1761 | /* Using the per-objfile private data mechanism, we store for each |
| 1762 | objfile an array of "struct spu_overlay_table" structures, one |
| 1763 | for each obj_section of the objfile. This structure holds two |
| 1764 | fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this |
| 1765 | is *not* an overlay section. If it is non-zero, it represents |
| 1766 | a target address. The overlay section is mapped iff the target |
| 1767 | integer at this location equals MAPPED_VAL. */ |
| 1768 | |
| 1769 | static const struct objfile_data *spu_overlay_data; |
| 1770 | |
| 1771 | struct spu_overlay_table |
| 1772 | { |
| 1773 | CORE_ADDR mapped_ptr; |
| 1774 | CORE_ADDR mapped_val; |
| 1775 | }; |
| 1776 | |
| 1777 | /* Retrieve the overlay table for OBJFILE. If not already cached, read |
| 1778 | the _ovly_table data structure from the target and initialize the |
| 1779 | spu_overlay_table data structure from it. */ |
| 1780 | static struct spu_overlay_table * |
| 1781 | spu_get_overlay_table (struct objfile *objfile) |
| 1782 | { |
| 1783 | enum bfd_endian byte_order = bfd_big_endian (objfile->obfd)? |
| 1784 | BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; |
| 1785 | struct bound_minimal_symbol ovly_table_msym, ovly_buf_table_msym; |
| 1786 | CORE_ADDR ovly_table_base, ovly_buf_table_base; |
| 1787 | unsigned ovly_table_size, ovly_buf_table_size; |
| 1788 | struct spu_overlay_table *tbl; |
| 1789 | struct obj_section *osect; |
| 1790 | gdb_byte *ovly_table; |
| 1791 | int i; |
| 1792 | |
| 1793 | tbl = (struct spu_overlay_table *) objfile_data (objfile, spu_overlay_data); |
| 1794 | if (tbl) |
| 1795 | return tbl; |
| 1796 | |
| 1797 | ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile); |
| 1798 | if (!ovly_table_msym.minsym) |
| 1799 | return NULL; |
| 1800 | |
| 1801 | ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table", |
| 1802 | NULL, objfile); |
| 1803 | if (!ovly_buf_table_msym.minsym) |
| 1804 | return NULL; |
| 1805 | |
| 1806 | ovly_table_base = BMSYMBOL_VALUE_ADDRESS (ovly_table_msym); |
| 1807 | ovly_table_size = MSYMBOL_SIZE (ovly_table_msym.minsym); |
| 1808 | |
| 1809 | ovly_buf_table_base = BMSYMBOL_VALUE_ADDRESS (ovly_buf_table_msym); |
| 1810 | ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym.minsym); |
| 1811 | |
| 1812 | ovly_table = (gdb_byte *) xmalloc (ovly_table_size); |
| 1813 | read_memory (ovly_table_base, ovly_table, ovly_table_size); |
| 1814 | |
| 1815 | tbl = OBSTACK_CALLOC (&objfile->objfile_obstack, |
| 1816 | objfile->sections_end - objfile->sections, |
| 1817 | struct spu_overlay_table); |
| 1818 | |
| 1819 | for (i = 0; i < ovly_table_size / 16; i++) |
| 1820 | { |
| 1821 | CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0, |
| 1822 | 4, byte_order); |
| 1823 | /* Note that this skips the "size" entry, which is at offset |
| 1824 | 4. */ |
| 1825 | CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8, |
| 1826 | 4, byte_order); |
| 1827 | CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12, |
| 1828 | 4, byte_order); |
| 1829 | |
| 1830 | if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size) |
| 1831 | continue; |
| 1832 | |
| 1833 | ALL_OBJFILE_OSECTIONS (objfile, osect) |
| 1834 | if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section) |
| 1835 | && pos == osect->the_bfd_section->filepos) |
| 1836 | { |
| 1837 | int ndx = osect - objfile->sections; |
| 1838 | tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4; |
| 1839 | tbl[ndx].mapped_val = i + 1; |
| 1840 | break; |
| 1841 | } |
| 1842 | } |
| 1843 | |
| 1844 | xfree (ovly_table); |
| 1845 | set_objfile_data (objfile, spu_overlay_data, tbl); |
| 1846 | return tbl; |
| 1847 | } |
| 1848 | |
| 1849 | /* Read _ovly_buf_table entry from the target to dermine whether |
| 1850 | OSECT is currently mapped, and update the mapped state. */ |
| 1851 | static void |
| 1852 | spu_overlay_update_osect (struct obj_section *osect) |
| 1853 | { |
| 1854 | enum bfd_endian byte_order = bfd_big_endian (osect->objfile->obfd)? |
| 1855 | BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; |
| 1856 | struct spu_overlay_table *ovly_table; |
| 1857 | CORE_ADDR id, val; |
| 1858 | |
| 1859 | ovly_table = spu_get_overlay_table (osect->objfile); |
| 1860 | if (!ovly_table) |
| 1861 | return; |
| 1862 | |
| 1863 | ovly_table += osect - osect->objfile->sections; |
| 1864 | if (ovly_table->mapped_ptr == 0) |
| 1865 | return; |
| 1866 | |
| 1867 | id = SPUADDR_SPU (obj_section_addr (osect)); |
| 1868 | val = read_memory_unsigned_integer (SPUADDR (id, ovly_table->mapped_ptr), |
| 1869 | 4, byte_order); |
| 1870 | osect->ovly_mapped = (val == ovly_table->mapped_val); |
| 1871 | } |
| 1872 | |
| 1873 | /* If OSECT is NULL, then update all sections' mapped state. |
| 1874 | If OSECT is non-NULL, then update only OSECT's mapped state. */ |
| 1875 | static void |
| 1876 | spu_overlay_update (struct obj_section *osect) |
| 1877 | { |
| 1878 | /* Just one section. */ |
| 1879 | if (osect) |
| 1880 | spu_overlay_update_osect (osect); |
| 1881 | |
| 1882 | /* All sections. */ |
| 1883 | else |
| 1884 | { |
| 1885 | struct objfile *objfile; |
| 1886 | |
| 1887 | ALL_OBJSECTIONS (objfile, osect) |
| 1888 | if (section_is_overlay (osect)) |
| 1889 | spu_overlay_update_osect (osect); |
| 1890 | } |
| 1891 | } |
| 1892 | |
| 1893 | /* Whenever a new objfile is loaded, read the target's _ovly_table. |
| 1894 | If there is one, go through all sections and make sure for non- |
| 1895 | overlay sections LMA equals VMA, while for overlay sections LMA |
| 1896 | is larger than SPU_OVERLAY_LMA. */ |
| 1897 | static void |
| 1898 | spu_overlay_new_objfile (struct objfile *objfile) |
| 1899 | { |
| 1900 | struct spu_overlay_table *ovly_table; |
| 1901 | struct obj_section *osect; |
| 1902 | |
| 1903 | /* If we've already touched this file, do nothing. */ |
| 1904 | if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL) |
| 1905 | return; |
| 1906 | |
| 1907 | /* Consider only SPU objfiles. */ |
| 1908 | if (bfd_get_arch (objfile->obfd) != bfd_arch_spu) |
| 1909 | return; |
| 1910 | |
| 1911 | /* Check if this objfile has overlays. */ |
| 1912 | ovly_table = spu_get_overlay_table (objfile); |
| 1913 | if (!ovly_table) |
| 1914 | return; |
| 1915 | |
| 1916 | /* Now go and fiddle with all the LMAs. */ |
| 1917 | ALL_OBJFILE_OSECTIONS (objfile, osect) |
| 1918 | { |
| 1919 | asection *bsect = osect->the_bfd_section; |
| 1920 | int ndx = osect - objfile->sections; |
| 1921 | |
| 1922 | if (ovly_table[ndx].mapped_ptr == 0) |
| 1923 | bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect); |
| 1924 | else |
| 1925 | bfd_section_lma (obfd, bsect) = SPU_OVERLAY_LMA + bsect->filepos; |
| 1926 | } |
| 1927 | } |
| 1928 | |
| 1929 | |
| 1930 | /* Insert temporary breakpoint on "main" function of newly loaded |
| 1931 | SPE context OBJFILE. */ |
| 1932 | static void |
| 1933 | spu_catch_start (struct objfile *objfile) |
| 1934 | { |
| 1935 | struct bound_minimal_symbol minsym; |
| 1936 | struct compunit_symtab *cust; |
| 1937 | CORE_ADDR pc; |
| 1938 | |
| 1939 | /* Do this only if requested by "set spu stop-on-load on". */ |
| 1940 | if (!spu_stop_on_load_p) |
| 1941 | return; |
| 1942 | |
| 1943 | /* Consider only SPU objfiles. */ |
| 1944 | if (!objfile || bfd_get_arch (objfile->obfd) != bfd_arch_spu) |
| 1945 | return; |
| 1946 | |
| 1947 | /* The main objfile is handled differently. */ |
| 1948 | if (objfile == symfile_objfile) |
| 1949 | return; |
| 1950 | |
| 1951 | /* There can be multiple symbols named "main". Search for the |
| 1952 | "main" in *this* objfile. */ |
| 1953 | minsym = lookup_minimal_symbol ("main", NULL, objfile); |
| 1954 | if (!minsym.minsym) |
| 1955 | return; |
| 1956 | |
| 1957 | /* If we have debugging information, try to use it -- this |
| 1958 | will allow us to properly skip the prologue. */ |
| 1959 | pc = BMSYMBOL_VALUE_ADDRESS (minsym); |
| 1960 | cust |
| 1961 | = find_pc_sect_compunit_symtab (pc, MSYMBOL_OBJ_SECTION (minsym.objfile, |
| 1962 | minsym.minsym)); |
| 1963 | if (cust != NULL) |
| 1964 | { |
| 1965 | const struct blockvector *bv = COMPUNIT_BLOCKVECTOR (cust); |
| 1966 | struct block *block = BLOCKVECTOR_BLOCK (bv, GLOBAL_BLOCK); |
| 1967 | struct symbol *sym; |
| 1968 | struct symtab_and_line sal; |
| 1969 | |
| 1970 | sym = block_lookup_symbol (block, "main", |
| 1971 | symbol_name_match_type::SEARCH_NAME, |
| 1972 | VAR_DOMAIN); |
| 1973 | if (sym) |
| 1974 | { |
| 1975 | fixup_symbol_section (sym, objfile); |
| 1976 | sal = find_function_start_sal (sym, 1); |
| 1977 | pc = sal.pc; |
| 1978 | } |
| 1979 | } |
| 1980 | |
| 1981 | /* Use a numerical address for the set_breakpoint command to avoid having |
| 1982 | the breakpoint re-set incorrectly. */ |
| 1983 | event_location_up location = new_address_location (pc, NULL, 0); |
| 1984 | create_breakpoint (get_objfile_arch (objfile), location.get (), |
| 1985 | NULL /* cond_string */, -1 /* thread */, |
| 1986 | NULL /* extra_string */, |
| 1987 | 0 /* parse_condition_and_thread */, 1 /* tempflag */, |
| 1988 | bp_breakpoint /* type_wanted */, |
| 1989 | 0 /* ignore_count */, |
| 1990 | AUTO_BOOLEAN_FALSE /* pending_break_support */, |
| 1991 | &bkpt_breakpoint_ops /* ops */, 0 /* from_tty */, |
| 1992 | 1 /* enabled */, 0 /* internal */, 0); |
| 1993 | } |
| 1994 | |
| 1995 | |
| 1996 | /* Look up OBJFILE loaded into FRAME's SPU context. */ |
| 1997 | static struct objfile * |
| 1998 | spu_objfile_from_frame (struct frame_info *frame) |
| 1999 | { |
| 2000 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2001 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2002 | struct objfile *obj; |
| 2003 | |
| 2004 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu) |
| 2005 | return NULL; |
| 2006 | |
| 2007 | ALL_OBJFILES (obj) |
| 2008 | { |
| 2009 | if (obj->sections != obj->sections_end |
| 2010 | && SPUADDR_SPU (obj_section_addr (obj->sections)) == tdep->id) |
| 2011 | return obj; |
| 2012 | } |
| 2013 | |
| 2014 | return NULL; |
| 2015 | } |
| 2016 | |
| 2017 | /* Flush cache for ea pointer access if available. */ |
| 2018 | static void |
| 2019 | flush_ea_cache (void) |
| 2020 | { |
| 2021 | struct bound_minimal_symbol msymbol; |
| 2022 | struct objfile *obj; |
| 2023 | |
| 2024 | if (!has_stack_frames ()) |
| 2025 | return; |
| 2026 | |
| 2027 | obj = spu_objfile_from_frame (get_current_frame ()); |
| 2028 | if (obj == NULL) |
| 2029 | return; |
| 2030 | |
| 2031 | /* Lookup inferior function __cache_flush. */ |
| 2032 | msymbol = lookup_minimal_symbol ("__cache_flush", NULL, obj); |
| 2033 | if (msymbol.minsym != NULL) |
| 2034 | { |
| 2035 | struct type *type; |
| 2036 | CORE_ADDR addr; |
| 2037 | |
| 2038 | type = objfile_type (obj)->builtin_void; |
| 2039 | type = lookup_function_type (type); |
| 2040 | type = lookup_pointer_type (type); |
| 2041 | addr = BMSYMBOL_VALUE_ADDRESS (msymbol); |
| 2042 | |
| 2043 | call_function_by_hand (value_from_pointer (type, addr), NULL, 0, NULL); |
| 2044 | } |
| 2045 | } |
| 2046 | |
| 2047 | /* This handler is called when the inferior has stopped. If it is stopped in |
| 2048 | SPU architecture then flush the ea cache if used. */ |
| 2049 | static void |
| 2050 | spu_attach_normal_stop (struct bpstats *bs, int print_frame) |
| 2051 | { |
| 2052 | if (!spu_auto_flush_cache_p) |
| 2053 | return; |
| 2054 | |
| 2055 | /* Temporarily reset spu_auto_flush_cache_p to avoid recursively |
| 2056 | re-entering this function when __cache_flush stops. */ |
| 2057 | spu_auto_flush_cache_p = 0; |
| 2058 | flush_ea_cache (); |
| 2059 | spu_auto_flush_cache_p = 1; |
| 2060 | } |
| 2061 | |
| 2062 | |
| 2063 | /* "info spu" commands. */ |
| 2064 | |
| 2065 | static void |
| 2066 | info_spu_event_command (const char *args, int from_tty) |
| 2067 | { |
| 2068 | struct frame_info *frame = get_selected_frame (NULL); |
| 2069 | ULONGEST event_status = 0; |
| 2070 | ULONGEST event_mask = 0; |
| 2071 | gdb_byte buf[100]; |
| 2072 | char annex[32]; |
| 2073 | LONGEST len; |
| 2074 | int id; |
| 2075 | |
| 2076 | if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu) |
| 2077 | error (_("\"info spu\" is only supported on the SPU architecture.")); |
| 2078 | |
| 2079 | id = get_frame_register_unsigned (frame, SPU_ID_REGNUM); |
| 2080 | |
| 2081 | xsnprintf (annex, sizeof annex, "%d/event_status", id); |
| 2082 | len = target_read (current_top_target (), TARGET_OBJECT_SPU, annex, |
| 2083 | buf, 0, (sizeof (buf) - 1)); |
| 2084 | if (len <= 0) |
| 2085 | error (_("Could not read event_status.")); |
| 2086 | buf[len] = '\0'; |
| 2087 | event_status = strtoulst ((char *) buf, NULL, 16); |
| 2088 | |
| 2089 | xsnprintf (annex, sizeof annex, "%d/event_mask", id); |
| 2090 | len = target_read (current_top_target (), TARGET_OBJECT_SPU, annex, |
| 2091 | buf, 0, (sizeof (buf) - 1)); |
| 2092 | if (len <= 0) |
| 2093 | error (_("Could not read event_mask.")); |
| 2094 | buf[len] = '\0'; |
| 2095 | event_mask = strtoulst ((char *) buf, NULL, 16); |
| 2096 | |
| 2097 | ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoEvent"); |
| 2098 | |
| 2099 | current_uiout->text (_("Event Status ")); |
| 2100 | current_uiout->field_fmt ("event_status", "0x%s", phex (event_status, 4)); |
| 2101 | current_uiout->text ("\n"); |
| 2102 | current_uiout->text (_("Event Mask ")); |
| 2103 | current_uiout->field_fmt ("event_mask", "0x%s", phex (event_mask, 4)); |
| 2104 | current_uiout->text ("\n"); |
| 2105 | } |
| 2106 | |
| 2107 | static void |
| 2108 | info_spu_signal_command (const char *args, int from_tty) |
| 2109 | { |
| 2110 | struct frame_info *frame = get_selected_frame (NULL); |
| 2111 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2112 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2113 | ULONGEST signal1 = 0; |
| 2114 | ULONGEST signal1_type = 0; |
| 2115 | int signal1_pending = 0; |
| 2116 | ULONGEST signal2 = 0; |
| 2117 | ULONGEST signal2_type = 0; |
| 2118 | int signal2_pending = 0; |
| 2119 | char annex[32]; |
| 2120 | gdb_byte buf[100]; |
| 2121 | LONGEST len; |
| 2122 | int id; |
| 2123 | |
| 2124 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu) |
| 2125 | error (_("\"info spu\" is only supported on the SPU architecture.")); |
| 2126 | |
| 2127 | id = get_frame_register_unsigned (frame, SPU_ID_REGNUM); |
| 2128 | |
| 2129 | xsnprintf (annex, sizeof annex, "%d/signal1", id); |
| 2130 | len = target_read (current_top_target (), TARGET_OBJECT_SPU, |
| 2131 | annex, buf, 0, 4); |
| 2132 | if (len < 0) |
| 2133 | error (_("Could not read signal1.")); |
| 2134 | else if (len == 4) |
| 2135 | { |
| 2136 | signal1 = extract_unsigned_integer (buf, 4, byte_order); |
| 2137 | signal1_pending = 1; |
| 2138 | } |
| 2139 | |
| 2140 | xsnprintf (annex, sizeof annex, "%d/signal1_type", id); |
| 2141 | len = target_read (current_top_target (), TARGET_OBJECT_SPU, annex, |
| 2142 | buf, 0, (sizeof (buf) - 1)); |
| 2143 | if (len <= 0) |
| 2144 | error (_("Could not read signal1_type.")); |
| 2145 | buf[len] = '\0'; |
| 2146 | signal1_type = strtoulst ((char *) buf, NULL, 16); |
| 2147 | |
| 2148 | xsnprintf (annex, sizeof annex, "%d/signal2", id); |
| 2149 | len = target_read (current_top_target (), TARGET_OBJECT_SPU, |
| 2150 | annex, buf, 0, 4); |
| 2151 | if (len < 0) |
| 2152 | error (_("Could not read signal2.")); |
| 2153 | else if (len == 4) |
| 2154 | { |
| 2155 | signal2 = extract_unsigned_integer (buf, 4, byte_order); |
| 2156 | signal2_pending = 1; |
| 2157 | } |
| 2158 | |
| 2159 | xsnprintf (annex, sizeof annex, "%d/signal2_type", id); |
| 2160 | len = target_read (current_top_target (), TARGET_OBJECT_SPU, annex, |
| 2161 | buf, 0, (sizeof (buf) - 1)); |
| 2162 | if (len <= 0) |
| 2163 | error (_("Could not read signal2_type.")); |
| 2164 | buf[len] = '\0'; |
| 2165 | signal2_type = strtoulst ((char *) buf, NULL, 16); |
| 2166 | |
| 2167 | ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoSignal"); |
| 2168 | |
| 2169 | if (current_uiout->is_mi_like_p ()) |
| 2170 | { |
| 2171 | current_uiout->field_int ("signal1_pending", signal1_pending); |
| 2172 | current_uiout->field_fmt ("signal1", "0x%s", phex_nz (signal1, 4)); |
| 2173 | current_uiout->field_int ("signal1_type", signal1_type); |
| 2174 | current_uiout->field_int ("signal2_pending", signal2_pending); |
| 2175 | current_uiout->field_fmt ("signal2", "0x%s", phex_nz (signal2, 4)); |
| 2176 | current_uiout->field_int ("signal2_type", signal2_type); |
| 2177 | } |
| 2178 | else |
| 2179 | { |
| 2180 | if (signal1_pending) |
| 2181 | printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4)); |
| 2182 | else |
| 2183 | printf_filtered (_("Signal 1 not pending ")); |
| 2184 | |
| 2185 | if (signal1_type) |
| 2186 | printf_filtered (_("(Type Or)\n")); |
| 2187 | else |
| 2188 | printf_filtered (_("(Type Overwrite)\n")); |
| 2189 | |
| 2190 | if (signal2_pending) |
| 2191 | printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4)); |
| 2192 | else |
| 2193 | printf_filtered (_("Signal 2 not pending ")); |
| 2194 | |
| 2195 | if (signal2_type) |
| 2196 | printf_filtered (_("(Type Or)\n")); |
| 2197 | else |
| 2198 | printf_filtered (_("(Type Overwrite)\n")); |
| 2199 | } |
| 2200 | } |
| 2201 | |
| 2202 | static void |
| 2203 | info_spu_mailbox_list (gdb_byte *buf, int nr, enum bfd_endian byte_order, |
| 2204 | const char *field, const char *msg) |
| 2205 | { |
| 2206 | int i; |
| 2207 | |
| 2208 | if (nr <= 0) |
| 2209 | return; |
| 2210 | |
| 2211 | ui_out_emit_table table_emitter (current_uiout, 1, nr, "mbox"); |
| 2212 | |
| 2213 | current_uiout->table_header (32, ui_left, field, msg); |
| 2214 | current_uiout->table_body (); |
| 2215 | |
| 2216 | for (i = 0; i < nr; i++) |
| 2217 | { |
| 2218 | { |
| 2219 | ULONGEST val; |
| 2220 | ui_out_emit_tuple tuple_emitter (current_uiout, "mbox"); |
| 2221 | val = extract_unsigned_integer (buf + 4*i, 4, byte_order); |
| 2222 | current_uiout->field_fmt (field, "0x%s", phex (val, 4)); |
| 2223 | } |
| 2224 | |
| 2225 | current_uiout->text ("\n"); |
| 2226 | } |
| 2227 | } |
| 2228 | |
| 2229 | static void |
| 2230 | info_spu_mailbox_command (const char *args, int from_tty) |
| 2231 | { |
| 2232 | struct frame_info *frame = get_selected_frame (NULL); |
| 2233 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2234 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2235 | char annex[32]; |
| 2236 | gdb_byte buf[1024]; |
| 2237 | LONGEST len; |
| 2238 | int id; |
| 2239 | |
| 2240 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu) |
| 2241 | error (_("\"info spu\" is only supported on the SPU architecture.")); |
| 2242 | |
| 2243 | id = get_frame_register_unsigned (frame, SPU_ID_REGNUM); |
| 2244 | |
| 2245 | ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoMailbox"); |
| 2246 | |
| 2247 | xsnprintf (annex, sizeof annex, "%d/mbox_info", id); |
| 2248 | len = target_read (current_top_target (), TARGET_OBJECT_SPU, annex, |
| 2249 | buf, 0, sizeof buf); |
| 2250 | if (len < 0) |
| 2251 | error (_("Could not read mbox_info.")); |
| 2252 | |
| 2253 | info_spu_mailbox_list (buf, len / 4, byte_order, |
| 2254 | "mbox", "SPU Outbound Mailbox"); |
| 2255 | |
| 2256 | xsnprintf (annex, sizeof annex, "%d/ibox_info", id); |
| 2257 | len = target_read (current_top_target (), TARGET_OBJECT_SPU, annex, |
| 2258 | buf, 0, sizeof buf); |
| 2259 | if (len < 0) |
| 2260 | error (_("Could not read ibox_info.")); |
| 2261 | |
| 2262 | info_spu_mailbox_list (buf, len / 4, byte_order, |
| 2263 | "ibox", "SPU Outbound Interrupt Mailbox"); |
| 2264 | |
| 2265 | xsnprintf (annex, sizeof annex, "%d/wbox_info", id); |
| 2266 | len = target_read (current_top_target (), TARGET_OBJECT_SPU, annex, |
| 2267 | buf, 0, sizeof buf); |
| 2268 | if (len < 0) |
| 2269 | error (_("Could not read wbox_info.")); |
| 2270 | |
| 2271 | info_spu_mailbox_list (buf, len / 4, byte_order, |
| 2272 | "wbox", "SPU Inbound Mailbox"); |
| 2273 | } |
| 2274 | |
| 2275 | static ULONGEST |
| 2276 | spu_mfc_get_bitfield (ULONGEST word, int first, int last) |
| 2277 | { |
| 2278 | ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1)); |
| 2279 | return (word >> (63 - last)) & mask; |
| 2280 | } |
| 2281 | |
| 2282 | static void |
| 2283 | info_spu_dma_cmdlist (gdb_byte *buf, int nr, enum bfd_endian byte_order) |
| 2284 | { |
| 2285 | static const char *spu_mfc_opcode[256] = |
| 2286 | { |
| 2287 | /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2288 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2289 | /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2290 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2291 | /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL, |
| 2292 | "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL, |
| 2293 | /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL, |
| 2294 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2295 | /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL, |
| 2296 | "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL, |
| 2297 | /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2298 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2299 | /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2300 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2301 | /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2302 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2303 | /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL, |
| 2304 | NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf", |
| 2305 | /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2306 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2307 | /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL, |
| 2308 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2309 | /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL, |
| 2310 | "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2311 | /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2312 | "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL, |
| 2313 | /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2314 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2315 | /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2316 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2317 | /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2318 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 2319 | }; |
| 2320 | |
| 2321 | int *seq = XALLOCAVEC (int, nr); |
| 2322 | int done = 0; |
| 2323 | int i, j; |
| 2324 | |
| 2325 | |
| 2326 | /* Determine sequence in which to display (valid) entries. */ |
| 2327 | for (i = 0; i < nr; i++) |
| 2328 | { |
| 2329 | /* Search for the first valid entry all of whose |
| 2330 | dependencies are met. */ |
| 2331 | for (j = 0; j < nr; j++) |
| 2332 | { |
| 2333 | ULONGEST mfc_cq_dw3; |
| 2334 | ULONGEST dependencies; |
| 2335 | |
| 2336 | if (done & (1 << (nr - 1 - j))) |
| 2337 | continue; |
| 2338 | |
| 2339 | mfc_cq_dw3 |
| 2340 | = extract_unsigned_integer (buf + 32*j + 24,8, byte_order); |
| 2341 | if (!spu_mfc_get_bitfield (mfc_cq_dw3, 16, 16)) |
| 2342 | continue; |
| 2343 | |
| 2344 | dependencies = spu_mfc_get_bitfield (mfc_cq_dw3, 0, nr - 1); |
| 2345 | if ((dependencies & done) != dependencies) |
| 2346 | continue; |
| 2347 | |
| 2348 | seq[i] = j; |
| 2349 | done |= 1 << (nr - 1 - j); |
| 2350 | break; |
| 2351 | } |
| 2352 | |
| 2353 | if (j == nr) |
| 2354 | break; |
| 2355 | } |
| 2356 | |
| 2357 | nr = i; |
| 2358 | |
| 2359 | |
| 2360 | ui_out_emit_table table_emitter (current_uiout, 10, nr, "dma_cmd"); |
| 2361 | |
| 2362 | current_uiout->table_header (7, ui_left, "opcode", "Opcode"); |
| 2363 | current_uiout->table_header (3, ui_left, "tag", "Tag"); |
| 2364 | current_uiout->table_header (3, ui_left, "tid", "TId"); |
| 2365 | current_uiout->table_header (3, ui_left, "rid", "RId"); |
| 2366 | current_uiout->table_header (18, ui_left, "ea", "EA"); |
| 2367 | current_uiout->table_header (7, ui_left, "lsa", "LSA"); |
| 2368 | current_uiout->table_header (7, ui_left, "size", "Size"); |
| 2369 | current_uiout->table_header (7, ui_left, "lstaddr", "LstAddr"); |
| 2370 | current_uiout->table_header (7, ui_left, "lstsize", "LstSize"); |
| 2371 | current_uiout->table_header (1, ui_left, "error_p", "E"); |
| 2372 | |
| 2373 | current_uiout->table_body (); |
| 2374 | |
| 2375 | for (i = 0; i < nr; i++) |
| 2376 | { |
| 2377 | ULONGEST mfc_cq_dw0; |
| 2378 | ULONGEST mfc_cq_dw1; |
| 2379 | ULONGEST mfc_cq_dw2; |
| 2380 | int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id; |
| 2381 | int list_lsa, list_size, mfc_lsa, mfc_size; |
| 2382 | ULONGEST mfc_ea; |
| 2383 | int list_valid_p, qw_valid_p, ea_valid_p, cmd_error_p; |
| 2384 | |
| 2385 | /* Decode contents of MFC Command Queue Context Save/Restore Registers. |
| 2386 | See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */ |
| 2387 | |
| 2388 | mfc_cq_dw0 |
| 2389 | = extract_unsigned_integer (buf + 32*seq[i], 8, byte_order); |
| 2390 | mfc_cq_dw1 |
| 2391 | = extract_unsigned_integer (buf + 32*seq[i] + 8, 8, byte_order); |
| 2392 | mfc_cq_dw2 |
| 2393 | = extract_unsigned_integer (buf + 32*seq[i] + 16, 8, byte_order); |
| 2394 | |
| 2395 | list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14); |
| 2396 | list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26); |
| 2397 | mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34); |
| 2398 | mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39); |
| 2399 | list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40); |
| 2400 | rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43); |
| 2401 | tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46); |
| 2402 | |
| 2403 | mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12 |
| 2404 | | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36); |
| 2405 | |
| 2406 | mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13); |
| 2407 | mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24); |
| 2408 | qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38); |
| 2409 | ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39); |
| 2410 | cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40); |
| 2411 | |
| 2412 | { |
| 2413 | ui_out_emit_tuple tuple_emitter (current_uiout, "cmd"); |
| 2414 | |
| 2415 | if (spu_mfc_opcode[mfc_cmd_opcode]) |
| 2416 | current_uiout->field_string ("opcode", spu_mfc_opcode[mfc_cmd_opcode]); |
| 2417 | else |
| 2418 | current_uiout->field_int ("opcode", mfc_cmd_opcode); |
| 2419 | |
| 2420 | current_uiout->field_int ("tag", mfc_cmd_tag); |
| 2421 | current_uiout->field_int ("tid", tclass_id); |
| 2422 | current_uiout->field_int ("rid", rclass_id); |
| 2423 | |
| 2424 | if (ea_valid_p) |
| 2425 | current_uiout->field_fmt ("ea", "0x%s", phex (mfc_ea, 8)); |
| 2426 | else |
| 2427 | current_uiout->field_skip ("ea"); |
| 2428 | |
| 2429 | current_uiout->field_fmt ("lsa", "0x%05x", mfc_lsa << 4); |
| 2430 | if (qw_valid_p) |
| 2431 | current_uiout->field_fmt ("size", "0x%05x", mfc_size << 4); |
| 2432 | else |
| 2433 | current_uiout->field_fmt ("size", "0x%05x", mfc_size); |
| 2434 | |
| 2435 | if (list_valid_p) |
| 2436 | { |
| 2437 | current_uiout->field_fmt ("lstaddr", "0x%05x", list_lsa << 3); |
| 2438 | current_uiout->field_fmt ("lstsize", "0x%05x", list_size << 3); |
| 2439 | } |
| 2440 | else |
| 2441 | { |
| 2442 | current_uiout->field_skip ("lstaddr"); |
| 2443 | current_uiout->field_skip ("lstsize"); |
| 2444 | } |
| 2445 | |
| 2446 | if (cmd_error_p) |
| 2447 | current_uiout->field_string ("error_p", "*"); |
| 2448 | else |
| 2449 | current_uiout->field_skip ("error_p"); |
| 2450 | } |
| 2451 | |
| 2452 | current_uiout->text ("\n"); |
| 2453 | } |
| 2454 | } |
| 2455 | |
| 2456 | static void |
| 2457 | info_spu_dma_command (const char *args, int from_tty) |
| 2458 | { |
| 2459 | struct frame_info *frame = get_selected_frame (NULL); |
| 2460 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2461 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2462 | ULONGEST dma_info_type; |
| 2463 | ULONGEST dma_info_mask; |
| 2464 | ULONGEST dma_info_status; |
| 2465 | ULONGEST dma_info_stall_and_notify; |
| 2466 | ULONGEST dma_info_atomic_command_status; |
| 2467 | char annex[32]; |
| 2468 | gdb_byte buf[1024]; |
| 2469 | LONGEST len; |
| 2470 | int id; |
| 2471 | |
| 2472 | if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu) |
| 2473 | error (_("\"info spu\" is only supported on the SPU architecture.")); |
| 2474 | |
| 2475 | id = get_frame_register_unsigned (frame, SPU_ID_REGNUM); |
| 2476 | |
| 2477 | xsnprintf (annex, sizeof annex, "%d/dma_info", id); |
| 2478 | len = target_read (current_top_target (), TARGET_OBJECT_SPU, annex, |
| 2479 | buf, 0, 40 + 16 * 32); |
| 2480 | if (len <= 0) |
| 2481 | error (_("Could not read dma_info.")); |
| 2482 | |
| 2483 | dma_info_type |
| 2484 | = extract_unsigned_integer (buf, 8, byte_order); |
| 2485 | dma_info_mask |
| 2486 | = extract_unsigned_integer (buf + 8, 8, byte_order); |
| 2487 | dma_info_status |
| 2488 | = extract_unsigned_integer (buf + 16, 8, byte_order); |
| 2489 | dma_info_stall_and_notify |
| 2490 | = extract_unsigned_integer (buf + 24, 8, byte_order); |
| 2491 | dma_info_atomic_command_status |
| 2492 | = extract_unsigned_integer (buf + 32, 8, byte_order); |
| 2493 | |
| 2494 | ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoDMA"); |
| 2495 | |
| 2496 | if (current_uiout->is_mi_like_p ()) |
| 2497 | { |
| 2498 | current_uiout->field_fmt ("dma_info_type", "0x%s", |
| 2499 | phex_nz (dma_info_type, 4)); |
| 2500 | current_uiout->field_fmt ("dma_info_mask", "0x%s", |
| 2501 | phex_nz (dma_info_mask, 4)); |
| 2502 | current_uiout->field_fmt ("dma_info_status", "0x%s", |
| 2503 | phex_nz (dma_info_status, 4)); |
| 2504 | current_uiout->field_fmt ("dma_info_stall_and_notify", "0x%s", |
| 2505 | phex_nz (dma_info_stall_and_notify, 4)); |
| 2506 | current_uiout->field_fmt ("dma_info_atomic_command_status", "0x%s", |
| 2507 | phex_nz (dma_info_atomic_command_status, 4)); |
| 2508 | } |
| 2509 | else |
| 2510 | { |
| 2511 | const char *query_msg = _("no query pending"); |
| 2512 | |
| 2513 | if (dma_info_type & 4) |
| 2514 | switch (dma_info_type & 3) |
| 2515 | { |
| 2516 | case 1: query_msg = _("'any' query pending"); break; |
| 2517 | case 2: query_msg = _("'all' query pending"); break; |
| 2518 | default: query_msg = _("undefined query type"); break; |
| 2519 | } |
| 2520 | |
| 2521 | printf_filtered (_("Tag-Group Status 0x%s\n"), |
| 2522 | phex (dma_info_status, 4)); |
| 2523 | printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"), |
| 2524 | phex (dma_info_mask, 4), query_msg); |
| 2525 | printf_filtered (_("Stall-and-Notify 0x%s\n"), |
| 2526 | phex (dma_info_stall_and_notify, 4)); |
| 2527 | printf_filtered (_("Atomic Cmd Status 0x%s\n"), |
| 2528 | phex (dma_info_atomic_command_status, 4)); |
| 2529 | printf_filtered ("\n"); |
| 2530 | } |
| 2531 | |
| 2532 | info_spu_dma_cmdlist (buf + 40, 16, byte_order); |
| 2533 | } |
| 2534 | |
| 2535 | static void |
| 2536 | info_spu_proxydma_command (const char *args, int from_tty) |
| 2537 | { |
| 2538 | struct frame_info *frame = get_selected_frame (NULL); |
| 2539 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2540 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2541 | ULONGEST dma_info_type; |
| 2542 | ULONGEST dma_info_mask; |
| 2543 | ULONGEST dma_info_status; |
| 2544 | char annex[32]; |
| 2545 | gdb_byte buf[1024]; |
| 2546 | LONGEST len; |
| 2547 | int id; |
| 2548 | |
| 2549 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu) |
| 2550 | error (_("\"info spu\" is only supported on the SPU architecture.")); |
| 2551 | |
| 2552 | id = get_frame_register_unsigned (frame, SPU_ID_REGNUM); |
| 2553 | |
| 2554 | xsnprintf (annex, sizeof annex, "%d/proxydma_info", id); |
| 2555 | len = target_read (current_top_target (), TARGET_OBJECT_SPU, annex, |
| 2556 | buf, 0, 24 + 8 * 32); |
| 2557 | if (len <= 0) |
| 2558 | error (_("Could not read proxydma_info.")); |
| 2559 | |
| 2560 | dma_info_type = extract_unsigned_integer (buf, 8, byte_order); |
| 2561 | dma_info_mask = extract_unsigned_integer (buf + 8, 8, byte_order); |
| 2562 | dma_info_status = extract_unsigned_integer (buf + 16, 8, byte_order); |
| 2563 | |
| 2564 | ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoProxyDMA"); |
| 2565 | |
| 2566 | if (current_uiout->is_mi_like_p ()) |
| 2567 | { |
| 2568 | current_uiout->field_fmt ("proxydma_info_type", "0x%s", |
| 2569 | phex_nz (dma_info_type, 4)); |
| 2570 | current_uiout->field_fmt ("proxydma_info_mask", "0x%s", |
| 2571 | phex_nz (dma_info_mask, 4)); |
| 2572 | current_uiout->field_fmt ("proxydma_info_status", "0x%s", |
| 2573 | phex_nz (dma_info_status, 4)); |
| 2574 | } |
| 2575 | else |
| 2576 | { |
| 2577 | const char *query_msg; |
| 2578 | |
| 2579 | switch (dma_info_type & 3) |
| 2580 | { |
| 2581 | case 0: query_msg = _("no query pending"); break; |
| 2582 | case 1: query_msg = _("'any' query pending"); break; |
| 2583 | case 2: query_msg = _("'all' query pending"); break; |
| 2584 | default: query_msg = _("undefined query type"); break; |
| 2585 | } |
| 2586 | |
| 2587 | printf_filtered (_("Tag-Group Status 0x%s\n"), |
| 2588 | phex (dma_info_status, 4)); |
| 2589 | printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"), |
| 2590 | phex (dma_info_mask, 4), query_msg); |
| 2591 | printf_filtered ("\n"); |
| 2592 | } |
| 2593 | |
| 2594 | info_spu_dma_cmdlist (buf + 24, 8, byte_order); |
| 2595 | } |
| 2596 | |
| 2597 | static void |
| 2598 | info_spu_command (const char *args, int from_tty) |
| 2599 | { |
| 2600 | printf_unfiltered (_("\"info spu\" must be followed by " |
| 2601 | "the name of an SPU facility.\n")); |
| 2602 | help_list (infospucmdlist, "info spu ", all_commands, gdb_stdout); |
| 2603 | } |
| 2604 | |
| 2605 | |
| 2606 | /* Root of all "set spu "/"show spu " commands. */ |
| 2607 | |
| 2608 | static void |
| 2609 | show_spu_command (const char *args, int from_tty) |
| 2610 | { |
| 2611 | help_list (showspucmdlist, "show spu ", all_commands, gdb_stdout); |
| 2612 | } |
| 2613 | |
| 2614 | static void |
| 2615 | set_spu_command (const char *args, int from_tty) |
| 2616 | { |
| 2617 | help_list (setspucmdlist, "set spu ", all_commands, gdb_stdout); |
| 2618 | } |
| 2619 | |
| 2620 | static void |
| 2621 | show_spu_stop_on_load (struct ui_file *file, int from_tty, |
| 2622 | struct cmd_list_element *c, const char *value) |
| 2623 | { |
| 2624 | fprintf_filtered (file, _("Stopping for new SPE threads is %s.\n"), |
| 2625 | value); |
| 2626 | } |
| 2627 | |
| 2628 | static void |
| 2629 | show_spu_auto_flush_cache (struct ui_file *file, int from_tty, |
| 2630 | struct cmd_list_element *c, const char *value) |
| 2631 | { |
| 2632 | fprintf_filtered (file, _("Automatic software-cache flush is %s.\n"), |
| 2633 | value); |
| 2634 | } |
| 2635 | |
| 2636 | |
| 2637 | /* Set up gdbarch struct. */ |
| 2638 | |
| 2639 | static struct gdbarch * |
| 2640 | spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 2641 | { |
| 2642 | struct gdbarch *gdbarch; |
| 2643 | struct gdbarch_tdep *tdep; |
| 2644 | int id = -1; |
| 2645 | |
| 2646 | /* Which spufs ID was requested as address space? */ |
| 2647 | if (info.id) |
| 2648 | id = *info.id; |
| 2649 | /* For objfile architectures of SPU solibs, decode the ID from the name. |
| 2650 | This assumes the filename convention employed by solib-spu.c. */ |
| 2651 | else if (info.abfd) |
| 2652 | { |
| 2653 | const char *name = strrchr (info.abfd->filename, '@'); |
| 2654 | if (name) |
| 2655 | sscanf (name, "@0x%*x <%d>", &id); |
| 2656 | } |
| 2657 | |
| 2658 | /* Find a candidate among extant architectures. */ |
| 2659 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
| 2660 | arches != NULL; |
| 2661 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) |
| 2662 | { |
| 2663 | tdep = gdbarch_tdep (arches->gdbarch); |
| 2664 | if (tdep && tdep->id == id) |
| 2665 | return arches->gdbarch; |
| 2666 | } |
| 2667 | |
| 2668 | /* None found, so create a new architecture. */ |
| 2669 | tdep = XCNEW (struct gdbarch_tdep); |
| 2670 | tdep->id = id; |
| 2671 | gdbarch = gdbarch_alloc (&info, tdep); |
| 2672 | |
| 2673 | /* Disassembler. */ |
| 2674 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_spu); |
| 2675 | |
| 2676 | /* Registers. */ |
| 2677 | set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS); |
| 2678 | set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS); |
| 2679 | set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM); |
| 2680 | set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM); |
| 2681 | set_gdbarch_read_pc (gdbarch, spu_read_pc); |
| 2682 | set_gdbarch_write_pc (gdbarch, spu_write_pc); |
| 2683 | set_gdbarch_register_name (gdbarch, spu_register_name); |
| 2684 | set_gdbarch_register_type (gdbarch, spu_register_type); |
| 2685 | set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read); |
| 2686 | set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write); |
| 2687 | set_gdbarch_value_from_register (gdbarch, spu_value_from_register); |
| 2688 | set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p); |
| 2689 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, spu_dwarf_reg_to_regnum); |
| 2690 | set_gdbarch_ax_pseudo_register_collect |
| 2691 | (gdbarch, spu_ax_pseudo_register_collect); |
| 2692 | set_gdbarch_ax_pseudo_register_push_stack |
| 2693 | (gdbarch, spu_ax_pseudo_register_push_stack); |
| 2694 | |
| 2695 | /* Data types. */ |
| 2696 | set_gdbarch_char_signed (gdbarch, 0); |
| 2697 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 2698 | set_gdbarch_addr_bit (gdbarch, 32); |
| 2699 | set_gdbarch_short_bit (gdbarch, 16); |
| 2700 | set_gdbarch_int_bit (gdbarch, 32); |
| 2701 | set_gdbarch_long_bit (gdbarch, 32); |
| 2702 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 2703 | set_gdbarch_float_bit (gdbarch, 32); |
| 2704 | set_gdbarch_double_bit (gdbarch, 64); |
| 2705 | set_gdbarch_long_double_bit (gdbarch, 64); |
| 2706 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
| 2707 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); |
| 2708 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); |
| 2709 | |
| 2710 | /* Address handling. */ |
| 2711 | set_gdbarch_address_to_pointer (gdbarch, spu_address_to_pointer); |
| 2712 | set_gdbarch_pointer_to_address (gdbarch, spu_pointer_to_address); |
| 2713 | set_gdbarch_integer_to_address (gdbarch, spu_integer_to_address); |
| 2714 | set_gdbarch_address_class_type_flags (gdbarch, spu_address_class_type_flags); |
| 2715 | set_gdbarch_address_class_type_flags_to_name |
| 2716 | (gdbarch, spu_address_class_type_flags_to_name); |
| 2717 | set_gdbarch_address_class_name_to_type_flags |
| 2718 | (gdbarch, spu_address_class_name_to_type_flags); |
| 2719 | |
| 2720 | /* We need to support more than "addr_bit" significant address bits |
| 2721 | in order to support SPUADDR_ADDR encoded values. */ |
| 2722 | set_gdbarch_significant_addr_bit (gdbarch, 64); |
| 2723 | |
| 2724 | /* Inferior function calls. */ |
| 2725 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
| 2726 | set_gdbarch_frame_align (gdbarch, spu_frame_align); |
| 2727 | set_gdbarch_frame_red_zone_size (gdbarch, 2000); |
| 2728 | set_gdbarch_push_dummy_code (gdbarch, spu_push_dummy_code); |
| 2729 | set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call); |
| 2730 | set_gdbarch_dummy_id (gdbarch, spu_dummy_id); |
| 2731 | set_gdbarch_return_value (gdbarch, spu_return_value); |
| 2732 | |
| 2733 | /* Frame handling. */ |
| 2734 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 2735 | dwarf2_append_unwinders (gdbarch); |
| 2736 | frame_unwind_append_unwinder (gdbarch, &spu_frame_unwind); |
| 2737 | frame_base_set_default (gdbarch, &spu_frame_base); |
| 2738 | set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc); |
| 2739 | set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp); |
| 2740 | set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer); |
| 2741 | set_gdbarch_frame_args_skip (gdbarch, 0); |
| 2742 | set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue); |
| 2743 | set_gdbarch_stack_frame_destroyed_p (gdbarch, spu_stack_frame_destroyed_p); |
| 2744 | |
| 2745 | /* Cell/B.E. cross-architecture unwinder support. */ |
| 2746 | frame_unwind_prepend_unwinder (gdbarch, &spu2ppu_unwind); |
| 2747 | |
| 2748 | /* Breakpoints. */ |
| 2749 | set_gdbarch_decr_pc_after_break (gdbarch, 4); |
| 2750 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, spu_breakpoint::kind_from_pc); |
| 2751 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, spu_breakpoint::bp_from_kind); |
| 2752 | set_gdbarch_memory_remove_breakpoint (gdbarch, spu_memory_remove_breakpoint); |
| 2753 | set_gdbarch_software_single_step (gdbarch, spu_software_single_step); |
| 2754 | set_gdbarch_get_longjmp_target (gdbarch, spu_get_longjmp_target); |
| 2755 | |
| 2756 | /* Overlays. */ |
| 2757 | set_gdbarch_overlay_update (gdbarch, spu_overlay_update); |
| 2758 | |
| 2759 | return gdbarch; |
| 2760 | } |
| 2761 | |
| 2762 | void |
| 2763 | _initialize_spu_tdep (void) |
| 2764 | { |
| 2765 | register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init); |
| 2766 | |
| 2767 | /* Add ourselves to objfile event chain. */ |
| 2768 | gdb::observers::new_objfile.attach (spu_overlay_new_objfile); |
| 2769 | spu_overlay_data = register_objfile_data (); |
| 2770 | |
| 2771 | /* Install spu stop-on-load handler. */ |
| 2772 | gdb::observers::new_objfile.attach (spu_catch_start); |
| 2773 | |
| 2774 | /* Add ourselves to normal_stop event chain. */ |
| 2775 | gdb::observers::normal_stop.attach (spu_attach_normal_stop); |
| 2776 | |
| 2777 | /* Add root prefix command for all "set spu"/"show spu" commands. */ |
| 2778 | add_prefix_cmd ("spu", no_class, set_spu_command, |
| 2779 | _("Various SPU specific commands."), |
| 2780 | &setspucmdlist, "set spu ", 0, &setlist); |
| 2781 | add_prefix_cmd ("spu", no_class, show_spu_command, |
| 2782 | _("Various SPU specific commands."), |
| 2783 | &showspucmdlist, "show spu ", 0, &showlist); |
| 2784 | |
| 2785 | /* Toggle whether or not to add a temporary breakpoint at the "main" |
| 2786 | function of new SPE contexts. */ |
| 2787 | add_setshow_boolean_cmd ("stop-on-load", class_support, |
| 2788 | &spu_stop_on_load_p, _("\ |
| 2789 | Set whether to stop for new SPE threads."), |
| 2790 | _("\ |
| 2791 | Show whether to stop for new SPE threads."), |
| 2792 | _("\ |
| 2793 | Use \"on\" to give control to the user when a new SPE thread\n\ |
| 2794 | enters its \"main\" function.\n\ |
| 2795 | Use \"off\" to disable stopping for new SPE threads."), |
| 2796 | NULL, |
| 2797 | show_spu_stop_on_load, |
| 2798 | &setspucmdlist, &showspucmdlist); |
| 2799 | |
| 2800 | /* Toggle whether or not to automatically flush the software-managed |
| 2801 | cache whenever SPE execution stops. */ |
| 2802 | add_setshow_boolean_cmd ("auto-flush-cache", class_support, |
| 2803 | &spu_auto_flush_cache_p, _("\ |
| 2804 | Set whether to automatically flush the software-managed cache."), |
| 2805 | _("\ |
| 2806 | Show whether to automatically flush the software-managed cache."), |
| 2807 | _("\ |
| 2808 | Use \"on\" to automatically flush the software-managed cache\n\ |
| 2809 | whenever SPE execution stops.\n\ |
| 2810 | Use \"off\" to never automatically flush the software-managed cache."), |
| 2811 | NULL, |
| 2812 | show_spu_auto_flush_cache, |
| 2813 | &setspucmdlist, &showspucmdlist); |
| 2814 | |
| 2815 | /* Add root prefix command for all "info spu" commands. */ |
| 2816 | add_prefix_cmd ("spu", class_info, info_spu_command, |
| 2817 | _("Various SPU specific commands."), |
| 2818 | &infospucmdlist, "info spu ", 0, &infolist); |
| 2819 | |
| 2820 | /* Add various "info spu" commands. */ |
| 2821 | add_cmd ("event", class_info, info_spu_event_command, |
| 2822 | _("Display SPU event facility status.\n"), |
| 2823 | &infospucmdlist); |
| 2824 | add_cmd ("signal", class_info, info_spu_signal_command, |
| 2825 | _("Display SPU signal notification facility status.\n"), |
| 2826 | &infospucmdlist); |
| 2827 | add_cmd ("mailbox", class_info, info_spu_mailbox_command, |
| 2828 | _("Display SPU mailbox facility status.\n"), |
| 2829 | &infospucmdlist); |
| 2830 | add_cmd ("dma", class_info, info_spu_dma_command, |
| 2831 | _("Display MFC DMA status.\n"), |
| 2832 | &infospucmdlist); |
| 2833 | add_cmd ("proxydma", class_info, info_spu_proxydma_command, |
| 2834 | _("Display MFC Proxy-DMA status.\n"), |
| 2835 | &infospucmdlist); |
| 2836 | } |