| 1 | /* SPU target-dependent code for GDB, the GNU debugger. |
| 2 | Copyright (C) 2006, 2007 Free Software Foundation, Inc. |
| 3 | |
| 4 | Contributed by Ulrich Weigand <uweigand@de.ibm.com>. |
| 5 | Based on a port by Sid Manning <sid@us.ibm.com>. |
| 6 | |
| 7 | This file is part of GDB. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 2 of the License, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program; if not, write to the Free Software |
| 21 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
| 22 | Boston, MA 02110-1301, USA. */ |
| 23 | |
| 24 | #include "defs.h" |
| 25 | #include "arch-utils.h" |
| 26 | #include "gdbtypes.h" |
| 27 | #include "gdbcmd.h" |
| 28 | #include "gdbcore.h" |
| 29 | #include "gdb_string.h" |
| 30 | #include "gdb_assert.h" |
| 31 | #include "frame.h" |
| 32 | #include "frame-unwind.h" |
| 33 | #include "frame-base.h" |
| 34 | #include "trad-frame.h" |
| 35 | #include "symtab.h" |
| 36 | #include "symfile.h" |
| 37 | #include "value.h" |
| 38 | #include "inferior.h" |
| 39 | #include "dis-asm.h" |
| 40 | #include "objfiles.h" |
| 41 | #include "language.h" |
| 42 | #include "regcache.h" |
| 43 | #include "reggroups.h" |
| 44 | #include "floatformat.h" |
| 45 | #include "observer.h" |
| 46 | |
| 47 | #include "spu-tdep.h" |
| 48 | |
| 49 | |
| 50 | /* The tdep structure. */ |
| 51 | struct gdbarch_tdep |
| 52 | { |
| 53 | /* SPU-specific vector type. */ |
| 54 | struct type *spu_builtin_type_vec128; |
| 55 | }; |
| 56 | |
| 57 | |
| 58 | /* SPU-specific vector type. */ |
| 59 | static struct type * |
| 60 | spu_builtin_type_vec128 (struct gdbarch *gdbarch) |
| 61 | { |
| 62 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 63 | |
| 64 | if (!tdep->spu_builtin_type_vec128) |
| 65 | { |
| 66 | struct type *t; |
| 67 | |
| 68 | t = init_composite_type ("__spu_builtin_type_vec128", TYPE_CODE_UNION); |
| 69 | append_composite_type_field (t, "uint128", builtin_type_int128); |
| 70 | append_composite_type_field (t, "v2_int64", |
| 71 | init_vector_type (builtin_type_int64, 2)); |
| 72 | append_composite_type_field (t, "v4_int32", |
| 73 | init_vector_type (builtin_type_int32, 4)); |
| 74 | append_composite_type_field (t, "v8_int16", |
| 75 | init_vector_type (builtin_type_int16, 8)); |
| 76 | append_composite_type_field (t, "v16_int8", |
| 77 | init_vector_type (builtin_type_int8, 16)); |
| 78 | append_composite_type_field (t, "v2_double", |
| 79 | init_vector_type (builtin_type_double, 2)); |
| 80 | append_composite_type_field (t, "v4_float", |
| 81 | init_vector_type (builtin_type_float, 4)); |
| 82 | |
| 83 | TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR; |
| 84 | TYPE_NAME (t) = "spu_builtin_type_vec128"; |
| 85 | |
| 86 | tdep->spu_builtin_type_vec128 = t; |
| 87 | } |
| 88 | |
| 89 | return tdep->spu_builtin_type_vec128; |
| 90 | } |
| 91 | |
| 92 | |
| 93 | /* The list of available "info spu " commands. */ |
| 94 | static struct cmd_list_element *infospucmdlist = NULL; |
| 95 | |
| 96 | /* Registers. */ |
| 97 | |
| 98 | static const char * |
| 99 | spu_register_name (int reg_nr) |
| 100 | { |
| 101 | static char *register_names[] = |
| 102 | { |
| 103 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 104 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 105 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
| 106 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
| 107 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", |
| 108 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", |
| 109 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", |
| 110 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", |
| 111 | "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71", |
| 112 | "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79", |
| 113 | "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", |
| 114 | "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95", |
| 115 | "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103", |
| 116 | "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111", |
| 117 | "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119", |
| 118 | "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127", |
| 119 | "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status" |
| 120 | }; |
| 121 | |
| 122 | if (reg_nr < 0) |
| 123 | return NULL; |
| 124 | if (reg_nr >= sizeof register_names / sizeof *register_names) |
| 125 | return NULL; |
| 126 | |
| 127 | return register_names[reg_nr]; |
| 128 | } |
| 129 | |
| 130 | static struct type * |
| 131 | spu_register_type (struct gdbarch *gdbarch, int reg_nr) |
| 132 | { |
| 133 | if (reg_nr < SPU_NUM_GPRS) |
| 134 | return spu_builtin_type_vec128 (gdbarch); |
| 135 | |
| 136 | switch (reg_nr) |
| 137 | { |
| 138 | case SPU_ID_REGNUM: |
| 139 | return builtin_type_uint32; |
| 140 | |
| 141 | case SPU_PC_REGNUM: |
| 142 | return builtin_type_void_func_ptr; |
| 143 | |
| 144 | case SPU_SP_REGNUM: |
| 145 | return builtin_type_void_data_ptr; |
| 146 | |
| 147 | case SPU_FPSCR_REGNUM: |
| 148 | return builtin_type_uint128; |
| 149 | |
| 150 | case SPU_SRR0_REGNUM: |
| 151 | return builtin_type_uint32; |
| 152 | |
| 153 | case SPU_LSLR_REGNUM: |
| 154 | return builtin_type_uint32; |
| 155 | |
| 156 | case SPU_DECR_REGNUM: |
| 157 | return builtin_type_uint32; |
| 158 | |
| 159 | case SPU_DECR_STATUS_REGNUM: |
| 160 | return builtin_type_uint32; |
| 161 | |
| 162 | default: |
| 163 | internal_error (__FILE__, __LINE__, "invalid regnum"); |
| 164 | } |
| 165 | } |
| 166 | |
| 167 | /* Pseudo registers for preferred slots - stack pointer. */ |
| 168 | |
| 169 | static void |
| 170 | spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname, |
| 171 | gdb_byte *buf) |
| 172 | { |
| 173 | gdb_byte reg[32]; |
| 174 | char annex[32]; |
| 175 | ULONGEST id; |
| 176 | |
| 177 | regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id); |
| 178 | xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname); |
| 179 | memset (reg, 0, sizeof reg); |
| 180 | target_read (¤t_target, TARGET_OBJECT_SPU, annex, |
| 181 | reg, 0, sizeof reg); |
| 182 | |
| 183 | store_unsigned_integer (buf, 4, strtoulst (reg, NULL, 16)); |
| 184 | } |
| 185 | |
| 186 | static void |
| 187 | spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
| 188 | int regnum, gdb_byte *buf) |
| 189 | { |
| 190 | gdb_byte reg[16]; |
| 191 | char annex[32]; |
| 192 | ULONGEST id; |
| 193 | |
| 194 | switch (regnum) |
| 195 | { |
| 196 | case SPU_SP_REGNUM: |
| 197 | regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg); |
| 198 | memcpy (buf, reg, 4); |
| 199 | break; |
| 200 | |
| 201 | case SPU_FPSCR_REGNUM: |
| 202 | regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id); |
| 203 | xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id); |
| 204 | target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 16); |
| 205 | break; |
| 206 | |
| 207 | case SPU_SRR0_REGNUM: |
| 208 | spu_pseudo_register_read_spu (regcache, "srr0", buf); |
| 209 | break; |
| 210 | |
| 211 | case SPU_LSLR_REGNUM: |
| 212 | spu_pseudo_register_read_spu (regcache, "lslr", buf); |
| 213 | break; |
| 214 | |
| 215 | case SPU_DECR_REGNUM: |
| 216 | spu_pseudo_register_read_spu (regcache, "decr", buf); |
| 217 | break; |
| 218 | |
| 219 | case SPU_DECR_STATUS_REGNUM: |
| 220 | spu_pseudo_register_read_spu (regcache, "decr_status", buf); |
| 221 | break; |
| 222 | |
| 223 | default: |
| 224 | internal_error (__FILE__, __LINE__, _("invalid regnum")); |
| 225 | } |
| 226 | } |
| 227 | |
| 228 | static void |
| 229 | spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname, |
| 230 | const gdb_byte *buf) |
| 231 | { |
| 232 | gdb_byte reg[32]; |
| 233 | char annex[32]; |
| 234 | ULONGEST id; |
| 235 | |
| 236 | regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id); |
| 237 | xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname); |
| 238 | xsnprintf (reg, sizeof reg, "0x%s", |
| 239 | phex_nz (extract_unsigned_integer (buf, 4), 4)); |
| 240 | target_write (¤t_target, TARGET_OBJECT_SPU, annex, |
| 241 | reg, 0, strlen (reg)); |
| 242 | } |
| 243 | |
| 244 | static void |
| 245 | spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
| 246 | int regnum, const gdb_byte *buf) |
| 247 | { |
| 248 | gdb_byte reg[16]; |
| 249 | char annex[32]; |
| 250 | ULONGEST id; |
| 251 | |
| 252 | switch (regnum) |
| 253 | { |
| 254 | case SPU_SP_REGNUM: |
| 255 | regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg); |
| 256 | memcpy (reg, buf, 4); |
| 257 | regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg); |
| 258 | break; |
| 259 | |
| 260 | case SPU_FPSCR_REGNUM: |
| 261 | regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id); |
| 262 | xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id); |
| 263 | target_write (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 16); |
| 264 | break; |
| 265 | |
| 266 | case SPU_SRR0_REGNUM: |
| 267 | spu_pseudo_register_write_spu (regcache, "srr0", buf); |
| 268 | break; |
| 269 | |
| 270 | case SPU_LSLR_REGNUM: |
| 271 | spu_pseudo_register_write_spu (regcache, "lslr", buf); |
| 272 | break; |
| 273 | |
| 274 | case SPU_DECR_REGNUM: |
| 275 | spu_pseudo_register_write_spu (regcache, "decr", buf); |
| 276 | break; |
| 277 | |
| 278 | case SPU_DECR_STATUS_REGNUM: |
| 279 | spu_pseudo_register_write_spu (regcache, "decr_status", buf); |
| 280 | break; |
| 281 | |
| 282 | default: |
| 283 | internal_error (__FILE__, __LINE__, _("invalid regnum")); |
| 284 | } |
| 285 | } |
| 286 | |
| 287 | /* Value conversion -- access scalar values at the preferred slot. */ |
| 288 | |
| 289 | static struct value * |
| 290 | spu_value_from_register (struct type *type, int regnum, |
| 291 | struct frame_info *frame) |
| 292 | { |
| 293 | struct value *value = default_value_from_register (type, regnum, frame); |
| 294 | int len = TYPE_LENGTH (type); |
| 295 | |
| 296 | if (regnum < SPU_NUM_GPRS && len < 16) |
| 297 | { |
| 298 | int preferred_slot = len < 4 ? 4 - len : 0; |
| 299 | set_value_offset (value, preferred_slot); |
| 300 | } |
| 301 | |
| 302 | return value; |
| 303 | } |
| 304 | |
| 305 | /* Register groups. */ |
| 306 | |
| 307 | static int |
| 308 | spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
| 309 | struct reggroup *group) |
| 310 | { |
| 311 | /* Registers displayed via 'info regs'. */ |
| 312 | if (group == general_reggroup) |
| 313 | return 1; |
| 314 | |
| 315 | /* Registers displayed via 'info float'. */ |
| 316 | if (group == float_reggroup) |
| 317 | return 0; |
| 318 | |
| 319 | /* Registers that need to be saved/restored in order to |
| 320 | push or pop frames. */ |
| 321 | if (group == save_reggroup || group == restore_reggroup) |
| 322 | return 1; |
| 323 | |
| 324 | return default_register_reggroup_p (gdbarch, regnum, group); |
| 325 | } |
| 326 | |
| 327 | |
| 328 | /* Decoding SPU instructions. */ |
| 329 | |
| 330 | enum |
| 331 | { |
| 332 | op_lqd = 0x34, |
| 333 | op_lqx = 0x3c4, |
| 334 | op_lqa = 0x61, |
| 335 | op_lqr = 0x67, |
| 336 | op_stqd = 0x24, |
| 337 | op_stqx = 0x144, |
| 338 | op_stqa = 0x41, |
| 339 | op_stqr = 0x47, |
| 340 | |
| 341 | op_il = 0x081, |
| 342 | op_ila = 0x21, |
| 343 | op_a = 0x0c0, |
| 344 | op_ai = 0x1c, |
| 345 | |
| 346 | op_selb = 0x4, |
| 347 | |
| 348 | op_br = 0x64, |
| 349 | op_bra = 0x60, |
| 350 | op_brsl = 0x66, |
| 351 | op_brasl = 0x62, |
| 352 | op_brnz = 0x42, |
| 353 | op_brz = 0x40, |
| 354 | op_brhnz = 0x46, |
| 355 | op_brhz = 0x44, |
| 356 | op_bi = 0x1a8, |
| 357 | op_bisl = 0x1a9, |
| 358 | op_biz = 0x128, |
| 359 | op_binz = 0x129, |
| 360 | op_bihz = 0x12a, |
| 361 | op_bihnz = 0x12b, |
| 362 | }; |
| 363 | |
| 364 | static int |
| 365 | is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb) |
| 366 | { |
| 367 | if ((insn >> 21) == op) |
| 368 | { |
| 369 | *rt = insn & 127; |
| 370 | *ra = (insn >> 7) & 127; |
| 371 | *rb = (insn >> 14) & 127; |
| 372 | return 1; |
| 373 | } |
| 374 | |
| 375 | return 0; |
| 376 | } |
| 377 | |
| 378 | static int |
| 379 | is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc) |
| 380 | { |
| 381 | if ((insn >> 28) == op) |
| 382 | { |
| 383 | *rt = (insn >> 21) & 127; |
| 384 | *ra = (insn >> 7) & 127; |
| 385 | *rb = (insn >> 14) & 127; |
| 386 | *rc = insn & 127; |
| 387 | return 1; |
| 388 | } |
| 389 | |
| 390 | return 0; |
| 391 | } |
| 392 | |
| 393 | static int |
| 394 | is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7) |
| 395 | { |
| 396 | if ((insn >> 21) == op) |
| 397 | { |
| 398 | *rt = insn & 127; |
| 399 | *ra = (insn >> 7) & 127; |
| 400 | *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40; |
| 401 | return 1; |
| 402 | } |
| 403 | |
| 404 | return 0; |
| 405 | } |
| 406 | |
| 407 | static int |
| 408 | is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10) |
| 409 | { |
| 410 | if ((insn >> 24) == op) |
| 411 | { |
| 412 | *rt = insn & 127; |
| 413 | *ra = (insn >> 7) & 127; |
| 414 | *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200; |
| 415 | return 1; |
| 416 | } |
| 417 | |
| 418 | return 0; |
| 419 | } |
| 420 | |
| 421 | static int |
| 422 | is_ri16 (unsigned int insn, int op, int *rt, int *i16) |
| 423 | { |
| 424 | if ((insn >> 23) == op) |
| 425 | { |
| 426 | *rt = insn & 127; |
| 427 | *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000; |
| 428 | return 1; |
| 429 | } |
| 430 | |
| 431 | return 0; |
| 432 | } |
| 433 | |
| 434 | static int |
| 435 | is_ri18 (unsigned int insn, int op, int *rt, int *i18) |
| 436 | { |
| 437 | if ((insn >> 25) == op) |
| 438 | { |
| 439 | *rt = insn & 127; |
| 440 | *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000; |
| 441 | return 1; |
| 442 | } |
| 443 | |
| 444 | return 0; |
| 445 | } |
| 446 | |
| 447 | static int |
| 448 | is_branch (unsigned int insn, int *offset, int *reg) |
| 449 | { |
| 450 | int rt, i7, i16; |
| 451 | |
| 452 | if (is_ri16 (insn, op_br, &rt, &i16) |
| 453 | || is_ri16 (insn, op_brsl, &rt, &i16) |
| 454 | || is_ri16 (insn, op_brnz, &rt, &i16) |
| 455 | || is_ri16 (insn, op_brz, &rt, &i16) |
| 456 | || is_ri16 (insn, op_brhnz, &rt, &i16) |
| 457 | || is_ri16 (insn, op_brhz, &rt, &i16)) |
| 458 | { |
| 459 | *reg = SPU_PC_REGNUM; |
| 460 | *offset = i16 << 2; |
| 461 | return 1; |
| 462 | } |
| 463 | |
| 464 | if (is_ri16 (insn, op_bra, &rt, &i16) |
| 465 | || is_ri16 (insn, op_brasl, &rt, &i16)) |
| 466 | { |
| 467 | *reg = -1; |
| 468 | *offset = i16 << 2; |
| 469 | return 1; |
| 470 | } |
| 471 | |
| 472 | if (is_ri7 (insn, op_bi, &rt, reg, &i7) |
| 473 | || is_ri7 (insn, op_bisl, &rt, reg, &i7) |
| 474 | || is_ri7 (insn, op_biz, &rt, reg, &i7) |
| 475 | || is_ri7 (insn, op_binz, &rt, reg, &i7) |
| 476 | || is_ri7 (insn, op_bihz, &rt, reg, &i7) |
| 477 | || is_ri7 (insn, op_bihnz, &rt, reg, &i7)) |
| 478 | { |
| 479 | *offset = 0; |
| 480 | return 1; |
| 481 | } |
| 482 | |
| 483 | return 0; |
| 484 | } |
| 485 | |
| 486 | |
| 487 | /* Prolog parsing. */ |
| 488 | |
| 489 | struct spu_prologue_data |
| 490 | { |
| 491 | /* Stack frame size. -1 if analysis was unsuccessful. */ |
| 492 | int size; |
| 493 | |
| 494 | /* How to find the CFA. The CFA is equal to SP at function entry. */ |
| 495 | int cfa_reg; |
| 496 | int cfa_offset; |
| 497 | |
| 498 | /* Offset relative to CFA where a register is saved. -1 if invalid. */ |
| 499 | int reg_offset[SPU_NUM_GPRS]; |
| 500 | }; |
| 501 | |
| 502 | static CORE_ADDR |
| 503 | spu_analyze_prologue (CORE_ADDR start_pc, CORE_ADDR end_pc, |
| 504 | struct spu_prologue_data *data) |
| 505 | { |
| 506 | int found_sp = 0; |
| 507 | int found_fp = 0; |
| 508 | int found_lr = 0; |
| 509 | int reg_immed[SPU_NUM_GPRS]; |
| 510 | gdb_byte buf[16]; |
| 511 | CORE_ADDR prolog_pc = start_pc; |
| 512 | CORE_ADDR pc; |
| 513 | int i; |
| 514 | |
| 515 | |
| 516 | /* Initialize DATA to default values. */ |
| 517 | data->size = -1; |
| 518 | |
| 519 | data->cfa_reg = SPU_RAW_SP_REGNUM; |
| 520 | data->cfa_offset = 0; |
| 521 | |
| 522 | for (i = 0; i < SPU_NUM_GPRS; i++) |
| 523 | data->reg_offset[i] = -1; |
| 524 | |
| 525 | /* Set up REG_IMMED array. This is non-zero for a register if we know its |
| 526 | preferred slot currently holds this immediate value. */ |
| 527 | for (i = 0; i < SPU_NUM_GPRS; i++) |
| 528 | reg_immed[i] = 0; |
| 529 | |
| 530 | /* Scan instructions until the first branch. |
| 531 | |
| 532 | The following instructions are important prolog components: |
| 533 | |
| 534 | - The first instruction to set up the stack pointer. |
| 535 | - The first instruction to set up the frame pointer. |
| 536 | - The first instruction to save the link register. |
| 537 | |
| 538 | We return the instruction after the latest of these three, |
| 539 | or the incoming PC if none is found. The first instruction |
| 540 | to set up the stack pointer also defines the frame size. |
| 541 | |
| 542 | Note that instructions saving incoming arguments to their stack |
| 543 | slots are not counted as important, because they are hard to |
| 544 | identify with certainty. This should not matter much, because |
| 545 | arguments are relevant only in code compiled with debug data, |
| 546 | and in such code the GDB core will advance until the first source |
| 547 | line anyway, using SAL data. |
| 548 | |
| 549 | For purposes of stack unwinding, we analyze the following types |
| 550 | of instructions in addition: |
| 551 | |
| 552 | - Any instruction adding to the current frame pointer. |
| 553 | - Any instruction loading an immediate constant into a register. |
| 554 | - Any instruction storing a register onto the stack. |
| 555 | |
| 556 | These are used to compute the CFA and REG_OFFSET output. */ |
| 557 | |
| 558 | for (pc = start_pc; pc < end_pc; pc += 4) |
| 559 | { |
| 560 | unsigned int insn; |
| 561 | int rt, ra, rb, rc, immed; |
| 562 | |
| 563 | if (target_read_memory (pc, buf, 4)) |
| 564 | break; |
| 565 | insn = extract_unsigned_integer (buf, 4); |
| 566 | |
| 567 | /* AI is the typical instruction to set up a stack frame. |
| 568 | It is also used to initialize the frame pointer. */ |
| 569 | if (is_ri10 (insn, op_ai, &rt, &ra, &immed)) |
| 570 | { |
| 571 | if (rt == data->cfa_reg && ra == data->cfa_reg) |
| 572 | data->cfa_offset -= immed; |
| 573 | |
| 574 | if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM |
| 575 | && !found_sp) |
| 576 | { |
| 577 | found_sp = 1; |
| 578 | prolog_pc = pc + 4; |
| 579 | |
| 580 | data->size = -immed; |
| 581 | } |
| 582 | else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM |
| 583 | && !found_fp) |
| 584 | { |
| 585 | found_fp = 1; |
| 586 | prolog_pc = pc + 4; |
| 587 | |
| 588 | data->cfa_reg = SPU_FP_REGNUM; |
| 589 | data->cfa_offset -= immed; |
| 590 | } |
| 591 | } |
| 592 | |
| 593 | /* A is used to set up stack frames of size >= 512 bytes. |
| 594 | If we have tracked the contents of the addend register, |
| 595 | we can handle this as well. */ |
| 596 | else if (is_rr (insn, op_a, &rt, &ra, &rb)) |
| 597 | { |
| 598 | if (rt == data->cfa_reg && ra == data->cfa_reg) |
| 599 | { |
| 600 | if (reg_immed[rb] != 0) |
| 601 | data->cfa_offset -= reg_immed[rb]; |
| 602 | else |
| 603 | data->cfa_reg = -1; /* We don't know the CFA any more. */ |
| 604 | } |
| 605 | |
| 606 | if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM |
| 607 | && !found_sp) |
| 608 | { |
| 609 | found_sp = 1; |
| 610 | prolog_pc = pc + 4; |
| 611 | |
| 612 | if (reg_immed[rb] != 0) |
| 613 | data->size = -reg_immed[rb]; |
| 614 | } |
| 615 | } |
| 616 | |
| 617 | /* We need to track IL and ILA used to load immediate constants |
| 618 | in case they are later used as input to an A instruction. */ |
| 619 | else if (is_ri16 (insn, op_il, &rt, &immed)) |
| 620 | { |
| 621 | reg_immed[rt] = immed; |
| 622 | |
| 623 | if (rt == SPU_RAW_SP_REGNUM && !found_sp) |
| 624 | found_sp = 1; |
| 625 | } |
| 626 | |
| 627 | else if (is_ri18 (insn, op_ila, &rt, &immed)) |
| 628 | { |
| 629 | reg_immed[rt] = immed & 0x3ffff; |
| 630 | |
| 631 | if (rt == SPU_RAW_SP_REGNUM && !found_sp) |
| 632 | found_sp = 1; |
| 633 | } |
| 634 | |
| 635 | /* STQD is used to save registers to the stack. */ |
| 636 | else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed)) |
| 637 | { |
| 638 | if (ra == data->cfa_reg) |
| 639 | data->reg_offset[rt] = data->cfa_offset - (immed << 4); |
| 640 | |
| 641 | if (ra == data->cfa_reg && rt == SPU_LR_REGNUM |
| 642 | && !found_lr) |
| 643 | { |
| 644 | found_lr = 1; |
| 645 | prolog_pc = pc + 4; |
| 646 | } |
| 647 | } |
| 648 | |
| 649 | /* _start uses SELB to set up the stack pointer. */ |
| 650 | else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc)) |
| 651 | { |
| 652 | if (rt == SPU_RAW_SP_REGNUM && !found_sp) |
| 653 | found_sp = 1; |
| 654 | } |
| 655 | |
| 656 | /* We terminate if we find a branch. */ |
| 657 | else if (is_branch (insn, &immed, &ra)) |
| 658 | break; |
| 659 | } |
| 660 | |
| 661 | |
| 662 | /* If we successfully parsed until here, and didn't find any instruction |
| 663 | modifying SP, we assume we have a frameless function. */ |
| 664 | if (!found_sp) |
| 665 | data->size = 0; |
| 666 | |
| 667 | /* Return cooked instead of raw SP. */ |
| 668 | if (data->cfa_reg == SPU_RAW_SP_REGNUM) |
| 669 | data->cfa_reg = SPU_SP_REGNUM; |
| 670 | |
| 671 | return prolog_pc; |
| 672 | } |
| 673 | |
| 674 | /* Return the first instruction after the prologue starting at PC. */ |
| 675 | static CORE_ADDR |
| 676 | spu_skip_prologue (CORE_ADDR pc) |
| 677 | { |
| 678 | struct spu_prologue_data data; |
| 679 | return spu_analyze_prologue (pc, (CORE_ADDR)-1, &data); |
| 680 | } |
| 681 | |
| 682 | /* Return the frame pointer in use at address PC. */ |
| 683 | static void |
| 684 | spu_virtual_frame_pointer (CORE_ADDR pc, int *reg, LONGEST *offset) |
| 685 | { |
| 686 | struct spu_prologue_data data; |
| 687 | spu_analyze_prologue (pc, (CORE_ADDR)-1, &data); |
| 688 | |
| 689 | if (data.size != -1 && data.cfa_reg != -1) |
| 690 | { |
| 691 | /* The 'frame pointer' address is CFA minus frame size. */ |
| 692 | *reg = data.cfa_reg; |
| 693 | *offset = data.cfa_offset - data.size; |
| 694 | } |
| 695 | else |
| 696 | { |
| 697 | /* ??? We don't really know ... */ |
| 698 | *reg = SPU_SP_REGNUM; |
| 699 | *offset = 0; |
| 700 | } |
| 701 | } |
| 702 | |
| 703 | /* Return true if we are in the function's epilogue, i.e. after the |
| 704 | instruction that destroyed the function's stack frame. |
| 705 | |
| 706 | 1) scan forward from the point of execution: |
| 707 | a) If you find an instruction that modifies the stack pointer |
| 708 | or transfers control (except a return), execution is not in |
| 709 | an epilogue, return. |
| 710 | b) Stop scanning if you find a return instruction or reach the |
| 711 | end of the function or reach the hard limit for the size of |
| 712 | an epilogue. |
| 713 | 2) scan backward from the point of execution: |
| 714 | a) If you find an instruction that modifies the stack pointer, |
| 715 | execution *is* in an epilogue, return. |
| 716 | b) Stop scanning if you reach an instruction that transfers |
| 717 | control or the beginning of the function or reach the hard |
| 718 | limit for the size of an epilogue. */ |
| 719 | |
| 720 | static int |
| 721 | spu_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 722 | { |
| 723 | CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end; |
| 724 | bfd_byte buf[4]; |
| 725 | unsigned int insn; |
| 726 | int rt, ra, rb, rc, immed; |
| 727 | |
| 728 | /* Find the search limits based on function boundaries and hard limit. |
| 729 | We assume the epilogue can be up to 64 instructions long. */ |
| 730 | |
| 731 | const int spu_max_epilogue_size = 64 * 4; |
| 732 | |
| 733 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) |
| 734 | return 0; |
| 735 | |
| 736 | if (pc - func_start < spu_max_epilogue_size) |
| 737 | epilogue_start = func_start; |
| 738 | else |
| 739 | epilogue_start = pc - spu_max_epilogue_size; |
| 740 | |
| 741 | if (func_end - pc < spu_max_epilogue_size) |
| 742 | epilogue_end = func_end; |
| 743 | else |
| 744 | epilogue_end = pc + spu_max_epilogue_size; |
| 745 | |
| 746 | /* Scan forward until next 'bi $0'. */ |
| 747 | |
| 748 | for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4) |
| 749 | { |
| 750 | if (target_read_memory (scan_pc, buf, 4)) |
| 751 | return 0; |
| 752 | insn = extract_unsigned_integer (buf, 4); |
| 753 | |
| 754 | if (is_branch (insn, &immed, &ra)) |
| 755 | { |
| 756 | if (immed == 0 && ra == SPU_LR_REGNUM) |
| 757 | break; |
| 758 | |
| 759 | return 0; |
| 760 | } |
| 761 | |
| 762 | if (is_ri10 (insn, op_ai, &rt, &ra, &immed) |
| 763 | || is_rr (insn, op_a, &rt, &ra, &rb) |
| 764 | || is_ri10 (insn, op_lqd, &rt, &ra, &immed)) |
| 765 | { |
| 766 | if (rt == SPU_RAW_SP_REGNUM) |
| 767 | return 0; |
| 768 | } |
| 769 | } |
| 770 | |
| 771 | if (scan_pc >= epilogue_end) |
| 772 | return 0; |
| 773 | |
| 774 | /* Scan backward until adjustment to stack pointer (R1). */ |
| 775 | |
| 776 | for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4) |
| 777 | { |
| 778 | if (target_read_memory (scan_pc, buf, 4)) |
| 779 | return 0; |
| 780 | insn = extract_unsigned_integer (buf, 4); |
| 781 | |
| 782 | if (is_branch (insn, &immed, &ra)) |
| 783 | return 0; |
| 784 | |
| 785 | if (is_ri10 (insn, op_ai, &rt, &ra, &immed) |
| 786 | || is_rr (insn, op_a, &rt, &ra, &rb) |
| 787 | || is_ri10 (insn, op_lqd, &rt, &ra, &immed)) |
| 788 | { |
| 789 | if (rt == SPU_RAW_SP_REGNUM) |
| 790 | return 1; |
| 791 | } |
| 792 | } |
| 793 | |
| 794 | return 0; |
| 795 | } |
| 796 | |
| 797 | |
| 798 | /* Normal stack frames. */ |
| 799 | |
| 800 | struct spu_unwind_cache |
| 801 | { |
| 802 | CORE_ADDR func; |
| 803 | CORE_ADDR frame_base; |
| 804 | CORE_ADDR local_base; |
| 805 | |
| 806 | struct trad_frame_saved_reg *saved_regs; |
| 807 | }; |
| 808 | |
| 809 | static struct spu_unwind_cache * |
| 810 | spu_frame_unwind_cache (struct frame_info *next_frame, |
| 811 | void **this_prologue_cache) |
| 812 | { |
| 813 | struct spu_unwind_cache *info; |
| 814 | struct spu_prologue_data data; |
| 815 | gdb_byte buf[16]; |
| 816 | |
| 817 | if (*this_prologue_cache) |
| 818 | return *this_prologue_cache; |
| 819 | |
| 820 | info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache); |
| 821 | *this_prologue_cache = info; |
| 822 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
| 823 | info->frame_base = 0; |
| 824 | info->local_base = 0; |
| 825 | |
| 826 | /* Find the start of the current function, and analyze its prologue. */ |
| 827 | info->func = frame_func_unwind (next_frame, NORMAL_FRAME); |
| 828 | if (info->func == 0) |
| 829 | { |
| 830 | /* Fall back to using the current PC as frame ID. */ |
| 831 | info->func = frame_pc_unwind (next_frame); |
| 832 | data.size = -1; |
| 833 | } |
| 834 | else |
| 835 | spu_analyze_prologue (info->func, frame_pc_unwind (next_frame), &data); |
| 836 | |
| 837 | |
| 838 | /* If successful, use prologue analysis data. */ |
| 839 | if (data.size != -1 && data.cfa_reg != -1) |
| 840 | { |
| 841 | CORE_ADDR cfa; |
| 842 | int i; |
| 843 | |
| 844 | /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */ |
| 845 | frame_unwind_register (next_frame, data.cfa_reg, buf); |
| 846 | cfa = extract_unsigned_integer (buf, 4) + data.cfa_offset; |
| 847 | |
| 848 | /* Call-saved register slots. */ |
| 849 | for (i = 0; i < SPU_NUM_GPRS; i++) |
| 850 | if (i == SPU_LR_REGNUM |
| 851 | || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM)) |
| 852 | if (data.reg_offset[i] != -1) |
| 853 | info->saved_regs[i].addr = cfa - data.reg_offset[i]; |
| 854 | |
| 855 | /* Frame bases. */ |
| 856 | info->frame_base = cfa; |
| 857 | info->local_base = cfa - data.size; |
| 858 | } |
| 859 | |
| 860 | /* Otherwise, fall back to reading the backchain link. */ |
| 861 | else |
| 862 | { |
| 863 | CORE_ADDR reg, backchain; |
| 864 | |
| 865 | /* Get the backchain. */ |
| 866 | reg = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM); |
| 867 | backchain = read_memory_unsigned_integer (reg, 4); |
| 868 | |
| 869 | /* A zero backchain terminates the frame chain. Also, sanity |
| 870 | check against the local store size limit. */ |
| 871 | if (backchain != 0 && backchain < SPU_LS_SIZE) |
| 872 | { |
| 873 | /* Assume the link register is saved into its slot. */ |
| 874 | if (backchain + 16 < SPU_LS_SIZE) |
| 875 | info->saved_regs[SPU_LR_REGNUM].addr = backchain + 16; |
| 876 | |
| 877 | /* Frame bases. */ |
| 878 | info->frame_base = backchain; |
| 879 | info->local_base = reg; |
| 880 | } |
| 881 | } |
| 882 | |
| 883 | /* The previous SP is equal to the CFA. */ |
| 884 | trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM, info->frame_base); |
| 885 | |
| 886 | /* Read full contents of the unwound link register in order to |
| 887 | be able to determine the return address. */ |
| 888 | if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM)) |
| 889 | target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16); |
| 890 | else |
| 891 | frame_unwind_register (next_frame, SPU_LR_REGNUM, buf); |
| 892 | |
| 893 | /* Normally, the return address is contained in the slot 0 of the |
| 894 | link register, and slots 1-3 are zero. For an overlay return, |
| 895 | slot 0 contains the address of the overlay manager return stub, |
| 896 | slot 1 contains the partition number of the overlay section to |
| 897 | be returned to, and slot 2 contains the return address within |
| 898 | that section. Return the latter address in that case. */ |
| 899 | if (extract_unsigned_integer (buf + 8, 4) != 0) |
| 900 | trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM, |
| 901 | extract_unsigned_integer (buf + 8, 4)); |
| 902 | else |
| 903 | trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM, |
| 904 | extract_unsigned_integer (buf, 4)); |
| 905 | |
| 906 | return info; |
| 907 | } |
| 908 | |
| 909 | static void |
| 910 | spu_frame_this_id (struct frame_info *next_frame, |
| 911 | void **this_prologue_cache, struct frame_id *this_id) |
| 912 | { |
| 913 | struct spu_unwind_cache *info = |
| 914 | spu_frame_unwind_cache (next_frame, this_prologue_cache); |
| 915 | |
| 916 | if (info->frame_base == 0) |
| 917 | return; |
| 918 | |
| 919 | *this_id = frame_id_build (info->frame_base, info->func); |
| 920 | } |
| 921 | |
| 922 | static void |
| 923 | spu_frame_prev_register (struct frame_info *next_frame, |
| 924 | void **this_prologue_cache, |
| 925 | int regnum, int *optimizedp, |
| 926 | enum lval_type *lvalp, CORE_ADDR * addrp, |
| 927 | int *realnump, gdb_byte *bufferp) |
| 928 | { |
| 929 | struct spu_unwind_cache *info |
| 930 | = spu_frame_unwind_cache (next_frame, this_prologue_cache); |
| 931 | |
| 932 | /* Special-case the stack pointer. */ |
| 933 | if (regnum == SPU_RAW_SP_REGNUM) |
| 934 | regnum = SPU_SP_REGNUM; |
| 935 | |
| 936 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
| 937 | optimizedp, lvalp, addrp, realnump, bufferp); |
| 938 | } |
| 939 | |
| 940 | static const struct frame_unwind spu_frame_unwind = { |
| 941 | NORMAL_FRAME, |
| 942 | spu_frame_this_id, |
| 943 | spu_frame_prev_register |
| 944 | }; |
| 945 | |
| 946 | const struct frame_unwind * |
| 947 | spu_frame_sniffer (struct frame_info *next_frame) |
| 948 | { |
| 949 | return &spu_frame_unwind; |
| 950 | } |
| 951 | |
| 952 | static CORE_ADDR |
| 953 | spu_frame_base_address (struct frame_info *next_frame, void **this_cache) |
| 954 | { |
| 955 | struct spu_unwind_cache *info |
| 956 | = spu_frame_unwind_cache (next_frame, this_cache); |
| 957 | return info->local_base; |
| 958 | } |
| 959 | |
| 960 | static const struct frame_base spu_frame_base = { |
| 961 | &spu_frame_unwind, |
| 962 | spu_frame_base_address, |
| 963 | spu_frame_base_address, |
| 964 | spu_frame_base_address |
| 965 | }; |
| 966 | |
| 967 | static CORE_ADDR |
| 968 | spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 969 | { |
| 970 | CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM); |
| 971 | /* Mask off interrupt enable bit. */ |
| 972 | return pc & -4; |
| 973 | } |
| 974 | |
| 975 | static CORE_ADDR |
| 976 | spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 977 | { |
| 978 | return frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM); |
| 979 | } |
| 980 | |
| 981 | static CORE_ADDR |
| 982 | spu_read_pc (struct regcache *regcache) |
| 983 | { |
| 984 | ULONGEST pc; |
| 985 | regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &pc); |
| 986 | /* Mask off interrupt enable bit. */ |
| 987 | return pc & -4; |
| 988 | } |
| 989 | |
| 990 | static void |
| 991 | spu_write_pc (struct regcache *regcache, CORE_ADDR pc) |
| 992 | { |
| 993 | /* Keep interrupt enabled state unchanged. */ |
| 994 | ULONGEST old_pc; |
| 995 | regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc); |
| 996 | regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM, |
| 997 | (pc & -4) | (old_pc & 3)); |
| 998 | } |
| 999 | |
| 1000 | |
| 1001 | /* Function calling convention. */ |
| 1002 | |
| 1003 | static CORE_ADDR |
| 1004 | spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
| 1005 | { |
| 1006 | return sp & ~15; |
| 1007 | } |
| 1008 | |
| 1009 | static int |
| 1010 | spu_scalar_value_p (struct type *type) |
| 1011 | { |
| 1012 | switch (TYPE_CODE (type)) |
| 1013 | { |
| 1014 | case TYPE_CODE_INT: |
| 1015 | case TYPE_CODE_ENUM: |
| 1016 | case TYPE_CODE_RANGE: |
| 1017 | case TYPE_CODE_CHAR: |
| 1018 | case TYPE_CODE_BOOL: |
| 1019 | case TYPE_CODE_PTR: |
| 1020 | case TYPE_CODE_REF: |
| 1021 | return TYPE_LENGTH (type) <= 16; |
| 1022 | |
| 1023 | default: |
| 1024 | return 0; |
| 1025 | } |
| 1026 | } |
| 1027 | |
| 1028 | static void |
| 1029 | spu_value_to_regcache (struct regcache *regcache, int regnum, |
| 1030 | struct type *type, const gdb_byte *in) |
| 1031 | { |
| 1032 | int len = TYPE_LENGTH (type); |
| 1033 | |
| 1034 | if (spu_scalar_value_p (type)) |
| 1035 | { |
| 1036 | int preferred_slot = len < 4 ? 4 - len : 0; |
| 1037 | regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in); |
| 1038 | } |
| 1039 | else |
| 1040 | { |
| 1041 | while (len >= 16) |
| 1042 | { |
| 1043 | regcache_cooked_write (regcache, regnum++, in); |
| 1044 | in += 16; |
| 1045 | len -= 16; |
| 1046 | } |
| 1047 | |
| 1048 | if (len > 0) |
| 1049 | regcache_cooked_write_part (regcache, regnum, 0, len, in); |
| 1050 | } |
| 1051 | } |
| 1052 | |
| 1053 | static void |
| 1054 | spu_regcache_to_value (struct regcache *regcache, int regnum, |
| 1055 | struct type *type, gdb_byte *out) |
| 1056 | { |
| 1057 | int len = TYPE_LENGTH (type); |
| 1058 | |
| 1059 | if (spu_scalar_value_p (type)) |
| 1060 | { |
| 1061 | int preferred_slot = len < 4 ? 4 - len : 0; |
| 1062 | regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out); |
| 1063 | } |
| 1064 | else |
| 1065 | { |
| 1066 | while (len >= 16) |
| 1067 | { |
| 1068 | regcache_cooked_read (regcache, regnum++, out); |
| 1069 | out += 16; |
| 1070 | len -= 16; |
| 1071 | } |
| 1072 | |
| 1073 | if (len > 0) |
| 1074 | regcache_cooked_read_part (regcache, regnum, 0, len, out); |
| 1075 | } |
| 1076 | } |
| 1077 | |
| 1078 | static CORE_ADDR |
| 1079 | spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 1080 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 1081 | int nargs, struct value **args, CORE_ADDR sp, |
| 1082 | int struct_return, CORE_ADDR struct_addr) |
| 1083 | { |
| 1084 | int i; |
| 1085 | int regnum = SPU_ARG1_REGNUM; |
| 1086 | int stack_arg = -1; |
| 1087 | gdb_byte buf[16]; |
| 1088 | |
| 1089 | /* Set the return address. */ |
| 1090 | memset (buf, 0, sizeof buf); |
| 1091 | store_unsigned_integer (buf, 4, bp_addr); |
| 1092 | regcache_cooked_write (regcache, SPU_LR_REGNUM, buf); |
| 1093 | |
| 1094 | /* If STRUCT_RETURN is true, then the struct return address (in |
| 1095 | STRUCT_ADDR) will consume the first argument-passing register. |
| 1096 | Both adjust the register count and store that value. */ |
| 1097 | if (struct_return) |
| 1098 | { |
| 1099 | memset (buf, 0, sizeof buf); |
| 1100 | store_unsigned_integer (buf, 4, struct_addr); |
| 1101 | regcache_cooked_write (regcache, regnum++, buf); |
| 1102 | } |
| 1103 | |
| 1104 | /* Fill in argument registers. */ |
| 1105 | for (i = 0; i < nargs; i++) |
| 1106 | { |
| 1107 | struct value *arg = args[i]; |
| 1108 | struct type *type = check_typedef (value_type (arg)); |
| 1109 | const gdb_byte *contents = value_contents (arg); |
| 1110 | int len = TYPE_LENGTH (type); |
| 1111 | int n_regs = align_up (len, 16) / 16; |
| 1112 | |
| 1113 | /* If the argument doesn't wholly fit into registers, it and |
| 1114 | all subsequent arguments go to the stack. */ |
| 1115 | if (regnum + n_regs - 1 > SPU_ARGN_REGNUM) |
| 1116 | { |
| 1117 | stack_arg = i; |
| 1118 | break; |
| 1119 | } |
| 1120 | |
| 1121 | spu_value_to_regcache (regcache, regnum, type, contents); |
| 1122 | regnum += n_regs; |
| 1123 | } |
| 1124 | |
| 1125 | /* Overflow arguments go to the stack. */ |
| 1126 | if (stack_arg != -1) |
| 1127 | { |
| 1128 | CORE_ADDR ap; |
| 1129 | |
| 1130 | /* Allocate all required stack size. */ |
| 1131 | for (i = stack_arg; i < nargs; i++) |
| 1132 | { |
| 1133 | struct type *type = check_typedef (value_type (args[i])); |
| 1134 | sp -= align_up (TYPE_LENGTH (type), 16); |
| 1135 | } |
| 1136 | |
| 1137 | /* Fill in stack arguments. */ |
| 1138 | ap = sp; |
| 1139 | for (i = stack_arg; i < nargs; i++) |
| 1140 | { |
| 1141 | struct value *arg = args[i]; |
| 1142 | struct type *type = check_typedef (value_type (arg)); |
| 1143 | int len = TYPE_LENGTH (type); |
| 1144 | int preferred_slot; |
| 1145 | |
| 1146 | if (spu_scalar_value_p (type)) |
| 1147 | preferred_slot = len < 4 ? 4 - len : 0; |
| 1148 | else |
| 1149 | preferred_slot = 0; |
| 1150 | |
| 1151 | target_write_memory (ap + preferred_slot, value_contents (arg), len); |
| 1152 | ap += align_up (TYPE_LENGTH (type), 16); |
| 1153 | } |
| 1154 | } |
| 1155 | |
| 1156 | /* Allocate stack frame header. */ |
| 1157 | sp -= 32; |
| 1158 | |
| 1159 | /* Store stack back chain. */ |
| 1160 | regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf); |
| 1161 | target_write_memory (sp, buf, 16); |
| 1162 | |
| 1163 | /* Finally, update the SP register. */ |
| 1164 | regcache_cooked_write_unsigned (regcache, SPU_SP_REGNUM, sp); |
| 1165 | |
| 1166 | return sp; |
| 1167 | } |
| 1168 | |
| 1169 | static struct frame_id |
| 1170 | spu_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1171 | { |
| 1172 | return frame_id_build (spu_unwind_sp (gdbarch, next_frame), |
| 1173 | spu_unwind_pc (gdbarch, next_frame)); |
| 1174 | } |
| 1175 | |
| 1176 | /* Function return value access. */ |
| 1177 | |
| 1178 | static enum return_value_convention |
| 1179 | spu_return_value (struct gdbarch *gdbarch, struct type *type, |
| 1180 | struct regcache *regcache, gdb_byte *out, const gdb_byte *in) |
| 1181 | { |
| 1182 | enum return_value_convention rvc; |
| 1183 | |
| 1184 | if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16) |
| 1185 | rvc = RETURN_VALUE_REGISTER_CONVENTION; |
| 1186 | else |
| 1187 | rvc = RETURN_VALUE_STRUCT_CONVENTION; |
| 1188 | |
| 1189 | if (in) |
| 1190 | { |
| 1191 | switch (rvc) |
| 1192 | { |
| 1193 | case RETURN_VALUE_REGISTER_CONVENTION: |
| 1194 | spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in); |
| 1195 | break; |
| 1196 | |
| 1197 | case RETURN_VALUE_STRUCT_CONVENTION: |
| 1198 | error ("Cannot set function return value."); |
| 1199 | break; |
| 1200 | } |
| 1201 | } |
| 1202 | else if (out) |
| 1203 | { |
| 1204 | switch (rvc) |
| 1205 | { |
| 1206 | case RETURN_VALUE_REGISTER_CONVENTION: |
| 1207 | spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out); |
| 1208 | break; |
| 1209 | |
| 1210 | case RETURN_VALUE_STRUCT_CONVENTION: |
| 1211 | error ("Function return value unknown."); |
| 1212 | break; |
| 1213 | } |
| 1214 | } |
| 1215 | |
| 1216 | return rvc; |
| 1217 | } |
| 1218 | |
| 1219 | |
| 1220 | /* Breakpoints. */ |
| 1221 | |
| 1222 | static const gdb_byte * |
| 1223 | spu_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) |
| 1224 | { |
| 1225 | static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff }; |
| 1226 | |
| 1227 | *lenptr = sizeof breakpoint; |
| 1228 | return breakpoint; |
| 1229 | } |
| 1230 | |
| 1231 | |
| 1232 | /* Software single-stepping support. */ |
| 1233 | |
| 1234 | int |
| 1235 | spu_software_single_step (struct frame_info *frame) |
| 1236 | { |
| 1237 | CORE_ADDR pc, next_pc; |
| 1238 | unsigned int insn; |
| 1239 | int offset, reg; |
| 1240 | gdb_byte buf[4]; |
| 1241 | |
| 1242 | pc = get_frame_pc (frame); |
| 1243 | |
| 1244 | if (target_read_memory (pc, buf, 4)) |
| 1245 | return 1; |
| 1246 | insn = extract_unsigned_integer (buf, 4); |
| 1247 | |
| 1248 | /* Next sequential instruction is at PC + 4, except if the current |
| 1249 | instruction is a PPE-assisted call, in which case it is at PC + 8. |
| 1250 | Wrap around LS limit to be on the safe side. */ |
| 1251 | if ((insn & 0xffffff00) == 0x00002100) |
| 1252 | next_pc = (pc + 8) & (SPU_LS_SIZE - 1); |
| 1253 | else |
| 1254 | next_pc = (pc + 4) & (SPU_LS_SIZE - 1); |
| 1255 | |
| 1256 | insert_single_step_breakpoint (next_pc); |
| 1257 | |
| 1258 | if (is_branch (insn, &offset, ®)) |
| 1259 | { |
| 1260 | CORE_ADDR target = offset; |
| 1261 | |
| 1262 | if (reg == SPU_PC_REGNUM) |
| 1263 | target += pc; |
| 1264 | else if (reg != -1) |
| 1265 | { |
| 1266 | get_frame_register_bytes (frame, reg, 0, 4, buf); |
| 1267 | target += extract_unsigned_integer (buf, 4) & -4; |
| 1268 | } |
| 1269 | |
| 1270 | target = target & (SPU_LS_SIZE - 1); |
| 1271 | if (target != next_pc) |
| 1272 | insert_single_step_breakpoint (target); |
| 1273 | } |
| 1274 | |
| 1275 | return 1; |
| 1276 | } |
| 1277 | |
| 1278 | /* Target overlays for the SPU overlay manager. |
| 1279 | |
| 1280 | See the documentation of simple_overlay_update for how the |
| 1281 | interface is supposed to work. |
| 1282 | |
| 1283 | Data structures used by the overlay manager: |
| 1284 | |
| 1285 | struct ovly_table |
| 1286 | { |
| 1287 | u32 vma; |
| 1288 | u32 size; |
| 1289 | u32 pos; |
| 1290 | u32 buf; |
| 1291 | } _ovly_table[]; -- one entry per overlay section |
| 1292 | |
| 1293 | struct ovly_buf_table |
| 1294 | { |
| 1295 | u32 mapped; |
| 1296 | } _ovly_buf_table[]; -- one entry per overlay buffer |
| 1297 | |
| 1298 | _ovly_table should never change. |
| 1299 | |
| 1300 | Both tables are aligned to a 16-byte boundary, the symbols _ovly_table |
| 1301 | and _ovly_buf_table are of type STT_OBJECT and their size set to the size |
| 1302 | of the respective array. buf in _ovly_table is an index into _ovly_buf_table. |
| 1303 | |
| 1304 | mapped is an index into _ovly_table. Both the mapped and buf indices start |
| 1305 | from one to reference the first entry in their respective tables. */ |
| 1306 | |
| 1307 | /* Using the per-objfile private data mechanism, we store for each |
| 1308 | objfile an array of "struct spu_overlay_table" structures, one |
| 1309 | for each obj_section of the objfile. This structure holds two |
| 1310 | fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this |
| 1311 | is *not* an overlay section. If it is non-zero, it represents |
| 1312 | a target address. The overlay section is mapped iff the target |
| 1313 | integer at this location equals MAPPED_VAL. */ |
| 1314 | |
| 1315 | static const struct objfile_data *spu_overlay_data; |
| 1316 | |
| 1317 | struct spu_overlay_table |
| 1318 | { |
| 1319 | CORE_ADDR mapped_ptr; |
| 1320 | CORE_ADDR mapped_val; |
| 1321 | }; |
| 1322 | |
| 1323 | /* Retrieve the overlay table for OBJFILE. If not already cached, read |
| 1324 | the _ovly_table data structure from the target and initialize the |
| 1325 | spu_overlay_table data structure from it. */ |
| 1326 | static struct spu_overlay_table * |
| 1327 | spu_get_overlay_table (struct objfile *objfile) |
| 1328 | { |
| 1329 | struct minimal_symbol *ovly_table_msym, *ovly_buf_table_msym; |
| 1330 | CORE_ADDR ovly_table_base, ovly_buf_table_base; |
| 1331 | unsigned ovly_table_size, ovly_buf_table_size; |
| 1332 | struct spu_overlay_table *tbl; |
| 1333 | struct obj_section *osect; |
| 1334 | char *ovly_table; |
| 1335 | int i; |
| 1336 | |
| 1337 | tbl = objfile_data (objfile, spu_overlay_data); |
| 1338 | if (tbl) |
| 1339 | return tbl; |
| 1340 | |
| 1341 | ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile); |
| 1342 | if (!ovly_table_msym) |
| 1343 | return NULL; |
| 1344 | |
| 1345 | ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table", NULL, objfile); |
| 1346 | if (!ovly_buf_table_msym) |
| 1347 | return NULL; |
| 1348 | |
| 1349 | ovly_table_base = SYMBOL_VALUE_ADDRESS (ovly_table_msym); |
| 1350 | ovly_table_size = MSYMBOL_SIZE (ovly_table_msym); |
| 1351 | |
| 1352 | ovly_buf_table_base = SYMBOL_VALUE_ADDRESS (ovly_buf_table_msym); |
| 1353 | ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym); |
| 1354 | |
| 1355 | ovly_table = xmalloc (ovly_table_size); |
| 1356 | read_memory (ovly_table_base, ovly_table, ovly_table_size); |
| 1357 | |
| 1358 | tbl = OBSTACK_CALLOC (&objfile->objfile_obstack, |
| 1359 | objfile->sections_end - objfile->sections, |
| 1360 | struct spu_overlay_table); |
| 1361 | |
| 1362 | for (i = 0; i < ovly_table_size / 16; i++) |
| 1363 | { |
| 1364 | CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0, 4); |
| 1365 | CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4, 4); |
| 1366 | CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8, 4); |
| 1367 | CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12, 4); |
| 1368 | |
| 1369 | if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size) |
| 1370 | continue; |
| 1371 | |
| 1372 | ALL_OBJFILE_OSECTIONS (objfile, osect) |
| 1373 | if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section) |
| 1374 | && pos == osect->the_bfd_section->filepos) |
| 1375 | { |
| 1376 | int ndx = osect - objfile->sections; |
| 1377 | tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4; |
| 1378 | tbl[ndx].mapped_val = i + 1; |
| 1379 | break; |
| 1380 | } |
| 1381 | } |
| 1382 | |
| 1383 | xfree (ovly_table); |
| 1384 | set_objfile_data (objfile, spu_overlay_data, tbl); |
| 1385 | return tbl; |
| 1386 | } |
| 1387 | |
| 1388 | /* Read _ovly_buf_table entry from the target to dermine whether |
| 1389 | OSECT is currently mapped, and update the mapped state. */ |
| 1390 | static void |
| 1391 | spu_overlay_update_osect (struct obj_section *osect) |
| 1392 | { |
| 1393 | struct spu_overlay_table *ovly_table; |
| 1394 | CORE_ADDR val; |
| 1395 | |
| 1396 | ovly_table = spu_get_overlay_table (osect->objfile); |
| 1397 | if (!ovly_table) |
| 1398 | return; |
| 1399 | |
| 1400 | ovly_table += osect - osect->objfile->sections; |
| 1401 | if (ovly_table->mapped_ptr == 0) |
| 1402 | return; |
| 1403 | |
| 1404 | val = read_memory_unsigned_integer (ovly_table->mapped_ptr, 4); |
| 1405 | osect->ovly_mapped = (val == ovly_table->mapped_val); |
| 1406 | } |
| 1407 | |
| 1408 | /* If OSECT is NULL, then update all sections' mapped state. |
| 1409 | If OSECT is non-NULL, then update only OSECT's mapped state. */ |
| 1410 | static void |
| 1411 | spu_overlay_update (struct obj_section *osect) |
| 1412 | { |
| 1413 | /* Just one section. */ |
| 1414 | if (osect) |
| 1415 | spu_overlay_update_osect (osect); |
| 1416 | |
| 1417 | /* All sections. */ |
| 1418 | else |
| 1419 | { |
| 1420 | struct objfile *objfile; |
| 1421 | |
| 1422 | ALL_OBJSECTIONS (objfile, osect) |
| 1423 | if (section_is_overlay (osect->the_bfd_section)) |
| 1424 | spu_overlay_update_osect (osect); |
| 1425 | } |
| 1426 | } |
| 1427 | |
| 1428 | /* Whenever a new objfile is loaded, read the target's _ovly_table. |
| 1429 | If there is one, go through all sections and make sure for non- |
| 1430 | overlay sections LMA equals VMA, while for overlay sections LMA |
| 1431 | is larger than local store size. */ |
| 1432 | static void |
| 1433 | spu_overlay_new_objfile (struct objfile *objfile) |
| 1434 | { |
| 1435 | struct spu_overlay_table *ovly_table; |
| 1436 | struct obj_section *osect; |
| 1437 | |
| 1438 | /* If we've already touched this file, do nothing. */ |
| 1439 | if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL) |
| 1440 | return; |
| 1441 | |
| 1442 | /* Check if this objfile has overlays. */ |
| 1443 | ovly_table = spu_get_overlay_table (objfile); |
| 1444 | if (!ovly_table) |
| 1445 | return; |
| 1446 | |
| 1447 | /* Now go and fiddle with all the LMAs. */ |
| 1448 | ALL_OBJFILE_OSECTIONS (objfile, osect) |
| 1449 | { |
| 1450 | bfd *obfd = objfile->obfd; |
| 1451 | asection *bsect = osect->the_bfd_section; |
| 1452 | int ndx = osect - objfile->sections; |
| 1453 | |
| 1454 | if (ovly_table[ndx].mapped_ptr == 0) |
| 1455 | bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect); |
| 1456 | else |
| 1457 | bfd_section_lma (obfd, bsect) = bsect->filepos + SPU_LS_SIZE; |
| 1458 | } |
| 1459 | } |
| 1460 | |
| 1461 | |
| 1462 | /* "info spu" commands. */ |
| 1463 | |
| 1464 | static void |
| 1465 | info_spu_event_command (char *args, int from_tty) |
| 1466 | { |
| 1467 | struct frame_info *frame = get_selected_frame (NULL); |
| 1468 | ULONGEST event_status = 0; |
| 1469 | ULONGEST event_mask = 0; |
| 1470 | struct cleanup *chain; |
| 1471 | gdb_byte buf[100]; |
| 1472 | char annex[32]; |
| 1473 | LONGEST len; |
| 1474 | int rc, id; |
| 1475 | |
| 1476 | id = get_frame_register_unsigned (frame, SPU_ID_REGNUM); |
| 1477 | |
| 1478 | xsnprintf (annex, sizeof annex, "%d/event_status", id); |
| 1479 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, |
| 1480 | buf, 0, sizeof buf); |
| 1481 | if (len <= 0) |
| 1482 | error (_("Could not read event_status.")); |
| 1483 | event_status = strtoulst (buf, NULL, 16); |
| 1484 | |
| 1485 | xsnprintf (annex, sizeof annex, "%d/event_mask", id); |
| 1486 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, |
| 1487 | buf, 0, sizeof buf); |
| 1488 | if (len <= 0) |
| 1489 | error (_("Could not read event_mask.")); |
| 1490 | event_mask = strtoulst (buf, NULL, 16); |
| 1491 | |
| 1492 | chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoEvent"); |
| 1493 | |
| 1494 | if (ui_out_is_mi_like_p (uiout)) |
| 1495 | { |
| 1496 | ui_out_field_fmt (uiout, "event_status", |
| 1497 | "0x%s", phex_nz (event_status, 4)); |
| 1498 | ui_out_field_fmt (uiout, "event_mask", |
| 1499 | "0x%s", phex_nz (event_mask, 4)); |
| 1500 | } |
| 1501 | else |
| 1502 | { |
| 1503 | printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4)); |
| 1504 | printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask, 4)); |
| 1505 | } |
| 1506 | |
| 1507 | do_cleanups (chain); |
| 1508 | } |
| 1509 | |
| 1510 | static void |
| 1511 | info_spu_signal_command (char *args, int from_tty) |
| 1512 | { |
| 1513 | struct frame_info *frame = get_selected_frame (NULL); |
| 1514 | ULONGEST signal1 = 0; |
| 1515 | ULONGEST signal1_type = 0; |
| 1516 | int signal1_pending = 0; |
| 1517 | ULONGEST signal2 = 0; |
| 1518 | ULONGEST signal2_type = 0; |
| 1519 | int signal2_pending = 0; |
| 1520 | struct cleanup *chain; |
| 1521 | char annex[32]; |
| 1522 | gdb_byte buf[100]; |
| 1523 | LONGEST len; |
| 1524 | int rc, id; |
| 1525 | |
| 1526 | id = get_frame_register_unsigned (frame, SPU_ID_REGNUM); |
| 1527 | |
| 1528 | xsnprintf (annex, sizeof annex, "%d/signal1", id); |
| 1529 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 4); |
| 1530 | if (len < 0) |
| 1531 | error (_("Could not read signal1.")); |
| 1532 | else if (len == 4) |
| 1533 | { |
| 1534 | signal1 = extract_unsigned_integer (buf, 4); |
| 1535 | signal1_pending = 1; |
| 1536 | } |
| 1537 | |
| 1538 | xsnprintf (annex, sizeof annex, "%d/signal1_type", id); |
| 1539 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, |
| 1540 | buf, 0, sizeof buf); |
| 1541 | if (len <= 0) |
| 1542 | error (_("Could not read signal1_type.")); |
| 1543 | signal1_type = strtoulst (buf, NULL, 16); |
| 1544 | |
| 1545 | xsnprintf (annex, sizeof annex, "%d/signal2", id); |
| 1546 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 4); |
| 1547 | if (len < 0) |
| 1548 | error (_("Could not read signal2.")); |
| 1549 | else if (len == 4) |
| 1550 | { |
| 1551 | signal2 = extract_unsigned_integer (buf, 4); |
| 1552 | signal2_pending = 1; |
| 1553 | } |
| 1554 | |
| 1555 | xsnprintf (annex, sizeof annex, "%d/signal2_type", id); |
| 1556 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, |
| 1557 | buf, 0, sizeof buf); |
| 1558 | if (len <= 0) |
| 1559 | error (_("Could not read signal2_type.")); |
| 1560 | signal2_type = strtoulst (buf, NULL, 16); |
| 1561 | |
| 1562 | chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoSignal"); |
| 1563 | |
| 1564 | if (ui_out_is_mi_like_p (uiout)) |
| 1565 | { |
| 1566 | ui_out_field_int (uiout, "signal1_pending", signal1_pending); |
| 1567 | ui_out_field_fmt (uiout, "signal1", "0x%s", phex_nz (signal1, 4)); |
| 1568 | ui_out_field_int (uiout, "signal1_type", signal1_type); |
| 1569 | ui_out_field_int (uiout, "signal2_pending", signal2_pending); |
| 1570 | ui_out_field_fmt (uiout, "signal2", "0x%s", phex_nz (signal2, 4)); |
| 1571 | ui_out_field_int (uiout, "signal2_type", signal2_type); |
| 1572 | } |
| 1573 | else |
| 1574 | { |
| 1575 | if (signal1_pending) |
| 1576 | printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4)); |
| 1577 | else |
| 1578 | printf_filtered (_("Signal 1 not pending ")); |
| 1579 | |
| 1580 | if (signal1_type) |
| 1581 | printf_filtered (_("(Type Overwrite)\n")); |
| 1582 | else |
| 1583 | printf_filtered (_("(Type Or)\n")); |
| 1584 | |
| 1585 | if (signal2_pending) |
| 1586 | printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4)); |
| 1587 | else |
| 1588 | printf_filtered (_("Signal 2 not pending ")); |
| 1589 | |
| 1590 | if (signal2_type) |
| 1591 | printf_filtered (_("(Type Overwrite)\n")); |
| 1592 | else |
| 1593 | printf_filtered (_("(Type Or)\n")); |
| 1594 | } |
| 1595 | |
| 1596 | do_cleanups (chain); |
| 1597 | } |
| 1598 | |
| 1599 | static void |
| 1600 | info_spu_mailbox_list (gdb_byte *buf, int nr, |
| 1601 | const char *field, const char *msg) |
| 1602 | { |
| 1603 | struct cleanup *chain; |
| 1604 | int i; |
| 1605 | |
| 1606 | if (nr <= 0) |
| 1607 | return; |
| 1608 | |
| 1609 | chain = make_cleanup_ui_out_table_begin_end (uiout, 1, nr, "mbox"); |
| 1610 | |
| 1611 | ui_out_table_header (uiout, 32, ui_left, field, msg); |
| 1612 | ui_out_table_body (uiout); |
| 1613 | |
| 1614 | for (i = 0; i < nr; i++) |
| 1615 | { |
| 1616 | struct cleanup *val_chain; |
| 1617 | ULONGEST val; |
| 1618 | val_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "mbox"); |
| 1619 | val = extract_unsigned_integer (buf + 4*i, 4); |
| 1620 | ui_out_field_fmt (uiout, field, "0x%s", phex (val, 4)); |
| 1621 | do_cleanups (val_chain); |
| 1622 | |
| 1623 | if (!ui_out_is_mi_like_p (uiout)) |
| 1624 | printf_filtered ("\n"); |
| 1625 | } |
| 1626 | |
| 1627 | do_cleanups (chain); |
| 1628 | } |
| 1629 | |
| 1630 | static void |
| 1631 | info_spu_mailbox_command (char *args, int from_tty) |
| 1632 | { |
| 1633 | struct frame_info *frame = get_selected_frame (NULL); |
| 1634 | struct cleanup *chain; |
| 1635 | char annex[32]; |
| 1636 | gdb_byte buf[1024]; |
| 1637 | LONGEST len; |
| 1638 | int i, id; |
| 1639 | |
| 1640 | id = get_frame_register_unsigned (frame, SPU_ID_REGNUM); |
| 1641 | |
| 1642 | chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoMailbox"); |
| 1643 | |
| 1644 | xsnprintf (annex, sizeof annex, "%d/mbox_info", id); |
| 1645 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, |
| 1646 | buf, 0, sizeof buf); |
| 1647 | if (len < 0) |
| 1648 | error (_("Could not read mbox_info.")); |
| 1649 | |
| 1650 | info_spu_mailbox_list (buf, len / 4, "mbox", "SPU Outbound Mailbox"); |
| 1651 | |
| 1652 | xsnprintf (annex, sizeof annex, "%d/ibox_info", id); |
| 1653 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, |
| 1654 | buf, 0, sizeof buf); |
| 1655 | if (len < 0) |
| 1656 | error (_("Could not read ibox_info.")); |
| 1657 | |
| 1658 | info_spu_mailbox_list (buf, len / 4, "ibox", "SPU Outbound Interrupt Mailbox"); |
| 1659 | |
| 1660 | xsnprintf (annex, sizeof annex, "%d/wbox_info", id); |
| 1661 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, |
| 1662 | buf, 0, sizeof buf); |
| 1663 | if (len < 0) |
| 1664 | error (_("Could not read wbox_info.")); |
| 1665 | |
| 1666 | info_spu_mailbox_list (buf, len / 4, "wbox", "SPU Inbound Mailbox"); |
| 1667 | |
| 1668 | do_cleanups (chain); |
| 1669 | } |
| 1670 | |
| 1671 | static ULONGEST |
| 1672 | spu_mfc_get_bitfield (ULONGEST word, int first, int last) |
| 1673 | { |
| 1674 | ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1)); |
| 1675 | return (word >> (63 - last)) & mask; |
| 1676 | } |
| 1677 | |
| 1678 | static void |
| 1679 | info_spu_dma_cmdlist (gdb_byte *buf, int nr) |
| 1680 | { |
| 1681 | static char *spu_mfc_opcode[256] = |
| 1682 | { |
| 1683 | /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1684 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1685 | /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1686 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1687 | /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL, |
| 1688 | "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL, |
| 1689 | /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL, |
| 1690 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1691 | /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL, |
| 1692 | "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL, |
| 1693 | /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1694 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1695 | /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1696 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1697 | /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1698 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1699 | /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL, |
| 1700 | NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf", |
| 1701 | /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1702 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1703 | /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL, |
| 1704 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1705 | /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL, |
| 1706 | "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1707 | /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1708 | "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL, |
| 1709 | /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1710 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1711 | /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1712 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1713 | /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1714 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 1715 | }; |
| 1716 | |
| 1717 | struct cleanup *chain; |
| 1718 | int i; |
| 1719 | |
| 1720 | chain = make_cleanup_ui_out_table_begin_end (uiout, 10, nr, "dma_cmd"); |
| 1721 | |
| 1722 | ui_out_table_header (uiout, 7, ui_left, "opcode", "Opcode"); |
| 1723 | ui_out_table_header (uiout, 3, ui_left, "tag", "Tag"); |
| 1724 | ui_out_table_header (uiout, 3, ui_left, "tid", "TId"); |
| 1725 | ui_out_table_header (uiout, 3, ui_left, "rid", "RId"); |
| 1726 | ui_out_table_header (uiout, 18, ui_left, "ea", "EA"); |
| 1727 | ui_out_table_header (uiout, 7, ui_left, "lsa", "LSA"); |
| 1728 | ui_out_table_header (uiout, 7, ui_left, "size", "Size"); |
| 1729 | ui_out_table_header (uiout, 7, ui_left, "lstaddr", "LstAddr"); |
| 1730 | ui_out_table_header (uiout, 7, ui_left, "lstsize", "LstSize"); |
| 1731 | ui_out_table_header (uiout, 1, ui_left, "error_p", "E"); |
| 1732 | |
| 1733 | ui_out_table_body (uiout); |
| 1734 | |
| 1735 | for (i = 0; i < nr; i++) |
| 1736 | { |
| 1737 | struct cleanup *cmd_chain; |
| 1738 | ULONGEST mfc_cq_dw0; |
| 1739 | ULONGEST mfc_cq_dw1; |
| 1740 | ULONGEST mfc_cq_dw2; |
| 1741 | ULONGEST mfc_cq_dw3; |
| 1742 | int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id; |
| 1743 | int lsa, size, list_lsa, list_size, mfc_lsa, mfc_size; |
| 1744 | ULONGEST mfc_ea; |
| 1745 | int list_valid_p, noop_valid_p, qw_valid_p, ea_valid_p, cmd_error_p; |
| 1746 | |
| 1747 | /* Decode contents of MFC Command Queue Context Save/Restore Registers. |
| 1748 | See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */ |
| 1749 | |
| 1750 | mfc_cq_dw0 = extract_unsigned_integer (buf + 32*i, 8); |
| 1751 | mfc_cq_dw1 = extract_unsigned_integer (buf + 32*i + 8, 8); |
| 1752 | mfc_cq_dw2 = extract_unsigned_integer (buf + 32*i + 16, 8); |
| 1753 | mfc_cq_dw3 = extract_unsigned_integer (buf + 32*i + 24, 8); |
| 1754 | |
| 1755 | list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14); |
| 1756 | list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26); |
| 1757 | mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34); |
| 1758 | mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39); |
| 1759 | list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40); |
| 1760 | rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43); |
| 1761 | tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46); |
| 1762 | |
| 1763 | mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12 |
| 1764 | | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36); |
| 1765 | |
| 1766 | mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13); |
| 1767 | mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24); |
| 1768 | noop_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 37, 37); |
| 1769 | qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38); |
| 1770 | ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39); |
| 1771 | cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40); |
| 1772 | |
| 1773 | cmd_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "cmd"); |
| 1774 | |
| 1775 | if (spu_mfc_opcode[mfc_cmd_opcode]) |
| 1776 | ui_out_field_string (uiout, "opcode", spu_mfc_opcode[mfc_cmd_opcode]); |
| 1777 | else |
| 1778 | ui_out_field_int (uiout, "opcode", mfc_cmd_opcode); |
| 1779 | |
| 1780 | ui_out_field_int (uiout, "tag", mfc_cmd_tag); |
| 1781 | ui_out_field_int (uiout, "tid", tclass_id); |
| 1782 | ui_out_field_int (uiout, "rid", rclass_id); |
| 1783 | |
| 1784 | if (ea_valid_p) |
| 1785 | ui_out_field_fmt (uiout, "ea", "0x%s", phex (mfc_ea, 8)); |
| 1786 | else |
| 1787 | ui_out_field_skip (uiout, "ea"); |
| 1788 | |
| 1789 | ui_out_field_fmt (uiout, "lsa", "0x%05x", mfc_lsa << 4); |
| 1790 | if (qw_valid_p) |
| 1791 | ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size << 4); |
| 1792 | else |
| 1793 | ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size); |
| 1794 | |
| 1795 | if (list_valid_p) |
| 1796 | { |
| 1797 | ui_out_field_fmt (uiout, "lstaddr", "0x%05x", list_lsa << 3); |
| 1798 | ui_out_field_fmt (uiout, "lstsize", "0x%05x", list_size << 3); |
| 1799 | } |
| 1800 | else |
| 1801 | { |
| 1802 | ui_out_field_skip (uiout, "lstaddr"); |
| 1803 | ui_out_field_skip (uiout, "lstsize"); |
| 1804 | } |
| 1805 | |
| 1806 | if (cmd_error_p) |
| 1807 | ui_out_field_string (uiout, "error_p", "*"); |
| 1808 | else |
| 1809 | ui_out_field_skip (uiout, "error_p"); |
| 1810 | |
| 1811 | do_cleanups (cmd_chain); |
| 1812 | |
| 1813 | if (!ui_out_is_mi_like_p (uiout)) |
| 1814 | printf_filtered ("\n"); |
| 1815 | } |
| 1816 | |
| 1817 | do_cleanups (chain); |
| 1818 | } |
| 1819 | |
| 1820 | static void |
| 1821 | info_spu_dma_command (char *args, int from_tty) |
| 1822 | { |
| 1823 | struct frame_info *frame = get_selected_frame (NULL); |
| 1824 | ULONGEST dma_info_type; |
| 1825 | ULONGEST dma_info_mask; |
| 1826 | ULONGEST dma_info_status; |
| 1827 | ULONGEST dma_info_stall_and_notify; |
| 1828 | ULONGEST dma_info_atomic_command_status; |
| 1829 | struct cleanup *chain; |
| 1830 | char annex[32]; |
| 1831 | gdb_byte buf[1024]; |
| 1832 | LONGEST len; |
| 1833 | int i, id; |
| 1834 | |
| 1835 | id = get_frame_register_unsigned (frame, SPU_ID_REGNUM); |
| 1836 | |
| 1837 | xsnprintf (annex, sizeof annex, "%d/dma_info", id); |
| 1838 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, |
| 1839 | buf, 0, 40 + 16 * 32); |
| 1840 | if (len <= 0) |
| 1841 | error (_("Could not read dma_info.")); |
| 1842 | |
| 1843 | dma_info_type = extract_unsigned_integer (buf, 8); |
| 1844 | dma_info_mask = extract_unsigned_integer (buf + 8, 8); |
| 1845 | dma_info_status = extract_unsigned_integer (buf + 16, 8); |
| 1846 | dma_info_stall_and_notify = extract_unsigned_integer (buf + 24, 8); |
| 1847 | dma_info_atomic_command_status = extract_unsigned_integer (buf + 32, 8); |
| 1848 | |
| 1849 | chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoDMA"); |
| 1850 | |
| 1851 | if (ui_out_is_mi_like_p (uiout)) |
| 1852 | { |
| 1853 | ui_out_field_fmt (uiout, "dma_info_type", "0x%s", |
| 1854 | phex_nz (dma_info_type, 4)); |
| 1855 | ui_out_field_fmt (uiout, "dma_info_mask", "0x%s", |
| 1856 | phex_nz (dma_info_mask, 4)); |
| 1857 | ui_out_field_fmt (uiout, "dma_info_status", "0x%s", |
| 1858 | phex_nz (dma_info_status, 4)); |
| 1859 | ui_out_field_fmt (uiout, "dma_info_stall_and_notify", "0x%s", |
| 1860 | phex_nz (dma_info_stall_and_notify, 4)); |
| 1861 | ui_out_field_fmt (uiout, "dma_info_atomic_command_status", "0x%s", |
| 1862 | phex_nz (dma_info_atomic_command_status, 4)); |
| 1863 | } |
| 1864 | else |
| 1865 | { |
| 1866 | const char *query_msg; |
| 1867 | |
| 1868 | switch (dma_info_type) |
| 1869 | { |
| 1870 | case 0: query_msg = _("no query pending"); break; |
| 1871 | case 1: query_msg = _("'any' query pending"); break; |
| 1872 | case 2: query_msg = _("'all' query pending"); break; |
| 1873 | default: query_msg = _("undefined query type"); break; |
| 1874 | } |
| 1875 | |
| 1876 | printf_filtered (_("Tag-Group Status 0x%s\n"), |
| 1877 | phex (dma_info_status, 4)); |
| 1878 | printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"), |
| 1879 | phex (dma_info_mask, 4), query_msg); |
| 1880 | printf_filtered (_("Stall-and-Notify 0x%s\n"), |
| 1881 | phex (dma_info_stall_and_notify, 4)); |
| 1882 | printf_filtered (_("Atomic Cmd Status 0x%s\n"), |
| 1883 | phex (dma_info_atomic_command_status, 4)); |
| 1884 | printf_filtered ("\n"); |
| 1885 | } |
| 1886 | |
| 1887 | info_spu_dma_cmdlist (buf + 40, 16); |
| 1888 | do_cleanups (chain); |
| 1889 | } |
| 1890 | |
| 1891 | static void |
| 1892 | info_spu_proxydma_command (char *args, int from_tty) |
| 1893 | { |
| 1894 | struct frame_info *frame = get_selected_frame (NULL); |
| 1895 | ULONGEST dma_info_type; |
| 1896 | ULONGEST dma_info_mask; |
| 1897 | ULONGEST dma_info_status; |
| 1898 | struct cleanup *chain; |
| 1899 | char annex[32]; |
| 1900 | gdb_byte buf[1024]; |
| 1901 | LONGEST len; |
| 1902 | int i, id; |
| 1903 | |
| 1904 | id = get_frame_register_unsigned (frame, SPU_ID_REGNUM); |
| 1905 | |
| 1906 | xsnprintf (annex, sizeof annex, "%d/proxydma_info", id); |
| 1907 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, |
| 1908 | buf, 0, 24 + 8 * 32); |
| 1909 | if (len <= 0) |
| 1910 | error (_("Could not read proxydma_info.")); |
| 1911 | |
| 1912 | dma_info_type = extract_unsigned_integer (buf, 8); |
| 1913 | dma_info_mask = extract_unsigned_integer (buf + 8, 8); |
| 1914 | dma_info_status = extract_unsigned_integer (buf + 16, 8); |
| 1915 | |
| 1916 | chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoProxyDMA"); |
| 1917 | |
| 1918 | if (ui_out_is_mi_like_p (uiout)) |
| 1919 | { |
| 1920 | ui_out_field_fmt (uiout, "proxydma_info_type", "0x%s", |
| 1921 | phex_nz (dma_info_type, 4)); |
| 1922 | ui_out_field_fmt (uiout, "proxydma_info_mask", "0x%s", |
| 1923 | phex_nz (dma_info_mask, 4)); |
| 1924 | ui_out_field_fmt (uiout, "proxydma_info_status", "0x%s", |
| 1925 | phex_nz (dma_info_status, 4)); |
| 1926 | } |
| 1927 | else |
| 1928 | { |
| 1929 | const char *query_msg; |
| 1930 | |
| 1931 | switch (dma_info_type) |
| 1932 | { |
| 1933 | case 0: query_msg = _("no query pending"); break; |
| 1934 | case 1: query_msg = _("'any' query pending"); break; |
| 1935 | case 2: query_msg = _("'all' query pending"); break; |
| 1936 | default: query_msg = _("undefined query type"); break; |
| 1937 | } |
| 1938 | |
| 1939 | printf_filtered (_("Tag-Group Status 0x%s\n"), |
| 1940 | phex (dma_info_status, 4)); |
| 1941 | printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"), |
| 1942 | phex (dma_info_mask, 4), query_msg); |
| 1943 | printf_filtered ("\n"); |
| 1944 | } |
| 1945 | |
| 1946 | info_spu_dma_cmdlist (buf + 24, 8); |
| 1947 | do_cleanups (chain); |
| 1948 | } |
| 1949 | |
| 1950 | static void |
| 1951 | info_spu_command (char *args, int from_tty) |
| 1952 | { |
| 1953 | printf_unfiltered (_("\"info spu\" must be followed by the name of an SPU facility.\n")); |
| 1954 | help_list (infospucmdlist, "info spu ", -1, gdb_stdout); |
| 1955 | } |
| 1956 | |
| 1957 | |
| 1958 | /* Set up gdbarch struct. */ |
| 1959 | |
| 1960 | static struct gdbarch * |
| 1961 | spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 1962 | { |
| 1963 | struct gdbarch *gdbarch; |
| 1964 | struct gdbarch_tdep *tdep; |
| 1965 | |
| 1966 | /* Find a candidate among the list of pre-declared architectures. */ |
| 1967 | arches = gdbarch_list_lookup_by_info (arches, &info); |
| 1968 | if (arches != NULL) |
| 1969 | return arches->gdbarch; |
| 1970 | |
| 1971 | /* Is is for us? */ |
| 1972 | if (info.bfd_arch_info->mach != bfd_mach_spu) |
| 1973 | return NULL; |
| 1974 | |
| 1975 | /* Yes, create a new architecture. */ |
| 1976 | tdep = XCALLOC (1, struct gdbarch_tdep); |
| 1977 | gdbarch = gdbarch_alloc (&info, tdep); |
| 1978 | |
| 1979 | /* Disassembler. */ |
| 1980 | set_gdbarch_print_insn (gdbarch, print_insn_spu); |
| 1981 | |
| 1982 | /* Registers. */ |
| 1983 | set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS); |
| 1984 | set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS); |
| 1985 | set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM); |
| 1986 | set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM); |
| 1987 | set_gdbarch_read_pc (gdbarch, spu_read_pc); |
| 1988 | set_gdbarch_write_pc (gdbarch, spu_write_pc); |
| 1989 | set_gdbarch_register_name (gdbarch, spu_register_name); |
| 1990 | set_gdbarch_register_type (gdbarch, spu_register_type); |
| 1991 | set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read); |
| 1992 | set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write); |
| 1993 | set_gdbarch_value_from_register (gdbarch, spu_value_from_register); |
| 1994 | set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p); |
| 1995 | |
| 1996 | /* Data types. */ |
| 1997 | set_gdbarch_char_signed (gdbarch, 0); |
| 1998 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 1999 | set_gdbarch_addr_bit (gdbarch, 32); |
| 2000 | set_gdbarch_short_bit (gdbarch, 16); |
| 2001 | set_gdbarch_int_bit (gdbarch, 32); |
| 2002 | set_gdbarch_long_bit (gdbarch, 32); |
| 2003 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 2004 | set_gdbarch_float_bit (gdbarch, 32); |
| 2005 | set_gdbarch_double_bit (gdbarch, 64); |
| 2006 | set_gdbarch_long_double_bit (gdbarch, 64); |
| 2007 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
| 2008 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); |
| 2009 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); |
| 2010 | |
| 2011 | /* Inferior function calls. */ |
| 2012 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
| 2013 | set_gdbarch_frame_align (gdbarch, spu_frame_align); |
| 2014 | set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call); |
| 2015 | set_gdbarch_unwind_dummy_id (gdbarch, spu_unwind_dummy_id); |
| 2016 | set_gdbarch_return_value (gdbarch, spu_return_value); |
| 2017 | |
| 2018 | /* Frame handling. */ |
| 2019 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 2020 | frame_unwind_append_sniffer (gdbarch, spu_frame_sniffer); |
| 2021 | frame_base_set_default (gdbarch, &spu_frame_base); |
| 2022 | set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc); |
| 2023 | set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp); |
| 2024 | set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer); |
| 2025 | set_gdbarch_frame_args_skip (gdbarch, 0); |
| 2026 | set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue); |
| 2027 | set_gdbarch_in_function_epilogue_p (gdbarch, spu_in_function_epilogue_p); |
| 2028 | |
| 2029 | /* Breakpoints. */ |
| 2030 | set_gdbarch_decr_pc_after_break (gdbarch, 4); |
| 2031 | set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc); |
| 2032 | set_gdbarch_cannot_step_breakpoint (gdbarch, 1); |
| 2033 | set_gdbarch_software_single_step (gdbarch, spu_software_single_step); |
| 2034 | |
| 2035 | /* Overlays. */ |
| 2036 | set_gdbarch_overlay_update (gdbarch, spu_overlay_update); |
| 2037 | |
| 2038 | return gdbarch; |
| 2039 | } |
| 2040 | |
| 2041 | void |
| 2042 | _initialize_spu_tdep (void) |
| 2043 | { |
| 2044 | register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init); |
| 2045 | |
| 2046 | /* Add ourselves to objfile event chain. */ |
| 2047 | observer_attach_new_objfile (spu_overlay_new_objfile); |
| 2048 | spu_overlay_data = register_objfile_data (); |
| 2049 | |
| 2050 | /* Add root prefix command for all "info spu" commands. */ |
| 2051 | add_prefix_cmd ("spu", class_info, info_spu_command, |
| 2052 | _("Various SPU specific commands."), |
| 2053 | &infospucmdlist, "info spu ", 0, &infolist); |
| 2054 | |
| 2055 | /* Add various "info spu" commands. */ |
| 2056 | add_cmd ("event", class_info, info_spu_event_command, |
| 2057 | _("Display SPU event facility status.\n"), |
| 2058 | &infospucmdlist); |
| 2059 | add_cmd ("signal", class_info, info_spu_signal_command, |
| 2060 | _("Display SPU signal notification facility status.\n"), |
| 2061 | &infospucmdlist); |
| 2062 | add_cmd ("mailbox", class_info, info_spu_mailbox_command, |
| 2063 | _("Display SPU mailbox facility status.\n"), |
| 2064 | &infospucmdlist); |
| 2065 | add_cmd ("dma", class_info, info_spu_dma_command, |
| 2066 | _("Display MFC DMA status.\n"), |
| 2067 | &infospucmdlist); |
| 2068 | add_cmd ("proxydma", class_info, info_spu_proxydma_command, |
| 2069 | _("Display MFC Proxy-DMA status.\n"), |
| 2070 | &infospucmdlist); |
| 2071 | } |