| 1 | /* SPU target-dependent code for GDB, the GNU debugger. |
| 2 | Copyright (C) 2006, 2007 Free Software Foundation, Inc. |
| 3 | |
| 4 | Contributed by Ulrich Weigand <uweigand@de.ibm.com>. |
| 5 | Based on a port by Sid Manning <sid@us.ibm.com>. |
| 6 | |
| 7 | This file is part of GDB. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 2 of the License, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program; if not, write to the Free Software |
| 21 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
| 22 | Boston, MA 02110-1301, USA. */ |
| 23 | |
| 24 | #include "defs.h" |
| 25 | #include "arch-utils.h" |
| 26 | #include "gdbtypes.h" |
| 27 | #include "gdbcmd.h" |
| 28 | #include "gdbcore.h" |
| 29 | #include "gdb_string.h" |
| 30 | #include "gdb_assert.h" |
| 31 | #include "frame.h" |
| 32 | #include "frame-unwind.h" |
| 33 | #include "frame-base.h" |
| 34 | #include "trad-frame.h" |
| 35 | #include "symtab.h" |
| 36 | #include "symfile.h" |
| 37 | #include "value.h" |
| 38 | #include "inferior.h" |
| 39 | #include "dis-asm.h" |
| 40 | #include "objfiles.h" |
| 41 | #include "language.h" |
| 42 | #include "regcache.h" |
| 43 | #include "reggroups.h" |
| 44 | #include "floatformat.h" |
| 45 | |
| 46 | #include "spu-tdep.h" |
| 47 | |
| 48 | /* SPU-specific vector type. */ |
| 49 | struct type *spu_builtin_type_vec128; |
| 50 | |
| 51 | /* Registers. */ |
| 52 | |
| 53 | static const char * |
| 54 | spu_register_name (int reg_nr) |
| 55 | { |
| 56 | static char *register_names[] = |
| 57 | { |
| 58 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 59 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 60 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
| 61 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
| 62 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", |
| 63 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", |
| 64 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", |
| 65 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", |
| 66 | "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71", |
| 67 | "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79", |
| 68 | "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", |
| 69 | "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95", |
| 70 | "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103", |
| 71 | "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111", |
| 72 | "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119", |
| 73 | "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127", |
| 74 | "id", "pc", "sp" |
| 75 | }; |
| 76 | |
| 77 | if (reg_nr < 0) |
| 78 | return NULL; |
| 79 | if (reg_nr >= sizeof register_names / sizeof *register_names) |
| 80 | return NULL; |
| 81 | |
| 82 | return register_names[reg_nr]; |
| 83 | } |
| 84 | |
| 85 | static struct type * |
| 86 | spu_register_type (struct gdbarch *gdbarch, int reg_nr) |
| 87 | { |
| 88 | if (reg_nr < SPU_NUM_GPRS) |
| 89 | return spu_builtin_type_vec128; |
| 90 | |
| 91 | switch (reg_nr) |
| 92 | { |
| 93 | case SPU_ID_REGNUM: |
| 94 | return builtin_type_uint32; |
| 95 | |
| 96 | case SPU_PC_REGNUM: |
| 97 | return builtin_type_void_func_ptr; |
| 98 | |
| 99 | case SPU_SP_REGNUM: |
| 100 | return builtin_type_void_data_ptr; |
| 101 | |
| 102 | default: |
| 103 | internal_error (__FILE__, __LINE__, "invalid regnum"); |
| 104 | } |
| 105 | } |
| 106 | |
| 107 | /* Pseudo registers for preferred slots - stack pointer. */ |
| 108 | |
| 109 | static void |
| 110 | spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
| 111 | int regnum, gdb_byte *buf) |
| 112 | { |
| 113 | gdb_byte reg[16]; |
| 114 | |
| 115 | switch (regnum) |
| 116 | { |
| 117 | case SPU_SP_REGNUM: |
| 118 | regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg); |
| 119 | memcpy (buf, reg, 4); |
| 120 | break; |
| 121 | |
| 122 | default: |
| 123 | internal_error (__FILE__, __LINE__, _("invalid regnum")); |
| 124 | } |
| 125 | } |
| 126 | |
| 127 | static void |
| 128 | spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
| 129 | int regnum, const gdb_byte *buf) |
| 130 | { |
| 131 | gdb_byte reg[16]; |
| 132 | |
| 133 | switch (regnum) |
| 134 | { |
| 135 | case SPU_SP_REGNUM: |
| 136 | regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg); |
| 137 | memcpy (reg, buf, 4); |
| 138 | regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg); |
| 139 | break; |
| 140 | |
| 141 | default: |
| 142 | internal_error (__FILE__, __LINE__, _("invalid regnum")); |
| 143 | } |
| 144 | } |
| 145 | |
| 146 | /* Value conversion -- access scalar values at the preferred slot. */ |
| 147 | |
| 148 | static struct value * |
| 149 | spu_value_from_register (struct type *type, int regnum, |
| 150 | struct frame_info *frame) |
| 151 | { |
| 152 | struct value *value = default_value_from_register (type, regnum, frame); |
| 153 | int len = TYPE_LENGTH (type); |
| 154 | |
| 155 | if (regnum < SPU_NUM_GPRS && len < 16) |
| 156 | { |
| 157 | int preferred_slot = len < 4 ? 4 - len : 0; |
| 158 | set_value_offset (value, preferred_slot); |
| 159 | } |
| 160 | |
| 161 | return value; |
| 162 | } |
| 163 | |
| 164 | /* Register groups. */ |
| 165 | |
| 166 | static int |
| 167 | spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
| 168 | struct reggroup *group) |
| 169 | { |
| 170 | /* Registers displayed via 'info regs'. */ |
| 171 | if (group == general_reggroup) |
| 172 | return 1; |
| 173 | |
| 174 | /* Registers displayed via 'info float'. */ |
| 175 | if (group == float_reggroup) |
| 176 | return 0; |
| 177 | |
| 178 | /* Registers that need to be saved/restored in order to |
| 179 | push or pop frames. */ |
| 180 | if (group == save_reggroup || group == restore_reggroup) |
| 181 | return 1; |
| 182 | |
| 183 | return default_register_reggroup_p (gdbarch, regnum, group); |
| 184 | } |
| 185 | |
| 186 | |
| 187 | /* Decoding SPU instructions. */ |
| 188 | |
| 189 | enum |
| 190 | { |
| 191 | op_lqd = 0x34, |
| 192 | op_lqx = 0x3c4, |
| 193 | op_lqa = 0x61, |
| 194 | op_lqr = 0x67, |
| 195 | op_stqd = 0x24, |
| 196 | op_stqx = 0x144, |
| 197 | op_stqa = 0x41, |
| 198 | op_stqr = 0x47, |
| 199 | |
| 200 | op_il = 0x081, |
| 201 | op_ila = 0x21, |
| 202 | op_a = 0x0c0, |
| 203 | op_ai = 0x1c, |
| 204 | |
| 205 | op_selb = 0x4, |
| 206 | |
| 207 | op_br = 0x64, |
| 208 | op_bra = 0x60, |
| 209 | op_brsl = 0x66, |
| 210 | op_brasl = 0x62, |
| 211 | op_brnz = 0x42, |
| 212 | op_brz = 0x40, |
| 213 | op_brhnz = 0x46, |
| 214 | op_brhz = 0x44, |
| 215 | op_bi = 0x1a8, |
| 216 | op_bisl = 0x1a9, |
| 217 | op_biz = 0x128, |
| 218 | op_binz = 0x129, |
| 219 | op_bihz = 0x12a, |
| 220 | op_bihnz = 0x12b, |
| 221 | }; |
| 222 | |
| 223 | static int |
| 224 | is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb) |
| 225 | { |
| 226 | if ((insn >> 21) == op) |
| 227 | { |
| 228 | *rt = insn & 127; |
| 229 | *ra = (insn >> 7) & 127; |
| 230 | *rb = (insn >> 14) & 127; |
| 231 | return 1; |
| 232 | } |
| 233 | |
| 234 | return 0; |
| 235 | } |
| 236 | |
| 237 | static int |
| 238 | is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc) |
| 239 | { |
| 240 | if ((insn >> 28) == op) |
| 241 | { |
| 242 | *rt = (insn >> 21) & 127; |
| 243 | *ra = (insn >> 7) & 127; |
| 244 | *rb = (insn >> 14) & 127; |
| 245 | *rc = insn & 127; |
| 246 | return 1; |
| 247 | } |
| 248 | |
| 249 | return 0; |
| 250 | } |
| 251 | |
| 252 | static int |
| 253 | is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7) |
| 254 | { |
| 255 | if ((insn >> 21) == op) |
| 256 | { |
| 257 | *rt = insn & 127; |
| 258 | *ra = (insn >> 7) & 127; |
| 259 | *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40; |
| 260 | return 1; |
| 261 | } |
| 262 | |
| 263 | return 0; |
| 264 | } |
| 265 | |
| 266 | static int |
| 267 | is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10) |
| 268 | { |
| 269 | if ((insn >> 24) == op) |
| 270 | { |
| 271 | *rt = insn & 127; |
| 272 | *ra = (insn >> 7) & 127; |
| 273 | *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200; |
| 274 | return 1; |
| 275 | } |
| 276 | |
| 277 | return 0; |
| 278 | } |
| 279 | |
| 280 | static int |
| 281 | is_ri16 (unsigned int insn, int op, int *rt, int *i16) |
| 282 | { |
| 283 | if ((insn >> 23) == op) |
| 284 | { |
| 285 | *rt = insn & 127; |
| 286 | *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000; |
| 287 | return 1; |
| 288 | } |
| 289 | |
| 290 | return 0; |
| 291 | } |
| 292 | |
| 293 | static int |
| 294 | is_ri18 (unsigned int insn, int op, int *rt, int *i18) |
| 295 | { |
| 296 | if ((insn >> 25) == op) |
| 297 | { |
| 298 | *rt = insn & 127; |
| 299 | *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000; |
| 300 | return 1; |
| 301 | } |
| 302 | |
| 303 | return 0; |
| 304 | } |
| 305 | |
| 306 | static int |
| 307 | is_branch (unsigned int insn, int *offset, int *reg) |
| 308 | { |
| 309 | int rt, i7, i16; |
| 310 | |
| 311 | if (is_ri16 (insn, op_br, &rt, &i16) |
| 312 | || is_ri16 (insn, op_brsl, &rt, &i16) |
| 313 | || is_ri16 (insn, op_brnz, &rt, &i16) |
| 314 | || is_ri16 (insn, op_brz, &rt, &i16) |
| 315 | || is_ri16 (insn, op_brhnz, &rt, &i16) |
| 316 | || is_ri16 (insn, op_brhz, &rt, &i16)) |
| 317 | { |
| 318 | *reg = SPU_PC_REGNUM; |
| 319 | *offset = i16 << 2; |
| 320 | return 1; |
| 321 | } |
| 322 | |
| 323 | if (is_ri16 (insn, op_bra, &rt, &i16) |
| 324 | || is_ri16 (insn, op_brasl, &rt, &i16)) |
| 325 | { |
| 326 | *reg = -1; |
| 327 | *offset = i16 << 2; |
| 328 | return 1; |
| 329 | } |
| 330 | |
| 331 | if (is_ri7 (insn, op_bi, &rt, reg, &i7) |
| 332 | || is_ri7 (insn, op_bisl, &rt, reg, &i7) |
| 333 | || is_ri7 (insn, op_biz, &rt, reg, &i7) |
| 334 | || is_ri7 (insn, op_binz, &rt, reg, &i7) |
| 335 | || is_ri7 (insn, op_bihz, &rt, reg, &i7) |
| 336 | || is_ri7 (insn, op_bihnz, &rt, reg, &i7)) |
| 337 | { |
| 338 | *offset = 0; |
| 339 | return 1; |
| 340 | } |
| 341 | |
| 342 | return 0; |
| 343 | } |
| 344 | |
| 345 | |
| 346 | /* Prolog parsing. */ |
| 347 | |
| 348 | struct spu_prologue_data |
| 349 | { |
| 350 | /* Stack frame size. -1 if analysis was unsuccessful. */ |
| 351 | int size; |
| 352 | |
| 353 | /* How to find the CFA. The CFA is equal to SP at function entry. */ |
| 354 | int cfa_reg; |
| 355 | int cfa_offset; |
| 356 | |
| 357 | /* Offset relative to CFA where a register is saved. -1 if invalid. */ |
| 358 | int reg_offset[SPU_NUM_GPRS]; |
| 359 | }; |
| 360 | |
| 361 | static CORE_ADDR |
| 362 | spu_analyze_prologue (CORE_ADDR start_pc, CORE_ADDR end_pc, |
| 363 | struct spu_prologue_data *data) |
| 364 | { |
| 365 | int found_sp = 0; |
| 366 | int found_fp = 0; |
| 367 | int found_lr = 0; |
| 368 | int reg_immed[SPU_NUM_GPRS]; |
| 369 | gdb_byte buf[16]; |
| 370 | CORE_ADDR prolog_pc = start_pc; |
| 371 | CORE_ADDR pc; |
| 372 | int i; |
| 373 | |
| 374 | |
| 375 | /* Initialize DATA to default values. */ |
| 376 | data->size = -1; |
| 377 | |
| 378 | data->cfa_reg = SPU_RAW_SP_REGNUM; |
| 379 | data->cfa_offset = 0; |
| 380 | |
| 381 | for (i = 0; i < SPU_NUM_GPRS; i++) |
| 382 | data->reg_offset[i] = -1; |
| 383 | |
| 384 | /* Set up REG_IMMED array. This is non-zero for a register if we know its |
| 385 | preferred slot currently holds this immediate value. */ |
| 386 | for (i = 0; i < SPU_NUM_GPRS; i++) |
| 387 | reg_immed[i] = 0; |
| 388 | |
| 389 | /* Scan instructions until the first branch. |
| 390 | |
| 391 | The following instructions are important prolog components: |
| 392 | |
| 393 | - The first instruction to set up the stack pointer. |
| 394 | - The first instruction to set up the frame pointer. |
| 395 | - The first instruction to save the link register. |
| 396 | |
| 397 | We return the instruction after the latest of these three, |
| 398 | or the incoming PC if none is found. The first instruction |
| 399 | to set up the stack pointer also defines the frame size. |
| 400 | |
| 401 | Note that instructions saving incoming arguments to their stack |
| 402 | slots are not counted as important, because they are hard to |
| 403 | identify with certainty. This should not matter much, because |
| 404 | arguments are relevant only in code compiled with debug data, |
| 405 | and in such code the GDB core will advance until the first source |
| 406 | line anyway, using SAL data. |
| 407 | |
| 408 | For purposes of stack unwinding, we analyze the following types |
| 409 | of instructions in addition: |
| 410 | |
| 411 | - Any instruction adding to the current frame pointer. |
| 412 | - Any instruction loading an immediate constant into a register. |
| 413 | - Any instruction storing a register onto the stack. |
| 414 | |
| 415 | These are used to compute the CFA and REG_OFFSET output. */ |
| 416 | |
| 417 | for (pc = start_pc; pc < end_pc; pc += 4) |
| 418 | { |
| 419 | unsigned int insn; |
| 420 | int rt, ra, rb, rc, immed; |
| 421 | |
| 422 | if (target_read_memory (pc, buf, 4)) |
| 423 | break; |
| 424 | insn = extract_unsigned_integer (buf, 4); |
| 425 | |
| 426 | /* AI is the typical instruction to set up a stack frame. |
| 427 | It is also used to initialize the frame pointer. */ |
| 428 | if (is_ri10 (insn, op_ai, &rt, &ra, &immed)) |
| 429 | { |
| 430 | if (rt == data->cfa_reg && ra == data->cfa_reg) |
| 431 | data->cfa_offset -= immed; |
| 432 | |
| 433 | if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM |
| 434 | && !found_sp) |
| 435 | { |
| 436 | found_sp = 1; |
| 437 | prolog_pc = pc + 4; |
| 438 | |
| 439 | data->size = -immed; |
| 440 | } |
| 441 | else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM |
| 442 | && !found_fp) |
| 443 | { |
| 444 | found_fp = 1; |
| 445 | prolog_pc = pc + 4; |
| 446 | |
| 447 | data->cfa_reg = SPU_FP_REGNUM; |
| 448 | data->cfa_offset -= immed; |
| 449 | } |
| 450 | } |
| 451 | |
| 452 | /* A is used to set up stack frames of size >= 512 bytes. |
| 453 | If we have tracked the contents of the addend register, |
| 454 | we can handle this as well. */ |
| 455 | else if (is_rr (insn, op_a, &rt, &ra, &rb)) |
| 456 | { |
| 457 | if (rt == data->cfa_reg && ra == data->cfa_reg) |
| 458 | { |
| 459 | if (reg_immed[rb] != 0) |
| 460 | data->cfa_offset -= reg_immed[rb]; |
| 461 | else |
| 462 | data->cfa_reg = -1; /* We don't know the CFA any more. */ |
| 463 | } |
| 464 | |
| 465 | if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM |
| 466 | && !found_sp) |
| 467 | { |
| 468 | found_sp = 1; |
| 469 | prolog_pc = pc + 4; |
| 470 | |
| 471 | if (reg_immed[rb] != 0) |
| 472 | data->size = -reg_immed[rb]; |
| 473 | } |
| 474 | } |
| 475 | |
| 476 | /* We need to track IL and ILA used to load immediate constants |
| 477 | in case they are later used as input to an A instruction. */ |
| 478 | else if (is_ri16 (insn, op_il, &rt, &immed)) |
| 479 | { |
| 480 | reg_immed[rt] = immed; |
| 481 | |
| 482 | if (rt == SPU_RAW_SP_REGNUM && !found_sp) |
| 483 | found_sp = 1; |
| 484 | } |
| 485 | |
| 486 | else if (is_ri18 (insn, op_ila, &rt, &immed)) |
| 487 | { |
| 488 | reg_immed[rt] = immed & 0x3ffff; |
| 489 | |
| 490 | if (rt == SPU_RAW_SP_REGNUM && !found_sp) |
| 491 | found_sp = 1; |
| 492 | } |
| 493 | |
| 494 | /* STQD is used to save registers to the stack. */ |
| 495 | else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed)) |
| 496 | { |
| 497 | if (ra == data->cfa_reg) |
| 498 | data->reg_offset[rt] = data->cfa_offset - (immed << 4); |
| 499 | |
| 500 | if (ra == data->cfa_reg && rt == SPU_LR_REGNUM |
| 501 | && !found_lr) |
| 502 | { |
| 503 | found_lr = 1; |
| 504 | prolog_pc = pc + 4; |
| 505 | } |
| 506 | } |
| 507 | |
| 508 | /* _start uses SELB to set up the stack pointer. */ |
| 509 | else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc)) |
| 510 | { |
| 511 | if (rt == SPU_RAW_SP_REGNUM && !found_sp) |
| 512 | found_sp = 1; |
| 513 | } |
| 514 | |
| 515 | /* We terminate if we find a branch. */ |
| 516 | else if (is_branch (insn, &immed, &ra)) |
| 517 | break; |
| 518 | } |
| 519 | |
| 520 | |
| 521 | /* If we successfully parsed until here, and didn't find any instruction |
| 522 | modifying SP, we assume we have a frameless function. */ |
| 523 | if (!found_sp) |
| 524 | data->size = 0; |
| 525 | |
| 526 | /* Return cooked instead of raw SP. */ |
| 527 | if (data->cfa_reg == SPU_RAW_SP_REGNUM) |
| 528 | data->cfa_reg = SPU_SP_REGNUM; |
| 529 | |
| 530 | return prolog_pc; |
| 531 | } |
| 532 | |
| 533 | /* Return the first instruction after the prologue starting at PC. */ |
| 534 | static CORE_ADDR |
| 535 | spu_skip_prologue (CORE_ADDR pc) |
| 536 | { |
| 537 | struct spu_prologue_data data; |
| 538 | return spu_analyze_prologue (pc, (CORE_ADDR)-1, &data); |
| 539 | } |
| 540 | |
| 541 | /* Return the frame pointer in use at address PC. */ |
| 542 | static void |
| 543 | spu_virtual_frame_pointer (CORE_ADDR pc, int *reg, LONGEST *offset) |
| 544 | { |
| 545 | struct spu_prologue_data data; |
| 546 | spu_analyze_prologue (pc, (CORE_ADDR)-1, &data); |
| 547 | |
| 548 | if (data.size != -1 && data.cfa_reg != -1) |
| 549 | { |
| 550 | /* The 'frame pointer' address is CFA minus frame size. */ |
| 551 | *reg = data.cfa_reg; |
| 552 | *offset = data.cfa_offset - data.size; |
| 553 | } |
| 554 | else |
| 555 | { |
| 556 | /* ??? We don't really know ... */ |
| 557 | *reg = SPU_SP_REGNUM; |
| 558 | *offset = 0; |
| 559 | } |
| 560 | } |
| 561 | |
| 562 | /* Normal stack frames. */ |
| 563 | |
| 564 | struct spu_unwind_cache |
| 565 | { |
| 566 | CORE_ADDR func; |
| 567 | CORE_ADDR frame_base; |
| 568 | CORE_ADDR local_base; |
| 569 | |
| 570 | struct trad_frame_saved_reg *saved_regs; |
| 571 | }; |
| 572 | |
| 573 | static struct spu_unwind_cache * |
| 574 | spu_frame_unwind_cache (struct frame_info *next_frame, |
| 575 | void **this_prologue_cache) |
| 576 | { |
| 577 | struct spu_unwind_cache *info; |
| 578 | struct spu_prologue_data data; |
| 579 | |
| 580 | if (*this_prologue_cache) |
| 581 | return *this_prologue_cache; |
| 582 | |
| 583 | info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache); |
| 584 | *this_prologue_cache = info; |
| 585 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
| 586 | info->frame_base = 0; |
| 587 | info->local_base = 0; |
| 588 | |
| 589 | /* Find the start of the current function, and analyze its prologue. */ |
| 590 | info->func = frame_func_unwind (next_frame, NORMAL_FRAME); |
| 591 | if (info->func == 0) |
| 592 | { |
| 593 | /* Fall back to using the current PC as frame ID. */ |
| 594 | info->func = frame_pc_unwind (next_frame); |
| 595 | data.size = -1; |
| 596 | } |
| 597 | else |
| 598 | spu_analyze_prologue (info->func, frame_pc_unwind (next_frame), &data); |
| 599 | |
| 600 | |
| 601 | /* If successful, use prologue analysis data. */ |
| 602 | if (data.size != -1 && data.cfa_reg != -1) |
| 603 | { |
| 604 | CORE_ADDR cfa; |
| 605 | int i; |
| 606 | gdb_byte buf[16]; |
| 607 | |
| 608 | /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */ |
| 609 | frame_unwind_register (next_frame, data.cfa_reg, buf); |
| 610 | cfa = extract_unsigned_integer (buf, 4) + data.cfa_offset; |
| 611 | |
| 612 | /* Call-saved register slots. */ |
| 613 | for (i = 0; i < SPU_NUM_GPRS; i++) |
| 614 | if (i == SPU_LR_REGNUM |
| 615 | || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM)) |
| 616 | if (data.reg_offset[i] != -1) |
| 617 | info->saved_regs[i].addr = cfa - data.reg_offset[i]; |
| 618 | |
| 619 | /* The previous PC comes from the link register. */ |
| 620 | if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM)) |
| 621 | info->saved_regs[SPU_PC_REGNUM] = info->saved_regs[SPU_LR_REGNUM]; |
| 622 | else |
| 623 | info->saved_regs[SPU_PC_REGNUM].realreg = SPU_LR_REGNUM; |
| 624 | |
| 625 | /* The previous SP is equal to the CFA. */ |
| 626 | trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM, cfa); |
| 627 | |
| 628 | /* Frame bases. */ |
| 629 | info->frame_base = cfa; |
| 630 | info->local_base = cfa - data.size; |
| 631 | } |
| 632 | |
| 633 | /* Otherwise, fall back to reading the backchain link. */ |
| 634 | else |
| 635 | { |
| 636 | CORE_ADDR reg, backchain; |
| 637 | |
| 638 | /* Get the backchain. */ |
| 639 | reg = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM); |
| 640 | backchain = read_memory_unsigned_integer (reg, 4); |
| 641 | |
| 642 | /* A zero backchain terminates the frame chain. Also, sanity |
| 643 | check against the local store size limit. */ |
| 644 | if (backchain != 0 && backchain < SPU_LS_SIZE) |
| 645 | { |
| 646 | /* Assume the link register is saved into its slot. */ |
| 647 | if (backchain + 16 < SPU_LS_SIZE) |
| 648 | info->saved_regs[SPU_LR_REGNUM].addr = backchain + 16; |
| 649 | |
| 650 | /* This will also be the previous PC. */ |
| 651 | if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM)) |
| 652 | info->saved_regs[SPU_PC_REGNUM] = info->saved_regs[SPU_LR_REGNUM]; |
| 653 | else |
| 654 | info->saved_regs[SPU_PC_REGNUM].realreg = SPU_LR_REGNUM; |
| 655 | |
| 656 | /* The previous SP will equal the backchain value. */ |
| 657 | trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM, backchain); |
| 658 | |
| 659 | /* Frame bases. */ |
| 660 | info->frame_base = backchain; |
| 661 | info->local_base = reg; |
| 662 | } |
| 663 | } |
| 664 | |
| 665 | return info; |
| 666 | } |
| 667 | |
| 668 | static void |
| 669 | spu_frame_this_id (struct frame_info *next_frame, |
| 670 | void **this_prologue_cache, struct frame_id *this_id) |
| 671 | { |
| 672 | struct spu_unwind_cache *info = |
| 673 | spu_frame_unwind_cache (next_frame, this_prologue_cache); |
| 674 | |
| 675 | if (info->frame_base == 0) |
| 676 | return; |
| 677 | |
| 678 | *this_id = frame_id_build (info->frame_base, info->func); |
| 679 | } |
| 680 | |
| 681 | static void |
| 682 | spu_frame_prev_register (struct frame_info *next_frame, |
| 683 | void **this_prologue_cache, |
| 684 | int regnum, int *optimizedp, |
| 685 | enum lval_type *lvalp, CORE_ADDR * addrp, |
| 686 | int *realnump, gdb_byte *bufferp) |
| 687 | { |
| 688 | struct spu_unwind_cache *info |
| 689 | = spu_frame_unwind_cache (next_frame, this_prologue_cache); |
| 690 | |
| 691 | /* Special-case the stack pointer. */ |
| 692 | if (regnum == SPU_RAW_SP_REGNUM) |
| 693 | regnum = SPU_SP_REGNUM; |
| 694 | |
| 695 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
| 696 | optimizedp, lvalp, addrp, realnump, bufferp); |
| 697 | } |
| 698 | |
| 699 | static const struct frame_unwind spu_frame_unwind = { |
| 700 | NORMAL_FRAME, |
| 701 | spu_frame_this_id, |
| 702 | spu_frame_prev_register |
| 703 | }; |
| 704 | |
| 705 | const struct frame_unwind * |
| 706 | spu_frame_sniffer (struct frame_info *next_frame) |
| 707 | { |
| 708 | return &spu_frame_unwind; |
| 709 | } |
| 710 | |
| 711 | static CORE_ADDR |
| 712 | spu_frame_base_address (struct frame_info *next_frame, void **this_cache) |
| 713 | { |
| 714 | struct spu_unwind_cache *info |
| 715 | = spu_frame_unwind_cache (next_frame, this_cache); |
| 716 | return info->local_base; |
| 717 | } |
| 718 | |
| 719 | static const struct frame_base spu_frame_base = { |
| 720 | &spu_frame_unwind, |
| 721 | spu_frame_base_address, |
| 722 | spu_frame_base_address, |
| 723 | spu_frame_base_address |
| 724 | }; |
| 725 | |
| 726 | static CORE_ADDR |
| 727 | spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 728 | { |
| 729 | return frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM); |
| 730 | } |
| 731 | |
| 732 | static CORE_ADDR |
| 733 | spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 734 | { |
| 735 | return frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM); |
| 736 | } |
| 737 | |
| 738 | |
| 739 | /* Function calling convention. */ |
| 740 | |
| 741 | static int |
| 742 | spu_scalar_value_p (struct type *type) |
| 743 | { |
| 744 | switch (TYPE_CODE (type)) |
| 745 | { |
| 746 | case TYPE_CODE_INT: |
| 747 | case TYPE_CODE_ENUM: |
| 748 | case TYPE_CODE_RANGE: |
| 749 | case TYPE_CODE_CHAR: |
| 750 | case TYPE_CODE_BOOL: |
| 751 | case TYPE_CODE_PTR: |
| 752 | case TYPE_CODE_REF: |
| 753 | return TYPE_LENGTH (type) <= 16; |
| 754 | |
| 755 | default: |
| 756 | return 0; |
| 757 | } |
| 758 | } |
| 759 | |
| 760 | static void |
| 761 | spu_value_to_regcache (struct regcache *regcache, int regnum, |
| 762 | struct type *type, const gdb_byte *in) |
| 763 | { |
| 764 | int len = TYPE_LENGTH (type); |
| 765 | |
| 766 | if (spu_scalar_value_p (type)) |
| 767 | { |
| 768 | int preferred_slot = len < 4 ? 4 - len : 0; |
| 769 | regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in); |
| 770 | } |
| 771 | else |
| 772 | { |
| 773 | while (len >= 16) |
| 774 | { |
| 775 | regcache_cooked_write (regcache, regnum++, in); |
| 776 | in += 16; |
| 777 | len -= 16; |
| 778 | } |
| 779 | |
| 780 | if (len > 0) |
| 781 | regcache_cooked_write_part (regcache, regnum, 0, len, in); |
| 782 | } |
| 783 | } |
| 784 | |
| 785 | static void |
| 786 | spu_regcache_to_value (struct regcache *regcache, int regnum, |
| 787 | struct type *type, gdb_byte *out) |
| 788 | { |
| 789 | int len = TYPE_LENGTH (type); |
| 790 | |
| 791 | if (spu_scalar_value_p (type)) |
| 792 | { |
| 793 | int preferred_slot = len < 4 ? 4 - len : 0; |
| 794 | regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out); |
| 795 | } |
| 796 | else |
| 797 | { |
| 798 | while (len >= 16) |
| 799 | { |
| 800 | regcache_cooked_read (regcache, regnum++, out); |
| 801 | out += 16; |
| 802 | len -= 16; |
| 803 | } |
| 804 | |
| 805 | if (len > 0) |
| 806 | regcache_cooked_read_part (regcache, regnum, 0, len, out); |
| 807 | } |
| 808 | } |
| 809 | |
| 810 | static CORE_ADDR |
| 811 | spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 812 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 813 | int nargs, struct value **args, CORE_ADDR sp, |
| 814 | int struct_return, CORE_ADDR struct_addr) |
| 815 | { |
| 816 | int i; |
| 817 | int regnum = SPU_ARG1_REGNUM; |
| 818 | int stack_arg = -1; |
| 819 | gdb_byte buf[16]; |
| 820 | |
| 821 | /* Set the return address. */ |
| 822 | memset (buf, 0, sizeof buf); |
| 823 | store_unsigned_integer (buf, 4, bp_addr); |
| 824 | regcache_cooked_write (regcache, SPU_LR_REGNUM, buf); |
| 825 | |
| 826 | /* If STRUCT_RETURN is true, then the struct return address (in |
| 827 | STRUCT_ADDR) will consume the first argument-passing register. |
| 828 | Both adjust the register count and store that value. */ |
| 829 | if (struct_return) |
| 830 | { |
| 831 | memset (buf, 0, sizeof buf); |
| 832 | store_unsigned_integer (buf, 4, struct_addr); |
| 833 | regcache_cooked_write (regcache, regnum++, buf); |
| 834 | } |
| 835 | |
| 836 | /* Fill in argument registers. */ |
| 837 | for (i = 0; i < nargs; i++) |
| 838 | { |
| 839 | struct value *arg = args[i]; |
| 840 | struct type *type = check_typedef (value_type (arg)); |
| 841 | const gdb_byte *contents = value_contents (arg); |
| 842 | int len = TYPE_LENGTH (type); |
| 843 | int n_regs = align_up (len, 16) / 16; |
| 844 | |
| 845 | /* If the argument doesn't wholly fit into registers, it and |
| 846 | all subsequent arguments go to the stack. */ |
| 847 | if (regnum + n_regs - 1 > SPU_ARGN_REGNUM) |
| 848 | { |
| 849 | stack_arg = i; |
| 850 | break; |
| 851 | } |
| 852 | |
| 853 | spu_value_to_regcache (regcache, regnum, type, contents); |
| 854 | regnum += n_regs; |
| 855 | } |
| 856 | |
| 857 | /* Overflow arguments go to the stack. */ |
| 858 | if (stack_arg != -1) |
| 859 | { |
| 860 | CORE_ADDR ap; |
| 861 | |
| 862 | /* Allocate all required stack size. */ |
| 863 | for (i = stack_arg; i < nargs; i++) |
| 864 | { |
| 865 | struct type *type = check_typedef (value_type (args[i])); |
| 866 | sp -= align_up (TYPE_LENGTH (type), 16); |
| 867 | } |
| 868 | |
| 869 | /* Fill in stack arguments. */ |
| 870 | ap = sp; |
| 871 | for (i = stack_arg; i < nargs; i++) |
| 872 | { |
| 873 | struct value *arg = args[i]; |
| 874 | struct type *type = check_typedef (value_type (arg)); |
| 875 | int len = TYPE_LENGTH (type); |
| 876 | int preferred_slot; |
| 877 | |
| 878 | if (spu_scalar_value_p (type)) |
| 879 | preferred_slot = len < 4 ? 4 - len : 0; |
| 880 | else |
| 881 | preferred_slot = 0; |
| 882 | |
| 883 | target_write_memory (ap + preferred_slot, value_contents (arg), len); |
| 884 | ap += align_up (TYPE_LENGTH (type), 16); |
| 885 | } |
| 886 | } |
| 887 | |
| 888 | /* Allocate stack frame header. */ |
| 889 | sp -= 32; |
| 890 | |
| 891 | /* Finally, update the SP register. */ |
| 892 | regcache_cooked_write_unsigned (regcache, SPU_SP_REGNUM, sp); |
| 893 | |
| 894 | return sp; |
| 895 | } |
| 896 | |
| 897 | static struct frame_id |
| 898 | spu_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 899 | { |
| 900 | return frame_id_build (spu_unwind_sp (gdbarch, next_frame), |
| 901 | spu_unwind_pc (gdbarch, next_frame)); |
| 902 | } |
| 903 | |
| 904 | /* Function return value access. */ |
| 905 | |
| 906 | static enum return_value_convention |
| 907 | spu_return_value (struct gdbarch *gdbarch, struct type *type, |
| 908 | struct regcache *regcache, gdb_byte *out, const gdb_byte *in) |
| 909 | { |
| 910 | enum return_value_convention rvc; |
| 911 | |
| 912 | if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16) |
| 913 | rvc = RETURN_VALUE_REGISTER_CONVENTION; |
| 914 | else |
| 915 | rvc = RETURN_VALUE_STRUCT_CONVENTION; |
| 916 | |
| 917 | if (in) |
| 918 | { |
| 919 | switch (rvc) |
| 920 | { |
| 921 | case RETURN_VALUE_REGISTER_CONVENTION: |
| 922 | spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in); |
| 923 | break; |
| 924 | |
| 925 | case RETURN_VALUE_STRUCT_CONVENTION: |
| 926 | error ("Cannot set function return value."); |
| 927 | break; |
| 928 | } |
| 929 | } |
| 930 | else if (out) |
| 931 | { |
| 932 | switch (rvc) |
| 933 | { |
| 934 | case RETURN_VALUE_REGISTER_CONVENTION: |
| 935 | spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out); |
| 936 | break; |
| 937 | |
| 938 | case RETURN_VALUE_STRUCT_CONVENTION: |
| 939 | error ("Function return value unknown."); |
| 940 | break; |
| 941 | } |
| 942 | } |
| 943 | |
| 944 | return rvc; |
| 945 | } |
| 946 | |
| 947 | |
| 948 | /* Breakpoints. */ |
| 949 | |
| 950 | static const gdb_byte * |
| 951 | spu_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) |
| 952 | { |
| 953 | static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff }; |
| 954 | |
| 955 | *lenptr = sizeof breakpoint; |
| 956 | return breakpoint; |
| 957 | } |
| 958 | |
| 959 | |
| 960 | /* Software single-stepping support. */ |
| 961 | |
| 962 | void |
| 963 | spu_software_single_step (enum target_signal signal, int insert_breakpoints_p) |
| 964 | { |
| 965 | if (insert_breakpoints_p) |
| 966 | { |
| 967 | CORE_ADDR pc, next_pc; |
| 968 | unsigned int insn; |
| 969 | int offset, reg; |
| 970 | gdb_byte buf[4]; |
| 971 | |
| 972 | regcache_cooked_read (current_regcache, SPU_PC_REGNUM, buf); |
| 973 | pc = extract_unsigned_integer (buf, 4); |
| 974 | |
| 975 | if (target_read_memory (pc, buf, 4)) |
| 976 | return; |
| 977 | insn = extract_unsigned_integer (buf, 4); |
| 978 | |
| 979 | /* Next sequential instruction is at PC + 4, except if the current |
| 980 | instruction is a PPE-assisted call, in which case it is at PC + 8. |
| 981 | Wrap around LS limit to be on the safe side. */ |
| 982 | if ((insn & 0xffffff00) == 0x00002100) |
| 983 | next_pc = (pc + 8) & (SPU_LS_SIZE - 1) & -4; |
| 984 | else |
| 985 | next_pc = (pc + 4) & (SPU_LS_SIZE - 1) & -4; |
| 986 | |
| 987 | insert_single_step_breakpoint (next_pc); |
| 988 | |
| 989 | if (is_branch (insn, &offset, ®)) |
| 990 | { |
| 991 | CORE_ADDR target = offset; |
| 992 | |
| 993 | if (reg == SPU_PC_REGNUM) |
| 994 | target += pc; |
| 995 | else if (reg != -1) |
| 996 | { |
| 997 | regcache_cooked_read_part (current_regcache, reg, 0, 4, buf); |
| 998 | target += extract_unsigned_integer (buf, 4); |
| 999 | } |
| 1000 | |
| 1001 | target = target & (SPU_LS_SIZE - 1) & -4; |
| 1002 | if (target != next_pc) |
| 1003 | insert_single_step_breakpoint (target); |
| 1004 | } |
| 1005 | } |
| 1006 | else |
| 1007 | remove_single_step_breakpoints (); |
| 1008 | } |
| 1009 | |
| 1010 | |
| 1011 | /* Set up gdbarch struct. */ |
| 1012 | |
| 1013 | static struct gdbarch * |
| 1014 | spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 1015 | { |
| 1016 | struct gdbarch *gdbarch; |
| 1017 | |
| 1018 | /* Find a candidate among the list of pre-declared architectures. */ |
| 1019 | arches = gdbarch_list_lookup_by_info (arches, &info); |
| 1020 | if (arches != NULL) |
| 1021 | return arches->gdbarch; |
| 1022 | |
| 1023 | /* Is is for us? */ |
| 1024 | if (info.bfd_arch_info->mach != bfd_mach_spu) |
| 1025 | return NULL; |
| 1026 | |
| 1027 | /* Yes, create a new architecture. */ |
| 1028 | gdbarch = gdbarch_alloc (&info, NULL); |
| 1029 | |
| 1030 | /* Disassembler. */ |
| 1031 | set_gdbarch_print_insn (gdbarch, print_insn_spu); |
| 1032 | |
| 1033 | /* Registers. */ |
| 1034 | set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS); |
| 1035 | set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS); |
| 1036 | set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM); |
| 1037 | set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM); |
| 1038 | set_gdbarch_register_name (gdbarch, spu_register_name); |
| 1039 | set_gdbarch_register_type (gdbarch, spu_register_type); |
| 1040 | set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read); |
| 1041 | set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write); |
| 1042 | set_gdbarch_value_from_register (gdbarch, spu_value_from_register); |
| 1043 | set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p); |
| 1044 | |
| 1045 | /* Data types. */ |
| 1046 | set_gdbarch_char_signed (gdbarch, 0); |
| 1047 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 1048 | set_gdbarch_addr_bit (gdbarch, 32); |
| 1049 | set_gdbarch_short_bit (gdbarch, 16); |
| 1050 | set_gdbarch_int_bit (gdbarch, 32); |
| 1051 | set_gdbarch_long_bit (gdbarch, 32); |
| 1052 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 1053 | set_gdbarch_float_bit (gdbarch, 32); |
| 1054 | set_gdbarch_double_bit (gdbarch, 64); |
| 1055 | set_gdbarch_long_double_bit (gdbarch, 64); |
| 1056 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
| 1057 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); |
| 1058 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); |
| 1059 | |
| 1060 | /* Inferior function calls. */ |
| 1061 | set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call); |
| 1062 | set_gdbarch_unwind_dummy_id (gdbarch, spu_unwind_dummy_id); |
| 1063 | set_gdbarch_return_value (gdbarch, spu_return_value); |
| 1064 | |
| 1065 | /* Frame handling. */ |
| 1066 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 1067 | frame_unwind_append_sniffer (gdbarch, spu_frame_sniffer); |
| 1068 | frame_base_set_default (gdbarch, &spu_frame_base); |
| 1069 | set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc); |
| 1070 | set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp); |
| 1071 | set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer); |
| 1072 | set_gdbarch_frame_args_skip (gdbarch, 0); |
| 1073 | set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue); |
| 1074 | |
| 1075 | /* Breakpoints. */ |
| 1076 | set_gdbarch_decr_pc_after_break (gdbarch, 4); |
| 1077 | set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc); |
| 1078 | set_gdbarch_cannot_step_breakpoint (gdbarch, 1); |
| 1079 | set_gdbarch_software_single_step (gdbarch, spu_software_single_step); |
| 1080 | |
| 1081 | return gdbarch; |
| 1082 | } |
| 1083 | |
| 1084 | /* Implement a SPU-specific vector type as replacement |
| 1085 | for __gdb_builtin_type_vec128. */ |
| 1086 | static void |
| 1087 | spu_init_vector_type (void) |
| 1088 | { |
| 1089 | struct type *type; |
| 1090 | |
| 1091 | type = init_composite_type ("__spu_builtin_type_vec128", TYPE_CODE_UNION); |
| 1092 | append_composite_type_field (type, "uint128", builtin_type_int128); |
| 1093 | append_composite_type_field (type, "v2_int64", builtin_type_v2_int64); |
| 1094 | append_composite_type_field (type, "v4_int32", builtin_type_v4_int32); |
| 1095 | append_composite_type_field (type, "v8_int16", builtin_type_v8_int16); |
| 1096 | append_composite_type_field (type, "v16_int8", builtin_type_v16_int8); |
| 1097 | append_composite_type_field (type, "v2_double", builtin_type_v2_double); |
| 1098 | append_composite_type_field (type, "v4_float", builtin_type_v4_float); |
| 1099 | |
| 1100 | TYPE_FLAGS (type) |= TYPE_FLAG_VECTOR; |
| 1101 | TYPE_NAME (type) = "spu_builtin_type_vec128"; |
| 1102 | spu_builtin_type_vec128 = type; |
| 1103 | } |
| 1104 | |
| 1105 | void |
| 1106 | _initialize_spu_tdep (void) |
| 1107 | { |
| 1108 | register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init); |
| 1109 | |
| 1110 | spu_init_vector_type (); |
| 1111 | } |