| 1 | /* Target-dependent code for the NEC V850 for GDB, the GNU debugger. |
| 2 | |
| 3 | Copyright (C) 1996-2015 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #include "defs.h" |
| 21 | #include "frame.h" |
| 22 | #include "frame-base.h" |
| 23 | #include "trad-frame.h" |
| 24 | #include "frame-unwind.h" |
| 25 | #include "dwarf2-frame.h" |
| 26 | #include "gdbtypes.h" |
| 27 | #include "inferior.h" |
| 28 | #include "gdbcore.h" |
| 29 | #include "arch-utils.h" |
| 30 | #include "regcache.h" |
| 31 | #include "dis-asm.h" |
| 32 | #include "osabi.h" |
| 33 | #include "elf-bfd.h" |
| 34 | #include "elf/v850.h" |
| 35 | |
| 36 | enum |
| 37 | { |
| 38 | /* General purpose registers. */ |
| 39 | E_R0_REGNUM, |
| 40 | E_R1_REGNUM, |
| 41 | E_R2_REGNUM, |
| 42 | E_R3_REGNUM, E_SP_REGNUM = E_R3_REGNUM, |
| 43 | E_R4_REGNUM, |
| 44 | E_R5_REGNUM, |
| 45 | E_R6_REGNUM, E_ARG0_REGNUM = E_R6_REGNUM, |
| 46 | E_R7_REGNUM, |
| 47 | E_R8_REGNUM, |
| 48 | E_R9_REGNUM, E_ARGLAST_REGNUM = E_R9_REGNUM, |
| 49 | E_R10_REGNUM, E_V0_REGNUM = E_R10_REGNUM, |
| 50 | E_R11_REGNUM, E_V1_REGNUM = E_R11_REGNUM, |
| 51 | E_R12_REGNUM, |
| 52 | E_R13_REGNUM, |
| 53 | E_R14_REGNUM, |
| 54 | E_R15_REGNUM, |
| 55 | E_R16_REGNUM, |
| 56 | E_R17_REGNUM, |
| 57 | E_R18_REGNUM, |
| 58 | E_R19_REGNUM, |
| 59 | E_R20_REGNUM, |
| 60 | E_R21_REGNUM, |
| 61 | E_R22_REGNUM, |
| 62 | E_R23_REGNUM, |
| 63 | E_R24_REGNUM, |
| 64 | E_R25_REGNUM, |
| 65 | E_R26_REGNUM, |
| 66 | E_R27_REGNUM, |
| 67 | E_R28_REGNUM, |
| 68 | E_R29_REGNUM, E_FP_REGNUM = E_R29_REGNUM, |
| 69 | E_R30_REGNUM, E_EP_REGNUM = E_R30_REGNUM, |
| 70 | E_R31_REGNUM, E_LP_REGNUM = E_R31_REGNUM, |
| 71 | |
| 72 | /* System registers - main banks. */ |
| 73 | E_R32_REGNUM, E_SR0_REGNUM = E_R32_REGNUM, |
| 74 | E_R33_REGNUM, |
| 75 | E_R34_REGNUM, |
| 76 | E_R35_REGNUM, |
| 77 | E_R36_REGNUM, |
| 78 | E_R37_REGNUM, E_PS_REGNUM = E_R37_REGNUM, |
| 79 | E_R38_REGNUM, |
| 80 | E_R39_REGNUM, |
| 81 | E_R40_REGNUM, |
| 82 | E_R41_REGNUM, |
| 83 | E_R42_REGNUM, |
| 84 | E_R43_REGNUM, |
| 85 | E_R44_REGNUM, |
| 86 | E_R45_REGNUM, |
| 87 | E_R46_REGNUM, |
| 88 | E_R47_REGNUM, |
| 89 | E_R48_REGNUM, |
| 90 | E_R49_REGNUM, |
| 91 | E_R50_REGNUM, |
| 92 | E_R51_REGNUM, |
| 93 | E_R52_REGNUM, E_CTBP_REGNUM = E_R52_REGNUM, |
| 94 | E_R53_REGNUM, |
| 95 | E_R54_REGNUM, |
| 96 | E_R55_REGNUM, |
| 97 | E_R56_REGNUM, |
| 98 | E_R57_REGNUM, |
| 99 | E_R58_REGNUM, |
| 100 | E_R59_REGNUM, |
| 101 | E_R60_REGNUM, |
| 102 | E_R61_REGNUM, |
| 103 | E_R62_REGNUM, |
| 104 | E_R63_REGNUM, |
| 105 | |
| 106 | /* PC. */ |
| 107 | E_R64_REGNUM, E_PC_REGNUM = E_R64_REGNUM, |
| 108 | E_R65_REGNUM, |
| 109 | E_NUM_OF_V850_REGS, |
| 110 | E_NUM_OF_V850E_REGS = E_NUM_OF_V850_REGS, |
| 111 | |
| 112 | /* System registers - MPV (PROT00) bank. */ |
| 113 | E_R66_REGNUM = E_NUM_OF_V850_REGS, |
| 114 | E_R67_REGNUM, |
| 115 | E_R68_REGNUM, |
| 116 | E_R69_REGNUM, |
| 117 | E_R70_REGNUM, |
| 118 | E_R71_REGNUM, |
| 119 | E_R72_REGNUM, |
| 120 | E_R73_REGNUM, |
| 121 | E_R74_REGNUM, |
| 122 | E_R75_REGNUM, |
| 123 | E_R76_REGNUM, |
| 124 | E_R77_REGNUM, |
| 125 | E_R78_REGNUM, |
| 126 | E_R79_REGNUM, |
| 127 | E_R80_REGNUM, |
| 128 | E_R81_REGNUM, |
| 129 | E_R82_REGNUM, |
| 130 | E_R83_REGNUM, |
| 131 | E_R84_REGNUM, |
| 132 | E_R85_REGNUM, |
| 133 | E_R86_REGNUM, |
| 134 | E_R87_REGNUM, |
| 135 | E_R88_REGNUM, |
| 136 | E_R89_REGNUM, |
| 137 | E_R90_REGNUM, |
| 138 | E_R91_REGNUM, |
| 139 | E_R92_REGNUM, |
| 140 | E_R93_REGNUM, |
| 141 | |
| 142 | /* System registers - MPU (PROT01) bank. */ |
| 143 | E_R94_REGNUM, |
| 144 | E_R95_REGNUM, |
| 145 | E_R96_REGNUM, |
| 146 | E_R97_REGNUM, |
| 147 | E_R98_REGNUM, |
| 148 | E_R99_REGNUM, |
| 149 | E_R100_REGNUM, |
| 150 | E_R101_REGNUM, |
| 151 | E_R102_REGNUM, |
| 152 | E_R103_REGNUM, |
| 153 | E_R104_REGNUM, |
| 154 | E_R105_REGNUM, |
| 155 | E_R106_REGNUM, |
| 156 | E_R107_REGNUM, |
| 157 | E_R108_REGNUM, |
| 158 | E_R109_REGNUM, |
| 159 | E_R110_REGNUM, |
| 160 | E_R111_REGNUM, |
| 161 | E_R112_REGNUM, |
| 162 | E_R113_REGNUM, |
| 163 | E_R114_REGNUM, |
| 164 | E_R115_REGNUM, |
| 165 | E_R116_REGNUM, |
| 166 | E_R117_REGNUM, |
| 167 | E_R118_REGNUM, |
| 168 | E_R119_REGNUM, |
| 169 | E_R120_REGNUM, |
| 170 | E_R121_REGNUM, |
| 171 | |
| 172 | /* FPU system registers. */ |
| 173 | E_R122_REGNUM, |
| 174 | E_R123_REGNUM, |
| 175 | E_R124_REGNUM, |
| 176 | E_R125_REGNUM, |
| 177 | E_R126_REGNUM, |
| 178 | E_R127_REGNUM, |
| 179 | E_R128_REGNUM, E_FPSR_REGNUM = E_R128_REGNUM, |
| 180 | E_R129_REGNUM, E_FPEPC_REGNUM = E_R129_REGNUM, |
| 181 | E_R130_REGNUM, E_FPST_REGNUM = E_R130_REGNUM, |
| 182 | E_R131_REGNUM, E_FPCC_REGNUM = E_R131_REGNUM, |
| 183 | E_R132_REGNUM, E_FPCFG_REGNUM = E_R132_REGNUM, |
| 184 | E_R133_REGNUM, |
| 185 | E_R134_REGNUM, |
| 186 | E_R135_REGNUM, |
| 187 | E_R136_REGNUM, |
| 188 | E_R137_REGNUM, |
| 189 | E_R138_REGNUM, |
| 190 | E_R139_REGNUM, |
| 191 | E_R140_REGNUM, |
| 192 | E_R141_REGNUM, |
| 193 | E_R142_REGNUM, |
| 194 | E_R143_REGNUM, |
| 195 | E_R144_REGNUM, |
| 196 | E_R145_REGNUM, |
| 197 | E_R146_REGNUM, |
| 198 | E_R147_REGNUM, |
| 199 | E_R148_REGNUM, |
| 200 | E_R149_REGNUM, |
| 201 | E_NUM_OF_V850E2_REGS, |
| 202 | |
| 203 | /* v850e3v5 system registers, selID 1 thru 7. */ |
| 204 | E_SELID_1_R0_REGNUM = E_NUM_OF_V850E2_REGS, |
| 205 | E_SELID_1_R31_REGNUM = E_SELID_1_R0_REGNUM + 31, |
| 206 | |
| 207 | E_SELID_2_R0_REGNUM, |
| 208 | E_SELID_2_R31_REGNUM = E_SELID_2_R0_REGNUM + 31, |
| 209 | |
| 210 | E_SELID_3_R0_REGNUM, |
| 211 | E_SELID_3_R31_REGNUM = E_SELID_3_R0_REGNUM + 31, |
| 212 | |
| 213 | E_SELID_4_R0_REGNUM, |
| 214 | E_SELID_4_R31_REGNUM = E_SELID_4_R0_REGNUM + 31, |
| 215 | |
| 216 | E_SELID_5_R0_REGNUM, |
| 217 | E_SELID_5_R31_REGNUM = E_SELID_5_R0_REGNUM + 31, |
| 218 | |
| 219 | E_SELID_6_R0_REGNUM, |
| 220 | E_SELID_6_R31_REGNUM = E_SELID_6_R0_REGNUM + 31, |
| 221 | |
| 222 | E_SELID_7_R0_REGNUM, |
| 223 | E_SELID_7_R31_REGNUM = E_SELID_7_R0_REGNUM + 31, |
| 224 | |
| 225 | /* v850e3v5 vector registers. */ |
| 226 | E_VR0_REGNUM, |
| 227 | E_VR31_REGNUM = E_VR0_REGNUM + 31, |
| 228 | |
| 229 | E_NUM_OF_V850E3V5_REGS, |
| 230 | |
| 231 | /* Total number of possible registers. */ |
| 232 | E_NUM_REGS = E_NUM_OF_V850E3V5_REGS |
| 233 | }; |
| 234 | |
| 235 | enum |
| 236 | { |
| 237 | v850_reg_size = 4 |
| 238 | }; |
| 239 | |
| 240 | /* Size of return datatype which fits into all return registers. */ |
| 241 | enum |
| 242 | { |
| 243 | E_MAX_RETTYPE_SIZE_IN_REGS = 2 * v850_reg_size |
| 244 | }; |
| 245 | |
| 246 | /* When v850 support was added to GCC in the late nineties, the intention |
| 247 | was to follow the Green Hills ABI for v850. In fact, the authors of |
| 248 | that support at the time thought that they were doing so. As far as |
| 249 | I can tell, the calling conventions are correct, but the return value |
| 250 | conventions were not quite right. Over time, the return value code |
| 251 | in this file was modified to mostly reflect what GCC was actually |
| 252 | doing instead of to actually follow the Green Hills ABI as it did |
| 253 | when the code was first written. |
| 254 | |
| 255 | Renesas defined the RH850 ABI which they use in their compiler. It |
| 256 | is similar to the original Green Hills ABI with some minor |
| 257 | differences. */ |
| 258 | |
| 259 | enum v850_abi |
| 260 | { |
| 261 | V850_ABI_GCC, |
| 262 | V850_ABI_RH850 |
| 263 | }; |
| 264 | |
| 265 | /* Architecture specific data. */ |
| 266 | |
| 267 | struct gdbarch_tdep |
| 268 | { |
| 269 | /* Fields from the ELF header. */ |
| 270 | int e_flags; |
| 271 | int e_machine; |
| 272 | |
| 273 | /* Which ABI are we using? */ |
| 274 | enum v850_abi abi; |
| 275 | int eight_byte_align; |
| 276 | }; |
| 277 | |
| 278 | struct v850_frame_cache |
| 279 | { |
| 280 | /* Base address. */ |
| 281 | CORE_ADDR base; |
| 282 | LONGEST sp_offset; |
| 283 | CORE_ADDR pc; |
| 284 | |
| 285 | /* Flag showing that a frame has been created in the prologue code. */ |
| 286 | int uses_fp; |
| 287 | |
| 288 | /* Saved registers. */ |
| 289 | struct trad_frame_saved_reg *saved_regs; |
| 290 | }; |
| 291 | |
| 292 | /* Info gleaned from scanning a function's prologue. */ |
| 293 | struct pifsr /* Info about one saved register. */ |
| 294 | { |
| 295 | int offset; /* Offset from sp or fp. */ |
| 296 | int cur_frameoffset; /* Current frameoffset. */ |
| 297 | int reg; /* Saved register number. */ |
| 298 | }; |
| 299 | |
| 300 | static const char * |
| 301 | v850_register_name (struct gdbarch *gdbarch, int regnum) |
| 302 | { |
| 303 | static const char *v850_reg_names[] = |
| 304 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 305 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 306 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
| 307 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
| 308 | "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7", |
| 309 | "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15", |
| 310 | "sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23", |
| 311 | "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31", |
| 312 | "pc", "fp" |
| 313 | }; |
| 314 | if (regnum < 0 || regnum > E_NUM_OF_V850_REGS) |
| 315 | return NULL; |
| 316 | return v850_reg_names[regnum]; |
| 317 | } |
| 318 | |
| 319 | static const char * |
| 320 | v850e_register_name (struct gdbarch *gdbarch, int regnum) |
| 321 | { |
| 322 | static const char *v850e_reg_names[] = |
| 323 | { |
| 324 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 325 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 326 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
| 327 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
| 328 | "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7", |
| 329 | "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15", |
| 330 | "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23", |
| 331 | "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31", |
| 332 | "pc", "fp" |
| 333 | }; |
| 334 | if (regnum < 0 || regnum > E_NUM_OF_V850E_REGS) |
| 335 | return NULL; |
| 336 | return v850e_reg_names[regnum]; |
| 337 | } |
| 338 | |
| 339 | static const char * |
| 340 | v850e2_register_name (struct gdbarch *gdbarch, int regnum) |
| 341 | { |
| 342 | static const char *v850e2_reg_names[] = |
| 343 | { |
| 344 | /* General purpose registers. */ |
| 345 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 346 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 347 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
| 348 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
| 349 | |
| 350 | /* System registers - main banks. */ |
| 351 | "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "pid", "cfg", |
| 352 | "", "", "", "sccfg", "scbp", "eiic", "feic", "dbic", |
| 353 | "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "dir", "", "", |
| 354 | "", "", "", "", "eiwr", "fewr", "dbwr", "bsel", |
| 355 | |
| 356 | |
| 357 | /* PC. */ |
| 358 | "pc", "", |
| 359 | |
| 360 | /* System registers - MPV (PROT00) bank. */ |
| 361 | "vsecr", "vstid", "vsadr", "", "vmecr", "vmtid", "vmadr", "", |
| 362 | "vpecr", "vptid", "vpadr", "", "", "", "", "", |
| 363 | "", "", "", "", "", "", "", "", |
| 364 | "mca", "mcs", "mcc", "mcr", |
| 365 | |
| 366 | /* System registers - MPU (PROT01) bank. */ |
| 367 | "mpm", "mpc", "tid", "", "", "", "ipa0l", "ipa0u", |
| 368 | "ipa1l", "ipa1u", "ipa2l", "ipa2u", "ipa3l", "ipa3u", "ipa4l", "ipa4u", |
| 369 | "dpa0l", "dpa0u", "dpa1l", "dpa1u", "dpa2l", "dpa2u", "dpa3l", "dpa3u", |
| 370 | "dpa4l", "dpa4u", "dpa5l", "dpa5u", |
| 371 | |
| 372 | /* FPU system registers. */ |
| 373 | "", "", "", "", "", "", "fpsr", "fpepc", |
| 374 | "fpst", "fpcc", "fpcfg", "fpec", "", "", "", "", |
| 375 | "", "", "", "", "", "", "", "", |
| 376 | "", "", "", "fpspc" |
| 377 | }; |
| 378 | if (regnum < 0 || regnum >= E_NUM_OF_V850E2_REGS) |
| 379 | return NULL; |
| 380 | return v850e2_reg_names[regnum]; |
| 381 | } |
| 382 | |
| 383 | /* Implement the "register_name" gdbarch method for v850e3v5. */ |
| 384 | |
| 385 | static const char * |
| 386 | v850e3v5_register_name (struct gdbarch *gdbarch, int regnum) |
| 387 | { |
| 388 | static const char *v850e3v5_reg_names[] = |
| 389 | { |
| 390 | /* General purpose registers. */ |
| 391 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 392 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 393 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
| 394 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
| 395 | |
| 396 | /* selID 0, not including FPU registers. The FPU registers are |
| 397 | listed later on. */ |
| 398 | "eipc", "eipsw", "fepc", "fepsw", |
| 399 | "", "psw", "" /* fpsr */, "" /* fpepc */, |
| 400 | "" /* fpst */, "" /* fpcc */, "" /* fpcfg */, "" /* fpec */, |
| 401 | "sesr", "eiic", "feic", "", |
| 402 | "ctpc", "ctpsw", "", "", "ctbp", "", "", "", |
| 403 | "", "", "", "", "eiwr", "fewr", "", "bsel", |
| 404 | |
| 405 | |
| 406 | /* PC. */ |
| 407 | "pc", "", |
| 408 | |
| 409 | /* v850e2 MPV bank. */ |
| 410 | "", "", "", "", "", "", "", "", |
| 411 | "", "", "", "", "", "", "", "", |
| 412 | "", "", "", "", "", "", "", "", |
| 413 | "", "", "", "", |
| 414 | |
| 415 | /* Skip v850e2 MPU bank. It's tempting to reuse these, but we need |
| 416 | 32 entries for this bank. */ |
| 417 | "", "", "", "", "", "", "", "", |
| 418 | "", "", "", "", "", "", "", "", |
| 419 | "", "", "", "", "", "", "", "", |
| 420 | "", "", "", "", |
| 421 | |
| 422 | /* FPU system registers. These are actually in selID 0, but |
| 423 | are placed here to preserve register numbering compatibility |
| 424 | with previous architectures. */ |
| 425 | "", "", "", "", "", "", "fpsr", "fpepc", |
| 426 | "fpst", "fpcc", "fpcfg", "fpec", "", "", "", "", |
| 427 | "", "", "", "", "", "", "", "", |
| 428 | "", "", "", "", |
| 429 | |
| 430 | /* selID 1. */ |
| 431 | "mcfg0", "mcfg1", "rbase", "ebase", "intbp", "mctl", "pid", "fpipr", |
| 432 | "", "", "tcsel", "sccfg", "scbp", "hvccfg", "hvcbp", "vsel", |
| 433 | "vmprt0", "vmprt1", "vmprt2", "", "", "", "", "vmscctl", |
| 434 | "vmsctbl0", "vmsctbl1", "vmsctbl2", "vmsctbl3", "", "", "", "", |
| 435 | |
| 436 | /* selID 2. */ |
| 437 | "htcfg0", "", "", "", "", "htctl", "mea", "asid", |
| 438 | "mei", "ispr", "pmr", "icsr", "intcfg", "", "", "", |
| 439 | "tlbsch", "", "", "", "", "", "", "htscctl", |
| 440 | "htsctbl0", "htsctbl1", "htsctbl2", "htsctbl3", |
| 441 | "htsctbl4", "htsctbl5", "htsctbl6", "htsctbl7", |
| 442 | |
| 443 | /* selID 3. */ |
| 444 | "", "", "", "", "", "", "", "", |
| 445 | "", "", "", "", "", "", "", "", |
| 446 | "", "", "", "", "", "", "", "", |
| 447 | "", "", "", "", "", "", "", "", |
| 448 | |
| 449 | /* selID 4. */ |
| 450 | "tlbidx", "", "", "", "telo0", "telo1", "tehi0", "tehi1", |
| 451 | "", "", "tlbcfg", "", "bwerrl", "bwerrh", "brerrl", "brerrh", |
| 452 | "ictagl", "ictagh", "icdatl", "icdath", |
| 453 | "dctagl", "dctagh", "dcdatl", "dcdath", |
| 454 | "icctrl", "dcctrl", "iccfg", "dccfg", "icerr", "dcerr", "", "", |
| 455 | |
| 456 | /* selID 5. */ |
| 457 | "mpm", "mprc", "", "", "mpbrgn", "mptrgn", "", "", |
| 458 | "mca", "mcs", "mcc", "mcr", "", "", "", "", |
| 459 | "", "", "", "", "mpprt0", "mpprt1", "mpprt2", "", |
| 460 | "", "", "", "", "", "", "", "", |
| 461 | |
| 462 | /* selID 6. */ |
| 463 | "mpla0", "mpua0", "mpat0", "", "mpla1", "mpua1", "mpat1", "", |
| 464 | "mpla2", "mpua2", "mpat2", "", "mpla3", "mpua3", "mpat3", "", |
| 465 | "mpla4", "mpua4", "mpat4", "", "mpla5", "mpua5", "mpat5", "", |
| 466 | "mpla6", "mpua6", "mpat6", "", "mpla7", "mpua7", "mpat7", "", |
| 467 | |
| 468 | /* selID 7. */ |
| 469 | "mpla8", "mpua8", "mpat8", "", "mpla9", "mpua9", "mpat9", "", |
| 470 | "mpla10", "mpua10", "mpat10", "", "mpla11", "mpua11", "mpat11", "", |
| 471 | "mpla12", "mpua12", "mpat12", "", "mpla13", "mpua13", "mpat13", "", |
| 472 | "mpla14", "mpua14", "mpat14", "", "mpla15", "mpua15", "mpat15", "", |
| 473 | |
| 474 | /* Vector Registers */ |
| 475 | "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", |
| 476 | "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", |
| 477 | "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23", |
| 478 | "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31", |
| 479 | }; |
| 480 | |
| 481 | if (regnum < 0 || regnum >= E_NUM_OF_V850E3V5_REGS) |
| 482 | return NULL; |
| 483 | return v850e3v5_reg_names[regnum]; |
| 484 | } |
| 485 | |
| 486 | /* Returns the default type for register N. */ |
| 487 | |
| 488 | static struct type * |
| 489 | v850_register_type (struct gdbarch *gdbarch, int regnum) |
| 490 | { |
| 491 | if (regnum == E_PC_REGNUM) |
| 492 | return builtin_type (gdbarch)->builtin_func_ptr; |
| 493 | else if (E_VR0_REGNUM <= regnum && regnum <= E_VR31_REGNUM) |
| 494 | return builtin_type (gdbarch)->builtin_uint64; |
| 495 | return builtin_type (gdbarch)->builtin_int32; |
| 496 | } |
| 497 | |
| 498 | static int |
| 499 | v850_type_is_scalar (struct type *t) |
| 500 | { |
| 501 | return (TYPE_CODE (t) != TYPE_CODE_STRUCT |
| 502 | && TYPE_CODE (t) != TYPE_CODE_UNION |
| 503 | && TYPE_CODE (t) != TYPE_CODE_ARRAY); |
| 504 | } |
| 505 | |
| 506 | /* Should call_function allocate stack space for a struct return? */ |
| 507 | |
| 508 | static int |
| 509 | v850_use_struct_convention (struct gdbarch *gdbarch, struct type *type) |
| 510 | { |
| 511 | int i; |
| 512 | struct type *fld_type, *tgt_type; |
| 513 | |
| 514 | if (gdbarch_tdep (gdbarch)->abi == V850_ABI_RH850) |
| 515 | { |
| 516 | if (v850_type_is_scalar (type) && TYPE_LENGTH(type) <= 8) |
| 517 | return 0; |
| 518 | |
| 519 | /* Structs are never returned in registers for this ABI. */ |
| 520 | return 1; |
| 521 | } |
| 522 | /* 1. The value is greater than 8 bytes -> returned by copying. */ |
| 523 | if (TYPE_LENGTH (type) > 8) |
| 524 | return 1; |
| 525 | |
| 526 | /* 2. The value is a single basic type -> returned in register. */ |
| 527 | if (v850_type_is_scalar (type)) |
| 528 | return 0; |
| 529 | |
| 530 | /* The value is a structure or union with a single element and that |
| 531 | element is either a single basic type or an array of a single basic |
| 532 | type whose size is greater than or equal to 4 -> returned in register. */ |
| 533 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 534 | || TYPE_CODE (type) == TYPE_CODE_UNION) |
| 535 | && TYPE_NFIELDS (type) == 1) |
| 536 | { |
| 537 | fld_type = TYPE_FIELD_TYPE (type, 0); |
| 538 | if (v850_type_is_scalar (fld_type) && TYPE_LENGTH (fld_type) >= 4) |
| 539 | return 0; |
| 540 | |
| 541 | if (TYPE_CODE (fld_type) == TYPE_CODE_ARRAY) |
| 542 | { |
| 543 | tgt_type = TYPE_TARGET_TYPE (fld_type); |
| 544 | if (v850_type_is_scalar (tgt_type) && TYPE_LENGTH (tgt_type) >= 4) |
| 545 | return 0; |
| 546 | } |
| 547 | } |
| 548 | |
| 549 | /* The value is a structure whose first element is an integer or a float, |
| 550 | and which contains no arrays of more than two elements -> returned in |
| 551 | register. */ |
| 552 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 553 | && v850_type_is_scalar (TYPE_FIELD_TYPE (type, 0)) |
| 554 | && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4) |
| 555 | { |
| 556 | for (i = 1; i < TYPE_NFIELDS (type); ++i) |
| 557 | { |
| 558 | fld_type = TYPE_FIELD_TYPE (type, 0); |
| 559 | if (TYPE_CODE (fld_type) == TYPE_CODE_ARRAY) |
| 560 | { |
| 561 | tgt_type = TYPE_TARGET_TYPE (fld_type); |
| 562 | if (TYPE_LENGTH (fld_type) >= 0 && TYPE_LENGTH (tgt_type) >= 0 |
| 563 | && TYPE_LENGTH (fld_type) / TYPE_LENGTH (tgt_type) > 2) |
| 564 | return 1; |
| 565 | } |
| 566 | } |
| 567 | return 0; |
| 568 | } |
| 569 | |
| 570 | /* The value is a union which contains at least one field which |
| 571 | would be returned in registers according to these rules -> |
| 572 | returned in register. */ |
| 573 | if (TYPE_CODE (type) == TYPE_CODE_UNION) |
| 574 | { |
| 575 | for (i = 0; i < TYPE_NFIELDS (type); ++i) |
| 576 | { |
| 577 | fld_type = TYPE_FIELD_TYPE (type, 0); |
| 578 | if (!v850_use_struct_convention (gdbarch, fld_type)) |
| 579 | return 0; |
| 580 | } |
| 581 | } |
| 582 | |
| 583 | return 1; |
| 584 | } |
| 585 | |
| 586 | /* Structure for mapping bits in register lists to register numbers. */ |
| 587 | |
| 588 | struct reg_list |
| 589 | { |
| 590 | long mask; |
| 591 | int regno; |
| 592 | }; |
| 593 | |
| 594 | /* Helper function for v850_scan_prologue to handle prepare instruction. */ |
| 595 | |
| 596 | static void |
| 597 | v850_handle_prepare (int insn, int insn2, CORE_ADDR * current_pc_ptr, |
| 598 | struct v850_frame_cache *pi, struct pifsr **pifsr_ptr) |
| 599 | { |
| 600 | CORE_ADDR current_pc = *current_pc_ptr; |
| 601 | struct pifsr *pifsr = *pifsr_ptr; |
| 602 | long next = insn2 & 0xffff; |
| 603 | long list12 = ((insn & 1) << 16) + (next & 0xffe0); |
| 604 | long offset = (insn & 0x3e) << 1; |
| 605 | static struct reg_list reg_table[] = |
| 606 | { |
| 607 | {0x00800, 20}, /* r20 */ |
| 608 | {0x00400, 21}, /* r21 */ |
| 609 | {0x00200, 22}, /* r22 */ |
| 610 | {0x00100, 23}, /* r23 */ |
| 611 | {0x08000, 24}, /* r24 */ |
| 612 | {0x04000, 25}, /* r25 */ |
| 613 | {0x02000, 26}, /* r26 */ |
| 614 | {0x01000, 27}, /* r27 */ |
| 615 | {0x00080, 28}, /* r28 */ |
| 616 | {0x00040, 29}, /* r29 */ |
| 617 | {0x10000, 30}, /* ep */ |
| 618 | {0x00020, 31}, /* lp */ |
| 619 | {0, 0} /* end of table */ |
| 620 | }; |
| 621 | int i; |
| 622 | |
| 623 | if ((next & 0x1f) == 0x0b) /* skip imm16 argument */ |
| 624 | current_pc += 2; |
| 625 | else if ((next & 0x1f) == 0x13) /* skip imm16 argument */ |
| 626 | current_pc += 2; |
| 627 | else if ((next & 0x1f) == 0x1b) /* skip imm32 argument */ |
| 628 | current_pc += 4; |
| 629 | |
| 630 | /* Calculate the total size of the saved registers, and add it to the |
| 631 | immediate value used to adjust SP. */ |
| 632 | for (i = 0; reg_table[i].mask != 0; i++) |
| 633 | if (list12 & reg_table[i].mask) |
| 634 | offset += v850_reg_size; |
| 635 | pi->sp_offset -= offset; |
| 636 | |
| 637 | /* Calculate the offsets of the registers relative to the value the SP |
| 638 | will have after the registers have been pushed and the imm5 value has |
| 639 | been subtracted from it. */ |
| 640 | if (pifsr) |
| 641 | { |
| 642 | for (i = 0; reg_table[i].mask != 0; i++) |
| 643 | { |
| 644 | if (list12 & reg_table[i].mask) |
| 645 | { |
| 646 | int reg = reg_table[i].regno; |
| 647 | offset -= v850_reg_size; |
| 648 | pifsr->reg = reg; |
| 649 | pifsr->offset = offset; |
| 650 | pifsr->cur_frameoffset = pi->sp_offset; |
| 651 | pifsr++; |
| 652 | } |
| 653 | } |
| 654 | } |
| 655 | |
| 656 | /* Set result parameters. */ |
| 657 | *current_pc_ptr = current_pc; |
| 658 | *pifsr_ptr = pifsr; |
| 659 | } |
| 660 | |
| 661 | |
| 662 | /* Helper function for v850_scan_prologue to handle pushm/pushl instructions. |
| 663 | The SR bit of the register list is not supported. gcc does not generate |
| 664 | this bit. */ |
| 665 | |
| 666 | static void |
| 667 | v850_handle_pushm (int insn, int insn2, struct v850_frame_cache *pi, |
| 668 | struct pifsr **pifsr_ptr) |
| 669 | { |
| 670 | struct pifsr *pifsr = *pifsr_ptr; |
| 671 | long list12 = ((insn & 0x0f) << 16) + (insn2 & 0xfff0); |
| 672 | long offset = 0; |
| 673 | static struct reg_list pushml_reg_table[] = |
| 674 | { |
| 675 | {0x80000, E_PS_REGNUM}, /* PSW */ |
| 676 | {0x40000, 1}, /* r1 */ |
| 677 | {0x20000, 2}, /* r2 */ |
| 678 | {0x10000, 3}, /* r3 */ |
| 679 | {0x00800, 4}, /* r4 */ |
| 680 | {0x00400, 5}, /* r5 */ |
| 681 | {0x00200, 6}, /* r6 */ |
| 682 | {0x00100, 7}, /* r7 */ |
| 683 | {0x08000, 8}, /* r8 */ |
| 684 | {0x04000, 9}, /* r9 */ |
| 685 | {0x02000, 10}, /* r10 */ |
| 686 | {0x01000, 11}, /* r11 */ |
| 687 | {0x00080, 12}, /* r12 */ |
| 688 | {0x00040, 13}, /* r13 */ |
| 689 | {0x00020, 14}, /* r14 */ |
| 690 | {0x00010, 15}, /* r15 */ |
| 691 | {0, 0} /* end of table */ |
| 692 | }; |
| 693 | static struct reg_list pushmh_reg_table[] = |
| 694 | { |
| 695 | {0x80000, 16}, /* r16 */ |
| 696 | {0x40000, 17}, /* r17 */ |
| 697 | {0x20000, 18}, /* r18 */ |
| 698 | {0x10000, 19}, /* r19 */ |
| 699 | {0x00800, 20}, /* r20 */ |
| 700 | {0x00400, 21}, /* r21 */ |
| 701 | {0x00200, 22}, /* r22 */ |
| 702 | {0x00100, 23}, /* r23 */ |
| 703 | {0x08000, 24}, /* r24 */ |
| 704 | {0x04000, 25}, /* r25 */ |
| 705 | {0x02000, 26}, /* r26 */ |
| 706 | {0x01000, 27}, /* r27 */ |
| 707 | {0x00080, 28}, /* r28 */ |
| 708 | {0x00040, 29}, /* r29 */ |
| 709 | {0x00010, 30}, /* r30 */ |
| 710 | {0x00020, 31}, /* r31 */ |
| 711 | {0, 0} /* end of table */ |
| 712 | }; |
| 713 | struct reg_list *reg_table; |
| 714 | int i; |
| 715 | |
| 716 | /* Is this a pushml or a pushmh? */ |
| 717 | if ((insn2 & 7) == 1) |
| 718 | reg_table = pushml_reg_table; |
| 719 | else |
| 720 | reg_table = pushmh_reg_table; |
| 721 | |
| 722 | /* Calculate the total size of the saved registers, and add it to the |
| 723 | immediate value used to adjust SP. */ |
| 724 | for (i = 0; reg_table[i].mask != 0; i++) |
| 725 | if (list12 & reg_table[i].mask) |
| 726 | offset += v850_reg_size; |
| 727 | pi->sp_offset -= offset; |
| 728 | |
| 729 | /* Calculate the offsets of the registers relative to the value the SP |
| 730 | will have after the registers have been pushed and the imm5 value is |
| 731 | subtracted from it. */ |
| 732 | if (pifsr) |
| 733 | { |
| 734 | for (i = 0; reg_table[i].mask != 0; i++) |
| 735 | { |
| 736 | if (list12 & reg_table[i].mask) |
| 737 | { |
| 738 | int reg = reg_table[i].regno; |
| 739 | offset -= v850_reg_size; |
| 740 | pifsr->reg = reg; |
| 741 | pifsr->offset = offset; |
| 742 | pifsr->cur_frameoffset = pi->sp_offset; |
| 743 | pifsr++; |
| 744 | } |
| 745 | } |
| 746 | } |
| 747 | |
| 748 | /* Set result parameters. */ |
| 749 | *pifsr_ptr = pifsr; |
| 750 | } |
| 751 | |
| 752 | /* Helper function to evaluate if register is one of the "save" registers. |
| 753 | This allows to simplify conditionals in v850_analyze_prologue a lot. */ |
| 754 | |
| 755 | static int |
| 756 | v850_is_save_register (int reg) |
| 757 | { |
| 758 | /* The caller-save registers are R2, R20 - R29 and R31. All other |
| 759 | registers are either special purpose (PC, SP), argument registers, |
| 760 | or just considered free for use in the caller. */ |
| 761 | return reg == E_R2_REGNUM |
| 762 | || (reg >= E_R20_REGNUM && reg <= E_R29_REGNUM) |
| 763 | || reg == E_R31_REGNUM; |
| 764 | } |
| 765 | |
| 766 | /* Scan the prologue of the function that contains PC, and record what |
| 767 | we find in PI. Returns the pc after the prologue. Note that the |
| 768 | addresses saved in frame->saved_regs are just frame relative (negative |
| 769 | offsets from the frame pointer). This is because we don't know the |
| 770 | actual value of the frame pointer yet. In some circumstances, the |
| 771 | frame pointer can't be determined till after we have scanned the |
| 772 | prologue. */ |
| 773 | |
| 774 | static CORE_ADDR |
| 775 | v850_analyze_prologue (struct gdbarch *gdbarch, |
| 776 | CORE_ADDR func_addr, CORE_ADDR pc, |
| 777 | struct v850_frame_cache *pi, ULONGEST ctbp) |
| 778 | { |
| 779 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 780 | CORE_ADDR prologue_end, current_pc; |
| 781 | struct pifsr pifsrs[E_NUM_REGS + 1]; |
| 782 | struct pifsr *pifsr, *pifsr_tmp; |
| 783 | int ep_used; |
| 784 | int reg; |
| 785 | CORE_ADDR save_pc, save_end; |
| 786 | int regsave_func_p; |
| 787 | int r12_tmp; |
| 788 | |
| 789 | memset (&pifsrs, 0, sizeof pifsrs); |
| 790 | pifsr = &pifsrs[0]; |
| 791 | |
| 792 | prologue_end = pc; |
| 793 | |
| 794 | /* Now, search the prologue looking for instructions that setup fp, save |
| 795 | rp, adjust sp and such. We also record the frame offset of any saved |
| 796 | registers. */ |
| 797 | |
| 798 | pi->sp_offset = 0; |
| 799 | pi->uses_fp = 0; |
| 800 | ep_used = 0; |
| 801 | regsave_func_p = 0; |
| 802 | save_pc = 0; |
| 803 | save_end = 0; |
| 804 | r12_tmp = 0; |
| 805 | |
| 806 | for (current_pc = func_addr; current_pc < prologue_end;) |
| 807 | { |
| 808 | int insn; |
| 809 | int insn2 = -1; /* dummy value */ |
| 810 | |
| 811 | insn = read_memory_integer (current_pc, 2, byte_order); |
| 812 | current_pc += 2; |
| 813 | if ((insn & 0x0780) >= 0x0600) /* Four byte instruction? */ |
| 814 | { |
| 815 | insn2 = read_memory_integer (current_pc, 2, byte_order); |
| 816 | current_pc += 2; |
| 817 | } |
| 818 | |
| 819 | if ((insn & 0xffc0) == ((10 << 11) | 0x0780) && !regsave_func_p) |
| 820 | { /* jarl <func>,10 */ |
| 821 | long low_disp = insn2 & ~(long) 1; |
| 822 | long disp = (((((insn & 0x3f) << 16) + low_disp) |
| 823 | & ~(long) 1) ^ 0x00200000) - 0x00200000; |
| 824 | |
| 825 | save_pc = current_pc; |
| 826 | save_end = prologue_end; |
| 827 | regsave_func_p = 1; |
| 828 | current_pc += disp - 4; |
| 829 | prologue_end = (current_pc |
| 830 | + (2 * 3) /* moves to/from ep */ |
| 831 | + 4 /* addi <const>,sp,sp */ |
| 832 | + 2 /* jmp [r10] */ |
| 833 | + (2 * 12) /* sst.w to save r2, r20-r29, r31 */ |
| 834 | + 20); /* slop area */ |
| 835 | } |
| 836 | else if ((insn & 0xffc0) == 0x0200 && !regsave_func_p) |
| 837 | { /* callt <imm6> */ |
| 838 | long adr = ctbp + ((insn & 0x3f) << 1); |
| 839 | |
| 840 | save_pc = current_pc; |
| 841 | save_end = prologue_end; |
| 842 | regsave_func_p = 1; |
| 843 | current_pc = ctbp + (read_memory_unsigned_integer (adr, 2, byte_order) |
| 844 | & 0xffff); |
| 845 | prologue_end = (current_pc |
| 846 | + (2 * 3) /* prepare list2,imm5,sp/imm */ |
| 847 | + 4 /* ctret */ |
| 848 | + 20); /* slop area */ |
| 849 | continue; |
| 850 | } |
| 851 | else if ((insn & 0xffc0) == 0x0780) /* prepare list2,imm5 */ |
| 852 | { |
| 853 | v850_handle_prepare (insn, insn2, ¤t_pc, pi, &pifsr); |
| 854 | continue; |
| 855 | } |
| 856 | else if (insn == 0x07e0 && regsave_func_p && insn2 == 0x0144) |
| 857 | { /* ctret after processing register save. */ |
| 858 | current_pc = save_pc; |
| 859 | prologue_end = save_end; |
| 860 | regsave_func_p = 0; |
| 861 | continue; |
| 862 | } |
| 863 | else if ((insn & 0xfff0) == 0x07e0 && (insn2 & 5) == 1) |
| 864 | { /* pushml, pushmh */ |
| 865 | v850_handle_pushm (insn, insn2, pi, &pifsr); |
| 866 | continue; |
| 867 | } |
| 868 | else if ((insn & 0xffe0) == 0x0060 && regsave_func_p) |
| 869 | { /* jmp after processing register save. */ |
| 870 | current_pc = save_pc; |
| 871 | prologue_end = save_end; |
| 872 | regsave_func_p = 0; |
| 873 | continue; |
| 874 | } |
| 875 | else if ((insn & 0x07c0) == 0x0780 /* jarl or jr */ |
| 876 | || (insn & 0xffe0) == 0x0060 /* jmp */ |
| 877 | || (insn & 0x0780) == 0x0580) /* branch */ |
| 878 | { |
| 879 | break; /* Ran into end of prologue. */ |
| 880 | } |
| 881 | |
| 882 | else if ((insn & 0xffe0) == ((E_SP_REGNUM << 11) | 0x0240)) |
| 883 | /* add <imm>,sp */ |
| 884 | pi->sp_offset += ((insn & 0x1f) ^ 0x10) - 0x10; |
| 885 | else if (insn == ((E_SP_REGNUM << 11) | 0x0600 | E_SP_REGNUM)) |
| 886 | /* addi <imm>,sp,sp */ |
| 887 | pi->sp_offset += insn2; |
| 888 | else if (insn == ((E_FP_REGNUM << 11) | 0x0000 | E_SP_REGNUM)) |
| 889 | /* mov sp,fp */ |
| 890 | pi->uses_fp = 1; |
| 891 | else if (insn == ((E_R12_REGNUM << 11) | 0x0640 | E_R0_REGNUM)) |
| 892 | /* movhi hi(const),r0,r12 */ |
| 893 | r12_tmp = insn2 << 16; |
| 894 | else if (insn == ((E_R12_REGNUM << 11) | 0x0620 | E_R12_REGNUM)) |
| 895 | /* movea lo(const),r12,r12 */ |
| 896 | r12_tmp += insn2; |
| 897 | else if (insn == ((E_SP_REGNUM << 11) | 0x01c0 | E_R12_REGNUM) && r12_tmp) |
| 898 | /* add r12,sp */ |
| 899 | pi->sp_offset += r12_tmp; |
| 900 | else if (insn == ((E_EP_REGNUM << 11) | 0x0000 | E_SP_REGNUM)) |
| 901 | /* mov sp,ep */ |
| 902 | ep_used = 1; |
| 903 | else if (insn == ((E_EP_REGNUM << 11) | 0x0000 | E_R1_REGNUM)) |
| 904 | /* mov r1,ep */ |
| 905 | ep_used = 0; |
| 906 | else if (((insn & 0x07ff) == (0x0760 | E_SP_REGNUM) |
| 907 | || (pi->uses_fp |
| 908 | && (insn & 0x07ff) == (0x0760 | E_FP_REGNUM))) |
| 909 | && pifsr |
| 910 | && v850_is_save_register (reg = (insn >> 11) & 0x1f)) |
| 911 | { |
| 912 | /* st.w <reg>,<offset>[sp] or st.w <reg>,<offset>[fp] */ |
| 913 | pifsr->reg = reg; |
| 914 | pifsr->offset = insn2 & ~1; |
| 915 | pifsr->cur_frameoffset = pi->sp_offset; |
| 916 | pifsr++; |
| 917 | } |
| 918 | else if (ep_used |
| 919 | && ((insn & 0x0781) == 0x0501) |
| 920 | && pifsr |
| 921 | && v850_is_save_register (reg = (insn >> 11) & 0x1f)) |
| 922 | { |
| 923 | /* sst.w <reg>,<offset>[ep] */ |
| 924 | pifsr->reg = reg; |
| 925 | pifsr->offset = (insn & 0x007e) << 1; |
| 926 | pifsr->cur_frameoffset = pi->sp_offset; |
| 927 | pifsr++; |
| 928 | } |
| 929 | } |
| 930 | |
| 931 | /* Fix up any offsets to the final offset. If a frame pointer was created, |
| 932 | use it instead of the stack pointer. */ |
| 933 | for (pifsr_tmp = pifsrs; pifsr_tmp != pifsr; pifsr_tmp++) |
| 934 | { |
| 935 | pifsr_tmp->offset -= pi->sp_offset - pifsr_tmp->cur_frameoffset; |
| 936 | pi->saved_regs[pifsr_tmp->reg].addr = pifsr_tmp->offset; |
| 937 | } |
| 938 | |
| 939 | return current_pc; |
| 940 | } |
| 941 | |
| 942 | /* Return the address of the first code past the prologue of the function. */ |
| 943 | |
| 944 | static CORE_ADDR |
| 945 | v850_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 946 | { |
| 947 | CORE_ADDR func_addr, func_end; |
| 948 | |
| 949 | /* See what the symbol table says. */ |
| 950 | |
| 951 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
| 952 | { |
| 953 | struct symtab_and_line sal; |
| 954 | |
| 955 | sal = find_pc_line (func_addr, 0); |
| 956 | if (sal.line != 0 && sal.end < func_end) |
| 957 | return sal.end; |
| 958 | |
| 959 | /* Either there's no line info, or the line after the prologue is after |
| 960 | the end of the function. In this case, there probably isn't a |
| 961 | prologue. */ |
| 962 | return pc; |
| 963 | } |
| 964 | |
| 965 | /* We can't find the start of this function, so there's nothing we |
| 966 | can do. */ |
| 967 | return pc; |
| 968 | } |
| 969 | |
| 970 | /* Return 1 if the data structure has any 8-byte fields that'll require |
| 971 | the entire data structure to be aligned. Otherwise, return 0. */ |
| 972 | |
| 973 | static int |
| 974 | v850_eight_byte_align_p (struct type *type) |
| 975 | { |
| 976 | type = check_typedef (type); |
| 977 | |
| 978 | if (v850_type_is_scalar (type)) |
| 979 | return (TYPE_LENGTH (type) == 8); |
| 980 | else |
| 981 | { |
| 982 | int i; |
| 983 | |
| 984 | for (i = 0; i < TYPE_NFIELDS (type); i++) |
| 985 | { |
| 986 | if (v850_eight_byte_align_p (TYPE_FIELD_TYPE (type, i))) |
| 987 | return 1; |
| 988 | } |
| 989 | } |
| 990 | return 0; |
| 991 | } |
| 992 | |
| 993 | static CORE_ADDR |
| 994 | v850_frame_align (struct gdbarch *ignore, CORE_ADDR sp) |
| 995 | { |
| 996 | return sp & ~3; |
| 997 | } |
| 998 | |
| 999 | /* Setup arguments and LP for a call to the target. First four args |
| 1000 | go in R6->R9, subsequent args go into sp + 16 -> sp + ... Structs |
| 1001 | are passed by reference. 64 bit quantities (doubles and long longs) |
| 1002 | may be split between the regs and the stack. When calling a function |
| 1003 | that returns a struct, a pointer to the struct is passed in as a secret |
| 1004 | first argument (always in R6). |
| 1005 | |
| 1006 | Stack space for the args has NOT been allocated: that job is up to us. */ |
| 1007 | |
| 1008 | static CORE_ADDR |
| 1009 | v850_push_dummy_call (struct gdbarch *gdbarch, |
| 1010 | struct value *function, |
| 1011 | struct regcache *regcache, |
| 1012 | CORE_ADDR bp_addr, |
| 1013 | int nargs, |
| 1014 | struct value **args, |
| 1015 | CORE_ADDR sp, |
| 1016 | int struct_return, |
| 1017 | CORE_ADDR struct_addr) |
| 1018 | { |
| 1019 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1020 | int argreg; |
| 1021 | int argnum; |
| 1022 | int len = 0; |
| 1023 | int stack_offset; |
| 1024 | |
| 1025 | if (gdbarch_tdep (gdbarch)->abi == V850_ABI_RH850) |
| 1026 | stack_offset = 0; |
| 1027 | else |
| 1028 | /* The offset onto the stack at which we will start copying parameters |
| 1029 | (after the registers are used up) begins at 16 rather than at zero. |
| 1030 | That's how the ABI is defined, though there's no indication that these |
| 1031 | 16 bytes are used for anything, not even for saving incoming |
| 1032 | argument registers. */ |
| 1033 | stack_offset = 16; |
| 1034 | |
| 1035 | /* Now make space on the stack for the args. */ |
| 1036 | for (argnum = 0; argnum < nargs; argnum++) |
| 1037 | len += ((TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3); |
| 1038 | sp -= len + stack_offset; |
| 1039 | |
| 1040 | argreg = E_ARG0_REGNUM; |
| 1041 | /* The struct_return pointer occupies the first parameter register. */ |
| 1042 | if (struct_return) |
| 1043 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
| 1044 | |
| 1045 | /* Now load as many as possible of the first arguments into |
| 1046 | registers, and push the rest onto the stack. There are 16 bytes |
| 1047 | in four registers available. Loop thru args from first to last. */ |
| 1048 | for (argnum = 0; argnum < nargs; argnum++) |
| 1049 | { |
| 1050 | int len; |
| 1051 | gdb_byte *val; |
| 1052 | gdb_byte valbuf[v850_reg_size]; |
| 1053 | |
| 1054 | if (!v850_type_is_scalar (value_type (*args)) |
| 1055 | && gdbarch_tdep (gdbarch)->abi == V850_ABI_GCC |
| 1056 | && TYPE_LENGTH (value_type (*args)) > E_MAX_RETTYPE_SIZE_IN_REGS) |
| 1057 | { |
| 1058 | store_unsigned_integer (valbuf, 4, byte_order, |
| 1059 | value_address (*args)); |
| 1060 | len = 4; |
| 1061 | val = valbuf; |
| 1062 | } |
| 1063 | else |
| 1064 | { |
| 1065 | len = TYPE_LENGTH (value_type (*args)); |
| 1066 | val = (gdb_byte *) value_contents (*args); |
| 1067 | } |
| 1068 | |
| 1069 | if (gdbarch_tdep (gdbarch)->eight_byte_align |
| 1070 | && v850_eight_byte_align_p (value_type (*args))) |
| 1071 | { |
| 1072 | if (argreg <= E_ARGLAST_REGNUM && (argreg & 1)) |
| 1073 | argreg++; |
| 1074 | else if (stack_offset & 0x4) |
| 1075 | stack_offset += 4; |
| 1076 | } |
| 1077 | |
| 1078 | while (len > 0) |
| 1079 | if (argreg <= E_ARGLAST_REGNUM) |
| 1080 | { |
| 1081 | CORE_ADDR regval; |
| 1082 | |
| 1083 | regval = extract_unsigned_integer (val, v850_reg_size, byte_order); |
| 1084 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 1085 | |
| 1086 | len -= v850_reg_size; |
| 1087 | val += v850_reg_size; |
| 1088 | argreg++; |
| 1089 | } |
| 1090 | else |
| 1091 | { |
| 1092 | write_memory (sp + stack_offset, val, 4); |
| 1093 | |
| 1094 | len -= 4; |
| 1095 | val += 4; |
| 1096 | stack_offset += 4; |
| 1097 | } |
| 1098 | args++; |
| 1099 | } |
| 1100 | |
| 1101 | /* Store return address. */ |
| 1102 | regcache_cooked_write_unsigned (regcache, E_LP_REGNUM, bp_addr); |
| 1103 | |
| 1104 | /* Update stack pointer. */ |
| 1105 | regcache_cooked_write_unsigned (regcache, E_SP_REGNUM, sp); |
| 1106 | |
| 1107 | return sp; |
| 1108 | } |
| 1109 | |
| 1110 | static void |
| 1111 | v850_extract_return_value (struct type *type, struct regcache *regcache, |
| 1112 | gdb_byte *valbuf) |
| 1113 | { |
| 1114 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 1115 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1116 | int len = TYPE_LENGTH (type); |
| 1117 | |
| 1118 | if (len <= v850_reg_size) |
| 1119 | { |
| 1120 | ULONGEST val; |
| 1121 | |
| 1122 | regcache_cooked_read_unsigned (regcache, E_V0_REGNUM, &val); |
| 1123 | store_unsigned_integer (valbuf, len, byte_order, val); |
| 1124 | } |
| 1125 | else if (len <= 2 * v850_reg_size) |
| 1126 | { |
| 1127 | int i, regnum = E_V0_REGNUM; |
| 1128 | gdb_byte buf[v850_reg_size]; |
| 1129 | for (i = 0; len > 0; i += 4, len -= 4) |
| 1130 | { |
| 1131 | regcache_raw_read (regcache, regnum++, buf); |
| 1132 | memcpy (valbuf + i, buf, len > 4 ? 4 : len); |
| 1133 | } |
| 1134 | } |
| 1135 | } |
| 1136 | |
| 1137 | static void |
| 1138 | v850_store_return_value (struct type *type, struct regcache *regcache, |
| 1139 | const gdb_byte *valbuf) |
| 1140 | { |
| 1141 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 1142 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1143 | int len = TYPE_LENGTH (type); |
| 1144 | |
| 1145 | if (len <= v850_reg_size) |
| 1146 | regcache_cooked_write_unsigned |
| 1147 | (regcache, E_V0_REGNUM, |
| 1148 | extract_unsigned_integer (valbuf, len, byte_order)); |
| 1149 | else if (len <= 2 * v850_reg_size) |
| 1150 | { |
| 1151 | int i, regnum = E_V0_REGNUM; |
| 1152 | for (i = 0; i < len; i += 4) |
| 1153 | regcache_raw_write (regcache, regnum++, valbuf + i); |
| 1154 | } |
| 1155 | } |
| 1156 | |
| 1157 | static enum return_value_convention |
| 1158 | v850_return_value (struct gdbarch *gdbarch, struct value *function, |
| 1159 | struct type *type, struct regcache *regcache, |
| 1160 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 1161 | { |
| 1162 | if (v850_use_struct_convention (gdbarch, type)) |
| 1163 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 1164 | if (writebuf) |
| 1165 | v850_store_return_value (type, regcache, writebuf); |
| 1166 | else if (readbuf) |
| 1167 | v850_extract_return_value (type, regcache, readbuf); |
| 1168 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 1169 | } |
| 1170 | |
| 1171 | static const unsigned char * |
| 1172 | v850_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, |
| 1173 | int *lenptr) |
| 1174 | { |
| 1175 | static unsigned char breakpoint[] = { 0x85, 0x05 }; |
| 1176 | |
| 1177 | *lenptr = sizeof (breakpoint); |
| 1178 | return breakpoint; |
| 1179 | } |
| 1180 | |
| 1181 | /* Implement software breakpoints by using the dbtrap instruction. |
| 1182 | Older architectures had no such instruction. For those, an |
| 1183 | unconditional branch to self instruction is used. */ |
| 1184 | |
| 1185 | static const unsigned char * |
| 1186 | v850_dbtrap_breakpoint_from_pc (struct gdbarch *gdbarch, |
| 1187 | CORE_ADDR *pcptr, int *lenptr) |
| 1188 | { |
| 1189 | static unsigned char breakpoint[] = { 0x40, 0xf8 }; |
| 1190 | |
| 1191 | *lenptr = sizeof (breakpoint); |
| 1192 | return breakpoint; |
| 1193 | } |
| 1194 | |
| 1195 | static struct v850_frame_cache * |
| 1196 | v850_alloc_frame_cache (struct frame_info *this_frame) |
| 1197 | { |
| 1198 | struct v850_frame_cache *cache; |
| 1199 | |
| 1200 | cache = FRAME_OBSTACK_ZALLOC (struct v850_frame_cache); |
| 1201 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 1202 | |
| 1203 | /* Base address. */ |
| 1204 | cache->base = 0; |
| 1205 | cache->sp_offset = 0; |
| 1206 | cache->pc = 0; |
| 1207 | |
| 1208 | /* Frameless until proven otherwise. */ |
| 1209 | cache->uses_fp = 0; |
| 1210 | |
| 1211 | return cache; |
| 1212 | } |
| 1213 | |
| 1214 | static struct v850_frame_cache * |
| 1215 | v850_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 1216 | { |
| 1217 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1218 | struct v850_frame_cache *cache; |
| 1219 | CORE_ADDR current_pc; |
| 1220 | int i; |
| 1221 | |
| 1222 | if (*this_cache) |
| 1223 | return *this_cache; |
| 1224 | |
| 1225 | cache = v850_alloc_frame_cache (this_frame); |
| 1226 | *this_cache = cache; |
| 1227 | |
| 1228 | /* In principle, for normal frames, fp holds the frame pointer, |
| 1229 | which holds the base address for the current stack frame. |
| 1230 | However, for functions that don't need it, the frame pointer is |
| 1231 | optional. For these "frameless" functions the frame pointer is |
| 1232 | actually the frame pointer of the calling frame. */ |
| 1233 | cache->base = get_frame_register_unsigned (this_frame, E_FP_REGNUM); |
| 1234 | if (cache->base == 0) |
| 1235 | return cache; |
| 1236 | |
| 1237 | cache->pc = get_frame_func (this_frame); |
| 1238 | current_pc = get_frame_pc (this_frame); |
| 1239 | if (cache->pc != 0) |
| 1240 | { |
| 1241 | ULONGEST ctbp; |
| 1242 | ctbp = get_frame_register_unsigned (this_frame, E_CTBP_REGNUM); |
| 1243 | v850_analyze_prologue (gdbarch, cache->pc, current_pc, cache, ctbp); |
| 1244 | } |
| 1245 | |
| 1246 | if (!cache->uses_fp) |
| 1247 | { |
| 1248 | /* We didn't find a valid frame, which means that CACHE->base |
| 1249 | currently holds the frame pointer for our calling frame. If |
| 1250 | we're at the start of a function, or somewhere half-way its |
| 1251 | prologue, the function's frame probably hasn't been fully |
| 1252 | setup yet. Try to reconstruct the base address for the stack |
| 1253 | frame by looking at the stack pointer. For truly "frameless" |
| 1254 | functions this might work too. */ |
| 1255 | cache->base = get_frame_register_unsigned (this_frame, E_SP_REGNUM); |
| 1256 | } |
| 1257 | |
| 1258 | /* Now that we have the base address for the stack frame we can |
| 1259 | calculate the value of sp in the calling frame. */ |
| 1260 | trad_frame_set_value (cache->saved_regs, E_SP_REGNUM, |
| 1261 | cache->base - cache->sp_offset); |
| 1262 | |
| 1263 | /* Adjust all the saved registers such that they contain addresses |
| 1264 | instead of offsets. */ |
| 1265 | for (i = 0; i < gdbarch_num_regs (gdbarch); i++) |
| 1266 | if (trad_frame_addr_p (cache->saved_regs, i)) |
| 1267 | cache->saved_regs[i].addr += cache->base; |
| 1268 | |
| 1269 | /* The call instruction moves the caller's PC in the callee's LP. |
| 1270 | Since this is an unwind, do the reverse. Copy the location of LP |
| 1271 | into PC (the address / regnum) so that a request for PC will be |
| 1272 | converted into a request for the LP. */ |
| 1273 | |
| 1274 | cache->saved_regs[E_PC_REGNUM] = cache->saved_regs[E_LP_REGNUM]; |
| 1275 | |
| 1276 | return cache; |
| 1277 | } |
| 1278 | |
| 1279 | |
| 1280 | static struct value * |
| 1281 | v850_frame_prev_register (struct frame_info *this_frame, |
| 1282 | void **this_cache, int regnum) |
| 1283 | { |
| 1284 | struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache); |
| 1285 | |
| 1286 | gdb_assert (regnum >= 0); |
| 1287 | |
| 1288 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, regnum); |
| 1289 | } |
| 1290 | |
| 1291 | static void |
| 1292 | v850_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 1293 | struct frame_id *this_id) |
| 1294 | { |
| 1295 | struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache); |
| 1296 | |
| 1297 | /* This marks the outermost frame. */ |
| 1298 | if (cache->base == 0) |
| 1299 | return; |
| 1300 | |
| 1301 | *this_id = frame_id_build (cache->saved_regs[E_SP_REGNUM].addr, cache->pc); |
| 1302 | } |
| 1303 | |
| 1304 | static const struct frame_unwind v850_frame_unwind = { |
| 1305 | NORMAL_FRAME, |
| 1306 | default_frame_unwind_stop_reason, |
| 1307 | v850_frame_this_id, |
| 1308 | v850_frame_prev_register, |
| 1309 | NULL, |
| 1310 | default_frame_sniffer |
| 1311 | }; |
| 1312 | |
| 1313 | static CORE_ADDR |
| 1314 | v850_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1315 | { |
| 1316 | return frame_unwind_register_unsigned (next_frame, |
| 1317 | gdbarch_sp_regnum (gdbarch)); |
| 1318 | } |
| 1319 | |
| 1320 | static CORE_ADDR |
| 1321 | v850_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1322 | { |
| 1323 | return frame_unwind_register_unsigned (next_frame, |
| 1324 | gdbarch_pc_regnum (gdbarch)); |
| 1325 | } |
| 1326 | |
| 1327 | static struct frame_id |
| 1328 | v850_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1329 | { |
| 1330 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, |
| 1331 | gdbarch_sp_regnum (gdbarch)); |
| 1332 | return frame_id_build (sp, get_frame_pc (this_frame)); |
| 1333 | } |
| 1334 | |
| 1335 | static CORE_ADDR |
| 1336 | v850_frame_base_address (struct frame_info *this_frame, void **this_cache) |
| 1337 | { |
| 1338 | struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache); |
| 1339 | |
| 1340 | return cache->base; |
| 1341 | } |
| 1342 | |
| 1343 | static const struct frame_base v850_frame_base = { |
| 1344 | &v850_frame_unwind, |
| 1345 | v850_frame_base_address, |
| 1346 | v850_frame_base_address, |
| 1347 | v850_frame_base_address |
| 1348 | }; |
| 1349 | |
| 1350 | static struct gdbarch * |
| 1351 | v850_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 1352 | { |
| 1353 | struct gdbarch *gdbarch; |
| 1354 | struct gdbarch_tdep *tdep; |
| 1355 | int e_flags, e_machine; |
| 1356 | |
| 1357 | /* Extract the elf_flags if available. */ |
| 1358 | if (info.abfd != NULL |
| 1359 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) |
| 1360 | { |
| 1361 | e_flags = elf_elfheader (info.abfd)->e_flags; |
| 1362 | e_machine = elf_elfheader (info.abfd)->e_machine; |
| 1363 | } |
| 1364 | else |
| 1365 | { |
| 1366 | e_flags = 0; |
| 1367 | e_machine = 0; |
| 1368 | } |
| 1369 | |
| 1370 | |
| 1371 | /* Try to find the architecture in the list of already defined |
| 1372 | architectures. */ |
| 1373 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
| 1374 | arches != NULL; |
| 1375 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) |
| 1376 | { |
| 1377 | if (gdbarch_tdep (arches->gdbarch)->e_flags != e_flags |
| 1378 | || gdbarch_tdep (arches->gdbarch)->e_machine != e_machine) |
| 1379 | continue; |
| 1380 | |
| 1381 | return arches->gdbarch; |
| 1382 | } |
| 1383 | tdep = XNEW (struct gdbarch_tdep); |
| 1384 | tdep->e_flags = e_flags; |
| 1385 | tdep->e_machine = e_machine; |
| 1386 | |
| 1387 | switch (tdep->e_machine) |
| 1388 | { |
| 1389 | case EM_V800: |
| 1390 | tdep->abi = V850_ABI_RH850; |
| 1391 | break; |
| 1392 | default: |
| 1393 | tdep->abi = V850_ABI_GCC; |
| 1394 | break; |
| 1395 | } |
| 1396 | |
| 1397 | tdep->eight_byte_align = (tdep->e_flags & EF_RH850_DATA_ALIGN8) ? 1 : 0; |
| 1398 | gdbarch = gdbarch_alloc (&info, tdep); |
| 1399 | |
| 1400 | switch (info.bfd_arch_info->mach) |
| 1401 | { |
| 1402 | case bfd_mach_v850: |
| 1403 | set_gdbarch_register_name (gdbarch, v850_register_name); |
| 1404 | set_gdbarch_num_regs (gdbarch, E_NUM_OF_V850_REGS); |
| 1405 | break; |
| 1406 | case bfd_mach_v850e: |
| 1407 | case bfd_mach_v850e1: |
| 1408 | set_gdbarch_register_name (gdbarch, v850e_register_name); |
| 1409 | set_gdbarch_num_regs (gdbarch, E_NUM_OF_V850E_REGS); |
| 1410 | break; |
| 1411 | case bfd_mach_v850e2: |
| 1412 | case bfd_mach_v850e2v3: |
| 1413 | set_gdbarch_register_name (gdbarch, v850e2_register_name); |
| 1414 | set_gdbarch_num_regs (gdbarch, E_NUM_REGS); |
| 1415 | break; |
| 1416 | case bfd_mach_v850e3v5: |
| 1417 | set_gdbarch_register_name (gdbarch, v850e3v5_register_name); |
| 1418 | set_gdbarch_num_regs (gdbarch, E_NUM_OF_V850E3V5_REGS); |
| 1419 | break; |
| 1420 | } |
| 1421 | |
| 1422 | set_gdbarch_num_pseudo_regs (gdbarch, 0); |
| 1423 | set_gdbarch_sp_regnum (gdbarch, E_SP_REGNUM); |
| 1424 | set_gdbarch_pc_regnum (gdbarch, E_PC_REGNUM); |
| 1425 | set_gdbarch_fp0_regnum (gdbarch, -1); |
| 1426 | |
| 1427 | set_gdbarch_register_type (gdbarch, v850_register_type); |
| 1428 | |
| 1429 | set_gdbarch_char_signed (gdbarch, 1); |
| 1430 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
| 1431 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 1432 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 1433 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 1434 | |
| 1435 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 1436 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 1437 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
| 1438 | |
| 1439 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 1440 | set_gdbarch_addr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
| 1441 | |
| 1442 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 1443 | switch (info.bfd_arch_info->mach) |
| 1444 | { |
| 1445 | case bfd_mach_v850e2: |
| 1446 | case bfd_mach_v850e2v3: |
| 1447 | case bfd_mach_v850e3v5: |
| 1448 | set_gdbarch_breakpoint_from_pc (gdbarch, v850_dbtrap_breakpoint_from_pc); |
| 1449 | break; |
| 1450 | default: |
| 1451 | set_gdbarch_breakpoint_from_pc (gdbarch, v850_breakpoint_from_pc); |
| 1452 | break; |
| 1453 | } |
| 1454 | |
| 1455 | set_gdbarch_return_value (gdbarch, v850_return_value); |
| 1456 | set_gdbarch_push_dummy_call (gdbarch, v850_push_dummy_call); |
| 1457 | set_gdbarch_skip_prologue (gdbarch, v850_skip_prologue); |
| 1458 | |
| 1459 | set_gdbarch_print_insn (gdbarch, print_insn_v850); |
| 1460 | |
| 1461 | set_gdbarch_frame_align (gdbarch, v850_frame_align); |
| 1462 | set_gdbarch_unwind_sp (gdbarch, v850_unwind_sp); |
| 1463 | set_gdbarch_unwind_pc (gdbarch, v850_unwind_pc); |
| 1464 | set_gdbarch_dummy_id (gdbarch, v850_dummy_id); |
| 1465 | frame_base_set_default (gdbarch, &v850_frame_base); |
| 1466 | |
| 1467 | /* Hook in ABI-specific overrides, if they have been registered. */ |
| 1468 | gdbarch_init_osabi (info, gdbarch); |
| 1469 | |
| 1470 | dwarf2_append_unwinders (gdbarch); |
| 1471 | frame_unwind_append_unwinder (gdbarch, &v850_frame_unwind); |
| 1472 | |
| 1473 | return gdbarch; |
| 1474 | } |
| 1475 | |
| 1476 | extern initialize_file_ftype _initialize_v850_tdep; /* -Wmissing-prototypes */ |
| 1477 | |
| 1478 | void |
| 1479 | _initialize_v850_tdep (void) |
| 1480 | { |
| 1481 | register_gdbarch_init (bfd_arch_v850, v850_gdbarch_init); |
| 1482 | register_gdbarch_init (bfd_arch_v850_rh850, v850_gdbarch_init); |
| 1483 | } |