| 1 | /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. |
| 2 | |
| 3 | Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program; if not, write to the Free Software |
| 19 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
| 20 | Boston, MA 02110-1301, USA. */ |
| 21 | |
| 22 | #include "defs.h" |
| 23 | #include "frame.h" |
| 24 | #include "symtab.h" |
| 25 | #include "symfile.h" |
| 26 | #include "objfiles.h" |
| 27 | #include "gdbtypes.h" |
| 28 | #include "gdbcore.h" |
| 29 | #include "value.h" |
| 30 | #include "dis-asm.h" |
| 31 | #include "inferior.h" |
| 32 | #include "floatformat.h" |
| 33 | #include "regcache.h" |
| 34 | #include "reggroups.h" |
| 35 | #include "regset.h" |
| 36 | |
| 37 | #include "dummy-frame.h" |
| 38 | #include "elf/dwarf2.h" |
| 39 | #include "dwarf2-frame.h" |
| 40 | #include "dwarf2loc.h" |
| 41 | #include "frame.h" |
| 42 | #include "frame-base.h" |
| 43 | #include "frame-unwind.h" |
| 44 | |
| 45 | #include "arch-utils.h" |
| 46 | #include "gdbarch.h" |
| 47 | #include "remote.h" |
| 48 | #include "serial.h" |
| 49 | |
| 50 | #include "command.h" |
| 51 | #include "gdbcmd.h" |
| 52 | #include "gdb_assert.h" |
| 53 | |
| 54 | #include "xtensa-tdep.h" |
| 55 | |
| 56 | |
| 57 | static int xtensa_debug_level = 0; |
| 58 | |
| 59 | #define DEBUGWARN(args...) \ |
| 60 | if (xtensa_debug_level > 0) \ |
| 61 | fprintf_unfiltered (gdb_stdlog, "(warn ) " args) |
| 62 | |
| 63 | #define DEBUGINFO(args...) \ |
| 64 | if (xtensa_debug_level > 1) \ |
| 65 | fprintf_unfiltered (gdb_stdlog, "(info ) " args) |
| 66 | |
| 67 | #define DEBUGTRACE(args...) \ |
| 68 | if (xtensa_debug_level > 2) \ |
| 69 | fprintf_unfiltered (gdb_stdlog, "(trace) " args) |
| 70 | |
| 71 | #define DEBUGVERB(args...) \ |
| 72 | if (xtensa_debug_level > 3) \ |
| 73 | fprintf_unfiltered (gdb_stdlog, "(verb ) " args) |
| 74 | |
| 75 | |
| 76 | /* According to the ABI, the SP must be aligned to 16-byte boundaries. */ |
| 77 | |
| 78 | #define SP_ALIGNMENT 16 |
| 79 | |
| 80 | |
| 81 | /* We use a6 through a11 for passing arguments to a function called by GDB. */ |
| 82 | |
| 83 | #define ARGS_FIRST_REG A6_REGNUM |
| 84 | #define ARGS_NUM_REGS 6 |
| 85 | #define REGISTER_SIZE 4 |
| 86 | |
| 87 | |
| 88 | /* Extract the call size from the return address or ps register. */ |
| 89 | |
| 90 | #define PS_CALLINC_SHIFT 16 |
| 91 | #define PS_CALLINC_MASK 0x00030000 |
| 92 | #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT) |
| 93 | #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3)) |
| 94 | |
| 95 | |
| 96 | /* Convert a live Ax register number to the corresponding Areg number. */ |
| 97 | |
| 98 | #define AREG_NUMBER(r, wb) \ |
| 99 | ((((r) - A0_REGNUM + (((wb) & WB_MASK)<<WB_SHIFT)) & AREGS_MASK) + AR_BASE) |
| 100 | |
| 101 | |
| 102 | /* Define prototypes. */ |
| 103 | |
| 104 | extern struct gdbarch_tdep *xtensa_config_tdep (struct gdbarch_info *); |
| 105 | extern int xtensa_config_byte_order (struct gdbarch_info *); |
| 106 | |
| 107 | |
| 108 | /* XTENSA_IS_ENTRY tests whether the first byte of an instruction |
| 109 | indicates that the instruction is an ENTRY instruction. */ |
| 110 | |
| 111 | #define XTENSA_IS_ENTRY(op1) \ |
| 112 | ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) ? ((op1) == 0x6c) : ((op1) == 0x36)) |
| 113 | |
| 114 | #define XTENSA_ENTRY_LENGTH 3 |
| 115 | |
| 116 | |
| 117 | /* windowing_enabled() returns true, if windowing is enabled. |
| 118 | WOE must be set to 1; EXCM to 0. |
| 119 | Note: We assume that EXCM is always 0 for XEA1. */ |
| 120 | |
| 121 | static inline int |
| 122 | windowing_enabled (CORE_ADDR ps) |
| 123 | { |
| 124 | return ((ps & (1 << 4)) == 0 && (ps & (1 << 18)) != 0); |
| 125 | } |
| 126 | |
| 127 | /* Return the window size of the previous call to the function from which we |
| 128 | have just returned. |
| 129 | |
| 130 | This function is used to extract the return value after a called function |
| 131 | has returned to the callee. On Xtensa, the register that holds the return |
| 132 | value (from the perspective of the caller) depends on what call |
| 133 | instruction was used. For now, we are assuming that the call instruction |
| 134 | precedes the current address, so we simply analyze the call instruction. |
| 135 | If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4' |
| 136 | method to call the inferior function. */ |
| 137 | |
| 138 | static int |
| 139 | extract_call_winsize (CORE_ADDR pc) |
| 140 | { |
| 141 | int winsize = 4; /* Default: No call, e.g. dummy frame. */ |
| 142 | int insn; |
| 143 | gdb_byte buf[4]; |
| 144 | |
| 145 | DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc); |
| 146 | |
| 147 | /* Read the previous instruction (should be a call[x]{4|8|12}. */ |
| 148 | read_memory (pc-3, buf, 3); |
| 149 | insn = extract_unsigned_integer (buf, 3); |
| 150 | |
| 151 | /* Decode call instruction: |
| 152 | Little Endian |
| 153 | call{0,4,8,12} OFFSET || {00,01,10,11} || 0101 |
| 154 | callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000 |
| 155 | Big Endian |
| 156 | call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET |
| 157 | callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */ |
| 158 | |
| 159 | /* Lookup call insn. |
| 160 | (Return the default value (4) if we can't find a valid call insn. */ |
| 161 | |
| 162 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) |
| 163 | { |
| 164 | if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0)) |
| 165 | winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12 */ |
| 166 | } |
| 167 | else |
| 168 | { |
| 169 | if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03)) |
| 170 | winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12 */ |
| 171 | } |
| 172 | return winsize; |
| 173 | } |
| 174 | |
| 175 | |
| 176 | /* REGISTER INFORMATION */ |
| 177 | |
| 178 | /* Returns the name of a register. */ |
| 179 | |
| 180 | static const char * |
| 181 | xtensa_register_name (int regnum) |
| 182 | { |
| 183 | /* Return the name stored in the register map. */ |
| 184 | if (regnum >= 0 && regnum < NUM_REGS + NUM_PSEUDO_REGS) |
| 185 | return REGMAP[regnum].name; |
| 186 | |
| 187 | /* Invalid register number. */ |
| 188 | internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum); |
| 189 | return 0; |
| 190 | } |
| 191 | |
| 192 | |
| 193 | /* Return the type of a register. Create a new type, if necessary. */ |
| 194 | |
| 195 | static struct ctype_cache |
| 196 | { |
| 197 | struct ctype_cache *next; |
| 198 | int size; |
| 199 | struct type *virtual_type; |
| 200 | } *type_entries = NULL; |
| 201 | |
| 202 | static struct type * |
| 203 | xtensa_register_type (struct gdbarch *gdbarch, int regnum) |
| 204 | { |
| 205 | /* Return signed integer for ARx and Ax registers. */ |
| 206 | if ((regnum >= AR_BASE && regnum < AR_BASE + NUM_AREGS) |
| 207 | || (regnum >= A0_BASE && regnum < A0_BASE + 16)) |
| 208 | return builtin_type_int; |
| 209 | |
| 210 | if (regnum == PC_REGNUM || regnum == A1_REGNUM) |
| 211 | return lookup_pointer_type (builtin_type_void); |
| 212 | |
| 213 | /* Return the stored type for all other registers. */ |
| 214 | else if (regnum >= 0 && regnum < NUM_REGS + NUM_PSEUDO_REGS) |
| 215 | { |
| 216 | xtensa_register_t* reg = ®MAP[regnum]; |
| 217 | |
| 218 | /* Set ctype for this register (only the first time we ask for it). */ |
| 219 | |
| 220 | if (reg->ctype == 0) |
| 221 | { |
| 222 | struct ctype_cache *tp; |
| 223 | int size = reg->byte_size; |
| 224 | |
| 225 | /* We always use the memory representation, even if the register |
| 226 | width is smaller. */ |
| 227 | switch (size) |
| 228 | { |
| 229 | case 1: |
| 230 | reg->ctype = builtin_type_uint8; |
| 231 | break; |
| 232 | |
| 233 | case 2: |
| 234 | reg->ctype = builtin_type_uint16; |
| 235 | break; |
| 236 | |
| 237 | case 4: |
| 238 | reg->ctype = builtin_type_uint32; |
| 239 | break; |
| 240 | |
| 241 | case 8: |
| 242 | reg->ctype = builtin_type_uint64; |
| 243 | break; |
| 244 | |
| 245 | case 16: |
| 246 | reg->ctype = builtin_type_uint128; |
| 247 | break; |
| 248 | |
| 249 | default: |
| 250 | for (tp = type_entries; tp != NULL; tp = tp->next) |
| 251 | if (tp->size == size) |
| 252 | break; |
| 253 | |
| 254 | if (tp == NULL) |
| 255 | { |
| 256 | char *name = xmalloc (16); |
| 257 | tp = xmalloc (sizeof (struct ctype_cache)); |
| 258 | tp->next = type_entries; |
| 259 | type_entries = tp; |
| 260 | tp->size = size; |
| 261 | |
| 262 | sprintf (name, "int%d", size * 8); |
| 263 | tp->virtual_type = init_type (TYPE_CODE_INT, size, |
| 264 | TYPE_FLAG_UNSIGNED, name, |
| 265 | NULL); |
| 266 | } |
| 267 | |
| 268 | reg->ctype = tp->virtual_type; |
| 269 | } |
| 270 | } |
| 271 | return reg->ctype; |
| 272 | } |
| 273 | |
| 274 | /* Invalid register number. */ |
| 275 | internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum); |
| 276 | return 0; |
| 277 | } |
| 278 | |
| 279 | |
| 280 | /* Returns the 'local' register number for stubs, dwarf2, etc. |
| 281 | The debugging information enumerates registers starting from 0 for A0 |
| 282 | to n for An. So, we only have to add the base number for A0. */ |
| 283 | |
| 284 | static int |
| 285 | xtensa_reg_to_regnum (int regnum) |
| 286 | { |
| 287 | int i; |
| 288 | |
| 289 | if (regnum >= 0 && regnum < 16) |
| 290 | return A0_BASE + regnum; |
| 291 | |
| 292 | for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++) |
| 293 | if (regnum == REGMAP[i].target_number) |
| 294 | return i; |
| 295 | |
| 296 | /* Invalid register number. */ |
| 297 | internal_error (__FILE__, __LINE__, |
| 298 | _("invalid dwarf/stabs register number %d"), regnum); |
| 299 | return 0; |
| 300 | } |
| 301 | |
| 302 | |
| 303 | /* Handle the special case of masked registers. */ |
| 304 | |
| 305 | /* Write the bits of a masked register to the various registers that |
| 306 | are combined into this register. Only the masked areas of these |
| 307 | registers are modified; the other fields are untouched. |
| 308 | (Note: The size of masked registers is always less or equal 32 bits.) */ |
| 309 | |
| 310 | static void |
| 311 | xtensa_register_write_masked (xtensa_register_t *reg, unsigned char *buffer) |
| 312 | { |
| 313 | unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; |
| 314 | |
| 315 | const xtensa_mask_t *mask = reg->mask; |
| 316 | |
| 317 | int shift = 0; /* Shift for next mask (mod 32). */ |
| 318 | int start, size; /* Start bit and size of current mask. */ |
| 319 | |
| 320 | unsigned int *ptr = value; |
| 321 | unsigned int regval, m, mem = 0; |
| 322 | |
| 323 | int bytesize = reg->byte_size; |
| 324 | int bitsize = bytesize * 8; |
| 325 | int i, r; |
| 326 | |
| 327 | DEBUGTRACE ("xtensa_register_write_masked ()\n"); |
| 328 | |
| 329 | /* Copy the masked register to host byte-order. */ |
| 330 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 331 | for (i = 0; i < bytesize; i++) |
| 332 | { |
| 333 | mem >>= 8; |
| 334 | mem |= (buffer[bytesize - i - 1] << 24); |
| 335 | if ((i & 3) == 3) |
| 336 | *ptr++ = mem; |
| 337 | } |
| 338 | else |
| 339 | for (i = 0; i < bytesize; i++) |
| 340 | { |
| 341 | mem >>= 8; |
| 342 | mem |= (buffer[i] << 24); |
| 343 | if ((i & 3) == 3) |
| 344 | *ptr++ = mem; |
| 345 | } |
| 346 | |
| 347 | /* We might have to shift the final value: |
| 348 | bytesize & 3 == 0 -> nothing to do, we use the full 32 bits, |
| 349 | bytesize & 3 == x -> shift (4-x) * 8. */ |
| 350 | |
| 351 | *ptr = mem >> (((0 - bytesize) & 3) * 8); |
| 352 | ptr = value; |
| 353 | mem = *ptr; |
| 354 | |
| 355 | /* Write the bits to the masked areas of the other registers. */ |
| 356 | for (i = 0; i < mask->count; i++) |
| 357 | { |
| 358 | start = mask->mask[i].bit_start; |
| 359 | size = mask->mask[i].bit_size; |
| 360 | regval = mem >> shift; |
| 361 | |
| 362 | if ((shift += size) > bitsize) |
| 363 | error (_("size of all masks is larger than the register")); |
| 364 | |
| 365 | if (shift >= 32) |
| 366 | { |
| 367 | mem = *(++ptr); |
| 368 | shift -= 32; |
| 369 | bitsize -= 32; |
| 370 | |
| 371 | if (shift > 0) |
| 372 | regval |= mem << (size - shift); |
| 373 | } |
| 374 | |
| 375 | /* Make sure we have a valid register. */ |
| 376 | r = mask->mask[i].reg_num; |
| 377 | if (r >= 0 && size > 0) |
| 378 | { |
| 379 | /* Don't overwrite the unmasked areas. */ |
| 380 | m = 0xffffffff >> (32 - size) << start; |
| 381 | regval <<= start; |
| 382 | regval = (regval & m) | (read_register (r) & ~m); |
| 383 | write_register (r, regval); |
| 384 | } |
| 385 | } |
| 386 | } |
| 387 | |
| 388 | |
| 389 | /* Read the masked areas of the registers and assemble it into a single |
| 390 | register. */ |
| 391 | |
| 392 | static void |
| 393 | xtensa_register_read_masked (xtensa_register_t *reg, unsigned char *buffer) |
| 394 | { |
| 395 | unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; |
| 396 | |
| 397 | const xtensa_mask_t *mask = reg->mask; |
| 398 | |
| 399 | int shift = 0; |
| 400 | int start, size; |
| 401 | |
| 402 | unsigned int *ptr = value; |
| 403 | unsigned int regval, mem = 0; |
| 404 | |
| 405 | int bytesize = reg->byte_size; |
| 406 | int bitsize = bytesize * 8; |
| 407 | int i; |
| 408 | |
| 409 | DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n", |
| 410 | reg->name == 0 ? "" : reg->name); |
| 411 | |
| 412 | /* Assemble the register from the masked areas of other registers. */ |
| 413 | for (i = 0; i < mask->count; i++) |
| 414 | { |
| 415 | int r = mask->mask[i].reg_num; |
| 416 | regval = (r >= 0) ? read_register (r) : 0; |
| 417 | start = mask->mask[i].bit_start; |
| 418 | size = mask->mask[i].bit_size; |
| 419 | |
| 420 | regval >>= start; |
| 421 | |
| 422 | if (size < 32) |
| 423 | regval &= (0xffffffff >> (32 - size)); |
| 424 | |
| 425 | mem |= regval << shift; |
| 426 | |
| 427 | if ((shift += size) > bitsize) |
| 428 | error (_("size of all masks is larger than the register")); |
| 429 | |
| 430 | if (shift >= 32) |
| 431 | { |
| 432 | *ptr++ = mem; |
| 433 | bitsize -= 32; |
| 434 | shift -= 32; |
| 435 | |
| 436 | if (shift == 0) |
| 437 | mem = 0; |
| 438 | else |
| 439 | mem = regval >> (size - shift); |
| 440 | } |
| 441 | } |
| 442 | |
| 443 | if (shift > 0) |
| 444 | *ptr = mem; |
| 445 | |
| 446 | /* Copy value to target byte order. */ |
| 447 | ptr = value; |
| 448 | mem = *ptr; |
| 449 | |
| 450 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 451 | for (i = 0; i < bytesize; i++) |
| 452 | { |
| 453 | if ((i & 3) == 0) |
| 454 | mem = *ptr++; |
| 455 | buffer[bytesize - i - 1] = mem & 0xff; |
| 456 | mem >>= 8; |
| 457 | } |
| 458 | else |
| 459 | for (i = 0; i < bytesize; i++) |
| 460 | { |
| 461 | if ((i & 3) == 0) |
| 462 | mem = *ptr++; |
| 463 | buffer[i] = mem & 0xff; |
| 464 | mem >>= 8; |
| 465 | } |
| 466 | } |
| 467 | |
| 468 | |
| 469 | /* Read pseudo registers. */ |
| 470 | |
| 471 | static void |
| 472 | xtensa_pseudo_register_read (struct gdbarch *gdbarch, |
| 473 | struct regcache *regcache, |
| 474 | int regnum, |
| 475 | gdb_byte *buffer) |
| 476 | { |
| 477 | DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n", |
| 478 | regnum, xtensa_register_name (regnum)); |
| 479 | |
| 480 | /* Check if it is FP (renumber it in this case -> A0...A15). */ |
| 481 | if (regnum == FP_ALIAS) |
| 482 | error (_("trying to read FP")); |
| 483 | |
| 484 | /* Read aliases a0..a15. */ |
| 485 | if (regnum >= A0_REGNUM && regnum <= A15_REGNUM) |
| 486 | { |
| 487 | gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); |
| 488 | |
| 489 | regcache_raw_read (regcache, WB_REGNUM, buf); |
| 490 | regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4)); |
| 491 | } |
| 492 | |
| 493 | /* We can always read 'regular' registers. */ |
| 494 | if (regnum >= 0 && regnum < NUM_REGS) |
| 495 | regcache_raw_read (regcache, regnum, buffer); |
| 496 | |
| 497 | /* Pseudo registers. */ |
| 498 | else if (regnum >= 0 && regnum < NUM_REGS + NUM_PSEUDO_REGS) |
| 499 | { |
| 500 | xtensa_register_t *reg = ®MAP[regnum]; |
| 501 | xtensa_register_type_t type = reg->type; |
| 502 | int flags = XTENSA_TARGET_FLAGS; |
| 503 | |
| 504 | /* Can we read Unknown or Unmapped registers? */ |
| 505 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
| 506 | { |
| 507 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) |
| 508 | { |
| 509 | warning (_("cannot read register %s"), |
| 510 | xtensa_register_name (regnum)); |
| 511 | return; |
| 512 | } |
| 513 | } |
| 514 | |
| 515 | /* Some targets cannot read TIE register files. */ |
| 516 | else if (type == xtRegisterTypeTieRegfile) |
| 517 | { |
| 518 | /* Use 'fetch' to get register? */ |
| 519 | if (flags & xtTargetFlagsUseFetchStore) |
| 520 | { |
| 521 | warning (_("cannot read register")); |
| 522 | return; |
| 523 | } |
| 524 | |
| 525 | /* On some targets (esp. simulators), we can always read the reg. */ |
| 526 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) |
| 527 | { |
| 528 | warning (_("cannot read register")); |
| 529 | return; |
| 530 | } |
| 531 | } |
| 532 | |
| 533 | /* We can always read mapped registers. */ |
| 534 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) |
| 535 | { |
| 536 | xtensa_register_read_masked (reg, (unsigned char *) buffer); |
| 537 | return; |
| 538 | } |
| 539 | |
| 540 | /* Assume that we can read the register. */ |
| 541 | regcache_raw_read (regcache, regnum, buffer); |
| 542 | } |
| 543 | |
| 544 | else |
| 545 | internal_error (__FILE__, __LINE__, |
| 546 | _("invalid register number %d"), regnum); |
| 547 | } |
| 548 | |
| 549 | |
| 550 | /* Write pseudo registers. */ |
| 551 | |
| 552 | static void |
| 553 | xtensa_pseudo_register_write (struct gdbarch *gdbarch, |
| 554 | struct regcache *regcache, |
| 555 | int regnum, |
| 556 | const gdb_byte *buffer) |
| 557 | { |
| 558 | DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n", |
| 559 | regnum, xtensa_register_name (regnum)); |
| 560 | |
| 561 | /* Check if this is FP. */ |
| 562 | if (regnum == FP_ALIAS) |
| 563 | error (_("trying to write FP")); |
| 564 | |
| 565 | /* Renumber register, if aliase a0..a15. */ |
| 566 | if (regnum >= A0_REGNUM && regnum <= A15_REGNUM) |
| 567 | { |
| 568 | gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); |
| 569 | unsigned int wb; |
| 570 | |
| 571 | regcache_raw_read (regcache, WB_REGNUM, buf); |
| 572 | regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4)); |
| 573 | } |
| 574 | |
| 575 | /* We can always write 'core' registers. |
| 576 | Note: We might have converted Ax->ARy. */ |
| 577 | if (regnum >= 0 && regnum < NUM_REGS) |
| 578 | regcache_raw_write (regcache, regnum, buffer); |
| 579 | |
| 580 | /* Pseudo registers. */ |
| 581 | else if (regnum >= 0 && regnum < NUM_REGS + NUM_PSEUDO_REGS) |
| 582 | { |
| 583 | xtensa_register_t *reg = ®MAP[regnum]; |
| 584 | xtensa_register_type_t type = reg->type; |
| 585 | int flags = XTENSA_TARGET_FLAGS; |
| 586 | |
| 587 | /* On most targets, we can't write registers of type "Unknown" |
| 588 | or "Unmapped". */ |
| 589 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
| 590 | { |
| 591 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) |
| 592 | { |
| 593 | warning (_("cannot write register %s"), |
| 594 | xtensa_register_name (regnum)); |
| 595 | return; |
| 596 | } |
| 597 | } |
| 598 | |
| 599 | /* Some targets cannot read TIE register files. */ |
| 600 | else if (type == xtRegisterTypeTieRegfile) |
| 601 | { |
| 602 | /* Use 'store' to get register? */ |
| 603 | if (flags & xtTargetFlagsUseFetchStore) |
| 604 | { |
| 605 | warning (_("cannot write register")); |
| 606 | return; |
| 607 | } |
| 608 | |
| 609 | /* On some targets (esp. simulators), we can always write |
| 610 | the register. */ |
| 611 | |
| 612 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) |
| 613 | { |
| 614 | warning (_("cannot write register")); |
| 615 | return; |
| 616 | } |
| 617 | } |
| 618 | |
| 619 | /* We can always write mapped registers. */ |
| 620 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) |
| 621 | { |
| 622 | xtensa_register_write_masked (reg, (unsigned char *) buffer); |
| 623 | return; |
| 624 | } |
| 625 | |
| 626 | /* Assume that we can write the register. */ |
| 627 | regcache_raw_write (regcache, regnum, buffer); |
| 628 | } |
| 629 | |
| 630 | else |
| 631 | internal_error (__FILE__, __LINE__, |
| 632 | _("invalid register number %d"), regnum); |
| 633 | } |
| 634 | |
| 635 | |
| 636 | static struct reggroup *xtensa_ar_reggroup; |
| 637 | static struct reggroup *xtensa_user_reggroup; |
| 638 | static struct reggroup *xtensa_vectra_reggroup; |
| 639 | |
| 640 | static void |
| 641 | xtensa_init_reggroups (void) |
| 642 | { |
| 643 | xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP); |
| 644 | xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP); |
| 645 | xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP); |
| 646 | } |
| 647 | |
| 648 | |
| 649 | static void |
| 650 | xtensa_add_reggroups (struct gdbarch *gdbarch) |
| 651 | { |
| 652 | reggroup_add (gdbarch, all_reggroup); |
| 653 | reggroup_add (gdbarch, save_reggroup); |
| 654 | reggroup_add (gdbarch, restore_reggroup); |
| 655 | reggroup_add (gdbarch, system_reggroup); |
| 656 | reggroup_add (gdbarch, vector_reggroup); /* vectra */ |
| 657 | reggroup_add (gdbarch, general_reggroup); /* core */ |
| 658 | reggroup_add (gdbarch, float_reggroup); /* float */ |
| 659 | |
| 660 | reggroup_add (gdbarch, xtensa_ar_reggroup); /* ar */ |
| 661 | reggroup_add (gdbarch, xtensa_user_reggroup); /* user */ |
| 662 | reggroup_add (gdbarch, xtensa_vectra_reggroup); /* vectra */ |
| 663 | } |
| 664 | |
| 665 | |
| 666 | #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \ |
| 667 | | XTENSA_REGISTER_FLAGS_WRITABLE \ |
| 668 | | XTENSA_REGISTER_FLAGS_VOLATILE) |
| 669 | |
| 670 | #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \ |
| 671 | | XTENSA_REGISTER_FLAGS_WRITABLE) |
| 672 | |
| 673 | static int |
| 674 | xtensa_register_reggroup_p (struct gdbarch *gdbarch, |
| 675 | int regnum, |
| 676 | struct reggroup *group) |
| 677 | { |
| 678 | xtensa_register_t* reg = ®MAP[regnum]; |
| 679 | xtensa_register_type_t type = reg->type; |
| 680 | xtensa_register_group_t rg = reg->group; |
| 681 | |
| 682 | /* First, skip registers that are not visible to this target |
| 683 | (unknown and unmapped registers when not using ISS). */ |
| 684 | |
| 685 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
| 686 | return 0; |
| 687 | if (group == all_reggroup) |
| 688 | return 1; |
| 689 | if (group == xtensa_ar_reggroup) |
| 690 | return rg & xtRegisterGroupAddrReg; |
| 691 | if (group == xtensa_user_reggroup) |
| 692 | return rg & xtRegisterGroupUser; |
| 693 | if (group == float_reggroup) |
| 694 | return rg & xtRegisterGroupFloat; |
| 695 | if (group == general_reggroup) |
| 696 | return rg & xtRegisterGroupGeneral; |
| 697 | if (group == float_reggroup) |
| 698 | return rg & xtRegisterGroupFloat; |
| 699 | if (group == system_reggroup) |
| 700 | return rg & xtRegisterGroupState; |
| 701 | if (group == vector_reggroup || group == xtensa_vectra_reggroup) |
| 702 | return rg & xtRegisterGroupVectra; |
| 703 | if (group == save_reggroup || group == restore_reggroup) |
| 704 | return (regnum < NUM_REGS |
| 705 | && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID); |
| 706 | else |
| 707 | return 1; |
| 708 | } |
| 709 | |
| 710 | |
| 711 | /* CORE FILE SUPPORT */ |
| 712 | |
| 713 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
| 714 | in the general-purpose register set REGSET to register cache |
| 715 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ |
| 716 | |
| 717 | static void |
| 718 | xtensa_supply_gregset (const struct regset *regset, |
| 719 | struct regcache *rc, |
| 720 | int regnum, |
| 721 | const void *gregs, |
| 722 | size_t len) |
| 723 | { |
| 724 | const xtensa_elf_gregset_t *regs = gregs; |
| 725 | int i; |
| 726 | |
| 727 | DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum); |
| 728 | |
| 729 | if (regnum == PC_REGNUM || regnum == -1) |
| 730 | regcache_raw_supply (rc, PC_REGNUM, (char *) ®s->pc); |
| 731 | if (regnum == PS_REGNUM || regnum == -1) |
| 732 | regcache_raw_supply (rc, PS_REGNUM, (char *) ®s->ps); |
| 733 | if (regnum == WB_REGNUM || regnum == -1) |
| 734 | regcache_raw_supply (rc, WB_REGNUM, (char *) ®s->windowbase); |
| 735 | if (regnum == WS_REGNUM || regnum == -1) |
| 736 | regcache_raw_supply (rc, WS_REGNUM, (char *) ®s->windowstart); |
| 737 | if (regnum == LBEG_REGNUM || regnum == -1) |
| 738 | regcache_raw_supply (rc, LBEG_REGNUM, (char *) ®s->lbeg); |
| 739 | if (regnum == LEND_REGNUM || regnum == -1) |
| 740 | regcache_raw_supply (rc, LEND_REGNUM, (char *) ®s->lend); |
| 741 | if (regnum == LCOUNT_REGNUM || regnum == -1) |
| 742 | regcache_raw_supply (rc, LCOUNT_REGNUM, (char *) ®s->lcount); |
| 743 | if (regnum == SAR_REGNUM || regnum == -1) |
| 744 | regcache_raw_supply (rc, SAR_REGNUM, (char *) ®s->sar); |
| 745 | if (regnum == EXCCAUSE_REGNUM || regnum == -1) |
| 746 | regcache_raw_supply (rc, EXCCAUSE_REGNUM, (char *) ®s->exccause); |
| 747 | if (regnum == EXCVADDR_REGNUM || regnum == -1) |
| 748 | regcache_raw_supply (rc, EXCVADDR_REGNUM, (char *) ®s->excvaddr); |
| 749 | if (regnum >= AR_BASE && regnum < AR_BASE + NUM_AREGS) |
| 750 | regcache_raw_supply (rc, regnum, (char *) ®s->ar[regnum - AR_BASE]); |
| 751 | else if (regnum == -1) |
| 752 | { |
| 753 | for (i = 0; i < NUM_AREGS; ++i) |
| 754 | regcache_raw_supply (rc, AR_BASE + i, (char *) ®s->ar[i]); |
| 755 | } |
| 756 | } |
| 757 | |
| 758 | |
| 759 | /* Xtensa register set. */ |
| 760 | |
| 761 | static struct regset |
| 762 | xtensa_gregset = |
| 763 | { |
| 764 | NULL, |
| 765 | xtensa_supply_gregset |
| 766 | }; |
| 767 | |
| 768 | |
| 769 | /* Return the appropriate register set for the core section identified |
| 770 | by SECT_NAME and SECT_SIZE. */ |
| 771 | |
| 772 | static const struct regset * |
| 773 | xtensa_regset_from_core_section (struct gdbarch *core_arch, |
| 774 | const char *sect_name, |
| 775 | size_t sect_size) |
| 776 | { |
| 777 | DEBUGTRACE ("xtensa_regset_from_core_section " |
| 778 | "(..., sect_name==\"%s\", sect_size==%x) \n", |
| 779 | sect_name, (int) sect_size); |
| 780 | |
| 781 | if (strcmp (sect_name, ".reg") == 0 |
| 782 | && sect_size >= sizeof(xtensa_elf_gregset_t)) |
| 783 | return &xtensa_gregset; |
| 784 | |
| 785 | return NULL; |
| 786 | } |
| 787 | |
| 788 | |
| 789 | /* F R A M E */ |
| 790 | |
| 791 | /* We currently don't support the call0-abi, so we have at max. 12 registers |
| 792 | saved on the stack. */ |
| 793 | |
| 794 | #define XTENSA_NUM_SAVED_AREGS 12 |
| 795 | |
| 796 | typedef struct xtensa_frame_cache |
| 797 | { |
| 798 | CORE_ADDR base; |
| 799 | CORE_ADDR pc; |
| 800 | CORE_ADDR ra; /* The raw return address; use to compute call_inc. */ |
| 801 | CORE_ADDR ps; |
| 802 | int wb; /* Base for this frame; -1 if not in regfile. */ |
| 803 | int callsize; /* Call size to next frame. */ |
| 804 | int ws; |
| 805 | CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS]; |
| 806 | CORE_ADDR prev_sp; |
| 807 | } xtensa_frame_cache_t; |
| 808 | |
| 809 | |
| 810 | static struct xtensa_frame_cache * |
| 811 | xtensa_alloc_frame_cache (void) |
| 812 | { |
| 813 | xtensa_frame_cache_t *cache; |
| 814 | int i; |
| 815 | |
| 816 | DEBUGTRACE ("xtensa_alloc_frame_cache ()\n"); |
| 817 | |
| 818 | cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t); |
| 819 | |
| 820 | cache->base = 0; |
| 821 | cache->pc = 0; |
| 822 | cache->ra = 0; |
| 823 | cache->wb = 0; |
| 824 | cache->ps = 0; |
| 825 | cache->callsize = -1; |
| 826 | cache->prev_sp = 0; |
| 827 | |
| 828 | for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++) |
| 829 | cache->aregs[i] = -1; |
| 830 | |
| 831 | return cache; |
| 832 | } |
| 833 | |
| 834 | |
| 835 | static CORE_ADDR |
| 836 | xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) |
| 837 | { |
| 838 | return address & ~15; |
| 839 | } |
| 840 | |
| 841 | |
| 842 | static CORE_ADDR |
| 843 | xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 844 | { |
| 845 | gdb_byte buf[8]; |
| 846 | |
| 847 | DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame); |
| 848 | |
| 849 | frame_unwind_register (next_frame, PC_REGNUM, buf); |
| 850 | |
| 851 | DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) |
| 852 | extract_typed_address (buf, builtin_type_void_func_ptr)); |
| 853 | |
| 854 | return extract_typed_address (buf, builtin_type_void_func_ptr); |
| 855 | } |
| 856 | |
| 857 | |
| 858 | static struct frame_id |
| 859 | xtensa_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 860 | { |
| 861 | CORE_ADDR pc, fp; |
| 862 | gdb_byte buf[4]; |
| 863 | |
| 864 | /* next_frame->prev is a dummy frame. Return a frame ID of that frame. */ |
| 865 | |
| 866 | DEBUGTRACE ("xtensa_unwind_dummy_id ()\n"); |
| 867 | |
| 868 | pc = frame_pc_unwind (next_frame); |
| 869 | frame_unwind_register (next_frame, A1_REGNUM, buf); |
| 870 | fp = extract_unsigned_integer (buf, 4); |
| 871 | |
| 872 | /* Make dummy frame ID unique by adding a constant. */ |
| 873 | return frame_id_build (fp+SP_ALIGNMENT, pc); |
| 874 | } |
| 875 | |
| 876 | |
| 877 | static struct xtensa_frame_cache * |
| 878 | xtensa_frame_cache (struct frame_info *next_frame, void **this_cache) |
| 879 | { |
| 880 | xtensa_frame_cache_t *cache; |
| 881 | char buf[4]; |
| 882 | CORE_ADDR ra, wb, ws, pc, sp, ps; |
| 883 | char op1; |
| 884 | |
| 885 | DEBUGTRACE ("xtensa_frame_cache (next_frame %p, *this_cache %p)\n", |
| 886 | next_frame, this_cache ? *this_cache : (void*)0xdeadbeef); |
| 887 | |
| 888 | /* Already cached? */ |
| 889 | if (*this_cache) |
| 890 | return *this_cache; |
| 891 | |
| 892 | /* Get pristine xtensa-frame. */ |
| 893 | cache = xtensa_alloc_frame_cache (); |
| 894 | *this_cache = cache; |
| 895 | |
| 896 | /* Get windowbase, windowstart, ps, and pc. */ |
| 897 | wb = frame_unwind_register_unsigned (next_frame, WB_REGNUM); |
| 898 | ws = frame_unwind_register_unsigned (next_frame, WS_REGNUM); |
| 899 | ps = frame_unwind_register_unsigned (next_frame, PS_REGNUM); |
| 900 | pc = frame_unwind_register_unsigned (next_frame, PC_REGNUM); |
| 901 | |
| 902 | op1 = read_memory_integer (pc, 1); |
| 903 | if (XTENSA_IS_ENTRY (op1) || !windowing_enabled (read_register (PS_REGNUM))) |
| 904 | { |
| 905 | int callinc = CALLINC (frame_unwind_register_unsigned (next_frame, |
| 906 | PS_REGNUM)); |
| 907 | ra = frame_unwind_register_unsigned (next_frame, |
| 908 | A0_REGNUM + callinc * 4); |
| 909 | |
| 910 | DEBUGINFO("[xtensa_frame_cache] 'entry' at 0x%08x\n (callinc = %d)", |
| 911 | (int)pc, callinc); |
| 912 | |
| 913 | /* ENTRY hasn't been executed yet, therefore callsize is still 0. */ |
| 914 | cache->callsize = 0; |
| 915 | cache->wb = wb; |
| 916 | cache->ws = ws; |
| 917 | cache->prev_sp = read_register (A1_REGNUM); |
| 918 | } |
| 919 | else |
| 920 | { |
| 921 | ra = frame_unwind_register_unsigned (next_frame, A0_REGNUM); |
| 922 | cache->callsize = WINSIZE (ra); |
| 923 | cache->wb = (wb - (cache->callsize / 4)) & ((NUM_AREGS / 4) - 1); |
| 924 | cache->ws = ws & ~(1 << wb); |
| 925 | } |
| 926 | |
| 927 | cache->pc = ((frame_func_unwind (next_frame, NORMAL_FRAME) & 0xc0000000) |
| 928 | | (ra & 0x3fffffff)); |
| 929 | cache->ps = (ps & ~PS_CALLINC_MASK) | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); |
| 930 | |
| 931 | |
| 932 | /* Note: We could also calculate the location on stack when we actually |
| 933 | access the register. However, this approach, saving the location |
| 934 | in the cache frame, is probably easier to support the call0 ABI. */ |
| 935 | |
| 936 | if (cache->ws == 0) |
| 937 | { |
| 938 | int i; |
| 939 | |
| 940 | /* Set A0...A3. */ |
| 941 | sp = frame_unwind_register_unsigned (next_frame, A1_REGNUM) - 16; |
| 942 | |
| 943 | for (i = 0; i < 4; i++, sp += 4) |
| 944 | { |
| 945 | cache->aregs[i] = sp; |
| 946 | } |
| 947 | |
| 948 | if (cache->callsize > 4) |
| 949 | { |
| 950 | /* Set A4...A7/A11. */ |
| 951 | |
| 952 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4); |
| 953 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4); |
| 954 | sp -= cache->callsize * 4; |
| 955 | |
| 956 | for ( /* i=4 */ ; i < cache->callsize; i++, sp += 4) |
| 957 | { |
| 958 | cache->aregs[i] = sp; |
| 959 | } |
| 960 | } |
| 961 | } |
| 962 | |
| 963 | if (cache->prev_sp == 0) |
| 964 | { |
| 965 | if (cache->ws == 0) |
| 966 | { |
| 967 | /* Register window overflow already happened. |
| 968 | We can read caller's frame SP from the proper spill loction. */ |
| 969 | cache->prev_sp = |
| 970 | read_memory_integer (cache->aregs[1], |
| 971 | register_size (current_gdbarch, |
| 972 | A1_REGNUM)); |
| 973 | } |
| 974 | else |
| 975 | { |
| 976 | /* Read caller's frame SP directly from the previous window. */ |
| 977 | |
| 978 | int regnum = AREG_NUMBER (A1_REGNUM, cache->wb); |
| 979 | |
| 980 | cache->prev_sp = read_register (regnum); |
| 981 | } |
| 982 | } |
| 983 | |
| 984 | cache->base = frame_unwind_register_unsigned (next_frame,A1_REGNUM); |
| 985 | |
| 986 | DEBUGINFO ("[xtensa_frame_cache] base 0x%08x, wb %d, " |
| 987 | "ws 0x%08x, callsize %d, pc 0x%08x, ps 0x%08x, prev_sp 0x%08x\n", |
| 988 | (unsigned int) cache->base, (unsigned int) cache->wb, |
| 989 | cache->ws, cache->callsize, (unsigned int) cache->pc, |
| 990 | (unsigned int) cache->ps, (unsigned int) cache->prev_sp); |
| 991 | |
| 992 | return cache; |
| 993 | } |
| 994 | |
| 995 | |
| 996 | static void |
| 997 | xtensa_frame_this_id (struct frame_info *next_frame, |
| 998 | void **this_cache, |
| 999 | struct frame_id *this_id) |
| 1000 | { |
| 1001 | struct xtensa_frame_cache *cache = |
| 1002 | xtensa_frame_cache (next_frame, this_cache); |
| 1003 | |
| 1004 | DEBUGTRACE ("xtensa_frame_this_id (next %p, *this %p)\n", |
| 1005 | next_frame, *this_cache); |
| 1006 | |
| 1007 | if (cache->prev_sp == 0) |
| 1008 | return; |
| 1009 | |
| 1010 | (*this_id) = frame_id_build (cache->prev_sp, cache->pc); |
| 1011 | } |
| 1012 | |
| 1013 | |
| 1014 | static void |
| 1015 | xtensa_frame_prev_register (struct frame_info *next_frame, |
| 1016 | void **this_cache, |
| 1017 | int regnum, |
| 1018 | int *optimizedp, |
| 1019 | enum lval_type *lvalp, |
| 1020 | CORE_ADDR *addrp, |
| 1021 | int *realnump, |
| 1022 | gdb_byte *valuep) |
| 1023 | { |
| 1024 | struct xtensa_frame_cache *cache = |
| 1025 | xtensa_frame_cache (next_frame, this_cache); |
| 1026 | CORE_ADDR saved_reg = 0; |
| 1027 | int done = 1; |
| 1028 | |
| 1029 | DEBUGTRACE ("xtensa_frame_prev_register (next %p, " |
| 1030 | "*this %p, regnum %d (%s), ...)\n", |
| 1031 | next_frame, |
| 1032 | *this_cache ? *this_cache : 0, regnum, |
| 1033 | xtensa_register_name (regnum)); |
| 1034 | |
| 1035 | if (regnum == WS_REGNUM) |
| 1036 | { |
| 1037 | if (cache->ws != 0) |
| 1038 | saved_reg = cache->ws; |
| 1039 | else |
| 1040 | saved_reg = 1 << cache->wb; |
| 1041 | } |
| 1042 | else if (regnum == WB_REGNUM) |
| 1043 | saved_reg = cache->wb; |
| 1044 | else if (regnum == PC_REGNUM) |
| 1045 | saved_reg = cache->pc; |
| 1046 | else if (regnum == PS_REGNUM) |
| 1047 | saved_reg = cache->ps; |
| 1048 | else |
| 1049 | done = 0; |
| 1050 | |
| 1051 | if (done) |
| 1052 | { |
| 1053 | *optimizedp = 0; |
| 1054 | *lvalp = not_lval; |
| 1055 | *addrp = 0; |
| 1056 | *realnump = -1; |
| 1057 | if (valuep) |
| 1058 | store_unsigned_integer (valuep, 4, saved_reg); |
| 1059 | |
| 1060 | return; |
| 1061 | } |
| 1062 | |
| 1063 | /* Convert Ax register numbers to ARx register numbers. */ |
| 1064 | if (regnum >= A0_REGNUM && regnum <= A15_REGNUM) |
| 1065 | regnum = AREG_NUMBER (regnum, cache->wb); |
| 1066 | |
| 1067 | /* Check if ARx register has been saved to stack. */ |
| 1068 | if (regnum >= AR_BASE && regnum <= (AR_BASE + NUM_AREGS)) |
| 1069 | { |
| 1070 | int areg = regnum - AR_BASE - (cache->wb * 4); |
| 1071 | |
| 1072 | if (areg >= 0 |
| 1073 | && areg < XTENSA_NUM_SAVED_AREGS |
| 1074 | && cache->aregs[areg] != -1) |
| 1075 | { |
| 1076 | *optimizedp = 0; |
| 1077 | *lvalp = lval_memory; |
| 1078 | *addrp = cache->aregs[areg]; |
| 1079 | *realnump = -1; |
| 1080 | |
| 1081 | if (valuep) |
| 1082 | read_memory (*addrp, valuep, |
| 1083 | register_size (current_gdbarch, regnum)); |
| 1084 | |
| 1085 | DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n"); |
| 1086 | return; |
| 1087 | } |
| 1088 | } |
| 1089 | |
| 1090 | /* Note: All other registers have been either saved to the dummy stack |
| 1091 | or are still alive in the processor. */ |
| 1092 | |
| 1093 | *optimizedp = 0; |
| 1094 | *lvalp = lval_register; |
| 1095 | *addrp = 0; |
| 1096 | *realnump = regnum; |
| 1097 | if (valuep) |
| 1098 | frame_unwind_register (next_frame, (*realnump), valuep); |
| 1099 | } |
| 1100 | |
| 1101 | |
| 1102 | static const struct frame_unwind |
| 1103 | xtensa_frame_unwind = |
| 1104 | { |
| 1105 | NORMAL_FRAME, |
| 1106 | xtensa_frame_this_id, |
| 1107 | xtensa_frame_prev_register |
| 1108 | }; |
| 1109 | |
| 1110 | static const struct frame_unwind * |
| 1111 | xtensa_frame_sniffer (struct frame_info *next_frame) |
| 1112 | { |
| 1113 | return &xtensa_frame_unwind; |
| 1114 | } |
| 1115 | |
| 1116 | static CORE_ADDR |
| 1117 | xtensa_frame_base_address (struct frame_info *next_frame, void **this_cache) |
| 1118 | { |
| 1119 | struct xtensa_frame_cache *cache = |
| 1120 | xtensa_frame_cache (next_frame, this_cache); |
| 1121 | |
| 1122 | return cache->base; |
| 1123 | } |
| 1124 | |
| 1125 | static const struct frame_base |
| 1126 | xtensa_frame_base = |
| 1127 | { |
| 1128 | &xtensa_frame_unwind, |
| 1129 | xtensa_frame_base_address, |
| 1130 | xtensa_frame_base_address, |
| 1131 | xtensa_frame_base_address |
| 1132 | }; |
| 1133 | |
| 1134 | |
| 1135 | static void |
| 1136 | xtensa_extract_return_value (struct type *type, |
| 1137 | struct regcache *regcache, |
| 1138 | void *dst) |
| 1139 | { |
| 1140 | bfd_byte *valbuf = dst; |
| 1141 | int len = TYPE_LENGTH (type); |
| 1142 | ULONGEST pc, wb; |
| 1143 | int callsize, areg; |
| 1144 | int offset = 0; |
| 1145 | |
| 1146 | DEBUGTRACE ("xtensa_extract_return_value (...)\n"); |
| 1147 | |
| 1148 | gdb_assert(len > 0); |
| 1149 | |
| 1150 | /* First, we have to find the caller window in the register file. */ |
| 1151 | regcache_raw_read_unsigned (regcache, PC_REGNUM, &pc); |
| 1152 | callsize = extract_call_winsize (pc); |
| 1153 | |
| 1154 | /* On Xtensa, we can return up to 4 words (or 2 when called by call12). */ |
| 1155 | if (len > (callsize > 8 ? 8 : 16)) |
| 1156 | internal_error (__FILE__, __LINE__, |
| 1157 | _("cannot extract return value of %d bytes long"), len); |
| 1158 | |
| 1159 | /* Get the register offset of the return register (A2) in the caller |
| 1160 | window. */ |
| 1161 | regcache_raw_read_unsigned (regcache, WB_REGNUM, &wb); |
| 1162 | areg = AREG_NUMBER(A2_REGNUM + callsize, wb); |
| 1163 | |
| 1164 | DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len); |
| 1165 | |
| 1166 | if (len < 4 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 1167 | offset = 4 - len; |
| 1168 | |
| 1169 | for (; len > 0; len -= 4, areg++, valbuf += 4) |
| 1170 | { |
| 1171 | if (len < 4) |
| 1172 | regcache_raw_read_part (regcache, areg, offset, len, valbuf); |
| 1173 | else |
| 1174 | regcache_raw_read (regcache, areg, valbuf); |
| 1175 | } |
| 1176 | } |
| 1177 | |
| 1178 | |
| 1179 | static void |
| 1180 | xtensa_store_return_value (struct type *type, |
| 1181 | struct regcache *regcache, |
| 1182 | const void *dst) |
| 1183 | { |
| 1184 | const bfd_byte *valbuf = dst; |
| 1185 | unsigned int areg; |
| 1186 | ULONGEST pc, wb; |
| 1187 | int callsize; |
| 1188 | int len = TYPE_LENGTH (type); |
| 1189 | int offset = 0; |
| 1190 | |
| 1191 | DEBUGTRACE ("xtensa_store_return_value (...)\n"); |
| 1192 | |
| 1193 | regcache_raw_read_unsigned (regcache, WB_REGNUM, &wb); |
| 1194 | regcache_raw_read_unsigned (regcache, PC_REGNUM, &pc); |
| 1195 | callsize = extract_call_winsize (pc); |
| 1196 | |
| 1197 | if (len > (callsize > 8 ? 8 : 16)) |
| 1198 | internal_error (__FILE__, __LINE__, |
| 1199 | _("unimplemented for this length: %d"), |
| 1200 | TYPE_LENGTH (type)); |
| 1201 | |
| 1202 | DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n", |
| 1203 | callsize, (int) wb); |
| 1204 | |
| 1205 | if (len < 4 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 1206 | offset = 4 - len; |
| 1207 | |
| 1208 | areg = AREG_NUMBER (A2_REGNUM + callsize, wb); |
| 1209 | |
| 1210 | for (; len > 0; len -= 4, areg++, valbuf += 4) |
| 1211 | { |
| 1212 | if (len < 4) |
| 1213 | regcache_raw_write_part (regcache, areg, offset, len, valbuf); |
| 1214 | else |
| 1215 | regcache_raw_write (regcache, areg, valbuf); |
| 1216 | } |
| 1217 | } |
| 1218 | |
| 1219 | |
| 1220 | enum return_value_convention |
| 1221 | xtensa_return_value (struct gdbarch *gdbarch, |
| 1222 | struct type *valtype, |
| 1223 | struct regcache *regcache, |
| 1224 | gdb_byte *readbuf, |
| 1225 | const gdb_byte *writebuf) |
| 1226 | { |
| 1227 | /* Note: Structures up to 16 bytes are returned in registers. */ |
| 1228 | |
| 1229 | int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
| 1230 | || TYPE_CODE (valtype) == TYPE_CODE_UNION |
| 1231 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) |
| 1232 | && TYPE_LENGTH (valtype) > 16); |
| 1233 | |
| 1234 | if (struct_return) |
| 1235 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 1236 | |
| 1237 | DEBUGTRACE ("xtensa_return_value(...)\n"); |
| 1238 | |
| 1239 | if (writebuf != NULL) |
| 1240 | { |
| 1241 | xtensa_store_return_value (valtype, regcache, writebuf); |
| 1242 | } |
| 1243 | |
| 1244 | if (readbuf != NULL) |
| 1245 | { |
| 1246 | gdb_assert (!struct_return); |
| 1247 | xtensa_extract_return_value (valtype, regcache, readbuf); |
| 1248 | } |
| 1249 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 1250 | } |
| 1251 | |
| 1252 | |
| 1253 | /* DUMMY FRAME */ |
| 1254 | |
| 1255 | static CORE_ADDR |
| 1256 | xtensa_push_dummy_call (struct gdbarch *gdbarch, |
| 1257 | struct value *function, |
| 1258 | struct regcache *regcache, |
| 1259 | CORE_ADDR bp_addr, |
| 1260 | int nargs, |
| 1261 | struct value **args, |
| 1262 | CORE_ADDR sp, |
| 1263 | int struct_return, |
| 1264 | CORE_ADDR struct_addr) |
| 1265 | { |
| 1266 | int i; |
| 1267 | int size, onstack_size; |
| 1268 | gdb_byte *buf = (gdb_byte *) alloca (16); |
| 1269 | CORE_ADDR ra, ps; |
| 1270 | struct argument_info |
| 1271 | { |
| 1272 | const bfd_byte *contents; |
| 1273 | int length; |
| 1274 | int onstack; /* onstack == 0 => in reg */ |
| 1275 | int align; /* alignment */ |
| 1276 | union |
| 1277 | { |
| 1278 | int offset; /* stack offset if on stack */ |
| 1279 | int regno; /* regno if in register */ |
| 1280 | } u; |
| 1281 | }; |
| 1282 | |
| 1283 | struct argument_info *arg_info = |
| 1284 | (struct argument_info *) alloca (nargs * sizeof (struct argument_info)); |
| 1285 | |
| 1286 | CORE_ADDR osp = sp; |
| 1287 | |
| 1288 | DEBUGTRACE ("xtensa_push_dummy_call (...)\n"); |
| 1289 | |
| 1290 | if (xtensa_debug_level > 3) |
| 1291 | { |
| 1292 | int i; |
| 1293 | DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs); |
| 1294 | DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, " |
| 1295 | "struct_addr=0x%x\n", |
| 1296 | (int) sp, (int) struct_return, (int) struct_addr); |
| 1297 | |
| 1298 | for (i = 0; i < nargs; i++) |
| 1299 | { |
| 1300 | struct value *arg = args[i]; |
| 1301 | struct type *arg_type = check_typedef (value_type (arg)); |
| 1302 | fprintf_unfiltered (gdb_stdlog, "%2d: %p %3d ", |
| 1303 | i, arg, TYPE_LENGTH (arg_type)); |
| 1304 | switch (TYPE_CODE (arg_type)) |
| 1305 | { |
| 1306 | case TYPE_CODE_INT: |
| 1307 | fprintf_unfiltered (gdb_stdlog, "int"); |
| 1308 | break; |
| 1309 | case TYPE_CODE_STRUCT: |
| 1310 | fprintf_unfiltered (gdb_stdlog, "struct"); |
| 1311 | break; |
| 1312 | default: |
| 1313 | fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type)); |
| 1314 | break; |
| 1315 | } |
| 1316 | fprintf_unfiltered (gdb_stdlog, " %p\n", |
| 1317 | value_contents (arg)); |
| 1318 | } |
| 1319 | } |
| 1320 | |
| 1321 | /* First loop: collect information. |
| 1322 | Cast into type_long. (This shouldn't happen often for C because |
| 1323 | GDB already does this earlier.) It's possible that GDB could |
| 1324 | do it all the time but it's harmless to leave this code here. */ |
| 1325 | |
| 1326 | size = 0; |
| 1327 | onstack_size = 0; |
| 1328 | i = 0; |
| 1329 | |
| 1330 | if (struct_return) |
| 1331 | size = REGISTER_SIZE; |
| 1332 | |
| 1333 | for (i = 0; i < nargs; i++) |
| 1334 | { |
| 1335 | struct argument_info *info = &arg_info[i]; |
| 1336 | struct value *arg = args[i]; |
| 1337 | struct type *arg_type = check_typedef (value_type (arg)); |
| 1338 | |
| 1339 | switch (TYPE_CODE (arg_type)) |
| 1340 | { |
| 1341 | case TYPE_CODE_INT: |
| 1342 | case TYPE_CODE_BOOL: |
| 1343 | case TYPE_CODE_CHAR: |
| 1344 | case TYPE_CODE_RANGE: |
| 1345 | case TYPE_CODE_ENUM: |
| 1346 | |
| 1347 | /* Cast argument to long if necessary as the mask does it too. */ |
| 1348 | if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long)) |
| 1349 | { |
| 1350 | arg_type = builtin_type_long; |
| 1351 | arg = value_cast (arg_type, arg); |
| 1352 | } |
| 1353 | info->align = TYPE_LENGTH (builtin_type_long); |
| 1354 | break; |
| 1355 | |
| 1356 | case TYPE_CODE_FLT: |
| 1357 | |
| 1358 | /* Align doubles correctly. */ |
| 1359 | if (TYPE_LENGTH (arg_type) == TYPE_LENGTH (builtin_type_double)) |
| 1360 | info->align = TYPE_LENGTH (builtin_type_double); |
| 1361 | else |
| 1362 | info->align = TYPE_LENGTH (builtin_type_long); |
| 1363 | break; |
| 1364 | |
| 1365 | case TYPE_CODE_STRUCT: |
| 1366 | default: |
| 1367 | info->align = TYPE_LENGTH (builtin_type_long); |
| 1368 | break; |
| 1369 | } |
| 1370 | info->length = TYPE_LENGTH (arg_type); |
| 1371 | info->contents = value_contents (arg); |
| 1372 | |
| 1373 | /* Align size and onstack_size. */ |
| 1374 | size = (size + info->align - 1) & ~(info->align - 1); |
| 1375 | onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1); |
| 1376 | |
| 1377 | if (size + info->length > REGISTER_SIZE * ARGS_NUM_REGS) |
| 1378 | { |
| 1379 | info->onstack = 1; |
| 1380 | info->u.offset = onstack_size; |
| 1381 | onstack_size += info->length; |
| 1382 | } |
| 1383 | else |
| 1384 | { |
| 1385 | info->onstack = 0; |
| 1386 | info->u.regno = ARGS_FIRST_REG + size / REGISTER_SIZE; |
| 1387 | } |
| 1388 | size += info->length; |
| 1389 | } |
| 1390 | |
| 1391 | /* Adjust the stack pointer and align it. */ |
| 1392 | sp = align_down (sp - onstack_size, SP_ALIGNMENT); |
| 1393 | |
| 1394 | /* Simulate MOVSP. */ |
| 1395 | if (sp != osp) |
| 1396 | { |
| 1397 | read_memory (osp - 16, buf, 16); |
| 1398 | write_memory (sp - 16, buf, 16); |
| 1399 | } |
| 1400 | |
| 1401 | /* Second Loop: Load arguments. */ |
| 1402 | |
| 1403 | if (struct_return) |
| 1404 | { |
| 1405 | store_unsigned_integer (buf, REGISTER_SIZE, struct_addr); |
| 1406 | regcache_cooked_write (regcache, ARGS_FIRST_REG, buf); |
| 1407 | } |
| 1408 | |
| 1409 | for (i = 0; i < nargs; i++) |
| 1410 | { |
| 1411 | struct argument_info *info = &arg_info[i]; |
| 1412 | |
| 1413 | if (info->onstack) |
| 1414 | { |
| 1415 | int n = info->length; |
| 1416 | CORE_ADDR offset = sp + info->u.offset; |
| 1417 | |
| 1418 | /* Odd-sized structs are aligned to the lower side of a memory |
| 1419 | word in big-endian mode and require a shift. This only |
| 1420 | applies for structures smaller than one word. */ |
| 1421 | |
| 1422 | if (n < REGISTER_SIZE && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 1423 | offset += (REGISTER_SIZE - n); |
| 1424 | |
| 1425 | write_memory (offset, info->contents, info->length); |
| 1426 | |
| 1427 | } |
| 1428 | else |
| 1429 | { |
| 1430 | int n = info->length; |
| 1431 | const bfd_byte *cp = info->contents; |
| 1432 | int r = info->u.regno; |
| 1433 | |
| 1434 | /* Odd-sized structs are aligned to the lower side of registers in |
| 1435 | big-endian mode and require a shift. The odd-sized leftover will |
| 1436 | be at the end. Note that this is only true for structures smaller |
| 1437 | than REGISTER_SIZE; for larger odd-sized structures the excess |
| 1438 | will be left-aligned in the register on both endiannesses. */ |
| 1439 | |
| 1440 | if (n < REGISTER_SIZE && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 1441 | { |
| 1442 | ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE); |
| 1443 | v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT); |
| 1444 | |
| 1445 | store_unsigned_integer (buf, REGISTER_SIZE, v); |
| 1446 | regcache_cooked_write (regcache, r, buf); |
| 1447 | |
| 1448 | cp += REGISTER_SIZE; |
| 1449 | n -= REGISTER_SIZE; |
| 1450 | r++; |
| 1451 | } |
| 1452 | else |
| 1453 | while (n > 0) |
| 1454 | { |
| 1455 | /* ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE);*/ |
| 1456 | regcache_cooked_write (regcache, r, cp); |
| 1457 | |
| 1458 | /* write_register (r, v); */ |
| 1459 | cp += REGISTER_SIZE; |
| 1460 | n -= REGISTER_SIZE; |
| 1461 | r++; |
| 1462 | } |
| 1463 | } |
| 1464 | } |
| 1465 | |
| 1466 | |
| 1467 | /* Set the return address of dummy frame to the dummy address. |
| 1468 | Note: The return address for the current function (in A0) is |
| 1469 | saved in the dummy frame, so we can savely overwrite A0 here. */ |
| 1470 | |
| 1471 | ra = (bp_addr & 0x3fffffff) | 0x40000000; |
| 1472 | regcache_raw_read (regcache, PS_REGNUM, buf); |
| 1473 | ps = extract_unsigned_integer (buf, 4) & ~0x00030000; |
| 1474 | regcache_cooked_write_unsigned (regcache, A4_REGNUM, ra); |
| 1475 | regcache_cooked_write_unsigned (regcache, PS_REGNUM, ps | 0x00010000); |
| 1476 | |
| 1477 | /* Set new stack pointer and return it. */ |
| 1478 | regcache_cooked_write_unsigned (regcache, A1_REGNUM, sp); |
| 1479 | /* Make dummy frame ID unique by adding a constant. */ |
| 1480 | return sp + SP_ALIGNMENT; |
| 1481 | } |
| 1482 | |
| 1483 | |
| 1484 | /* Return a breakpoint for the current location of PC. We always use |
| 1485 | the density version if we have density instructions (regardless of the |
| 1486 | current instruction at PC), and use regular instructions otherwise. */ |
| 1487 | |
| 1488 | #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 } |
| 1489 | #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 } |
| 1490 | #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f } |
| 1491 | #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 } |
| 1492 | |
| 1493 | const unsigned char * |
| 1494 | xtensa_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
| 1495 | { |
| 1496 | static unsigned char big_breakpoint[] = BIG_BREAKPOINT; |
| 1497 | static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; |
| 1498 | static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT; |
| 1499 | static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT; |
| 1500 | |
| 1501 | DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr); |
| 1502 | |
| 1503 | if (ISA_USE_DENSITY_INSTRUCTIONS) |
| 1504 | { |
| 1505 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 1506 | { |
| 1507 | *lenptr = sizeof (density_big_breakpoint); |
| 1508 | return density_big_breakpoint; |
| 1509 | } |
| 1510 | else |
| 1511 | { |
| 1512 | *lenptr = sizeof (density_little_breakpoint); |
| 1513 | return density_little_breakpoint; |
| 1514 | } |
| 1515 | } |
| 1516 | else |
| 1517 | { |
| 1518 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 1519 | { |
| 1520 | *lenptr = sizeof (big_breakpoint); |
| 1521 | return big_breakpoint; |
| 1522 | } |
| 1523 | else |
| 1524 | { |
| 1525 | *lenptr = sizeof (little_breakpoint); |
| 1526 | return little_breakpoint; |
| 1527 | } |
| 1528 | } |
| 1529 | } |
| 1530 | |
| 1531 | |
| 1532 | /* Return the pc of the first real instruction. We assume that this |
| 1533 | machine uses register windows. |
| 1534 | |
| 1535 | If we have debug info ( line-number info, in particular ) we simply skip |
| 1536 | the code associated with the first function line effectively skipping |
| 1537 | the prologue code. It works even in cases like |
| 1538 | |
| 1539 | int main() |
| 1540 | { int local_var = 1; |
| 1541 | .... |
| 1542 | } |
| 1543 | |
| 1544 | because, for this source code, both Xtensa compilers will generate two |
| 1545 | separate entries ( with the same line number ) in dwarf line-number |
| 1546 | section to make sure there is a boundary between the prologue code and |
| 1547 | the rest of the function. |
| 1548 | |
| 1549 | If there is no debug info, we need to analyze the code. */ |
| 1550 | |
| 1551 | CORE_ADDR |
| 1552 | xtensa_skip_prologue (CORE_ADDR start_pc) |
| 1553 | { |
| 1554 | DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc); |
| 1555 | |
| 1556 | if (ISA_USE_WINDOWED_REGISTERS) |
| 1557 | { |
| 1558 | unsigned char op1; |
| 1559 | struct symtab_and_line prologue_sal; |
| 1560 | |
| 1561 | op1 = read_memory_integer (start_pc, 1); |
| 1562 | if (!XTENSA_IS_ENTRY (op1)) |
| 1563 | return start_pc; |
| 1564 | |
| 1565 | prologue_sal = find_pc_line (start_pc, 0); |
| 1566 | if (prologue_sal.line != 0) |
| 1567 | return prologue_sal.end; |
| 1568 | else |
| 1569 | return start_pc + XTENSA_ENTRY_LENGTH; |
| 1570 | } |
| 1571 | else |
| 1572 | { |
| 1573 | internal_error (__FILE__, __LINE__, |
| 1574 | _("non-windowed configurations are not supported")); |
| 1575 | return start_pc; |
| 1576 | } |
| 1577 | } |
| 1578 | |
| 1579 | |
| 1580 | /* CONFIGURATION CHECK */ |
| 1581 | |
| 1582 | /* Verify the current configuration. */ |
| 1583 | |
| 1584 | static void |
| 1585 | xtensa_verify_config (struct gdbarch *gdbarch) |
| 1586 | { |
| 1587 | struct ui_file *log; |
| 1588 | struct cleanup *cleanups; |
| 1589 | struct gdbarch_tdep *tdep; |
| 1590 | long dummy; |
| 1591 | char *buf; |
| 1592 | |
| 1593 | tdep = gdbarch_tdep (gdbarch); |
| 1594 | log = mem_fileopen (); |
| 1595 | cleanups = make_cleanup_ui_file_delete (log); |
| 1596 | |
| 1597 | /* Verify that we got a reasonable number of AREGS. */ |
| 1598 | if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs) |
| 1599 | fprintf_unfiltered (log, "\n\tnum_aregs: Number of AR registers (%d) " |
| 1600 | "is not a power of two!", tdep->num_aregs); |
| 1601 | |
| 1602 | /* Verify that certain registers exist. */ |
| 1603 | if (tdep->pc_regnum == -1) |
| 1604 | fprintf_unfiltered (log, "\n\tpc_regnum: No PC register"); |
| 1605 | if (tdep->ps_regnum == -1) |
| 1606 | fprintf_unfiltered (log, "\n\tps_regnum: No PS register"); |
| 1607 | if (tdep->wb_regnum == -1) |
| 1608 | fprintf_unfiltered (log, "\n\twb_regnum: No WB register"); |
| 1609 | if (tdep->ws_regnum == -1) |
| 1610 | fprintf_unfiltered (log, "\n\tws_regnum: No WS register"); |
| 1611 | if (tdep->ar_base == -1) |
| 1612 | fprintf_unfiltered (log, "\n\tar_base: No AR registers"); |
| 1613 | if (tdep->a0_base == -1) |
| 1614 | fprintf_unfiltered (log, "\n\ta0_base: No Ax registers"); |
| 1615 | |
| 1616 | buf = ui_file_xstrdup (log, &dummy); |
| 1617 | make_cleanup (xfree, buf); |
| 1618 | if (strlen (buf) > 0) |
| 1619 | internal_error (__FILE__, __LINE__, |
| 1620 | _("the following are invalid: %s"), buf); |
| 1621 | do_cleanups (cleanups); |
| 1622 | } |
| 1623 | |
| 1624 | |
| 1625 | /* Module "constructor" function. */ |
| 1626 | |
| 1627 | static struct gdbarch * |
| 1628 | xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 1629 | { |
| 1630 | struct gdbarch_tdep *tdep; |
| 1631 | struct gdbarch *gdbarch; |
| 1632 | struct xtensa_abi_handler *abi_handler; |
| 1633 | |
| 1634 | DEBUGTRACE ("gdbarch_init()\n"); |
| 1635 | |
| 1636 | /* We have to set the byte order before we call gdbarch_alloc. */ |
| 1637 | info.byte_order = xtensa_config_byte_order (&info); |
| 1638 | |
| 1639 | tdep = xtensa_config_tdep (&info); |
| 1640 | gdbarch = gdbarch_alloc (&info, tdep); |
| 1641 | |
| 1642 | /* Verify our configuration. */ |
| 1643 | xtensa_verify_config (gdbarch); |
| 1644 | |
| 1645 | /* Pseudo-Register read/write */ |
| 1646 | set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read); |
| 1647 | set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write); |
| 1648 | |
| 1649 | /* Set target information. */ |
| 1650 | set_gdbarch_num_regs (gdbarch, tdep->num_regs); |
| 1651 | set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs); |
| 1652 | set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1); |
| 1653 | set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum); |
| 1654 | set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum); |
| 1655 | |
| 1656 | /* Renumber registers for known formats (stab, dwarf, and dwarf2). */ |
| 1657 | set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); |
| 1658 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); |
| 1659 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); |
| 1660 | |
| 1661 | /* We provide our own function to get register information. */ |
| 1662 | set_gdbarch_register_name (gdbarch, xtensa_register_name); |
| 1663 | set_gdbarch_register_type (gdbarch, xtensa_register_type); |
| 1664 | |
| 1665 | /* To call functions from GDB using dummy frame */ |
| 1666 | set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call); |
| 1667 | |
| 1668 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
| 1669 | |
| 1670 | set_gdbarch_return_value (gdbarch, xtensa_return_value); |
| 1671 | |
| 1672 | /* Advance PC across any prologue instructions to reach "real" code. */ |
| 1673 | set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue); |
| 1674 | |
| 1675 | /* Stack grows downward. */ |
| 1676 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 1677 | |
| 1678 | /* Set breakpoints. */ |
| 1679 | set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc); |
| 1680 | |
| 1681 | /* After breakpoint instruction or illegal instruction, pc still |
| 1682 | points at break instruction, so don't decrement. */ |
| 1683 | set_gdbarch_decr_pc_after_break (gdbarch, 0); |
| 1684 | |
| 1685 | /* We don't skip args. */ |
| 1686 | set_gdbarch_frame_args_skip (gdbarch, 0); |
| 1687 | |
| 1688 | set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc); |
| 1689 | |
| 1690 | set_gdbarch_frame_align (gdbarch, xtensa_frame_align); |
| 1691 | |
| 1692 | set_gdbarch_unwind_dummy_id (gdbarch, xtensa_unwind_dummy_id); |
| 1693 | |
| 1694 | /* Frame handling. */ |
| 1695 | frame_base_set_default (gdbarch, &xtensa_frame_base); |
| 1696 | frame_unwind_append_sniffer (gdbarch, xtensa_frame_sniffer); |
| 1697 | |
| 1698 | set_gdbarch_print_insn (gdbarch, print_insn_xtensa); |
| 1699 | |
| 1700 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
| 1701 | |
| 1702 | xtensa_add_reggroups (gdbarch); |
| 1703 | set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p); |
| 1704 | |
| 1705 | set_gdbarch_regset_from_core_section (gdbarch, |
| 1706 | xtensa_regset_from_core_section); |
| 1707 | |
| 1708 | return gdbarch; |
| 1709 | } |
| 1710 | |
| 1711 | |
| 1712 | /* Dump xtensa tdep structure. */ |
| 1713 | |
| 1714 | static void |
| 1715 | xtensa_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) |
| 1716 | { |
| 1717 | error (_("xtensa_dump_tdep(): not implemented")); |
| 1718 | } |
| 1719 | |
| 1720 | |
| 1721 | void |
| 1722 | _initialize_xtensa_tdep (void) |
| 1723 | { |
| 1724 | struct cmd_list_element *c; |
| 1725 | |
| 1726 | gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep); |
| 1727 | xtensa_init_reggroups (); |
| 1728 | |
| 1729 | add_setshow_zinteger_cmd ("xtensa", |
| 1730 | class_maintenance, |
| 1731 | &xtensa_debug_level, _("\ |
| 1732 | Set Xtensa debugging."), _("\ |
| 1733 | Show Xtensa debugging."), _("\ |
| 1734 | When non-zero, Xtensa-specific debugging is enabled. \ |
| 1735 | Can be 1, 2, 3, or 4 indicating the level of debugging."), |
| 1736 | NULL, |
| 1737 | NULL, |
| 1738 | &setdebuglist, &showdebuglist); |
| 1739 | } |