| 1 | /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. |
| 2 | |
| 3 | Copyright (C) 2003, 2005, 2006 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program; if not, write to the Free Software |
| 19 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
| 20 | Boston, MA 02110-1301, USA. */ |
| 21 | |
| 22 | |
| 23 | /* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION |
| 24 | whenever the "tdep" structure changes in an incompatible way. */ |
| 25 | |
| 26 | #define XTENSA_TDEP_VERSION 0x60 |
| 27 | |
| 28 | /* Xtensa register type. */ |
| 29 | |
| 30 | typedef enum |
| 31 | { |
| 32 | xtRegisterTypeArRegfile = 1, /* Register File ar0..arXX. */ |
| 33 | xtRegisterTypeSpecialReg, /* CPU states, such as PS, Booleans, (rsr). */ |
| 34 | xtRegisterTypeUserReg, /* User defined registers (rur). */ |
| 35 | xtRegisterTypeTieRegfile, /* User define register files. */ |
| 36 | xtRegisterTypeTieState, /* TIE States (mapped on user regs). */ |
| 37 | xtRegisterTypeMapped, /* Mapped on Special Registers. */ |
| 38 | xtRegisterTypeUnmapped, /* Special case of masked registers. */ |
| 39 | xtRegisterTypeWindow, /* Live window registers (a0..a15). */ |
| 40 | xtRegisterTypeVirtual, /* PC, FP. */ |
| 41 | xtRegisterTypeUnknown |
| 42 | } xtensa_register_type_t; |
| 43 | |
| 44 | |
| 45 | /* Xtensa register group. */ |
| 46 | |
| 47 | typedef enum |
| 48 | { |
| 49 | xtRegisterGroupUnknown = 0, |
| 50 | xtRegisterGroupRegFile = 0x0001, /* Register files without ARx. */ |
| 51 | xtRegisterGroupAddrReg = 0x0002, /* ARx. */ |
| 52 | xtRegisterGroupSpecialReg = 0x0004, /* SRxx. */ |
| 53 | xtRegisterGroupUserReg = 0x0008, /* URxx. */ |
| 54 | xtRegisterGroupState = 0x0010, /* States. */ |
| 55 | |
| 56 | xtRegisterGroupGeneral = 0x0100, /* General registers, Ax, SR. */ |
| 57 | xtRegisterGroupUser = 0x0200, /* User registers. */ |
| 58 | xtRegisterGroupFloat = 0x0400, /* Floating Point. */ |
| 59 | xtRegisterGroupVectra = 0x0800, /* Vectra. */ |
| 60 | xtRegisterGroupSystem = 0x1000, /* System. */ |
| 61 | } xtensa_register_group_t; |
| 62 | |
| 63 | |
| 64 | /* Xtensa target flags. */ |
| 65 | |
| 66 | typedef enum |
| 67 | { |
| 68 | xtTargetFlagsNonVisibleRegs = 0x0001, |
| 69 | xtTargetFlagsUseFetchStore = 0x0002, |
| 70 | } xtensa_target_flags_t; |
| 71 | |
| 72 | |
| 73 | /* Xtensa ELF core file register set representation ('.reg' section). |
| 74 | Copied from target-side ELF header <xtensa/elf.h>. */ |
| 75 | |
| 76 | typedef unsigned long xtensa_elf_greg_t; |
| 77 | |
| 78 | typedef struct |
| 79 | { |
| 80 | xtensa_elf_greg_t xchal_config_id0; |
| 81 | xtensa_elf_greg_t xchal_config_id1; |
| 82 | xtensa_elf_greg_t cpux; |
| 83 | xtensa_elf_greg_t cpuy; |
| 84 | xtensa_elf_greg_t pc; |
| 85 | xtensa_elf_greg_t ps; |
| 86 | xtensa_elf_greg_t exccause; |
| 87 | xtensa_elf_greg_t excvaddr; |
| 88 | xtensa_elf_greg_t windowbase; |
| 89 | xtensa_elf_greg_t windowstart; |
| 90 | xtensa_elf_greg_t lbeg; |
| 91 | xtensa_elf_greg_t lend; |
| 92 | xtensa_elf_greg_t lcount; |
| 93 | xtensa_elf_greg_t sar; |
| 94 | xtensa_elf_greg_t syscall; |
| 95 | xtensa_elf_greg_t ar[0]; /* variable size (per config). */ |
| 96 | } xtensa_elf_gregset_t; |
| 97 | |
| 98 | #define SIZEOF_GREGSET (sizeof (xtensa_elf_gregset_t) + NUM_AREGS * 4) |
| 99 | #define XTENSA_ELF_NGREG (SIZEOF_GREGSET / sizeof(xtensa_elf_greg_t)) |
| 100 | |
| 101 | |
| 102 | /* Mask. */ |
| 103 | |
| 104 | typedef struct |
| 105 | { |
| 106 | int count; |
| 107 | struct |
| 108 | { |
| 109 | int reg_num; |
| 110 | int bit_start; |
| 111 | int bit_size; |
| 112 | } mask[0]; |
| 113 | } xtensa_mask_t; |
| 114 | |
| 115 | |
| 116 | /* Xtensa register representation. */ |
| 117 | |
| 118 | typedef struct |
| 119 | { |
| 120 | char* name; /* Register name. */ |
| 121 | int offset; /* Offset. */ |
| 122 | xtensa_register_type_t type; /* Register type. */ |
| 123 | xtensa_register_group_t group;/* Register group. */ |
| 124 | struct type* ctype; /* C-type. */ |
| 125 | int bit_size; /* The actual bit size in the target. */ |
| 126 | int byte_size; /* Actual space allocated in registers[]. */ |
| 127 | int align; /* Alignment for this register. */ |
| 128 | |
| 129 | unsigned int target_number; /* Register target number. */ |
| 130 | |
| 131 | int flags; /* Flags. */ |
| 132 | |
| 133 | const xtensa_mask_t *mask; /* Register is a compilation of other regs. */ |
| 134 | const char *fetch; /* Instruction sequence to fetch register. */ |
| 135 | const char *store; /* Instruction sequence to store register. */ |
| 136 | } xtensa_register_t; |
| 137 | |
| 138 | |
| 139 | #define XTENSA_REGISTER_FLAGS_PRIVILEDGED 0x0001 |
| 140 | #define XTENSA_REGISTER_FLAGS_READABLE 0x0002 |
| 141 | #define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004 |
| 142 | #define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008 |
| 143 | |
| 144 | |
| 145 | /* Call-ABI for stack frame. */ |
| 146 | |
| 147 | typedef enum |
| 148 | { |
| 149 | CallAbiDefault = 0, /* Any 'callX' instructions; default stack. */ |
| 150 | CallAbiCall0Only, /* Only 'call0' instructions; flat stack. */ |
| 151 | } call_abi_t; |
| 152 | |
| 153 | |
| 154 | /* Xtensa-specific target dependencies. */ |
| 155 | |
| 156 | struct gdbarch_tdep |
| 157 | { |
| 158 | unsigned int target_flags; |
| 159 | |
| 160 | /* Spill location for TIE register files under ocd. */ |
| 161 | |
| 162 | unsigned int spill_location; |
| 163 | unsigned int spill_size; |
| 164 | |
| 165 | char *unused; /* Placeholder for compatibility. */ |
| 166 | call_abi_t call_abi; /* Calling convention. */ |
| 167 | |
| 168 | /* CPU configuration. */ |
| 169 | |
| 170 | unsigned int debug_interrupt_level; |
| 171 | |
| 172 | unsigned int icache_line_bytes; |
| 173 | unsigned int dcache_line_bytes; |
| 174 | unsigned int dcache_writeback; |
| 175 | |
| 176 | unsigned int isa_use_windowed_registers; |
| 177 | unsigned int isa_use_density_instructions; |
| 178 | unsigned int isa_use_exceptions; |
| 179 | unsigned int isa_use_ext_l32r; |
| 180 | unsigned int isa_max_insn_size; /* Maximum instruction length. */ |
| 181 | unsigned int debug_num_ibreaks; /* Number of IBREAKs. */ |
| 182 | unsigned int debug_num_dbreaks; |
| 183 | |
| 184 | /* Register map. */ |
| 185 | |
| 186 | xtensa_register_t* regmap; |
| 187 | |
| 188 | unsigned int num_regs; /* Number of registers in regmap. */ |
| 189 | unsigned int num_pseudo_regs; /* Number of pseudo registers. */ |
| 190 | unsigned int num_aregs; /* Size of register file. */ |
| 191 | unsigned int num_contexts; |
| 192 | |
| 193 | int ar_base; /* Register number for AR0. */ |
| 194 | int a0_base; /* Register number for A0 (pseudo). */ |
| 195 | int wb_regnum; /* Register number for WB. */ |
| 196 | int ws_regnum; /* Register number for WS. */ |
| 197 | int pc_regnum; /* Register number for PC. */ |
| 198 | int ps_regnum; /* Register number for PS. */ |
| 199 | int lbeg_regnum; /* Register numbers for count regs. */ |
| 200 | int lend_regnum; |
| 201 | int lcount_regnum; |
| 202 | int sar_regnum; /* Register number of SAR. */ |
| 203 | int litbase_regnum; /* Register number of LITBASE. */ |
| 204 | |
| 205 | int interrupt_regnum; /* Register number for interrupt. */ |
| 206 | int interrupt2_regnum; /* Register number for interrupt2. */ |
| 207 | int cpenable_regnum; /* Register number for cpenable. */ |
| 208 | int debugcause_regnum; /* Register number for debugcause. */ |
| 209 | int exccause_regnum; /* Register number for exccause. */ |
| 210 | int excvaddr_regnum; /* Register number for excvaddr. */ |
| 211 | |
| 212 | int max_register_raw_size; |
| 213 | int max_register_virtual_size; |
| 214 | unsigned long *fp_layout; /* Layout of custom/TIE regs in 'FP' area. */ |
| 215 | unsigned int fp_layout_bytes; /* Size of layout information (in bytes). */ |
| 216 | unsigned long *gregmap; |
| 217 | }; |
| 218 | |
| 219 | |
| 220 | /* Define macros to access some of the gdbarch entries. */ |
| 221 | #define XTENSA_TARGET_FLAGS \ |
| 222 | (gdbarch_tdep (current_gdbarch)->target_flags) |
| 223 | #define SPILL_LOCATION \ |
| 224 | (gdbarch_tdep (current_gdbarch)->spill_location) |
| 225 | #define SPILL_SIZE \ |
| 226 | (gdbarch_tdep (current_gdbarch)->spill_size) |
| 227 | #define CALL_ABI \ |
| 228 | (gdbarch_tdep (current_gdbarch)->call_abi) |
| 229 | #define ISA_USE_WINDOWED_REGISTERS \ |
| 230 | (gdbarch_tdep (current_gdbarch)->isa_use_windowed_registers) |
| 231 | #define ISA_USE_DENSITY_INSTRUCTIONS \ |
| 232 | (gdbarch_tdep (current_gdbarch)->isa_use_density_instructions) |
| 233 | #define ISA_USE_EXCEPTIONS \ |
| 234 | (gdbarch_tdep (current_gdbarch)->isa_use_exceptions) |
| 235 | #define ISA_USE_EXT_L32R \ |
| 236 | (gdbarch_tdep (current_gdbarch)->isa_use_ext_l32r) |
| 237 | #define DEBUG_DATA_VADDR_TRAP_COUNT \ |
| 238 | (gdbarch_tdep (current_gdbarch)->debug_data_vaddr_trap_count) |
| 239 | #define DEBUG_INST_VADDR_TRAP_COUNT \ |
| 240 | (gdbarch_tdep (current_gdbarch)->debug_inst_vaddr_trap_count) |
| 241 | #define ISA_MAX_INSN_SIZE \ |
| 242 | (gdbarch_tdep (current_gdbarch)->isa_max_insn_size) |
| 243 | #define DEBUG_NUM_IBREAKS \ |
| 244 | (gdbarch_tdep (current_gdbarch)->debug_num_ibreaks) |
| 245 | #define DEBUG_NUM_DBREAKS \ |
| 246 | (gdbarch_tdep (current_gdbarch)->debug_num_dbreaks) |
| 247 | |
| 248 | #define NUM_AREGS (gdbarch_tdep (current_gdbarch)->num_aregs) |
| 249 | #define WB_REGNUM (gdbarch_tdep (current_gdbarch)->wb_regnum) |
| 250 | #define WS_REGNUM (gdbarch_tdep (current_gdbarch)->ws_regnum) |
| 251 | #define LBEG_REGNUM (gdbarch_tdep (current_gdbarch)->lbeg_regnum) |
| 252 | #define LEND_REGNUM (gdbarch_tdep (current_gdbarch)->lend_regnum) |
| 253 | #define LCOUNT_REGNUM (gdbarch_tdep (current_gdbarch)->lcount_regnum) |
| 254 | #define SAR_REGNUM (gdbarch_tdep (current_gdbarch)->sar_regnum) |
| 255 | #define REGMAP (gdbarch_tdep (current_gdbarch)->regmap) |
| 256 | |
| 257 | #define LITBASE_REGNUM (gdbarch_tdep (current_gdbarch)->litbase_regnum) |
| 258 | #define DEBUGCAUSE_REGNUM (gdbarch_tdep (current_gdbarch)->debugcause_regnum) |
| 259 | #define EXCCAUSE_REGNUM (gdbarch_tdep (current_gdbarch)->exccause_regnum) |
| 260 | #define EXCVADDR_REGNUM (gdbarch_tdep (current_gdbarch)->excvaddr_regnum) |
| 261 | #define NUM_IBREAKS (gdbarch_tdep (current_gdbarch)->num_ibreaks) |
| 262 | #define REGMAP_BYTES (gdbarch_tdep (current_gdbarch)->regmap_bytes) |
| 263 | #define A0_BASE (gdbarch_tdep (current_gdbarch)->a0_base) |
| 264 | #define AR_BASE (gdbarch_tdep (current_gdbarch)->ar_base) |
| 265 | #define FP_ALIAS (NUM_REGS + NUM_PSEUDO_REGS) |
| 266 | #define CALL_ABI (gdbarch_tdep (current_gdbarch)->call_abi) |
| 267 | #define NUM_CONTEXTS (gdbarch_tdep (current_gdbarch)->num_contexts) |
| 268 | |
| 269 | #define FP_LAYOUT (gdbarch_tdep (current_gdbarch)->fp_layout) |
| 270 | #define FP_LAYOUT_BYTES (gdbarch_tdep (current_gdbarch)->fp_layout_bytes) |
| 271 | #define GREGMAP (gdbarch_tdep (current_gdbarch)->gregmap) |
| 272 | |
| 273 | #define AREGS_MASK (NUM_AREGS - 1) |
| 274 | #define WB_MASK (AREGS_MASK >> 2) |
| 275 | #define WB_SHIFT 2 |
| 276 | |
| 277 | /* We assign fixed numbers to the registers of the "current" window |
| 278 | (i.e., relative to WB). The registers get remapped via the reg_map |
| 279 | data structure to their corresponding register in the AR register |
| 280 | file (see xtensa-tdep.c). */ |
| 281 | |
| 282 | #define A0_REGNUM (A0_BASE + 0) |
| 283 | #define A1_REGNUM (A0_BASE + 1) |
| 284 | #define A2_REGNUM (A0_BASE + 2) |
| 285 | #define A3_REGNUM (A0_BASE + 3) |
| 286 | #define A4_REGNUM (A0_BASE + 4) |
| 287 | #define A5_REGNUM (A0_BASE + 5) |
| 288 | #define A6_REGNUM (A0_BASE + 6) |
| 289 | #define A7_REGNUM (A0_BASE + 7) |
| 290 | #define A8_REGNUM (A0_BASE + 8) |
| 291 | #define A9_REGNUM (A0_BASE + 9) |
| 292 | #define A10_REGNUM (A0_BASE + 10) |
| 293 | #define A11_REGNUM (A0_BASE + 11) |
| 294 | #define A12_REGNUM (A0_BASE + 12) |
| 295 | #define A13_REGNUM (A0_BASE + 13) |
| 296 | #define A14_REGNUM (A0_BASE + 14) |
| 297 | #define A15_REGNUM (A0_BASE + 15) |
| 298 | |