| 1 | /* GNU/Linux/RISC-V specific low level interface, for the remote server |
| 2 | for GDB. |
| 3 | Copyright (C) 2020 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #include "server.h" |
| 21 | |
| 22 | #include "linux-low.h" |
| 23 | #include "tdesc.h" |
| 24 | #include "elf/common.h" |
| 25 | #include "nat/riscv-linux-tdesc.h" |
| 26 | #include "opcode/riscv.h" |
| 27 | |
| 28 | /* Work around glibc header breakage causing ELF_NFPREG not to be usable. */ |
| 29 | #ifndef NFPREG |
| 30 | # define NFPREG 33 |
| 31 | #endif |
| 32 | |
| 33 | /* Linux target op definitions for the RISC-V architecture. */ |
| 34 | |
| 35 | class riscv_target : public linux_process_target |
| 36 | { |
| 37 | public: |
| 38 | |
| 39 | const regs_info *get_regs_info () override; |
| 40 | |
| 41 | int breakpoint_kind_from_pc (CORE_ADDR *pcptr) override; |
| 42 | |
| 43 | protected: |
| 44 | |
| 45 | void low_arch_setup () override; |
| 46 | |
| 47 | bool low_cannot_fetch_register (int regno) override; |
| 48 | |
| 49 | bool low_cannot_store_register (int regno) override; |
| 50 | |
| 51 | bool low_fetch_register (regcache *regcache, int regno) override; |
| 52 | |
| 53 | bool low_supports_breakpoints () override; |
| 54 | |
| 55 | CORE_ADDR low_get_pc (regcache *regcache) override; |
| 56 | |
| 57 | void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; |
| 58 | }; |
| 59 | |
| 60 | /* The singleton target ops object. */ |
| 61 | |
| 62 | static riscv_target the_riscv_target; |
| 63 | |
| 64 | bool |
| 65 | riscv_target::low_cannot_fetch_register (int regno) |
| 66 | { |
| 67 | gdb_assert_not_reached ("linux target op low_cannot_fetch_register " |
| 68 | "is not implemented by the target"); |
| 69 | } |
| 70 | |
| 71 | bool |
| 72 | riscv_target::low_cannot_store_register (int regno) |
| 73 | { |
| 74 | gdb_assert_not_reached ("linux target op low_cannot_store_register " |
| 75 | "is not implemented by the target"); |
| 76 | } |
| 77 | |
| 78 | /* Implementation of linux target ops method "low_arch_setup". */ |
| 79 | |
| 80 | void |
| 81 | riscv_target::low_arch_setup () |
| 82 | { |
| 83 | static const char *expedite_regs[] = { "sp", "pc", NULL }; |
| 84 | |
| 85 | const riscv_gdbarch_features features |
| 86 | = riscv_linux_read_features (lwpid_of (current_thread)); |
| 87 | target_desc *tdesc = riscv_create_target_description (features); |
| 88 | |
| 89 | if (!tdesc->expedite_regs) |
| 90 | init_target_desc (tdesc, expedite_regs); |
| 91 | current_process ()->tdesc = tdesc; |
| 92 | } |
| 93 | |
| 94 | /* Collect GPRs from REGCACHE into BUF. */ |
| 95 | |
| 96 | static void |
| 97 | riscv_fill_gregset (struct regcache *regcache, void *buf) |
| 98 | { |
| 99 | const struct target_desc *tdesc = regcache->tdesc; |
| 100 | elf_gregset_t *regset = (elf_gregset_t *) buf; |
| 101 | int regno = find_regno (tdesc, "zero"); |
| 102 | int i; |
| 103 | |
| 104 | collect_register_by_name (regcache, "pc", *regset); |
| 105 | for (i = 1; i < ARRAY_SIZE (*regset); i++) |
| 106 | collect_register (regcache, regno + i, *regset + i); |
| 107 | } |
| 108 | |
| 109 | /* Supply GPRs from BUF into REGCACHE. */ |
| 110 | |
| 111 | static void |
| 112 | riscv_store_gregset (struct regcache *regcache, const void *buf) |
| 113 | { |
| 114 | const elf_gregset_t *regset = (const elf_gregset_t *) buf; |
| 115 | const struct target_desc *tdesc = regcache->tdesc; |
| 116 | int regno = find_regno (tdesc, "zero"); |
| 117 | int i; |
| 118 | |
| 119 | supply_register_by_name (regcache, "pc", *regset); |
| 120 | supply_register_zeroed (regcache, regno); |
| 121 | for (i = 1; i < ARRAY_SIZE (*regset); i++) |
| 122 | supply_register (regcache, regno + i, *regset + i); |
| 123 | } |
| 124 | |
| 125 | /* Collect FPRs from REGCACHE into BUF. */ |
| 126 | |
| 127 | static void |
| 128 | riscv_fill_fpregset (struct regcache *regcache, void *buf) |
| 129 | { |
| 130 | const struct target_desc *tdesc = regcache->tdesc; |
| 131 | int regno = find_regno (tdesc, "ft0"); |
| 132 | int flen = register_size (regcache->tdesc, regno); |
| 133 | gdb_byte *regbuf = (gdb_byte *) buf; |
| 134 | int i; |
| 135 | |
| 136 | for (i = 0; i < ELF_NFPREG - 1; i++, regbuf += flen) |
| 137 | collect_register (regcache, regno + i, regbuf); |
| 138 | collect_register_by_name (regcache, "fcsr", regbuf); |
| 139 | } |
| 140 | |
| 141 | /* Supply FPRs from BUF into REGCACHE. */ |
| 142 | |
| 143 | static void |
| 144 | riscv_store_fpregset (struct regcache *regcache, const void *buf) |
| 145 | { |
| 146 | const struct target_desc *tdesc = regcache->tdesc; |
| 147 | int regno = find_regno (tdesc, "ft0"); |
| 148 | int flen = register_size (regcache->tdesc, regno); |
| 149 | const gdb_byte *regbuf = (const gdb_byte *) buf; |
| 150 | int i; |
| 151 | |
| 152 | for (i = 0; i < ELF_NFPREG - 1; i++, regbuf += flen) |
| 153 | supply_register (regcache, regno + i, regbuf); |
| 154 | supply_register_by_name (regcache, "fcsr", regbuf); |
| 155 | } |
| 156 | |
| 157 | /* RISC-V/Linux regsets. FPRs are optional and come in different sizes, |
| 158 | so define multiple regsets for them marking them all as OPTIONAL_REGS |
| 159 | rather than FP_REGS, so that "regsets_fetch_inferior_registers" picks |
| 160 | the right one according to size. */ |
| 161 | static struct regset_info riscv_regsets[] = { |
| 162 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, |
| 163 | sizeof (elf_gregset_t), GENERAL_REGS, |
| 164 | riscv_fill_gregset, riscv_store_gregset }, |
| 165 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, |
| 166 | sizeof (struct __riscv_mc_q_ext_state), OPTIONAL_REGS, |
| 167 | riscv_fill_fpregset, riscv_store_fpregset }, |
| 168 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, |
| 169 | sizeof (struct __riscv_mc_d_ext_state), OPTIONAL_REGS, |
| 170 | riscv_fill_fpregset, riscv_store_fpregset }, |
| 171 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, |
| 172 | sizeof (struct __riscv_mc_f_ext_state), OPTIONAL_REGS, |
| 173 | riscv_fill_fpregset, riscv_store_fpregset }, |
| 174 | NULL_REGSET |
| 175 | }; |
| 176 | |
| 177 | /* RISC-V/Linux regset information. */ |
| 178 | static struct regsets_info riscv_regsets_info = |
| 179 | { |
| 180 | riscv_regsets, /* regsets */ |
| 181 | 0, /* num_regsets */ |
| 182 | NULL, /* disabled_regsets */ |
| 183 | }; |
| 184 | |
| 185 | /* Definition of linux_target_ops data member "regs_info". */ |
| 186 | static struct regs_info riscv_regs = |
| 187 | { |
| 188 | NULL, /* regset_bitmap */ |
| 189 | NULL, /* usrregs */ |
| 190 | &riscv_regsets_info, |
| 191 | }; |
| 192 | |
| 193 | /* Implementation of linux target ops method "get_regs_info". */ |
| 194 | |
| 195 | const regs_info * |
| 196 | riscv_target::get_regs_info () |
| 197 | { |
| 198 | return &riscv_regs; |
| 199 | } |
| 200 | |
| 201 | /* Implementation of linux target ops method "low_fetch_register". */ |
| 202 | |
| 203 | bool |
| 204 | riscv_target::low_fetch_register (regcache *regcache, int regno) |
| 205 | { |
| 206 | const struct target_desc *tdesc = regcache->tdesc; |
| 207 | |
| 208 | if (regno != find_regno (tdesc, "zero")) |
| 209 | return false; |
| 210 | supply_register_zeroed (regcache, regno); |
| 211 | return true; |
| 212 | } |
| 213 | |
| 214 | bool |
| 215 | riscv_target::low_supports_breakpoints () |
| 216 | { |
| 217 | return true; |
| 218 | } |
| 219 | |
| 220 | /* Implementation of linux target ops method "low_get_pc". */ |
| 221 | |
| 222 | CORE_ADDR |
| 223 | riscv_target::low_get_pc (regcache *regcache) |
| 224 | { |
| 225 | elf_gregset_t regset; |
| 226 | |
| 227 | if (sizeof (regset[0]) == 8) |
| 228 | return linux_get_pc_64bit (regcache); |
| 229 | else |
| 230 | return linux_get_pc_32bit (regcache); |
| 231 | } |
| 232 | |
| 233 | /* Implementation of linux target ops method "low_set_pc". */ |
| 234 | |
| 235 | void |
| 236 | riscv_target::low_set_pc (regcache *regcache, CORE_ADDR newpc) |
| 237 | { |
| 238 | elf_gregset_t regset; |
| 239 | |
| 240 | if (sizeof (regset[0]) == 8) |
| 241 | linux_set_pc_64bit (regcache, newpc); |
| 242 | else |
| 243 | linux_set_pc_32bit (regcache, newpc); |
| 244 | } |
| 245 | |
| 246 | /* Correct in either endianness. */ |
| 247 | static const uint16_t riscv_ibreakpoint[] = { 0x0073, 0x0010 }; |
| 248 | static const uint16_t riscv_cbreakpoint = 0x9002; |
| 249 | |
| 250 | /* Implementation of target ops method "breakpoint_kind_from_pc". */ |
| 251 | |
| 252 | int |
| 253 | riscv_target::breakpoint_kind_from_pc (CORE_ADDR *pcptr) |
| 254 | { |
| 255 | union |
| 256 | { |
| 257 | gdb_byte bytes[2]; |
| 258 | uint16_t insn; |
| 259 | } |
| 260 | buf; |
| 261 | |
| 262 | if (target_read_memory (*pcptr, buf.bytes, sizeof (buf.insn)) == 0 |
| 263 | && riscv_insn_length (buf.insn == sizeof (riscv_ibreakpoint))) |
| 264 | return sizeof (riscv_ibreakpoint); |
| 265 | else |
| 266 | return sizeof (riscv_cbreakpoint); |
| 267 | } |
| 268 | |
| 269 | /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ |
| 270 | |
| 271 | static const gdb_byte * |
| 272 | riscv_sw_breakpoint_from_kind (int kind, int *size) |
| 273 | { |
| 274 | *size = kind; |
| 275 | switch (kind) |
| 276 | { |
| 277 | case sizeof (riscv_ibreakpoint): |
| 278 | return (const gdb_byte *) &riscv_ibreakpoint; |
| 279 | default: |
| 280 | return (const gdb_byte *) &riscv_cbreakpoint; |
| 281 | } |
| 282 | } |
| 283 | |
| 284 | /* Implementation of linux_target_ops method "breakpoint_at". */ |
| 285 | |
| 286 | static int |
| 287 | riscv_breakpoint_at (CORE_ADDR pc) |
| 288 | { |
| 289 | union |
| 290 | { |
| 291 | gdb_byte bytes[2]; |
| 292 | uint16_t insn; |
| 293 | } |
| 294 | buf; |
| 295 | |
| 296 | if (target_read_memory (pc, buf.bytes, sizeof (buf.insn)) == 0 |
| 297 | && (buf.insn == riscv_cbreakpoint |
| 298 | || (buf.insn == riscv_ibreakpoint[0] |
| 299 | && target_read_memory (pc + sizeof (buf.insn), buf.bytes, |
| 300 | sizeof (buf.insn)) == 0 |
| 301 | && buf.insn == riscv_ibreakpoint[1]))) |
| 302 | return 1; |
| 303 | else |
| 304 | return 0; |
| 305 | } |
| 306 | |
| 307 | /* RISC-V/Linux target operations. */ |
| 308 | struct linux_target_ops the_low_target = |
| 309 | { |
| 310 | riscv_sw_breakpoint_from_kind, |
| 311 | NULL, /* get_next_pcs */ |
| 312 | 0, /* decr_pc_after_break */ |
| 313 | riscv_breakpoint_at, |
| 314 | }; |
| 315 | |
| 316 | /* The linux target ops object. */ |
| 317 | |
| 318 | linux_process_target *the_linux_target = &the_riscv_target; |
| 319 | |
| 320 | /* Initialize the RISC-V/Linux target. */ |
| 321 | |
| 322 | void |
| 323 | initialize_low_arch () |
| 324 | { |
| 325 | initialize_regsets_info (&riscv_regsets_info); |
| 326 | } |