[deliverable/linux.git] / include / asm-x86 / apic.h

#ifndef ASM_X86__APIC_H
#define ASM_X86__APIC_H

#include <linux/pm.h>
#include <linux/delay.h>

#include <asm/alternative.h>
#include <asm/fixmap.h>
#include <asm/apicdef.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/cpufeature.h>
#include <asm/msr.h>

#define ARCH_APICTIMER_STOPS_ON_C3	1

/*
 * Debugging macros
 */
#define APIC_QUIET   0
#define APIC_VERBOSE 1
#define APIC_DEBUG   2

/*
 * Define the default level of output to be very little
 * This can be turned up by using apic=verbose for more
 * information and apic=debug for _lots_ of information.
 * apic_verbosity is defined in apic.c
 */
#define apic_printk(v, s, a...) do {       \
		if ((v) <= apic_verbosity) \
			printk(s, ##a);    \
	} while (0)


extern void generic_apic_probe(void);

#ifdef CONFIG_X86_LOCAL_APIC

extern unsigned int apic_verbosity;
extern int local_apic_timer_c2_ok;

extern int disable_apic;
/*
 * Basic functions accessing APICs.
 */
#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#else
#define setup_boot_clock setup_boot_APIC_clock
#define setup_secondary_clock setup_secondary_APIC_clock
#endif

extern int is_vsmp_box(void);
extern void xapic_wait_icr_idle(void);
extern u32 safe_xapic_wait_icr_idle(void);
extern u64 xapic_icr_read(void);
extern void xapic_icr_write(u32, u32);
extern int setup_profiling_timer(unsigned int);

static inline void native_apic_mem_write(u32 reg, u32 v)
{
	volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);

	alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
		       ASM_OUTPUT2("=r" (v), "=m" (*addr)),
		       ASM_OUTPUT2("0" (v), "m" (*addr)));
}

static inline u32 native_apic_mem_read(u32 reg)
{
	return *((volatile u32 *)(APIC_BASE + reg));
}

static inline void native_apic_msr_write(u32 reg, u32 v)
{
	if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
	    reg == APIC_LVR)
		return;

	wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
}

static inline u32 native_apic_msr_read(u32 reg)
{
	u32 low, high;

	if (reg == APIC_DFR)
		return -1;

	rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
	return low;
}

#ifndef CONFIG_X86_32
extern int x2apic, x2apic_preenabled;
extern void check_x2apic(void);
extern void enable_x2apic(void);
extern void enable_IR_x2apic(void);
extern void x2apic_icr_write(u32 low, u32 id);
#endif

struct apic_ops {
	u32 (*read)(u32 reg);
	void (*write)(u32 reg, u32 v);
	u64 (*icr_read)(void);
	void (*icr_write)(u32 low, u32 high);
	void (*wait_icr_idle)(void);
	u32 (*safe_wait_icr_idle)(void);
};

extern struct apic_ops *apic_ops;

#define apic_read (apic_ops->read)
#define apic_write (apic_ops->write)
#define apic_icr_read (apic_ops->icr_read)
#define apic_icr_write (apic_ops->icr_write)
#define apic_wait_icr_idle (apic_ops->wait_icr_idle)
#define safe_apic_wait_icr_idle (apic_ops->safe_wait_icr_idle)

extern int get_physical_broadcast(void);

#ifdef CONFIG_X86_64
static inline void ack_x2APIC_irq(void)
{
	/* Docs say use 0 for future compatibility */
	native_apic_msr_write(APIC_EOI, 0);
}
#endif


static inline void ack_APIC_irq(void)
{
	/*
	 * ack_APIC_irq() actually gets compiled as a single instruction
	 * ... yummie.
	 */

	/* Docs say use 0 for future compatibility */
	apic_write(APIC_EOI, 0);
}

extern int lapic_get_maxlvt(void);
extern void clear_local_APIC(void);
extern void connect_bsp_APIC(void);
extern void disconnect_bsp_APIC(int virt_wire_setup);
extern void disable_local_APIC(void);
extern void lapic_shutdown(void);
extern int verify_local_APIC(void);
extern void cache_APIC_registers(void);
extern void sync_Arb_IDs(void);
extern void init_bsp_APIC(void);
extern void setup_local_APIC(void);
extern void end_local_APIC_setup(void);
extern void init_apic_mappings(void);
extern void setup_boot_APIC_clock(void);
extern void setup_secondary_APIC_clock(void);
extern int APIC_init_uniprocessor(void);
extern void enable_NMI_through_LVT0(void);

/*
 * On 32bit this is mach-xxx local
 */
#ifdef CONFIG_X86_64
extern void early_init_lapic_mapping(void);
extern int apic_is_clustered_box(void);
#else
static inline int apic_is_clustered_box(void)
{
	return 0;
}
#endif

extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);


#else /* !CONFIG_X86_LOCAL_APIC */
static inline void lapic_shutdown(void) { }
#define local_apic_timer_c2_ok		1
static inline void init_apic_mappings(void) { }

#endif /* !CONFIG_X86_LOCAL_APIC */

#endif /* ASM_X86__APIC_H */
Commit	Line	Data
	1	#ifndef ASM_X86__APIC_H
	2	#define ASM_X86__APIC_H
	3
	4	#include <linux/pm.h>
	5	#include <linux/delay.h>
	6
	7	#include <asm/alternative.h>
	8	#include <asm/fixmap.h>
	9	#include <asm/apicdef.h>
	10	#include <asm/processor.h>
	11	#include <asm/system.h>
	12	#include <asm/cpufeature.h>
	13	#include <asm/msr.h>
	14
	15	#define ARCH_APICTIMER_STOPS_ON_C3 1
	16
	17	/*
	18	* Debugging macros
	19	*/
	20	#define APIC_QUIET 0
	21	#define APIC_VERBOSE 1
	22	#define APIC_DEBUG 2
	23
	24	/*
	25	* Define the default level of output to be very little
	26	* This can be turned up by using apic=verbose for more
	27	* information and apic=debug for _lots_ of information.
	28	* apic_verbosity is defined in apic.c
	29	*/
	30	#define apic_printk(v, s, a...) do { \
	31	if ((v) <= apic_verbosity) \
	32	printk(s, ##a); \
	33	} while (0)
	34
	35
	36	extern void generic_apic_probe(void);
	37
	38	#ifdef CONFIG_X86_LOCAL_APIC
	39
	40	extern unsigned int apic_verbosity;
	41	extern int local_apic_timer_c2_ok;
	42
	43	extern int disable_apic;
	44	/*
	45	* Basic functions accessing APICs.
	46	*/
	47	#ifdef CONFIG_PARAVIRT
	48	#include <asm/paravirt.h>
	49	#else
	50	#define setup_boot_clock setup_boot_APIC_clock
	51	#define setup_secondary_clock setup_secondary_APIC_clock
	52	#endif
	53
	54	extern int is_vsmp_box(void);
	55	extern void xapic_wait_icr_idle(void);
	56	extern u32 safe_xapic_wait_icr_idle(void);
	57	extern u64 xapic_icr_read(void);
	58	extern void xapic_icr_write(u32, u32);
	59	extern int setup_profiling_timer(unsigned int);
	60
	61	static inline void native_apic_mem_write(u32 reg, u32 v)
	62	{
	63	volatile u32 addr = (volatile u32 )(APIC_BASE + reg);
	64
	65	alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
	66	ASM_OUTPUT2("=r" (v), "=m" (*addr)),
	67	ASM_OUTPUT2("0" (v), "m" (*addr)));
	68	}
	69
	70	static inline u32 native_apic_mem_read(u32 reg)
	71	{
	72	return ((volatile u32 )(APIC_BASE + reg));
	73	}
	74
	75	static inline void native_apic_msr_write(u32 reg, u32 v)
	76	{
	77	if (reg == APIC_DFR \|\| reg == APIC_ID \|\| reg == APIC_LDR \|\|
	78	reg == APIC_LVR)
	79	return;
	80
	81	wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
	82	}
	83
	84	static inline u32 native_apic_msr_read(u32 reg)
	85	{
	86	u32 low, high;
	87
	88	if (reg == APIC_DFR)
	89	return -1;
	90
	91	rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
	92	return low;
	93	}
	94
	95	#ifndef CONFIG_X86_32
	96	extern int x2apic, x2apic_preenabled;
	97	extern void check_x2apic(void);
	98	extern void enable_x2apic(void);
	99	extern void enable_IR_x2apic(void);
	100	extern void x2apic_icr_write(u32 low, u32 id);
	101	#endif
	102
	103	struct apic_ops {
	104	u32 (*read)(u32 reg);
	105	void (*write)(u32 reg, u32 v);
	106	u64 (*icr_read)(void);
	107	void (*icr_write)(u32 low, u32 high);
	108	void (*wait_icr_idle)(void);
	109	u32 (*safe_wait_icr_idle)(void);
	110	};
	111
	112	extern struct apic_ops *apic_ops;
	113
	114	#define apic_read (apic_ops->read)
	115	#define apic_write (apic_ops->write)
	116	#define apic_icr_read (apic_ops->icr_read)
	117	#define apic_icr_write (apic_ops->icr_write)
	118	#define apic_wait_icr_idle (apic_ops->wait_icr_idle)
	119	#define safe_apic_wait_icr_idle (apic_ops->safe_wait_icr_idle)
	120
	121	extern int get_physical_broadcast(void);
	122
	123	#ifdef CONFIG_X86_64
	124	static inline void ack_x2APIC_irq(void)
	125	{
	126	/* Docs say use 0 for future compatibility */
	127	native_apic_msr_write(APIC_EOI, 0);
	128	}
	129	#endif
	130
	131
	132	static inline void ack_APIC_irq(void)
	133	{
	134	/*
	135	* ack_APIC_irq() actually gets compiled as a single instruction
	136	* ... yummie.
	137	*/
	138
	139	/* Docs say use 0 for future compatibility */
	140	apic_write(APIC_EOI, 0);
	141	}
	142
	143	extern int lapic_get_maxlvt(void);
	144	extern void clear_local_APIC(void);
	145	extern void connect_bsp_APIC(void);
	146	extern void disconnect_bsp_APIC(int virt_wire_setup);
	147	extern void disable_local_APIC(void);
	148	extern void lapic_shutdown(void);
	149	extern int verify_local_APIC(void);
	150	extern void cache_APIC_registers(void);
	151	extern void sync_Arb_IDs(void);
	152	extern void init_bsp_APIC(void);
	153	extern void setup_local_APIC(void);
	154	extern void end_local_APIC_setup(void);
	155	extern void init_apic_mappings(void);
	156	extern void setup_boot_APIC_clock(void);
	157	extern void setup_secondary_APIC_clock(void);
	158	extern int APIC_init_uniprocessor(void);
	159	extern void enable_NMI_through_LVT0(void);
	160
	161	/*
	162	* On 32bit this is mach-xxx local
	163	*/
	164	#ifdef CONFIG_X86_64
	165	extern void early_init_lapic_mapping(void);
	166	extern int apic_is_clustered_box(void);
	167	#else
	168	static inline int apic_is_clustered_box(void)
	169	{
	170	return 0;
	171	}
	172	#endif
	173
	174	extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
	175	extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
	176
	177
	178	#else /* !CONFIG_X86_LOCAL_APIC */
	179	static inline void lapic_shutdown(void) { }
	180	#define local_apic_timer_c2_ok 1
	181	static inline void init_apic_mappings(void) { }
	182
	183	#endif /* !CONFIG_X86_LOCAL_APIC */
	184
	185	#endif /* ASM_X86__APIC_H */