[deliverable/linux.git] / include / linux / dma_remapping.h

#ifndef _DMA_REMAPPING_H
#define _DMA_REMAPPING_H

/*
 * VT-d hardware uses 4KiB page size regardless of host page size.
 */
#define VTD_PAGE_SHIFT		(12)
#define VTD_PAGE_SIZE		(1UL << VTD_PAGE_SHIFT)
#define VTD_PAGE_MASK		(((u64)-1) << VTD_PAGE_SHIFT)
#define VTD_PAGE_ALIGN(addr)	(((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK)

#define VTD_STRIDE_SHIFT        (9)
#define VTD_STRIDE_MASK         (((u64)-1) << VTD_STRIDE_SHIFT)

#define DMA_PTE_READ (1)
#define DMA_PTE_WRITE (2)
#define DMA_PTE_LARGE_PAGE (1 << 7)
#define DMA_PTE_SNP (1 << 11)

#define CONTEXT_TT_MULTI_LEVEL	0
#define CONTEXT_TT_DEV_IOTLB	1
#define CONTEXT_TT_PASS_THROUGH 2
/* Extended context entry types */
#define CONTEXT_TT_PT_PASID	4
#define CONTEXT_TT_PT_PASID_DEV_IOTLB 5
#define CONTEXT_TT_MASK (7ULL << 2)

#define CONTEXT_DINVE		(1ULL << 8)
#define CONTEXT_PRS		(1ULL << 9)
#define CONTEXT_PASIDE		(1ULL << 11)

struct intel_iommu;
struct dmar_domain;
struct root_entry;


#ifdef CONFIG_INTEL_IOMMU
extern int iommu_calculate_agaw(struct intel_iommu *iommu);
extern int iommu_calculate_max_sagaw(struct intel_iommu *iommu);
extern int dmar_disabled;
extern int intel_iommu_enabled;
#else
static inline int iommu_calculate_agaw(struct intel_iommu *iommu)
{
	return 0;
}
static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
{
	return 0;
}
#define dmar_disabled	(1)
#define intel_iommu_enabled (0)
#endif


#endif
Commit	Line	Data
	1	#ifndef _DMA_REMAPPING_H
	2	#define _DMA_REMAPPING_H
	3
	4	/*
	5	* VT-d hardware uses 4KiB page size regardless of host page size.
	6	*/
	7	#define VTD_PAGE_SHIFT (12)
	8	#define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT)
	9	#define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT)
	10	#define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK)
	11
	12	#define VTD_STRIDE_SHIFT (9)
	13	#define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT)
	14
	15	#define DMA_PTE_READ (1)
	16	#define DMA_PTE_WRITE (2)
	17	#define DMA_PTE_LARGE_PAGE (1 << 7)
	18	#define DMA_PTE_SNP (1 << 11)
	19
	20	#define CONTEXT_TT_MULTI_LEVEL 0
	21	#define CONTEXT_TT_DEV_IOTLB 1
	22	#define CONTEXT_TT_PASS_THROUGH 2
	23	/* Extended context entry types */
	24	#define CONTEXT_TT_PT_PASID 4
	25	#define CONTEXT_TT_PT_PASID_DEV_IOTLB 5
	26	#define CONTEXT_TT_MASK (7ULL << 2)
	27
	28	#define CONTEXT_DINVE (1ULL << 8)
	29	#define CONTEXT_PRS (1ULL << 9)
	30	#define CONTEXT_PASIDE (1ULL << 11)
	31
	32	struct intel_iommu;
	33	struct dmar_domain;
	34	struct root_entry;
	35
	36
	37	#ifdef CONFIG_INTEL_IOMMU
	38	extern int iommu_calculate_agaw(struct intel_iommu *iommu);
	39	extern int iommu_calculate_max_sagaw(struct intel_iommu *iommu);
	40	extern int dmar_disabled;
	41	extern int intel_iommu_enabled;
	42	#else
	43	static inline int iommu_calculate_agaw(struct intel_iommu *iommu)
	44	{
	45	return 0;
	46	}
	47	static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
	48	{
	49	return 0;
	50	}
	51	#define dmar_disabled (1)
	52	#define intel_iommu_enabled (0)
	53	#endif
	54
	55
	56	#endif