projects / deliverable / linux.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
Slab allocators: consistent ZERO_SIZE_PTR support and NULL result semantics
[deliverable/linux.git] / include / linux / pci.h
... / ...
CommitLineData
1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
20/* Include the pci register defines */
21#include <linux/pci_regs.h>
22
23/*
24 * The PCI interface treats multi-function devices as independent
25 * devices. The slot/function address of each device is encoded
26 * in a single byte as follows:
27 *
28 * 7:3 = slot
29 * 2:0 = function
30 */
31#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
32#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
33#define PCI_FUNC(devfn) ((devfn) & 0x07)
34
35/* Ioctls for /proc/bus/pci/X/Y nodes. */
36#define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
37#define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
38#define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
39#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
40#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
41
42#ifdef __KERNEL__
43
44#include <linux/mod_devicetable.h>
45
46#include <linux/types.h>
47#include <linux/ioport.h>
48#include <linux/list.h>
49#include <linux/compiler.h>
50#include <linux/errno.h>
51#include <asm/atomic.h>
52#include <linux/device.h>
53
54/* Include the ID list */
55#include <linux/pci_ids.h>
56
57/* File state for mmap()s on /proc/bus/pci/X/Y */
58enum pci_mmap_state {
59 pci_mmap_io,
60 pci_mmap_mem
61};
62
63/* This defines the direction arg to the DMA mapping routines. */
64#define PCI_DMA_BIDIRECTIONAL 0
65#define PCI_DMA_TODEVICE 1
66#define PCI_DMA_FROMDEVICE 2
67#define PCI_DMA_NONE 3
68
69#define DEVICE_COUNT_COMPATIBLE 4
70#define DEVICE_COUNT_RESOURCE 12
71
72typedef int __bitwise pci_power_t;
73
74#define PCI_D0 ((pci_power_t __force) 0)
75#define PCI_D1 ((pci_power_t __force) 1)
76#define PCI_D2 ((pci_power_t __force) 2)
77#define PCI_D3hot ((pci_power_t __force) 3)
78#define PCI_D3cold ((pci_power_t __force) 4)
79#define PCI_UNKNOWN ((pci_power_t __force) 5)
80#define PCI_POWER_ERROR ((pci_power_t __force) -1)
81
82/** The pci_channel state describes connectivity between the CPU and
83 * the pci device. If some PCI bus between here and the pci device
84 * has crashed or locked up, this info is reflected here.
85 */
86typedef unsigned int __bitwise pci_channel_state_t;
87
88enum pci_channel_state {
89 /* I/O channel is in normal state */
90 pci_channel_io_normal = (__force pci_channel_state_t) 1,
91
92 /* I/O to channel is blocked */
93 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
94
95 /* PCI card is dead */
96 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
97};
98
99typedef unsigned int __bitwise pcie_reset_state_t;
100
101enum pcie_reset_state {
102 /* Reset is NOT asserted (Use to deassert reset) */
103 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
104
105 /* Use #PERST to reset PCI-E device */
106 pcie_warm_reset = (__force pcie_reset_state_t) 2,
107
108 /* Use PCI-E Hot Reset to reset device */
109 pcie_hot_reset = (__force pcie_reset_state_t) 3
110};
111
112typedef unsigned short __bitwise pci_bus_flags_t;
113enum pci_bus_flags {
114 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
115 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
116};
117
118struct pci_cap_saved_state {
119 struct hlist_node next;
120 char cap_nr;
121 u32 data[0];
122};
123
124/*
125 * The pci_dev structure is used to describe PCI devices.
126 */
127struct pci_dev {
128 struct list_head global_list; /* node in list of all PCI devices */
129 struct list_head bus_list; /* node in per-bus list */
130 struct pci_bus *bus; /* bus this device is on */
131 struct pci_bus *subordinate; /* bus this device bridges to */
132
133 void *sysdata; /* hook for sys-specific extension */
134 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
135
136 unsigned int devfn; /* encoded device & function index */
137 unsigned short vendor;
138 unsigned short device;
139 unsigned short subsystem_vendor;
140 unsigned short subsystem_device;
141 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
142 u8 revision; /* PCI revision, low byte of class word */
143 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
144 u8 rom_base_reg; /* which config register controls the ROM */
145 u8 pin; /* which interrupt pin this device uses */
146
147 struct pci_driver *driver; /* which driver has allocated this device */
148 u64 dma_mask; /* Mask of the bits of bus address this
149 device implements. Normally this is
150 0xffffffff. You only need to change
151 this if your device has broken DMA
152 or supports 64-bit transfers. */
153
154 pci_power_t current_state; /* Current operating state. In ACPI-speak,
155 this is D0-D3, D0 being fully functional,
156 and D3 being off. */
157
158 pci_channel_state_t error_state; /* current connectivity state */
159 struct device dev; /* Generic device interface */
160
161 /* device is compatible with these IDs */
162 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
163 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
164
165 int cfg_size; /* Size of configuration space */
166
167 /*
168 * Instead of touching interrupt line and base address registers
169 * directly, use the values stored here. They might be different!
170 */
171 unsigned int irq;
172 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
173
174 /* These fields are used by common fixups */
175 unsigned int transparent:1; /* Transparent PCI bridge */
176 unsigned int multifunction:1;/* Part of multi-function device */
177 /* keep track of device state */
178 unsigned int is_busmaster:1; /* device is busmaster */
179 unsigned int no_msi:1; /* device may not use msi */
180 unsigned int no_d1d2:1; /* only allow d0 or d3 */
181 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
182 unsigned int broken_parity_status:1; /* Device generates false positive parity */
183 unsigned int msi_enabled:1;
184 unsigned int msix_enabled:1;
185 unsigned int is_managed:1;
186 atomic_t enable_cnt; /* pci_enable_device has been called */
187
188 u32 saved_config_space[16]; /* config space saved at suspend time */
189 struct hlist_head saved_cap_space;
190 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
191 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
192 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
193#ifdef CONFIG_PCI_MSI
194 struct list_head msi_list;
195#endif
196};
197
198extern struct pci_dev *alloc_pci_dev(void);
199
200#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
201#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
202#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
203#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
204
205static inline int pci_channel_offline(struct pci_dev *pdev)
206{
207 return (pdev->error_state != pci_channel_io_normal);
208}
209
210static inline struct pci_cap_saved_state *pci_find_saved_cap(
211 struct pci_dev *pci_dev,char cap)
212{
213 struct pci_cap_saved_state *tmp;
214 struct hlist_node *pos;
215
216 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
217 if (tmp->cap_nr == cap)
218 return tmp;
219 }
220 return NULL;
221}
222
223static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
224 struct pci_cap_saved_state *new_cap)
225{
226 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
227}
228
229/*
230 * For PCI devices, the region numbers are assigned this way:
231 *
232 * 0-5 standard PCI regions
233 * 6 expansion ROM
234 * 7-10 bridges: address space assigned to buses behind the bridge
235 */
236
237#define PCI_ROM_RESOURCE 6
238#define PCI_BRIDGE_RESOURCES 7
239#define PCI_NUM_RESOURCES 11
240
241#ifndef PCI_BUS_NUM_RESOURCES
242#define PCI_BUS_NUM_RESOURCES 8
243#endif
244
245#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
246
247struct pci_bus {
248 struct list_head node; /* node in list of buses */
249 struct pci_bus *parent; /* parent bus this bridge is on */
250 struct list_head children; /* list of child buses */
251 struct list_head devices; /* list of devices on this bus */
252 struct pci_dev *self; /* bridge device as seen by parent */
253 struct resource *resource[PCI_BUS_NUM_RESOURCES];
254 /* address space routed to this bus */
255
256 struct pci_ops *ops; /* configuration access functions */
257 void *sysdata; /* hook for sys-specific extension */
258 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
259
260 unsigned char number; /* bus number */
261 unsigned char primary; /* number of primary bridge */
262 unsigned char secondary; /* number of secondary bridge */
263 unsigned char subordinate; /* max number of subordinate buses */
264
265 char name[48];
266
267 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
268 pci_bus_flags_t bus_flags; /* Inherited by child busses */
269 struct device *bridge;
270 struct class_device class_dev;
271 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
272 struct bin_attribute *legacy_mem; /* legacy mem */
273};
274
275#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
276#define to_pci_bus(n) container_of(n, struct pci_bus, class_dev)
277
278/*
279 * Error values that may be returned by PCI functions.
280 */
281#define PCIBIOS_SUCCESSFUL 0x00
282#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
283#define PCIBIOS_BAD_VENDOR_ID 0x83
284#define PCIBIOS_DEVICE_NOT_FOUND 0x86
285#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
286#define PCIBIOS_SET_FAILED 0x88
287#define PCIBIOS_BUFFER_TOO_SMALL 0x89
288
289/* Low-level architecture-dependent routines */
290
291struct pci_ops {
292 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
293 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
294};
295
296struct pci_raw_ops {
297 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
298 int reg, int len, u32 *val);
299 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
300 int reg, int len, u32 val);
301};
302
303extern struct pci_raw_ops *raw_pci_ops;
304
305struct pci_bus_region {
306 unsigned long start;
307 unsigned long end;
308};
309
310struct pci_dynids {
311 spinlock_t lock; /* protects list, index */
312 struct list_head list; /* for IDs added at runtime */
313 unsigned int use_driver_data:1; /* pci_driver->driver_data is used */
314};
315
316/* ---------------------------------------------------------------- */
317/** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
318 * a set of callbacks in struct pci_error_handlers, then that device driver
319 * will be notified of PCI bus errors, and will be driven to recovery
320 * when an error occurs.
321 */
322
323typedef unsigned int __bitwise pci_ers_result_t;
324
325enum pci_ers_result {
326 /* no result/none/not supported in device driver */
327 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
328
329 /* Device driver can recover without slot reset */
330 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
331
332 /* Device driver wants slot to be reset. */
333 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
334
335 /* Device has completely failed, is unrecoverable */
336 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
337
338 /* Device driver is fully recovered and operational */
339 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
340};
341
342/* PCI bus error event callbacks */
343struct pci_error_handlers
344{
345 /* PCI bus error detected on this device */
346 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
347 enum pci_channel_state error);
348
349 /* MMIO has been re-enabled, but not DMA */
350 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
351
352 /* PCI Express link has been reset */
353 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
354
355 /* PCI slot has been reset */
356 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
357
358 /* Device driver may resume normal operations */
359 void (*resume)(struct pci_dev *dev);
360};
361
362/* ---------------------------------------------------------------- */
363
364struct module;
365struct pci_driver {
366 struct list_head node;
367 char *name;
368 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
369 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
370 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
371 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
372 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
373 int (*resume_early) (struct pci_dev *dev);
374 int (*resume) (struct pci_dev *dev); /* Device woken up */
375 void (*shutdown) (struct pci_dev *dev);
376
377 struct pci_error_handlers *err_handler;
378 struct device_driver driver;
379 struct pci_dynids dynids;
380};
381
382#define to_pci_driver(drv) container_of(drv,struct pci_driver, driver)
383
384/**
385 * PCI_DEVICE - macro used to describe a specific pci device
386 * @vend: the 16 bit PCI Vendor ID
387 * @dev: the 16 bit PCI Device ID
388 *
389 * This macro is used to create a struct pci_device_id that matches a
390 * specific device. The subvendor and subdevice fields will be set to
391 * PCI_ANY_ID.
392 */
393#define PCI_DEVICE(vend,dev) \
394 .vendor = (vend), .device = (dev), \
395 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
396
397/**
398 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
399 * @dev_class: the class, subclass, prog-if triple for this device
400 * @dev_class_mask: the class mask for this device
401 *
402 * This macro is used to create a struct pci_device_id that matches a
403 * specific PCI class. The vendor, device, subvendor, and subdevice
404 * fields will be set to PCI_ANY_ID.
405 */
406#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
407 .class = (dev_class), .class_mask = (dev_class_mask), \
408 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
409 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
410
411/**
412 * PCI_VDEVICE - macro used to describe a specific pci device in short form
413 * @vend: the vendor name
414 * @dev: the 16 bit PCI Device ID
415 *
416 * This macro is used to create a struct pci_device_id that matches a
417 * specific PCI device. The subvendor, and subdevice fields will be set
418 * to PCI_ANY_ID. The macro allows the next field to follow as the device
419 * private data.
420 */
421
422#define PCI_VDEVICE(vendor, device) \
423 PCI_VENDOR_ID_##vendor, (device), \
424 PCI_ANY_ID, PCI_ANY_ID, 0, 0
425
426/* these external functions are only available when PCI support is enabled */
427#ifdef CONFIG_PCI
428
429extern struct bus_type pci_bus_type;
430
431/* Do NOT directly access these two variables, unless you are arch specific pci
432 * code, or pci core code. */
433extern struct list_head pci_root_buses; /* list of all known PCI buses */
434extern struct list_head pci_devices; /* list of all devices */
435/* Some device drivers need know if pci is initiated */
436extern int no_pci_devices(void);
437
438void pcibios_fixup_bus(struct pci_bus *);
439int __must_check pcibios_enable_device(struct pci_dev *, int mask);
440char *pcibios_setup (char *str);
441
442/* Used only when drivers/pci/setup.c is used */
443void pcibios_align_resource(void *, struct resource *, resource_size_t,
444 resource_size_t);
445void pcibios_update_irq(struct pci_dev *, int irq);
446
447/* Generic PCI functions used internally */
448
449extern struct pci_bus *pci_find_bus(int domain, int busnr);
450void pci_bus_add_devices(struct pci_bus *bus);
451struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
452static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
453{
454 struct pci_bus *root_bus;
455 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
456 if (root_bus)
457 pci_bus_add_devices(root_bus);
458 return root_bus;
459}
460struct pci_bus *pci_create_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
461struct pci_bus * pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr);
462int pci_scan_slot(struct pci_bus *bus, int devfn);
463struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn);
464void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
465unsigned int pci_scan_child_bus(struct pci_bus *bus);
466int __must_check pci_bus_add_device(struct pci_dev *dev);
467void pci_read_bridge_bases(struct pci_bus *child);
468struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
469int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
470extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
471extern void pci_dev_put(struct pci_dev *dev);
472extern void pci_remove_bus(struct pci_bus *b);
473extern void pci_remove_bus_device(struct pci_dev *dev);
474extern void pci_stop_bus_device(struct pci_dev *dev);
475void pci_setup_cardbus(struct pci_bus *bus);
476extern void pci_sort_breadthfirst(void);
477
478/* Generic PCI functions exported to card drivers */
479
480struct pci_dev __deprecated *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from);
481struct pci_dev __deprecated *pci_find_slot (unsigned int bus, unsigned int devfn);
482int pci_find_capability (struct pci_dev *dev, int cap);
483int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap);
484int pci_find_ext_capability (struct pci_dev *dev, int cap);
485int pci_find_ht_capability (struct pci_dev *dev, int ht_cap);
486int pci_find_next_ht_capability (struct pci_dev *dev, int pos, int ht_cap);
487struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
488
489struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
490 struct pci_dev *from);
491struct pci_dev *pci_get_device_reverse(unsigned int vendor, unsigned int device,
492 struct pci_dev *from);
493
494struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
495 unsigned int ss_vendor, unsigned int ss_device,
496 struct pci_dev *from);
497struct pci_dev *pci_get_slot (struct pci_bus *bus, unsigned int devfn);
498struct pci_dev *pci_get_bus_and_slot (unsigned int bus, unsigned int devfn);
499struct pci_dev *pci_get_class (unsigned int class, struct pci_dev *from);
500int pci_dev_present(const struct pci_device_id *ids);
501const struct pci_device_id *pci_find_present(const struct pci_device_id *ids);
502
503int pci_bus_read_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 *val);
504int pci_bus_read_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 *val);
505int pci_bus_read_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 *val);
506int pci_bus_write_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 val);
507int pci_bus_write_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 val);
508int pci_bus_write_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 val);
509
510static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
511{
512 return pci_bus_read_config_byte (dev->bus, dev->devfn, where, val);
513}
514static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
515{
516 return pci_bus_read_config_word (dev->bus, dev->devfn, where, val);
517}
518static inline int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
519{
520 return pci_bus_read_config_dword (dev->bus, dev->devfn, where, val);
521}
522static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
523{
524 return pci_bus_write_config_byte (dev->bus, dev->devfn, where, val);
525}
526static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
527{
528 return pci_bus_write_config_word (dev->bus, dev->devfn, where, val);
529}
530static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
531{
532 return pci_bus_write_config_dword (dev->bus, dev->devfn, where, val);
533}
534
535int __must_check pci_enable_device(struct pci_dev *dev);
536int __must_check pci_enable_device_bars(struct pci_dev *dev, int mask);
537int __must_check pcim_enable_device(struct pci_dev *pdev);
538void pcim_pin_device(struct pci_dev *pdev);
539
540static inline int pci_is_managed(struct pci_dev *pdev)
541{
542 return pdev->is_managed;
543}
544
545void pci_disable_device(struct pci_dev *dev);
546void pci_set_master(struct pci_dev *dev);
547int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
548#define HAVE_PCI_SET_MWI
549int __must_check pci_set_mwi(struct pci_dev *dev);
550int pci_try_set_mwi(struct pci_dev *dev);
551void pci_clear_mwi(struct pci_dev *dev);
552void pci_intx(struct pci_dev *dev, int enable);
553void pci_msi_off(struct pci_dev *dev);
554int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
555int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
556int pcix_get_max_mmrbc(struct pci_dev *dev);
557int pcix_get_mmrbc(struct pci_dev *dev);
558int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
559int pcie_set_readrq(struct pci_dev *dev, int rq);
560void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
561int __must_check pci_assign_resource(struct pci_dev *dev, int i);
562int __must_check pci_assign_resource_fixed(struct pci_dev *dev, int i);
563void pci_restore_bars(struct pci_dev *dev);
564int pci_select_bars(struct pci_dev *dev, unsigned long flags);
565
566/* ROM control related routines */
567void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
568void __iomem __must_check *pci_map_rom_copy(struct pci_dev *pdev, size_t *size);
569void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
570void pci_remove_rom(struct pci_dev *pdev);
571size_t pci_get_rom_size(void __iomem *rom, size_t size);
572
573/* Power management related routines */
574int pci_save_state(struct pci_dev *dev);
575int pci_restore_state(struct pci_dev *dev);
576int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
577pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
578int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
579
580/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
581void pci_bus_assign_resources(struct pci_bus *bus);
582void pci_bus_size_bridges(struct pci_bus *bus);
583int pci_claim_resource(struct pci_dev *, int);
584void pci_assign_unassigned_resources(void);
585void pdev_enable_device(struct pci_dev *);
586void pdev_sort_resources(struct pci_dev *, struct resource_list *);
587void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
588 int (*)(struct pci_dev *, u8, u8));
589#define HAVE_PCI_REQ_REGIONS 2
590int __must_check pci_request_regions(struct pci_dev *, const char *);
591void pci_release_regions(struct pci_dev *);
592int __must_check pci_request_region(struct pci_dev *, int, const char *);
593void pci_release_region(struct pci_dev *, int);
594int pci_request_selected_regions(struct pci_dev *, int, const char *);
595void pci_release_selected_regions(struct pci_dev *, int);
596
597/* drivers/pci/bus.c */
598int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
599 struct resource *res, resource_size_t size,
600 resource_size_t align, resource_size_t min,
601 unsigned int type_mask,
602 void (*alignf)(void *, struct resource *,
603 resource_size_t, resource_size_t),
604 void *alignf_data);
605void pci_enable_bridges(struct pci_bus *bus);
606
607/* Proper probing supporting hot-pluggable devices */
608int __must_check __pci_register_driver(struct pci_driver *, struct module *,
609 const char *mod_name);
610static inline int __must_check pci_register_driver(struct pci_driver *driver)
611{
612 return __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME);
613}
614
615void pci_unregister_driver(struct pci_driver *);
616void pci_remove_behind_bridge(struct pci_dev *);
617struct pci_driver *pci_dev_driver(const struct pci_dev *);
618const struct pci_device_id *pci_match_device(struct pci_driver *drv, struct pci_dev *dev);
619const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev);
620int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
621
622void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
623 void *userdata);
624int pci_cfg_space_size(struct pci_dev *dev);
625unsigned char pci_bus_max_busnr(struct pci_bus* bus);
626
627/* kmem_cache style wrapper around pci_alloc_consistent() */
628
629#include <linux/dmapool.h>
630
631#define pci_pool dma_pool
632#define pci_pool_create(name, pdev, size, align, allocation) \
633 dma_pool_create(name, &pdev->dev, size, align, allocation)
634#define pci_pool_destroy(pool) dma_pool_destroy(pool)
635#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
636#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
637
638enum pci_dma_burst_strategy {
639 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
640 strategy_parameter is N/A */
641 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
642 byte boundaries */
643 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
644 strategy_parameter byte boundaries */
645};
646
647struct msix_entry {
648 u16 vector; /* kernel uses to write allocated vector */
649 u16 entry; /* driver uses to specify entry, OS writes */
650};
651
652
653#ifndef CONFIG_PCI_MSI
654static inline int pci_enable_msi(struct pci_dev *dev) {return -1;}
655static inline void pci_disable_msi(struct pci_dev *dev) {}
656static inline int pci_enable_msix(struct pci_dev* dev,
657 struct msix_entry *entries, int nvec) {return -1;}
658static inline void pci_disable_msix(struct pci_dev *dev) {}
659static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) {}
660#else
661extern int pci_enable_msi(struct pci_dev *dev);
662extern void pci_disable_msi(struct pci_dev *dev);
663extern int pci_enable_msix(struct pci_dev* dev,
664 struct msix_entry *entries, int nvec);
665extern void pci_disable_msix(struct pci_dev *dev);
666extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
667#endif
668
669#ifdef CONFIG_HT_IRQ
670/* The functions a driver should call */
671int ht_create_irq(struct pci_dev *dev, int idx);
672void ht_destroy_irq(unsigned int irq);
673#endif /* CONFIG_HT_IRQ */
674
675extern void pci_block_user_cfg_access(struct pci_dev *dev);
676extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
677
678/*
679 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
680 * a PCI domain is defined to be a set of PCI busses which share
681 * configuration space.
682 */
683#ifndef CONFIG_PCI_DOMAINS
684static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
685static inline int pci_proc_domain(struct pci_bus *bus)
686{
687 return 0;
688}
689#endif
690
691#else /* CONFIG_PCI is not enabled */
692
693/*
694 * If the system does not have PCI, clearly these return errors. Define
695 * these as simple inline functions to avoid hair in drivers.
696 */
697
698#define _PCI_NOP(o,s,t) \
699 static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
700 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
701#define _PCI_NOP_ALL(o,x) _PCI_NOP(o,byte,u8 x) \
702 _PCI_NOP(o,word,u16 x) \
703 _PCI_NOP(o,dword,u32 x)
704_PCI_NOP_ALL(read, *)
705_PCI_NOP_ALL(write,)
706
707static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
708{ return NULL; }
709
710static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn)
711{ return NULL; }
712
713static inline struct pci_dev *pci_get_device(unsigned int vendor,
714 unsigned int device, struct pci_dev *from)
715{ return NULL; }
716
717static inline struct pci_dev *pci_get_device_reverse(unsigned int vendor,
718 unsigned int device, struct pci_dev *from)
719{ return NULL; }
720
721static inline struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
722unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from)
723{ return NULL; }
724
725static inline struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
726{ return NULL; }
727
728#define pci_dev_present(ids) (0)
729#define no_pci_devices() (1)
730#define pci_find_present(ids) (NULL)
731#define pci_dev_put(dev) do { } while (0)
732
733static inline void pci_set_master(struct pci_dev *dev) { }
734static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
735static inline void pci_disable_device(struct pci_dev *dev) { }
736static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
737static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;}
738static inline int __pci_register_driver(struct pci_driver *drv, struct module *owner) { return 0;}
739static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
740static inline void pci_unregister_driver(struct pci_driver *drv) { }
741static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
742static inline int pci_find_next_capability (struct pci_dev *dev, u8 post, int cap) { return 0; }
743static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; }
744static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
745
746/* Power management related routines */
747static inline int pci_save_state(struct pci_dev *dev) { return 0; }
748static inline int pci_restore_state(struct pci_dev *dev) { return 0; }
749static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) { return 0; }
750static inline pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) { return PCI_D0; }
751static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) { return 0; }
752
753static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) { return -EIO; }
754static inline void pci_release_regions(struct pci_dev *dev) { }
755
756#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
757
758static inline void pci_block_user_cfg_access(struct pci_dev *dev) { }
759static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) { }
760
761static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
762{ return NULL; }
763
764static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
765 unsigned int devfn)
766{ return NULL; }
767
768static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
769 unsigned int devfn)
770{ return NULL; }
771
772#endif /* CONFIG_PCI */
773
774/* Include architecture-dependent settings and functions */
775
776#include <asm/pci.h>
777
778/* these helpers provide future and backwards compatibility
779 * for accessing popular PCI BAR info */
780#define pci_resource_start(dev,bar) ((dev)->resource[(bar)].start)
781#define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end)
782#define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags)
783#define pci_resource_len(dev,bar) \
784 ((pci_resource_start((dev),(bar)) == 0 && \
785 pci_resource_end((dev),(bar)) == \
786 pci_resource_start((dev),(bar))) ? 0 : \
787 \
788 (pci_resource_end((dev),(bar)) - \
789 pci_resource_start((dev),(bar)) + 1))
790
791/* Similar to the helpers above, these manipulate per-pci_dev
792 * driver-specific data. They are really just a wrapper around
793 * the generic device structure functions of these calls.
794 */
795static inline void *pci_get_drvdata (struct pci_dev *pdev)
796{
797 return dev_get_drvdata(&pdev->dev);
798}
799
800static inline void pci_set_drvdata (struct pci_dev *pdev, void *data)
801{
802 dev_set_drvdata(&pdev->dev, data);
803}
804
805/* If you want to know what to call your pci_dev, ask this function.
806 * Again, it's a wrapper around the generic device.
807 */
808static inline char *pci_name(struct pci_dev *pdev)
809{
810 return pdev->dev.bus_id;
811}
812
813
814/* Some archs don't want to expose struct resource to userland as-is
815 * in sysfs and /proc
816 */
817#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
818static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
819 const struct resource *rsrc, resource_size_t *start,
820 resource_size_t *end)
821{
822 *start = rsrc->start;
823 *end = rsrc->end;
824}
825#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
826
827
828/*
829 * The world is not perfect and supplies us with broken PCI devices.
830 * For at least a part of these bugs we need a work-around, so both
831 * generic (drivers/pci/quirks.c) and per-architecture code can define
832 * fixup hooks to be called for particular buggy devices.
833 */
834
835struct pci_fixup {
836 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
837 void (*hook)(struct pci_dev *dev);
838};
839
840enum pci_fixup_pass {
841 pci_fixup_early, /* Before probing BARs */
842 pci_fixup_header, /* After reading configuration header */
843 pci_fixup_final, /* Final phase of device fixups */
844 pci_fixup_enable, /* pci_enable_device() time */
845 pci_fixup_resume, /* pci_enable_device() time */
846};
847
848/* Anonymous variables would be nice... */
849#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
850 static const struct pci_fixup __pci_fixup_##name __attribute_used__ \
851 __attribute__((__section__(#section))) = { vendor, device, hook };
852#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
853 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
854 vendor##device##hook, vendor, device, hook)
855#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
856 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
857 vendor##device##hook, vendor, device, hook)
858#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
859 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
860 vendor##device##hook, vendor, device, hook)
861#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
862 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
863 vendor##device##hook, vendor, device, hook)
864#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
865 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
866 resume##vendor##device##hook, vendor, device, hook)
867
868
869void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
870
871void __iomem * pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
872void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
873void __iomem * const * pcim_iomap_table(struct pci_dev *pdev);
874int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
875void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
876
877extern int pci_pci_problems;
878#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
879#define PCIPCI_TRITON 2
880#define PCIPCI_NATOMA 4
881#define PCIPCI_VIAETBF 8
882#define PCIPCI_VSFX 16
883#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
884#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
885
886extern unsigned long pci_cardbus_io_size;
887extern unsigned long pci_cardbus_mem_size;
888
889extern int pcibios_add_platform_entries(struct pci_dev *dev);
890
891#endif /* __KERNEL__ */
892#endif /* LINUX_PCI_H */
Linux kernel - Deliverables
This page took 0.035899 seconds and 5 git commands to generate.