| 1 | /* |
| 2 | * pci.h |
| 3 | * |
| 4 | * PCI defines and function prototypes |
| 5 | * Copyright 1994, Drew Eckhardt |
| 6 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> |
| 7 | * |
| 8 | * For more information, please consult the following manuals (look at |
| 9 | * http://www.pcisig.com/ for how to get them): |
| 10 | * |
| 11 | * PCI BIOS Specification |
| 12 | * PCI Local Bus Specification |
| 13 | * PCI to PCI Bridge Specification |
| 14 | * PCI System Design Guide |
| 15 | */ |
| 16 | |
| 17 | #ifndef LINUX_PCI_H |
| 18 | #define LINUX_PCI_H |
| 19 | |
| 20 | #include <linux/pci_regs.h> /* The pci register defines */ |
| 21 | |
| 22 | /* |
| 23 | * The PCI interface treats multi-function devices as independent |
| 24 | * devices. The slot/function address of each device is encoded |
| 25 | * in a single byte as follows: |
| 26 | * |
| 27 | * 7:3 = slot |
| 28 | * 2:0 = function |
| 29 | */ |
| 30 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
| 31 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
| 32 | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
| 33 | |
| 34 | /* Ioctls for /proc/bus/pci/X/Y nodes. */ |
| 35 | #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8) |
| 36 | #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */ |
| 37 | #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */ |
| 38 | #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */ |
| 39 | #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */ |
| 40 | |
| 41 | #ifdef __KERNEL__ |
| 42 | |
| 43 | #include <linux/mod_devicetable.h> |
| 44 | |
| 45 | #include <linux/types.h> |
| 46 | #include <linux/init.h> |
| 47 | #include <linux/ioport.h> |
| 48 | #include <linux/list.h> |
| 49 | #include <linux/compiler.h> |
| 50 | #include <linux/errno.h> |
| 51 | #include <linux/kobject.h> |
| 52 | #include <linux/atomic.h> |
| 53 | #include <linux/device.h> |
| 54 | #include <linux/io.h> |
| 55 | #include <linux/irqreturn.h> |
| 56 | |
| 57 | /* Include the ID list */ |
| 58 | #include <linux/pci_ids.h> |
| 59 | |
| 60 | /* pci_slot represents a physical slot */ |
| 61 | struct pci_slot { |
| 62 | struct pci_bus *bus; /* The bus this slot is on */ |
| 63 | struct list_head list; /* node in list of slots on this bus */ |
| 64 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ |
| 65 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ |
| 66 | struct kobject kobj; |
| 67 | }; |
| 68 | |
| 69 | static inline const char *pci_slot_name(const struct pci_slot *slot) |
| 70 | { |
| 71 | return kobject_name(&slot->kobj); |
| 72 | } |
| 73 | |
| 74 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
| 75 | enum pci_mmap_state { |
| 76 | pci_mmap_io, |
| 77 | pci_mmap_mem |
| 78 | }; |
| 79 | |
| 80 | /* This defines the direction arg to the DMA mapping routines. */ |
| 81 | #define PCI_DMA_BIDIRECTIONAL 0 |
| 82 | #define PCI_DMA_TODEVICE 1 |
| 83 | #define PCI_DMA_FROMDEVICE 2 |
| 84 | #define PCI_DMA_NONE 3 |
| 85 | |
| 86 | /* |
| 87 | * For PCI devices, the region numbers are assigned this way: |
| 88 | */ |
| 89 | enum { |
| 90 | /* #0-5: standard PCI resources */ |
| 91 | PCI_STD_RESOURCES, |
| 92 | PCI_STD_RESOURCE_END = 5, |
| 93 | |
| 94 | /* #6: expansion ROM resource */ |
| 95 | PCI_ROM_RESOURCE, |
| 96 | |
| 97 | /* device specific resources */ |
| 98 | #ifdef CONFIG_PCI_IOV |
| 99 | PCI_IOV_RESOURCES, |
| 100 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, |
| 101 | #endif |
| 102 | |
| 103 | /* resources assigned to buses behind the bridge */ |
| 104 | #define PCI_BRIDGE_RESOURCE_NUM 4 |
| 105 | |
| 106 | PCI_BRIDGE_RESOURCES, |
| 107 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + |
| 108 | PCI_BRIDGE_RESOURCE_NUM - 1, |
| 109 | |
| 110 | /* total resources associated with a PCI device */ |
| 111 | PCI_NUM_RESOURCES, |
| 112 | |
| 113 | /* preserve this for compatibility */ |
| 114 | DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, |
| 115 | }; |
| 116 | |
| 117 | typedef int __bitwise pci_power_t; |
| 118 | |
| 119 | #define PCI_D0 ((pci_power_t __force) 0) |
| 120 | #define PCI_D1 ((pci_power_t __force) 1) |
| 121 | #define PCI_D2 ((pci_power_t __force) 2) |
| 122 | #define PCI_D3hot ((pci_power_t __force) 3) |
| 123 | #define PCI_D3cold ((pci_power_t __force) 4) |
| 124 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
| 125 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
| 126 | |
| 127 | /* Remember to update this when the list above changes! */ |
| 128 | extern const char *pci_power_names[]; |
| 129 | |
| 130 | static inline const char *pci_power_name(pci_power_t state) |
| 131 | { |
| 132 | return pci_power_names[1 + (int) state]; |
| 133 | } |
| 134 | |
| 135 | #define PCI_PM_D2_DELAY 200 |
| 136 | #define PCI_PM_D3_WAIT 10 |
| 137 | #define PCI_PM_BUS_WAIT 50 |
| 138 | |
| 139 | /** The pci_channel state describes connectivity between the CPU and |
| 140 | * the pci device. If some PCI bus between here and the pci device |
| 141 | * has crashed or locked up, this info is reflected here. |
| 142 | */ |
| 143 | typedef unsigned int __bitwise pci_channel_state_t; |
| 144 | |
| 145 | enum pci_channel_state { |
| 146 | /* I/O channel is in normal state */ |
| 147 | pci_channel_io_normal = (__force pci_channel_state_t) 1, |
| 148 | |
| 149 | /* I/O to channel is blocked */ |
| 150 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, |
| 151 | |
| 152 | /* PCI card is dead */ |
| 153 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, |
| 154 | }; |
| 155 | |
| 156 | typedef unsigned int __bitwise pcie_reset_state_t; |
| 157 | |
| 158 | enum pcie_reset_state { |
| 159 | /* Reset is NOT asserted (Use to deassert reset) */ |
| 160 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, |
| 161 | |
| 162 | /* Use #PERST to reset PCI-E device */ |
| 163 | pcie_warm_reset = (__force pcie_reset_state_t) 2, |
| 164 | |
| 165 | /* Use PCI-E Hot Reset to reset device */ |
| 166 | pcie_hot_reset = (__force pcie_reset_state_t) 3 |
| 167 | }; |
| 168 | |
| 169 | typedef unsigned short __bitwise pci_dev_flags_t; |
| 170 | enum pci_dev_flags { |
| 171 | /* INTX_DISABLE in PCI_COMMAND register disables MSI |
| 172 | * generation too. |
| 173 | */ |
| 174 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, |
| 175 | /* Device configuration is irrevocably lost if disabled into D3 */ |
| 176 | PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2, |
| 177 | /* Provide indication device is assigned by a Virtual Machine Manager */ |
| 178 | PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4, |
| 179 | }; |
| 180 | |
| 181 | enum pci_irq_reroute_variant { |
| 182 | INTEL_IRQ_REROUTE_VARIANT = 1, |
| 183 | MAX_IRQ_REROUTE_VARIANTS = 3 |
| 184 | }; |
| 185 | |
| 186 | typedef unsigned short __bitwise pci_bus_flags_t; |
| 187 | enum pci_bus_flags { |
| 188 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
| 189 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, |
| 190 | }; |
| 191 | |
| 192 | /* Based on the PCI Hotplug Spec, but some values are made up by us */ |
| 193 | enum pci_bus_speed { |
| 194 | PCI_SPEED_33MHz = 0x00, |
| 195 | PCI_SPEED_66MHz = 0x01, |
| 196 | PCI_SPEED_66MHz_PCIX = 0x02, |
| 197 | PCI_SPEED_100MHz_PCIX = 0x03, |
| 198 | PCI_SPEED_133MHz_PCIX = 0x04, |
| 199 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, |
| 200 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, |
| 201 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, |
| 202 | PCI_SPEED_66MHz_PCIX_266 = 0x09, |
| 203 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, |
| 204 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, |
| 205 | AGP_UNKNOWN = 0x0c, |
| 206 | AGP_1X = 0x0d, |
| 207 | AGP_2X = 0x0e, |
| 208 | AGP_4X = 0x0f, |
| 209 | AGP_8X = 0x10, |
| 210 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
| 211 | PCI_SPEED_100MHz_PCIX_533 = 0x12, |
| 212 | PCI_SPEED_133MHz_PCIX_533 = 0x13, |
| 213 | PCIE_SPEED_2_5GT = 0x14, |
| 214 | PCIE_SPEED_5_0GT = 0x15, |
| 215 | PCIE_SPEED_8_0GT = 0x16, |
| 216 | PCI_SPEED_UNKNOWN = 0xff, |
| 217 | }; |
| 218 | |
| 219 | struct pci_cap_saved_data { |
| 220 | char cap_nr; |
| 221 | unsigned int size; |
| 222 | u32 data[0]; |
| 223 | }; |
| 224 | |
| 225 | struct pci_cap_saved_state { |
| 226 | struct hlist_node next; |
| 227 | struct pci_cap_saved_data cap; |
| 228 | }; |
| 229 | |
| 230 | struct pcie_link_state; |
| 231 | struct pci_vpd; |
| 232 | struct pci_sriov; |
| 233 | struct pci_ats; |
| 234 | |
| 235 | /* |
| 236 | * The pci_dev structure is used to describe PCI devices. |
| 237 | */ |
| 238 | struct pci_dev { |
| 239 | struct list_head bus_list; /* node in per-bus list */ |
| 240 | struct pci_bus *bus; /* bus this device is on */ |
| 241 | struct pci_bus *subordinate; /* bus this device bridges to */ |
| 242 | |
| 243 | void *sysdata; /* hook for sys-specific extension */ |
| 244 | struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ |
| 245 | struct pci_slot *slot; /* Physical slot this device is in */ |
| 246 | |
| 247 | unsigned int devfn; /* encoded device & function index */ |
| 248 | unsigned short vendor; |
| 249 | unsigned short device; |
| 250 | unsigned short subsystem_vendor; |
| 251 | unsigned short subsystem_device; |
| 252 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ |
| 253 | u8 revision; /* PCI revision, low byte of class word */ |
| 254 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
| 255 | u8 pcie_cap; /* PCI-E capability offset */ |
| 256 | u8 pcie_type:4; /* PCI-E device/port type */ |
| 257 | u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ |
| 258 | u8 rom_base_reg; /* which config register controls the ROM */ |
| 259 | u8 pin; /* which interrupt pin this device uses */ |
| 260 | |
| 261 | struct pci_driver *driver; /* which driver has allocated this device */ |
| 262 | u64 dma_mask; /* Mask of the bits of bus address this |
| 263 | device implements. Normally this is |
| 264 | 0xffffffff. You only need to change |
| 265 | this if your device has broken DMA |
| 266 | or supports 64-bit transfers. */ |
| 267 | |
| 268 | struct device_dma_parameters dma_parms; |
| 269 | |
| 270 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
| 271 | this is D0-D3, D0 being fully functional, |
| 272 | and D3 being off. */ |
| 273 | int pm_cap; /* PM capability offset in the |
| 274 | configuration space */ |
| 275 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
| 276 | can be generated */ |
| 277 | unsigned int pme_interrupt:1; |
| 278 | unsigned int pme_poll:1; /* Poll device's PME status bit */ |
| 279 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
| 280 | unsigned int d2_support:1; /* Low power state D2 is supported */ |
| 281 | unsigned int no_d1d2:1; /* Only allow D0 and D3 */ |
| 282 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
| 283 | decoding during bar sizing */ |
| 284 | unsigned int wakeup_prepared:1; |
| 285 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
| 286 | |
| 287 | #ifdef CONFIG_PCIEASPM |
| 288 | struct pcie_link_state *link_state; /* ASPM link state. */ |
| 289 | #endif |
| 290 | |
| 291 | pci_channel_state_t error_state; /* current connectivity state */ |
| 292 | struct device dev; /* Generic device interface */ |
| 293 | |
| 294 | int cfg_size; /* Size of configuration space */ |
| 295 | |
| 296 | /* |
| 297 | * Instead of touching interrupt line and base address registers |
| 298 | * directly, use the values stored here. They might be different! |
| 299 | */ |
| 300 | unsigned int irq; |
| 301 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
| 302 | |
| 303 | /* These fields are used by common fixups */ |
| 304 | unsigned int transparent:1; /* Transparent PCI bridge */ |
| 305 | unsigned int multifunction:1;/* Part of multi-function device */ |
| 306 | /* keep track of device state */ |
| 307 | unsigned int is_added:1; |
| 308 | unsigned int is_busmaster:1; /* device is busmaster */ |
| 309 | unsigned int no_msi:1; /* device may not use msi */ |
| 310 | unsigned int block_cfg_access:1; /* config space access is blocked */ |
| 311 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
| 312 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
| 313 | unsigned int msi_enabled:1; |
| 314 | unsigned int msix_enabled:1; |
| 315 | unsigned int ari_enabled:1; /* ARI forwarding */ |
| 316 | unsigned int is_managed:1; |
| 317 | unsigned int is_pcie:1; /* Obsolete. Will be removed. |
| 318 | Use pci_is_pcie() instead */ |
| 319 | unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
| 320 | unsigned int state_saved:1; |
| 321 | unsigned int is_physfn:1; |
| 322 | unsigned int is_virtfn:1; |
| 323 | unsigned int reset_fn:1; |
| 324 | unsigned int is_hotplug_bridge:1; |
| 325 | unsigned int __aer_firmware_first_valid:1; |
| 326 | unsigned int __aer_firmware_first:1; |
| 327 | pci_dev_flags_t dev_flags; |
| 328 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
| 329 | |
| 330 | u32 saved_config_space[16]; /* config space saved at suspend time */ |
| 331 | struct hlist_head saved_cap_space; |
| 332 | struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
| 333 | int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
| 334 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
| 335 | struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
| 336 | #ifdef CONFIG_PCI_MSI |
| 337 | struct list_head msi_list; |
| 338 | struct kset *msi_kset; |
| 339 | #endif |
| 340 | struct pci_vpd *vpd; |
| 341 | #ifdef CONFIG_PCI_ATS |
| 342 | union { |
| 343 | struct pci_sriov *sriov; /* SR-IOV capability related */ |
| 344 | struct pci_dev *physfn; /* the PF this VF is associated with */ |
| 345 | }; |
| 346 | struct pci_ats *ats; /* Address Translation Service */ |
| 347 | #endif |
| 348 | }; |
| 349 | |
| 350 | static inline struct pci_dev *pci_physfn(struct pci_dev *dev) |
| 351 | { |
| 352 | #ifdef CONFIG_PCI_IOV |
| 353 | if (dev->is_virtfn) |
| 354 | dev = dev->physfn; |
| 355 | #endif |
| 356 | |
| 357 | return dev; |
| 358 | } |
| 359 | |
| 360 | extern struct pci_dev *alloc_pci_dev(void); |
| 361 | |
| 362 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
| 363 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
| 364 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) |
| 365 | |
| 366 | static inline int pci_channel_offline(struct pci_dev *pdev) |
| 367 | { |
| 368 | return (pdev->error_state != pci_channel_io_normal); |
| 369 | } |
| 370 | |
| 371 | struct pci_host_bridge_window { |
| 372 | struct list_head list; |
| 373 | struct resource *res; /* host bridge aperture (CPU address) */ |
| 374 | resource_size_t offset; /* bus address + offset = CPU address */ |
| 375 | }; |
| 376 | |
| 377 | struct pci_host_bridge { |
| 378 | struct device dev; |
| 379 | struct pci_bus *bus; /* root bus */ |
| 380 | struct list_head windows; /* pci_host_bridge_windows */ |
| 381 | void (*release_fn)(struct pci_host_bridge *); |
| 382 | void *release_data; |
| 383 | }; |
| 384 | |
| 385 | #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) |
| 386 | void pci_set_host_bridge_release(struct pci_host_bridge *bridge, |
| 387 | void (*release_fn)(struct pci_host_bridge *), |
| 388 | void *release_data); |
| 389 | |
| 390 | /* |
| 391 | * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond |
| 392 | * to P2P or CardBus bridge windows) go in a table. Additional ones (for |
| 393 | * buses below host bridges or subtractive decode bridges) go in the list. |
| 394 | * Use pci_bus_for_each_resource() to iterate through all the resources. |
| 395 | */ |
| 396 | |
| 397 | /* |
| 398 | * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly |
| 399 | * and there's no way to program the bridge with the details of the window. |
| 400 | * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- |
| 401 | * decode bit set, because they are explicit and can be programmed with _SRS. |
| 402 | */ |
| 403 | #define PCI_SUBTRACTIVE_DECODE 0x1 |
| 404 | |
| 405 | struct pci_bus_resource { |
| 406 | struct list_head list; |
| 407 | struct resource *res; |
| 408 | unsigned int flags; |
| 409 | }; |
| 410 | |
| 411 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ |
| 412 | |
| 413 | struct pci_bus { |
| 414 | struct list_head node; /* node in list of buses */ |
| 415 | struct pci_bus *parent; /* parent bus this bridge is on */ |
| 416 | struct list_head children; /* list of child buses */ |
| 417 | struct list_head devices; /* list of devices on this bus */ |
| 418 | struct pci_dev *self; /* bridge device as seen by parent */ |
| 419 | struct list_head slots; /* list of slots on this bus */ |
| 420 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
| 421 | struct list_head resources; /* address space routed to this bus */ |
| 422 | |
| 423 | struct pci_ops *ops; /* configuration access functions */ |
| 424 | void *sysdata; /* hook for sys-specific extension */ |
| 425 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ |
| 426 | |
| 427 | unsigned char number; /* bus number */ |
| 428 | unsigned char primary; /* number of primary bridge */ |
| 429 | unsigned char secondary; /* number of secondary bridge */ |
| 430 | unsigned char subordinate; /* max number of subordinate buses */ |
| 431 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
| 432 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ |
| 433 | |
| 434 | char name[48]; |
| 435 | |
| 436 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ |
| 437 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
| 438 | struct device *bridge; |
| 439 | struct device dev; |
| 440 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
| 441 | struct bin_attribute *legacy_mem; /* legacy mem */ |
| 442 | unsigned int is_added:1; |
| 443 | }; |
| 444 | |
| 445 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
| 446 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
| 447 | |
| 448 | /* |
| 449 | * Returns true if the pci bus is root (behind host-pci bridge), |
| 450 | * false otherwise |
| 451 | */ |
| 452 | static inline bool pci_is_root_bus(struct pci_bus *pbus) |
| 453 | { |
| 454 | return !(pbus->parent); |
| 455 | } |
| 456 | |
| 457 | #ifdef CONFIG_PCI_MSI |
| 458 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) |
| 459 | { |
| 460 | return pci_dev->msi_enabled || pci_dev->msix_enabled; |
| 461 | } |
| 462 | #else |
| 463 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } |
| 464 | #endif |
| 465 | |
| 466 | /* |
| 467 | * Error values that may be returned by PCI functions. |
| 468 | */ |
| 469 | #define PCIBIOS_SUCCESSFUL 0x00 |
| 470 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 |
| 471 | #define PCIBIOS_BAD_VENDOR_ID 0x83 |
| 472 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 |
| 473 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 |
| 474 | #define PCIBIOS_SET_FAILED 0x88 |
| 475 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 |
| 476 | |
| 477 | /* Low-level architecture-dependent routines */ |
| 478 | |
| 479 | struct pci_ops { |
| 480 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
| 481 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); |
| 482 | }; |
| 483 | |
| 484 | /* |
| 485 | * ACPI needs to be able to access PCI config space before we've done a |
| 486 | * PCI bus scan and created pci_bus structures. |
| 487 | */ |
| 488 | extern int raw_pci_read(unsigned int domain, unsigned int bus, |
| 489 | unsigned int devfn, int reg, int len, u32 *val); |
| 490 | extern int raw_pci_write(unsigned int domain, unsigned int bus, |
| 491 | unsigned int devfn, int reg, int len, u32 val); |
| 492 | |
| 493 | struct pci_bus_region { |
| 494 | resource_size_t start; |
| 495 | resource_size_t end; |
| 496 | }; |
| 497 | |
| 498 | struct pci_dynids { |
| 499 | spinlock_t lock; /* protects list, index */ |
| 500 | struct list_head list; /* for IDs added at runtime */ |
| 501 | }; |
| 502 | |
| 503 | /* ---------------------------------------------------------------- */ |
| 504 | /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides |
| 505 | * a set of callbacks in struct pci_error_handlers, then that device driver |
| 506 | * will be notified of PCI bus errors, and will be driven to recovery |
| 507 | * when an error occurs. |
| 508 | */ |
| 509 | |
| 510 | typedef unsigned int __bitwise pci_ers_result_t; |
| 511 | |
| 512 | enum pci_ers_result { |
| 513 | /* no result/none/not supported in device driver */ |
| 514 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, |
| 515 | |
| 516 | /* Device driver can recover without slot reset */ |
| 517 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, |
| 518 | |
| 519 | /* Device driver wants slot to be reset. */ |
| 520 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, |
| 521 | |
| 522 | /* Device has completely failed, is unrecoverable */ |
| 523 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, |
| 524 | |
| 525 | /* Device driver is fully recovered and operational */ |
| 526 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, |
| 527 | }; |
| 528 | |
| 529 | /* PCI bus error event callbacks */ |
| 530 | struct pci_error_handlers { |
| 531 | /* PCI bus error detected on this device */ |
| 532 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, |
| 533 | enum pci_channel_state error); |
| 534 | |
| 535 | /* MMIO has been re-enabled, but not DMA */ |
| 536 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); |
| 537 | |
| 538 | /* PCI Express link has been reset */ |
| 539 | pci_ers_result_t (*link_reset)(struct pci_dev *dev); |
| 540 | |
| 541 | /* PCI slot has been reset */ |
| 542 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); |
| 543 | |
| 544 | /* Device driver may resume normal operations */ |
| 545 | void (*resume)(struct pci_dev *dev); |
| 546 | }; |
| 547 | |
| 548 | /* ---------------------------------------------------------------- */ |
| 549 | |
| 550 | struct module; |
| 551 | struct pci_driver { |
| 552 | struct list_head node; |
| 553 | const char *name; |
| 554 | const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ |
| 555 | int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ |
| 556 | void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ |
| 557 | int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ |
| 558 | int (*suspend_late) (struct pci_dev *dev, pm_message_t state); |
| 559 | int (*resume_early) (struct pci_dev *dev); |
| 560 | int (*resume) (struct pci_dev *dev); /* Device woken up */ |
| 561 | void (*shutdown) (struct pci_dev *dev); |
| 562 | struct pci_error_handlers *err_handler; |
| 563 | struct device_driver driver; |
| 564 | struct pci_dynids dynids; |
| 565 | }; |
| 566 | |
| 567 | #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
| 568 | |
| 569 | /** |
| 570 | * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table |
| 571 | * @_table: device table name |
| 572 | * |
| 573 | * This macro is used to create a struct pci_device_id array (a device table) |
| 574 | * in a generic manner. |
| 575 | */ |
| 576 | #define DEFINE_PCI_DEVICE_TABLE(_table) \ |
| 577 | const struct pci_device_id _table[] __devinitconst |
| 578 | |
| 579 | /** |
| 580 | * PCI_DEVICE - macro used to describe a specific pci device |
| 581 | * @vend: the 16 bit PCI Vendor ID |
| 582 | * @dev: the 16 bit PCI Device ID |
| 583 | * |
| 584 | * This macro is used to create a struct pci_device_id that matches a |
| 585 | * specific device. The subvendor and subdevice fields will be set to |
| 586 | * PCI_ANY_ID. |
| 587 | */ |
| 588 | #define PCI_DEVICE(vend,dev) \ |
| 589 | .vendor = (vend), .device = (dev), \ |
| 590 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID |
| 591 | |
| 592 | /** |
| 593 | * PCI_DEVICE_CLASS - macro used to describe a specific pci device class |
| 594 | * @dev_class: the class, subclass, prog-if triple for this device |
| 595 | * @dev_class_mask: the class mask for this device |
| 596 | * |
| 597 | * This macro is used to create a struct pci_device_id that matches a |
| 598 | * specific PCI class. The vendor, device, subvendor, and subdevice |
| 599 | * fields will be set to PCI_ANY_ID. |
| 600 | */ |
| 601 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ |
| 602 | .class = (dev_class), .class_mask = (dev_class_mask), \ |
| 603 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ |
| 604 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID |
| 605 | |
| 606 | /** |
| 607 | * PCI_VDEVICE - macro used to describe a specific pci device in short form |
| 608 | * @vendor: the vendor name |
| 609 | * @device: the 16 bit PCI Device ID |
| 610 | * |
| 611 | * This macro is used to create a struct pci_device_id that matches a |
| 612 | * specific PCI device. The subvendor, and subdevice fields will be set |
| 613 | * to PCI_ANY_ID. The macro allows the next field to follow as the device |
| 614 | * private data. |
| 615 | */ |
| 616 | |
| 617 | #define PCI_VDEVICE(vendor, device) \ |
| 618 | PCI_VENDOR_ID_##vendor, (device), \ |
| 619 | PCI_ANY_ID, PCI_ANY_ID, 0, 0 |
| 620 | |
| 621 | /* these external functions are only available when PCI support is enabled */ |
| 622 | #ifdef CONFIG_PCI |
| 623 | |
| 624 | extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss); |
| 625 | |
| 626 | enum pcie_bus_config_types { |
| 627 | PCIE_BUS_TUNE_OFF, |
| 628 | PCIE_BUS_SAFE, |
| 629 | PCIE_BUS_PERFORMANCE, |
| 630 | PCIE_BUS_PEER2PEER, |
| 631 | }; |
| 632 | |
| 633 | extern enum pcie_bus_config_types pcie_bus_config; |
| 634 | |
| 635 | extern struct bus_type pci_bus_type; |
| 636 | |
| 637 | /* Do NOT directly access these two variables, unless you are arch specific pci |
| 638 | * code, or pci core code. */ |
| 639 | extern struct list_head pci_root_buses; /* list of all known PCI buses */ |
| 640 | /* Some device drivers need know if pci is initiated */ |
| 641 | extern int no_pci_devices(void); |
| 642 | |
| 643 | void pcibios_fixup_bus(struct pci_bus *); |
| 644 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
| 645 | /* Architecture specific versions may override this (weak) */ |
| 646 | char *pcibios_setup(char *str); |
| 647 | |
| 648 | /* Used only when drivers/pci/setup.c is used */ |
| 649 | resource_size_t pcibios_align_resource(void *, const struct resource *, |
| 650 | resource_size_t, |
| 651 | resource_size_t); |
| 652 | void pcibios_update_irq(struct pci_dev *, int irq); |
| 653 | |
| 654 | /* Weak but can be overriden by arch */ |
| 655 | void pci_fixup_cardbus(struct pci_bus *); |
| 656 | |
| 657 | /* Generic PCI functions used internally */ |
| 658 | |
| 659 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, |
| 660 | struct resource *res); |
| 661 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, |
| 662 | struct pci_bus_region *region); |
| 663 | void pcibios_scan_specific_bus(int busn); |
| 664 | extern struct pci_bus *pci_find_bus(int domain, int busnr); |
| 665 | void pci_bus_add_devices(const struct pci_bus *bus); |
| 666 | struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, |
| 667 | struct pci_ops *ops, void *sysdata); |
| 668 | struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); |
| 669 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
| 670 | struct pci_ops *ops, void *sysdata, |
| 671 | struct list_head *resources); |
| 672 | struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus, |
| 673 | struct pci_ops *ops, void *sysdata, |
| 674 | struct list_head *resources); |
| 675 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, |
| 676 | int busnr); |
| 677 | void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); |
| 678 | struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
| 679 | const char *name, |
| 680 | struct hotplug_slot *hotplug); |
| 681 | void pci_destroy_slot(struct pci_slot *slot); |
| 682 | void pci_renumber_slot(struct pci_slot *slot, int slot_nr); |
| 683 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
| 684 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
| 685 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
| 686 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
| 687 | int __must_check pci_bus_add_device(struct pci_dev *dev); |
| 688 | void pci_read_bridge_bases(struct pci_bus *child); |
| 689 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
| 690 | struct resource *res); |
| 691 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); |
| 692 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
| 693 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
| 694 | extern struct pci_dev *pci_dev_get(struct pci_dev *dev); |
| 695 | extern void pci_dev_put(struct pci_dev *dev); |
| 696 | extern void pci_remove_bus(struct pci_bus *b); |
| 697 | extern void __pci_remove_bus_device(struct pci_dev *dev); |
| 698 | extern void pci_stop_and_remove_bus_device(struct pci_dev *dev); |
| 699 | extern void pci_stop_bus_device(struct pci_dev *dev); |
| 700 | void pci_setup_cardbus(struct pci_bus *bus); |
| 701 | extern void pci_sort_breadthfirst(void); |
| 702 | #define dev_is_pci(d) ((d)->bus == &pci_bus_type) |
| 703 | #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) |
| 704 | #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) |
| 705 | |
| 706 | /* Generic PCI functions exported to card drivers */ |
| 707 | |
| 708 | enum pci_lost_interrupt_reason { |
| 709 | PCI_LOST_IRQ_NO_INFORMATION = 0, |
| 710 | PCI_LOST_IRQ_DISABLE_MSI, |
| 711 | PCI_LOST_IRQ_DISABLE_MSIX, |
| 712 | PCI_LOST_IRQ_DISABLE_ACPI, |
| 713 | }; |
| 714 | enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); |
| 715 | int pci_find_capability(struct pci_dev *dev, int cap); |
| 716 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); |
| 717 | int pci_find_ext_capability(struct pci_dev *dev, int cap); |
| 718 | int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn, |
| 719 | int cap); |
| 720 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); |
| 721 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); |
| 722 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
| 723 | |
| 724 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
| 725 | struct pci_dev *from); |
| 726 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
| 727 | unsigned int ss_vendor, unsigned int ss_device, |
| 728 | struct pci_dev *from); |
| 729 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
| 730 | struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, |
| 731 | unsigned int devfn); |
| 732 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, |
| 733 | unsigned int devfn) |
| 734 | { |
| 735 | return pci_get_domain_bus_and_slot(0, bus, devfn); |
| 736 | } |
| 737 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
| 738 | int pci_dev_present(const struct pci_device_id *ids); |
| 739 | |
| 740 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
| 741 | int where, u8 *val); |
| 742 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, |
| 743 | int where, u16 *val); |
| 744 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, |
| 745 | int where, u32 *val); |
| 746 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, |
| 747 | int where, u8 val); |
| 748 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, |
| 749 | int where, u16 val); |
| 750 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, |
| 751 | int where, u32 val); |
| 752 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); |
| 753 | |
| 754 | static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) |
| 755 | { |
| 756 | return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); |
| 757 | } |
| 758 | static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) |
| 759 | { |
| 760 | return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); |
| 761 | } |
| 762 | static inline int pci_read_config_dword(const struct pci_dev *dev, int where, |
| 763 | u32 *val) |
| 764 | { |
| 765 | return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); |
| 766 | } |
| 767 | static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) |
| 768 | { |
| 769 | return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); |
| 770 | } |
| 771 | static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) |
| 772 | { |
| 773 | return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); |
| 774 | } |
| 775 | static inline int pci_write_config_dword(const struct pci_dev *dev, int where, |
| 776 | u32 val) |
| 777 | { |
| 778 | return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); |
| 779 | } |
| 780 | |
| 781 | int __must_check pci_enable_device(struct pci_dev *dev); |
| 782 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
| 783 | int __must_check pci_enable_device_mem(struct pci_dev *dev); |
| 784 | int __must_check pci_reenable_device(struct pci_dev *); |
| 785 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
| 786 | void pcim_pin_device(struct pci_dev *pdev); |
| 787 | |
| 788 | static inline int pci_is_enabled(struct pci_dev *pdev) |
| 789 | { |
| 790 | return (atomic_read(&pdev->enable_cnt) > 0); |
| 791 | } |
| 792 | |
| 793 | static inline int pci_is_managed(struct pci_dev *pdev) |
| 794 | { |
| 795 | return pdev->is_managed; |
| 796 | } |
| 797 | |
| 798 | void pci_disable_device(struct pci_dev *dev); |
| 799 | |
| 800 | extern unsigned int pcibios_max_latency; |
| 801 | void pci_set_master(struct pci_dev *dev); |
| 802 | void pci_clear_master(struct pci_dev *dev); |
| 803 | |
| 804 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
| 805 | int pci_set_cacheline_size(struct pci_dev *dev); |
| 806 | #define HAVE_PCI_SET_MWI |
| 807 | int __must_check pci_set_mwi(struct pci_dev *dev); |
| 808 | int pci_try_set_mwi(struct pci_dev *dev); |
| 809 | void pci_clear_mwi(struct pci_dev *dev); |
| 810 | void pci_intx(struct pci_dev *dev, int enable); |
| 811 | bool pci_intx_mask_supported(struct pci_dev *dev); |
| 812 | bool pci_check_and_mask_intx(struct pci_dev *dev); |
| 813 | bool pci_check_and_unmask_intx(struct pci_dev *dev); |
| 814 | void pci_msi_off(struct pci_dev *dev); |
| 815 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); |
| 816 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); |
| 817 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
| 818 | int pcix_get_mmrbc(struct pci_dev *dev); |
| 819 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); |
| 820 | int pcie_get_readrq(struct pci_dev *dev); |
| 821 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
| 822 | int pcie_get_mps(struct pci_dev *dev); |
| 823 | int pcie_set_mps(struct pci_dev *dev, int mps); |
| 824 | int __pci_reset_function(struct pci_dev *dev); |
| 825 | int __pci_reset_function_locked(struct pci_dev *dev); |
| 826 | int pci_reset_function(struct pci_dev *dev); |
| 827 | void pci_update_resource(struct pci_dev *dev, int resno); |
| 828 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
| 829 | int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); |
| 830 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
| 831 | |
| 832 | /* ROM control related routines */ |
| 833 | int pci_enable_rom(struct pci_dev *pdev); |
| 834 | void pci_disable_rom(struct pci_dev *pdev); |
| 835 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
| 836 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
| 837 | size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); |
| 838 | |
| 839 | /* Power management related routines */ |
| 840 | int pci_save_state(struct pci_dev *dev); |
| 841 | void pci_restore_state(struct pci_dev *dev); |
| 842 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); |
| 843 | int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state); |
| 844 | int pci_load_and_free_saved_state(struct pci_dev *dev, |
| 845 | struct pci_saved_state **state); |
| 846 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); |
| 847 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
| 848 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); |
| 849 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); |
| 850 | void pci_pme_active(struct pci_dev *dev, bool enable); |
| 851 | int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
| 852 | bool runtime, bool enable); |
| 853 | int pci_wake_from_d3(struct pci_dev *dev, bool enable); |
| 854 | pci_power_t pci_target_state(struct pci_dev *dev); |
| 855 | int pci_prepare_to_sleep(struct pci_dev *dev); |
| 856 | int pci_back_from_sleep(struct pci_dev *dev); |
| 857 | bool pci_dev_run_wake(struct pci_dev *dev); |
| 858 | bool pci_check_pme_status(struct pci_dev *dev); |
| 859 | void pci_pme_wakeup_bus(struct pci_bus *bus); |
| 860 | |
| 861 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
| 862 | bool enable) |
| 863 | { |
| 864 | return __pci_enable_wake(dev, state, false, enable); |
| 865 | } |
| 866 | |
| 867 | #define PCI_EXP_IDO_REQUEST (1<<0) |
| 868 | #define PCI_EXP_IDO_COMPLETION (1<<1) |
| 869 | void pci_enable_ido(struct pci_dev *dev, unsigned long type); |
| 870 | void pci_disable_ido(struct pci_dev *dev, unsigned long type); |
| 871 | |
| 872 | enum pci_obff_signal_type { |
| 873 | PCI_EXP_OBFF_SIGNAL_L0 = 0, |
| 874 | PCI_EXP_OBFF_SIGNAL_ALWAYS = 1, |
| 875 | }; |
| 876 | int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type); |
| 877 | void pci_disable_obff(struct pci_dev *dev); |
| 878 | |
| 879 | bool pci_ltr_supported(struct pci_dev *dev); |
| 880 | int pci_enable_ltr(struct pci_dev *dev); |
| 881 | void pci_disable_ltr(struct pci_dev *dev); |
| 882 | int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns); |
| 883 | |
| 884 | /* For use by arch with custom probe code */ |
| 885 | void set_pcie_port_type(struct pci_dev *pdev); |
| 886 | void set_pcie_hotplug_bridge(struct pci_dev *pdev); |
| 887 | |
| 888 | /* Functions for PCI Hotplug drivers to use */ |
| 889 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
| 890 | #ifdef CONFIG_HOTPLUG |
| 891 | unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); |
| 892 | unsigned int pci_rescan_bus(struct pci_bus *bus); |
| 893 | #endif |
| 894 | |
| 895 | /* Vital product data routines */ |
| 896 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); |
| 897 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); |
| 898 | int pci_vpd_truncate(struct pci_dev *dev, size_t size); |
| 899 | |
| 900 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
| 901 | resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); |
| 902 | void pci_bus_assign_resources(const struct pci_bus *bus); |
| 903 | void pci_bus_size_bridges(struct pci_bus *bus); |
| 904 | int pci_claim_resource(struct pci_dev *, int); |
| 905 | void pci_assign_unassigned_resources(void); |
| 906 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); |
| 907 | void pdev_enable_device(struct pci_dev *); |
| 908 | int pci_enable_resources(struct pci_dev *, int mask); |
| 909 | void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), |
| 910 | int (*)(const struct pci_dev *, u8, u8)); |
| 911 | #define HAVE_PCI_REQ_REGIONS 2 |
| 912 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
| 913 | int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); |
| 914 | void pci_release_regions(struct pci_dev *); |
| 915 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
| 916 | int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); |
| 917 | void pci_release_region(struct pci_dev *, int); |
| 918 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
| 919 | int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); |
| 920 | void pci_release_selected_regions(struct pci_dev *, int); |
| 921 | |
| 922 | /* drivers/pci/bus.c */ |
| 923 | void pci_add_resource(struct list_head *resources, struct resource *res); |
| 924 | void pci_add_resource_offset(struct list_head *resources, struct resource *res, |
| 925 | resource_size_t offset); |
| 926 | void pci_free_resource_list(struct list_head *resources); |
| 927 | void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); |
| 928 | struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); |
| 929 | void pci_bus_remove_resources(struct pci_bus *bus); |
| 930 | |
| 931 | #define pci_bus_for_each_resource(bus, res, i) \ |
| 932 | for (i = 0; \ |
| 933 | (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ |
| 934 | i++) |
| 935 | |
| 936 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
| 937 | struct resource *res, resource_size_t size, |
| 938 | resource_size_t align, resource_size_t min, |
| 939 | unsigned int type_mask, |
| 940 | resource_size_t (*alignf)(void *, |
| 941 | const struct resource *, |
| 942 | resource_size_t, |
| 943 | resource_size_t), |
| 944 | void *alignf_data); |
| 945 | void pci_enable_bridges(struct pci_bus *bus); |
| 946 | |
| 947 | /* Proper probing supporting hot-pluggable devices */ |
| 948 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
| 949 | const char *mod_name); |
| 950 | |
| 951 | /* |
| 952 | * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded |
| 953 | */ |
| 954 | #define pci_register_driver(driver) \ |
| 955 | __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) |
| 956 | |
| 957 | void pci_unregister_driver(struct pci_driver *dev); |
| 958 | |
| 959 | /** |
| 960 | * module_pci_driver() - Helper macro for registering a PCI driver |
| 961 | * @__pci_driver: pci_driver struct |
| 962 | * |
| 963 | * Helper macro for PCI drivers which do not do anything special in module |
| 964 | * init/exit. This eliminates a lot of boilerplate. Each module may only |
| 965 | * use this macro once, and calling it replaces module_init() and module_exit() |
| 966 | */ |
| 967 | #define module_pci_driver(__pci_driver) \ |
| 968 | module_driver(__pci_driver, pci_register_driver, \ |
| 969 | pci_unregister_driver) |
| 970 | |
| 971 | void pci_stop_and_remove_behind_bridge(struct pci_dev *dev); |
| 972 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); |
| 973 | int pci_add_dynid(struct pci_driver *drv, |
| 974 | unsigned int vendor, unsigned int device, |
| 975 | unsigned int subvendor, unsigned int subdevice, |
| 976 | unsigned int class, unsigned int class_mask, |
| 977 | unsigned long driver_data); |
| 978 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, |
| 979 | struct pci_dev *dev); |
| 980 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, |
| 981 | int pass); |
| 982 | |
| 983 | void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), |
| 984 | void *userdata); |
| 985 | int pci_cfg_space_size_ext(struct pci_dev *dev); |
| 986 | int pci_cfg_space_size(struct pci_dev *dev); |
| 987 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
| 988 | void pci_setup_bridge(struct pci_bus *bus); |
| 989 | |
| 990 | #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) |
| 991 | #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) |
| 992 | |
| 993 | int pci_set_vga_state(struct pci_dev *pdev, bool decode, |
| 994 | unsigned int command_bits, u32 flags); |
| 995 | /* kmem_cache style wrapper around pci_alloc_consistent() */ |
| 996 | |
| 997 | #include <linux/pci-dma.h> |
| 998 | #include <linux/dmapool.h> |
| 999 | |
| 1000 | #define pci_pool dma_pool |
| 1001 | #define pci_pool_create(name, pdev, size, align, allocation) \ |
| 1002 | dma_pool_create(name, &pdev->dev, size, align, allocation) |
| 1003 | #define pci_pool_destroy(pool) dma_pool_destroy(pool) |
| 1004 | #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) |
| 1005 | #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) |
| 1006 | |
| 1007 | enum pci_dma_burst_strategy { |
| 1008 | PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, |
| 1009 | strategy_parameter is N/A */ |
| 1010 | PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter |
| 1011 | byte boundaries */ |
| 1012 | PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of |
| 1013 | strategy_parameter byte boundaries */ |
| 1014 | }; |
| 1015 | |
| 1016 | struct msix_entry { |
| 1017 | u32 vector; /* kernel uses to write allocated vector */ |
| 1018 | u16 entry; /* driver uses to specify entry, OS writes */ |
| 1019 | }; |
| 1020 | |
| 1021 | |
| 1022 | #ifndef CONFIG_PCI_MSI |
| 1023 | static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) |
| 1024 | { |
| 1025 | return -1; |
| 1026 | } |
| 1027 | |
| 1028 | static inline void pci_msi_shutdown(struct pci_dev *dev) |
| 1029 | { } |
| 1030 | static inline void pci_disable_msi(struct pci_dev *dev) |
| 1031 | { } |
| 1032 | |
| 1033 | static inline int pci_msix_table_size(struct pci_dev *dev) |
| 1034 | { |
| 1035 | return 0; |
| 1036 | } |
| 1037 | static inline int pci_enable_msix(struct pci_dev *dev, |
| 1038 | struct msix_entry *entries, int nvec) |
| 1039 | { |
| 1040 | return -1; |
| 1041 | } |
| 1042 | |
| 1043 | static inline void pci_msix_shutdown(struct pci_dev *dev) |
| 1044 | { } |
| 1045 | static inline void pci_disable_msix(struct pci_dev *dev) |
| 1046 | { } |
| 1047 | |
| 1048 | static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) |
| 1049 | { } |
| 1050 | |
| 1051 | static inline void pci_restore_msi_state(struct pci_dev *dev) |
| 1052 | { } |
| 1053 | static inline int pci_msi_enabled(void) |
| 1054 | { |
| 1055 | return 0; |
| 1056 | } |
| 1057 | #else |
| 1058 | extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec); |
| 1059 | extern void pci_msi_shutdown(struct pci_dev *dev); |
| 1060 | extern void pci_disable_msi(struct pci_dev *dev); |
| 1061 | extern int pci_msix_table_size(struct pci_dev *dev); |
| 1062 | extern int pci_enable_msix(struct pci_dev *dev, |
| 1063 | struct msix_entry *entries, int nvec); |
| 1064 | extern void pci_msix_shutdown(struct pci_dev *dev); |
| 1065 | extern void pci_disable_msix(struct pci_dev *dev); |
| 1066 | extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); |
| 1067 | extern void pci_restore_msi_state(struct pci_dev *dev); |
| 1068 | extern int pci_msi_enabled(void); |
| 1069 | #endif |
| 1070 | |
| 1071 | #ifdef CONFIG_PCIEPORTBUS |
| 1072 | extern bool pcie_ports_disabled; |
| 1073 | extern bool pcie_ports_auto; |
| 1074 | #else |
| 1075 | #define pcie_ports_disabled true |
| 1076 | #define pcie_ports_auto false |
| 1077 | #endif |
| 1078 | |
| 1079 | #ifndef CONFIG_PCIEASPM |
| 1080 | static inline int pcie_aspm_enabled(void) { return 0; } |
| 1081 | static inline bool pcie_aspm_support_enabled(void) { return false; } |
| 1082 | #else |
| 1083 | extern int pcie_aspm_enabled(void); |
| 1084 | extern bool pcie_aspm_support_enabled(void); |
| 1085 | #endif |
| 1086 | |
| 1087 | #ifdef CONFIG_PCIEAER |
| 1088 | void pci_no_aer(void); |
| 1089 | bool pci_aer_available(void); |
| 1090 | #else |
| 1091 | static inline void pci_no_aer(void) { } |
| 1092 | static inline bool pci_aer_available(void) { return false; } |
| 1093 | #endif |
| 1094 | |
| 1095 | #ifndef CONFIG_PCIE_ECRC |
| 1096 | static inline void pcie_set_ecrc_checking(struct pci_dev *dev) |
| 1097 | { |
| 1098 | return; |
| 1099 | } |
| 1100 | static inline void pcie_ecrc_get_policy(char *str) {}; |
| 1101 | #else |
| 1102 | extern void pcie_set_ecrc_checking(struct pci_dev *dev); |
| 1103 | extern void pcie_ecrc_get_policy(char *str); |
| 1104 | #endif |
| 1105 | |
| 1106 | #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1) |
| 1107 | |
| 1108 | #ifdef CONFIG_HT_IRQ |
| 1109 | /* The functions a driver should call */ |
| 1110 | int ht_create_irq(struct pci_dev *dev, int idx); |
| 1111 | void ht_destroy_irq(unsigned int irq); |
| 1112 | #endif /* CONFIG_HT_IRQ */ |
| 1113 | |
| 1114 | extern void pci_cfg_access_lock(struct pci_dev *dev); |
| 1115 | extern bool pci_cfg_access_trylock(struct pci_dev *dev); |
| 1116 | extern void pci_cfg_access_unlock(struct pci_dev *dev); |
| 1117 | |
| 1118 | /* |
| 1119 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), |
| 1120 | * a PCI domain is defined to be a set of PCI busses which share |
| 1121 | * configuration space. |
| 1122 | */ |
| 1123 | #ifdef CONFIG_PCI_DOMAINS |
| 1124 | extern int pci_domains_supported; |
| 1125 | #else |
| 1126 | enum { pci_domains_supported = 0 }; |
| 1127 | static inline int pci_domain_nr(struct pci_bus *bus) |
| 1128 | { |
| 1129 | return 0; |
| 1130 | } |
| 1131 | |
| 1132 | static inline int pci_proc_domain(struct pci_bus *bus) |
| 1133 | { |
| 1134 | return 0; |
| 1135 | } |
| 1136 | #endif /* CONFIG_PCI_DOMAINS */ |
| 1137 | |
| 1138 | /* some architectures require additional setup to direct VGA traffic */ |
| 1139 | typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, |
| 1140 | unsigned int command_bits, u32 flags); |
| 1141 | extern void pci_register_set_vga_state(arch_set_vga_state_t func); |
| 1142 | |
| 1143 | #else /* CONFIG_PCI is not enabled */ |
| 1144 | |
| 1145 | /* |
| 1146 | * If the system does not have PCI, clearly these return errors. Define |
| 1147 | * these as simple inline functions to avoid hair in drivers. |
| 1148 | */ |
| 1149 | |
| 1150 | #define _PCI_NOP(o, s, t) \ |
| 1151 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ |
| 1152 | int where, t val) \ |
| 1153 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
| 1154 | |
| 1155 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ |
| 1156 | _PCI_NOP(o, word, u16 x) \ |
| 1157 | _PCI_NOP(o, dword, u32 x) |
| 1158 | _PCI_NOP_ALL(read, *) |
| 1159 | _PCI_NOP_ALL(write,) |
| 1160 | |
| 1161 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
| 1162 | unsigned int device, |
| 1163 | struct pci_dev *from) |
| 1164 | { |
| 1165 | return NULL; |
| 1166 | } |
| 1167 | |
| 1168 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
| 1169 | unsigned int device, |
| 1170 | unsigned int ss_vendor, |
| 1171 | unsigned int ss_device, |
| 1172 | struct pci_dev *from) |
| 1173 | { |
| 1174 | return NULL; |
| 1175 | } |
| 1176 | |
| 1177 | static inline struct pci_dev *pci_get_class(unsigned int class, |
| 1178 | struct pci_dev *from) |
| 1179 | { |
| 1180 | return NULL; |
| 1181 | } |
| 1182 | |
| 1183 | #define pci_dev_present(ids) (0) |
| 1184 | #define no_pci_devices() (1) |
| 1185 | #define pci_dev_put(dev) do { } while (0) |
| 1186 | |
| 1187 | static inline void pci_set_master(struct pci_dev *dev) |
| 1188 | { } |
| 1189 | |
| 1190 | static inline int pci_enable_device(struct pci_dev *dev) |
| 1191 | { |
| 1192 | return -EIO; |
| 1193 | } |
| 1194 | |
| 1195 | static inline void pci_disable_device(struct pci_dev *dev) |
| 1196 | { } |
| 1197 | |
| 1198 | static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) |
| 1199 | { |
| 1200 | return -EIO; |
| 1201 | } |
| 1202 | |
| 1203 | static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) |
| 1204 | { |
| 1205 | return -EIO; |
| 1206 | } |
| 1207 | |
| 1208 | static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, |
| 1209 | unsigned int size) |
| 1210 | { |
| 1211 | return -EIO; |
| 1212 | } |
| 1213 | |
| 1214 | static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, |
| 1215 | unsigned long mask) |
| 1216 | { |
| 1217 | return -EIO; |
| 1218 | } |
| 1219 | |
| 1220 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
| 1221 | { |
| 1222 | return -EBUSY; |
| 1223 | } |
| 1224 | |
| 1225 | static inline int __pci_register_driver(struct pci_driver *drv, |
| 1226 | struct module *owner) |
| 1227 | { |
| 1228 | return 0; |
| 1229 | } |
| 1230 | |
| 1231 | static inline int pci_register_driver(struct pci_driver *drv) |
| 1232 | { |
| 1233 | return 0; |
| 1234 | } |
| 1235 | |
| 1236 | static inline void pci_unregister_driver(struct pci_driver *drv) |
| 1237 | { } |
| 1238 | |
| 1239 | static inline int pci_find_capability(struct pci_dev *dev, int cap) |
| 1240 | { |
| 1241 | return 0; |
| 1242 | } |
| 1243 | |
| 1244 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, |
| 1245 | int cap) |
| 1246 | { |
| 1247 | return 0; |
| 1248 | } |
| 1249 | |
| 1250 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) |
| 1251 | { |
| 1252 | return 0; |
| 1253 | } |
| 1254 | |
| 1255 | /* Power management related routines */ |
| 1256 | static inline int pci_save_state(struct pci_dev *dev) |
| 1257 | { |
| 1258 | return 0; |
| 1259 | } |
| 1260 | |
| 1261 | static inline void pci_restore_state(struct pci_dev *dev) |
| 1262 | { } |
| 1263 | |
| 1264 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
| 1265 | { |
| 1266 | return 0; |
| 1267 | } |
| 1268 | |
| 1269 | static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) |
| 1270 | { |
| 1271 | return 0; |
| 1272 | } |
| 1273 | |
| 1274 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, |
| 1275 | pm_message_t state) |
| 1276 | { |
| 1277 | return PCI_D0; |
| 1278 | } |
| 1279 | |
| 1280 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
| 1281 | int enable) |
| 1282 | { |
| 1283 | return 0; |
| 1284 | } |
| 1285 | |
| 1286 | static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type) |
| 1287 | { |
| 1288 | } |
| 1289 | |
| 1290 | static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type) |
| 1291 | { |
| 1292 | } |
| 1293 | |
| 1294 | static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type) |
| 1295 | { |
| 1296 | return 0; |
| 1297 | } |
| 1298 | |
| 1299 | static inline void pci_disable_obff(struct pci_dev *dev) |
| 1300 | { |
| 1301 | } |
| 1302 | |
| 1303 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) |
| 1304 | { |
| 1305 | return -EIO; |
| 1306 | } |
| 1307 | |
| 1308 | static inline void pci_release_regions(struct pci_dev *dev) |
| 1309 | { } |
| 1310 | |
| 1311 | #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) |
| 1312 | |
| 1313 | static inline void pci_block_cfg_access(struct pci_dev *dev) |
| 1314 | { } |
| 1315 | |
| 1316 | static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) |
| 1317 | { return 0; } |
| 1318 | |
| 1319 | static inline void pci_unblock_cfg_access(struct pci_dev *dev) |
| 1320 | { } |
| 1321 | |
| 1322 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
| 1323 | { return NULL; } |
| 1324 | |
| 1325 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, |
| 1326 | unsigned int devfn) |
| 1327 | { return NULL; } |
| 1328 | |
| 1329 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, |
| 1330 | unsigned int devfn) |
| 1331 | { return NULL; } |
| 1332 | |
| 1333 | static inline int pci_domain_nr(struct pci_bus *bus) |
| 1334 | { return 0; } |
| 1335 | |
| 1336 | #define dev_is_pci(d) (false) |
| 1337 | #define dev_is_pf(d) (false) |
| 1338 | #define dev_num_vf(d) (0) |
| 1339 | #endif /* CONFIG_PCI */ |
| 1340 | |
| 1341 | /* Include architecture-dependent settings and functions */ |
| 1342 | |
| 1343 | #include <asm/pci.h> |
| 1344 | |
| 1345 | #ifndef PCIBIOS_MAX_MEM_32 |
| 1346 | #define PCIBIOS_MAX_MEM_32 (-1) |
| 1347 | #endif |
| 1348 | |
| 1349 | /* these helpers provide future and backwards compatibility |
| 1350 | * for accessing popular PCI BAR info */ |
| 1351 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
| 1352 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
| 1353 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
| 1354 | #define pci_resource_len(dev,bar) \ |
| 1355 | ((pci_resource_start((dev), (bar)) == 0 && \ |
| 1356 | pci_resource_end((dev), (bar)) == \ |
| 1357 | pci_resource_start((dev), (bar))) ? 0 : \ |
| 1358 | \ |
| 1359 | (pci_resource_end((dev), (bar)) - \ |
| 1360 | pci_resource_start((dev), (bar)) + 1)) |
| 1361 | |
| 1362 | /* Similar to the helpers above, these manipulate per-pci_dev |
| 1363 | * driver-specific data. They are really just a wrapper around |
| 1364 | * the generic device structure functions of these calls. |
| 1365 | */ |
| 1366 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
| 1367 | { |
| 1368 | return dev_get_drvdata(&pdev->dev); |
| 1369 | } |
| 1370 | |
| 1371 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
| 1372 | { |
| 1373 | dev_set_drvdata(&pdev->dev, data); |
| 1374 | } |
| 1375 | |
| 1376 | /* If you want to know what to call your pci_dev, ask this function. |
| 1377 | * Again, it's a wrapper around the generic device. |
| 1378 | */ |
| 1379 | static inline const char *pci_name(const struct pci_dev *pdev) |
| 1380 | { |
| 1381 | return dev_name(&pdev->dev); |
| 1382 | } |
| 1383 | |
| 1384 | |
| 1385 | /* Some archs don't want to expose struct resource to userland as-is |
| 1386 | * in sysfs and /proc |
| 1387 | */ |
| 1388 | #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER |
| 1389 | static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, |
| 1390 | const struct resource *rsrc, resource_size_t *start, |
| 1391 | resource_size_t *end) |
| 1392 | { |
| 1393 | *start = rsrc->start; |
| 1394 | *end = rsrc->end; |
| 1395 | } |
| 1396 | #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ |
| 1397 | |
| 1398 | |
| 1399 | /* |
| 1400 | * The world is not perfect and supplies us with broken PCI devices. |
| 1401 | * For at least a part of these bugs we need a work-around, so both |
| 1402 | * generic (drivers/pci/quirks.c) and per-architecture code can define |
| 1403 | * fixup hooks to be called for particular buggy devices. |
| 1404 | */ |
| 1405 | |
| 1406 | struct pci_fixup { |
| 1407 | u16 vendor; /* You can use PCI_ANY_ID here of course */ |
| 1408 | u16 device; /* You can use PCI_ANY_ID here of course */ |
| 1409 | u32 class; /* You can use PCI_ANY_ID here too */ |
| 1410 | unsigned int class_shift; /* should be 0, 8, 16 */ |
| 1411 | void (*hook)(struct pci_dev *dev); |
| 1412 | }; |
| 1413 | |
| 1414 | enum pci_fixup_pass { |
| 1415 | pci_fixup_early, /* Before probing BARs */ |
| 1416 | pci_fixup_header, /* After reading configuration header */ |
| 1417 | pci_fixup_final, /* Final phase of device fixups */ |
| 1418 | pci_fixup_enable, /* pci_enable_device() time */ |
| 1419 | pci_fixup_resume, /* pci_device_resume() */ |
| 1420 | pci_fixup_suspend, /* pci_device_suspend */ |
| 1421 | pci_fixup_resume_early, /* pci_device_resume_early() */ |
| 1422 | }; |
| 1423 | |
| 1424 | /* Anonymous variables would be nice... */ |
| 1425 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ |
| 1426 | class_shift, hook) \ |
| 1427 | static const struct pci_fixup const __pci_fixup_##name __used \ |
| 1428 | __attribute__((__section__(#section), aligned((sizeof(void *))))) \ |
| 1429 | = { vendor, device, class, class_shift, hook }; |
| 1430 | |
| 1431 | #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ |
| 1432 | class_shift, hook) \ |
| 1433 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ |
| 1434 | vendor##device##hook, vendor, device, class, class_shift, hook) |
| 1435 | #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ |
| 1436 | class_shift, hook) \ |
| 1437 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ |
| 1438 | vendor##device##hook, vendor, device, class, class_shift, hook) |
| 1439 | #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ |
| 1440 | class_shift, hook) \ |
| 1441 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ |
| 1442 | vendor##device##hook, vendor, device, class, class_shift, hook) |
| 1443 | #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ |
| 1444 | class_shift, hook) \ |
| 1445 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ |
| 1446 | vendor##device##hook, vendor, device, class, class_shift, hook) |
| 1447 | #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ |
| 1448 | class_shift, hook) \ |
| 1449 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ |
| 1450 | resume##vendor##device##hook, vendor, device, class, \ |
| 1451 | class_shift, hook) |
| 1452 | #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ |
| 1453 | class_shift, hook) \ |
| 1454 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ |
| 1455 | resume_early##vendor##device##hook, vendor, device, \ |
| 1456 | class, class_shift, hook) |
| 1457 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ |
| 1458 | class_shift, hook) \ |
| 1459 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ |
| 1460 | suspend##vendor##device##hook, vendor, device, class, \ |
| 1461 | class_shift, hook) |
| 1462 | |
| 1463 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ |
| 1464 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ |
| 1465 | vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook) |
| 1466 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ |
| 1467 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ |
| 1468 | vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook) |
| 1469 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ |
| 1470 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ |
| 1471 | vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook) |
| 1472 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ |
| 1473 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ |
| 1474 | vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook) |
| 1475 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
| 1476 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ |
| 1477 | resume##vendor##device##hook, vendor, device, \ |
| 1478 | PCI_ANY_ID, 0, hook) |
| 1479 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
| 1480 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ |
| 1481 | resume_early##vendor##device##hook, vendor, device, \ |
| 1482 | PCI_ANY_ID, 0, hook) |
| 1483 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ |
| 1484 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ |
| 1485 | suspend##vendor##device##hook, vendor, device, \ |
| 1486 | PCI_ANY_ID, 0, hook) |
| 1487 | |
| 1488 | #ifdef CONFIG_PCI_QUIRKS |
| 1489 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); |
| 1490 | #else |
| 1491 | static inline void pci_fixup_device(enum pci_fixup_pass pass, |
| 1492 | struct pci_dev *dev) {} |
| 1493 | #endif |
| 1494 | |
| 1495 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
| 1496 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
| 1497 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
| 1498 | int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); |
| 1499 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, |
| 1500 | const char *name); |
| 1501 | void pcim_iounmap_regions(struct pci_dev *pdev, int mask); |
| 1502 | |
| 1503 | extern int pci_pci_problems; |
| 1504 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
| 1505 | #define PCIPCI_TRITON 2 |
| 1506 | #define PCIPCI_NATOMA 4 |
| 1507 | #define PCIPCI_VIAETBF 8 |
| 1508 | #define PCIPCI_VSFX 16 |
| 1509 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
| 1510 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ |
| 1511 | |
| 1512 | extern unsigned long pci_cardbus_io_size; |
| 1513 | extern unsigned long pci_cardbus_mem_size; |
| 1514 | extern u8 __devinitdata pci_dfl_cache_line_size; |
| 1515 | extern u8 pci_cache_line_size; |
| 1516 | |
| 1517 | extern unsigned long pci_hotplug_io_size; |
| 1518 | extern unsigned long pci_hotplug_mem_size; |
| 1519 | |
| 1520 | /* Architecture specific versions may override these (weak) */ |
| 1521 | int pcibios_add_platform_entries(struct pci_dev *dev); |
| 1522 | void pcibios_disable_device(struct pci_dev *dev); |
| 1523 | void pcibios_set_master(struct pci_dev *dev); |
| 1524 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, |
| 1525 | enum pcie_reset_state state); |
| 1526 | |
| 1527 | #ifdef CONFIG_PCI_MMCONFIG |
| 1528 | extern void __init pci_mmcfg_early_init(void); |
| 1529 | extern void __init pci_mmcfg_late_init(void); |
| 1530 | #else |
| 1531 | static inline void pci_mmcfg_early_init(void) { } |
| 1532 | static inline void pci_mmcfg_late_init(void) { } |
| 1533 | #endif |
| 1534 | |
| 1535 | int pci_ext_cfg_avail(struct pci_dev *dev); |
| 1536 | |
| 1537 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); |
| 1538 | |
| 1539 | #ifdef CONFIG_PCI_IOV |
| 1540 | extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); |
| 1541 | extern void pci_disable_sriov(struct pci_dev *dev); |
| 1542 | extern irqreturn_t pci_sriov_migration(struct pci_dev *dev); |
| 1543 | extern int pci_num_vf(struct pci_dev *dev); |
| 1544 | #else |
| 1545 | static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) |
| 1546 | { |
| 1547 | return -ENODEV; |
| 1548 | } |
| 1549 | static inline void pci_disable_sriov(struct pci_dev *dev) |
| 1550 | { |
| 1551 | } |
| 1552 | static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev) |
| 1553 | { |
| 1554 | return IRQ_NONE; |
| 1555 | } |
| 1556 | static inline int pci_num_vf(struct pci_dev *dev) |
| 1557 | { |
| 1558 | return 0; |
| 1559 | } |
| 1560 | #endif |
| 1561 | |
| 1562 | #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) |
| 1563 | extern void pci_hp_create_module_link(struct pci_slot *pci_slot); |
| 1564 | extern void pci_hp_remove_module_link(struct pci_slot *pci_slot); |
| 1565 | #endif |
| 1566 | |
| 1567 | /** |
| 1568 | * pci_pcie_cap - get the saved PCIe capability offset |
| 1569 | * @dev: PCI device |
| 1570 | * |
| 1571 | * PCIe capability offset is calculated at PCI device initialization |
| 1572 | * time and saved in the data structure. This function returns saved |
| 1573 | * PCIe capability offset. Using this instead of pci_find_capability() |
| 1574 | * reduces unnecessary search in the PCI configuration space. If you |
| 1575 | * need to calculate PCIe capability offset from raw device for some |
| 1576 | * reasons, please use pci_find_capability() instead. |
| 1577 | */ |
| 1578 | static inline int pci_pcie_cap(struct pci_dev *dev) |
| 1579 | { |
| 1580 | return dev->pcie_cap; |
| 1581 | } |
| 1582 | |
| 1583 | /** |
| 1584 | * pci_is_pcie - check if the PCI device is PCI Express capable |
| 1585 | * @dev: PCI device |
| 1586 | * |
| 1587 | * Retrun true if the PCI device is PCI Express capable, false otherwise. |
| 1588 | */ |
| 1589 | static inline bool pci_is_pcie(struct pci_dev *dev) |
| 1590 | { |
| 1591 | return !!pci_pcie_cap(dev); |
| 1592 | } |
| 1593 | |
| 1594 | void pci_request_acs(void); |
| 1595 | |
| 1596 | |
| 1597 | #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ |
| 1598 | #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT) |
| 1599 | |
| 1600 | /* Large Resource Data Type Tag Item Names */ |
| 1601 | #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ |
| 1602 | #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ |
| 1603 | #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ |
| 1604 | |
| 1605 | #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) |
| 1606 | #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) |
| 1607 | #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) |
| 1608 | |
| 1609 | /* Small Resource Data Type Tag Item Names */ |
| 1610 | #define PCI_VPD_STIN_END 0x78 /* End */ |
| 1611 | |
| 1612 | #define PCI_VPD_SRDT_END PCI_VPD_STIN_END |
| 1613 | |
| 1614 | #define PCI_VPD_SRDT_TIN_MASK 0x78 |
| 1615 | #define PCI_VPD_SRDT_LEN_MASK 0x07 |
| 1616 | |
| 1617 | #define PCI_VPD_LRDT_TAG_SIZE 3 |
| 1618 | #define PCI_VPD_SRDT_TAG_SIZE 1 |
| 1619 | |
| 1620 | #define PCI_VPD_INFO_FLD_HDR_SIZE 3 |
| 1621 | |
| 1622 | #define PCI_VPD_RO_KEYWORD_PARTNO "PN" |
| 1623 | #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" |
| 1624 | #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" |
| 1625 | #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" |
| 1626 | |
| 1627 | /** |
| 1628 | * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length |
| 1629 | * @lrdt: Pointer to the beginning of the Large Resource Data Type tag |
| 1630 | * |
| 1631 | * Returns the extracted Large Resource Data Type length. |
| 1632 | */ |
| 1633 | static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) |
| 1634 | { |
| 1635 | return (u16)lrdt[1] + ((u16)lrdt[2] << 8); |
| 1636 | } |
| 1637 | |
| 1638 | /** |
| 1639 | * pci_vpd_srdt_size - Extracts the Small Resource Data Type length |
| 1640 | * @lrdt: Pointer to the beginning of the Small Resource Data Type tag |
| 1641 | * |
| 1642 | * Returns the extracted Small Resource Data Type length. |
| 1643 | */ |
| 1644 | static inline u8 pci_vpd_srdt_size(const u8 *srdt) |
| 1645 | { |
| 1646 | return (*srdt) & PCI_VPD_SRDT_LEN_MASK; |
| 1647 | } |
| 1648 | |
| 1649 | /** |
| 1650 | * pci_vpd_info_field_size - Extracts the information field length |
| 1651 | * @lrdt: Pointer to the beginning of an information field header |
| 1652 | * |
| 1653 | * Returns the extracted information field length. |
| 1654 | */ |
| 1655 | static inline u8 pci_vpd_info_field_size(const u8 *info_field) |
| 1656 | { |
| 1657 | return info_field[2]; |
| 1658 | } |
| 1659 | |
| 1660 | /** |
| 1661 | * pci_vpd_find_tag - Locates the Resource Data Type tag provided |
| 1662 | * @buf: Pointer to buffered vpd data |
| 1663 | * @off: The offset into the buffer at which to begin the search |
| 1664 | * @len: The length of the vpd buffer |
| 1665 | * @rdt: The Resource Data Type to search for |
| 1666 | * |
| 1667 | * Returns the index where the Resource Data Type was found or |
| 1668 | * -ENOENT otherwise. |
| 1669 | */ |
| 1670 | int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); |
| 1671 | |
| 1672 | /** |
| 1673 | * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD |
| 1674 | * @buf: Pointer to buffered vpd data |
| 1675 | * @off: The offset into the buffer at which to begin the search |
| 1676 | * @len: The length of the buffer area, relative to off, in which to search |
| 1677 | * @kw: The keyword to search for |
| 1678 | * |
| 1679 | * Returns the index where the information field keyword was found or |
| 1680 | * -ENOENT otherwise. |
| 1681 | */ |
| 1682 | int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, |
| 1683 | unsigned int len, const char *kw); |
| 1684 | |
| 1685 | /* PCI <-> OF binding helpers */ |
| 1686 | #ifdef CONFIG_OF |
| 1687 | struct device_node; |
| 1688 | extern void pci_set_of_node(struct pci_dev *dev); |
| 1689 | extern void pci_release_of_node(struct pci_dev *dev); |
| 1690 | extern void pci_set_bus_of_node(struct pci_bus *bus); |
| 1691 | extern void pci_release_bus_of_node(struct pci_bus *bus); |
| 1692 | |
| 1693 | /* Arch may override this (weak) */ |
| 1694 | extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus); |
| 1695 | |
| 1696 | static inline struct device_node * |
| 1697 | pci_device_to_OF_node(const struct pci_dev *pdev) |
| 1698 | { |
| 1699 | return pdev ? pdev->dev.of_node : NULL; |
| 1700 | } |
| 1701 | |
| 1702 | static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) |
| 1703 | { |
| 1704 | return bus ? bus->dev.of_node : NULL; |
| 1705 | } |
| 1706 | |
| 1707 | #else /* CONFIG_OF */ |
| 1708 | static inline void pci_set_of_node(struct pci_dev *dev) { } |
| 1709 | static inline void pci_release_of_node(struct pci_dev *dev) { } |
| 1710 | static inline void pci_set_bus_of_node(struct pci_bus *bus) { } |
| 1711 | static inline void pci_release_bus_of_node(struct pci_bus *bus) { } |
| 1712 | #endif /* CONFIG_OF */ |
| 1713 | |
| 1714 | #ifdef CONFIG_EEH |
| 1715 | static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) |
| 1716 | { |
| 1717 | return pdev->dev.archdata.edev; |
| 1718 | } |
| 1719 | #endif |
| 1720 | |
| 1721 | /** |
| 1722 | * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device |
| 1723 | * @pdev: the PCI device |
| 1724 | * |
| 1725 | * if the device is PCIE, return NULL |
| 1726 | * if the device isn't connected to a PCIe bridge (that is its parent is a |
| 1727 | * legacy PCI bridge and the bridge is directly connected to bus 0), return its |
| 1728 | * parent |
| 1729 | */ |
| 1730 | struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev); |
| 1731 | |
| 1732 | #endif /* __KERNEL__ */ |
| 1733 | #endif /* LINUX_PCI_H */ |