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12006-05-25 Richard Sandiford <richard@codesourcery.com>
2
3 * m68k.h (mcf_mask): Define.
4
52006-05-05 Thiemo Seufer <ths@mips.com>
6 David Ung <davidu@mips.com>
7
8 * mips.h (enum): Add macro M_CACHE_AB.
9
102006-05-04 Thiemo Seufer <ths@mips.com>
11 Nigel Stephens <nigel@mips.com>
12 David Ung <davidu@mips.com>
13
14 * mips.h: Add INSN_SMARTMIPS define.
15
162006-04-30 Thiemo Seufer <ths@mips.com>
17 David Ung <davidu@mips.com>
18
19 * mips.h: Defines udi bits and masks. Add description of
20 characters which may appear in the args field of udi
21 instructions.
22
232006-04-26 Thiemo Seufer <ths@networkno.de>
24
25 * mips.h: Improve comments describing the bitfield instruction
26 fields.
27
282006-04-26 Julian Brown <julian@codesourcery.com>
29
30 * arm.h (FPU_VFP_EXT_V3): Define constant.
31 (FPU_NEON_EXT_V1): Likewise.
32 (FPU_VFP_HARD): Update.
33 (FPU_VFP_V3): Define macro.
34 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
35
362006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
37
38 * avr.h (AVR_ISA_PWMx): New.
39
402006-03-28 Nathan Sidwell <nathan@codesourcery.com>
41
42 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
43 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
44 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
45 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
46 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
47
482006-03-10 Paul Brook <paul@codesourcery.com>
49
50 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
51
522006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
53
54 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
55 first. Correct mask of bb "B" opcode.
56
572006-02-27 H.J. Lu <hongjiu.lu@intel.com>
58
59 * i386.h (i386_optab): Support Intel Merom New Instructions.
60
612006-02-24 Paul Brook <paul@codesourcery.com>
62
63 * arm.h: Add V7 feature bits.
64
652006-02-23 H.J. Lu <hongjiu.lu@intel.com>
66
67 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
68
692006-01-31 Paul Brook <paul@codesourcery.com>
70 Richard Earnshaw <rearnsha@arm.com>
71
72 * arm.h: Use ARM_CPU_FEATURE.
73 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
74 (arm_feature_set): Change to a structure.
75 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
76 ARM_FEATURE): New macros.
77
782005-12-07 Hans-Peter Nilsson <hp@axis.com>
79
80 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
81 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
82 (ADD_PC_INCR_OPCODE): Don't define.
83
842005-12-06 H.J. Lu <hongjiu.lu@intel.com>
85
86 PR gas/1874
87 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
88
892005-11-14 David Ung <davidu@mips.com>
90
91 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
92 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
93 save/restore encoding of the args field.
94
952005-10-28 Dave Brolley <brolley@redhat.com>
96
97 Contribute the following changes:
98 2005-02-16 Dave Brolley <brolley@redhat.com>
99
100 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
101 cgen_isa_mask_* to cgen_bitset_*.
102 * cgen.h: Likewise.
103
104 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
105
106 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
107 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
108 (CGEN_CPU_TABLE): Make isas a ponter.
109
110 2003-09-29 Dave Brolley <brolley@redhat.com>
111
112 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
113 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
114 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
115
116 2002-12-13 Dave Brolley <brolley@redhat.com>
117
118 * cgen.h (symcat.h): #include it.
119 (cgen-bitset.h): #include it.
120 (CGEN_ATTR_VALUE_TYPE): Now a union.
121 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
122 (CGEN_ATTR_ENTRY): 'value' now unsigned.
123 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
124 * cgen-bitset.h: New file.
125
1262005-09-30 Catherine Moore <clm@cm00re.com>
127
128 * bfin.h: New file.
129
1302005-10-24 Jan Beulich <jbeulich@novell.com>
131
132 * ia64.h (enum ia64_opnd): Move memory operand out of set of
133 indirect operands.
134
1352005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
136
137 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
138 Add FLAG_STRICT to pa10 ftest opcode.
139
1402005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
141
142 * hppa.h (pa_opcodes): Remove lha entries.
143
1442005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
145
146 * hppa.h (FLAG_STRICT): Revise comment.
147 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
148 before corresponding pa11 opcodes. Add strict pa10 register-immediate
149 entries for "fdc".
150
1512005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
152
153 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
154
1552005-09-06 Chao-ying Fu <fu@mips.com>
156
157 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
158 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
159 define.
160 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
161 (INSN_ASE_MASK): Update to include INSN_MT.
162 (INSN_MT): New define for MT ASE.
163
1642005-08-25 Chao-ying Fu <fu@mips.com>
165
166 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
167 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
168 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
169 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
170 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
171 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
172 instructions.
173 (INSN_DSP): New define for DSP ASE.
174
1752005-08-18 Alan Modra <amodra@bigpond.net.au>
176
177 * a29k.h: Delete.
178
1792005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
180
181 * ppc.h (PPC_OPCODE_E300): Define.
182
1832005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
184
185 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
186
1872005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
188
189 PR gas/336
190 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
191 and pitlb.
192
1932005-07-27 Jan Beulich <jbeulich@novell.com>
194
195 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
196 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
197 Add movq-s as 64-bit variants of movd-s.
198
1992005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
200
201 * hppa.h: Fix punctuation in comment.
202
203 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
204 implicit space-register addressing. Set space-register bits on opcodes
205 using implicit space-register addressing. Add various missing pa20
206 long-immediate opcodes. Remove various opcodes using implicit 3-bit
207 space-register addressing. Use "fE" instead of "fe" in various
208 fstw opcodes.
209
2102005-07-18 Jan Beulich <jbeulich@novell.com>
211
212 * i386.h (i386_optab): Operands of aam and aad are unsigned.
213
2142007-07-15 H.J. Lu <hongjiu.lu@intel.com>
215
216 * i386.h (i386_optab): Support Intel VMX Instructions.
217
2182005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
219
220 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
221
2222005-07-05 Jan Beulich <jbeulich@novell.com>
223
224 * i386.h (i386_optab): Add new insns.
225
2262005-07-01 Nick Clifton <nickc@redhat.com>
227
228 * sparc.h: Add typedefs to structure declarations.
229
2302005-06-20 H.J. Lu <hongjiu.lu@intel.com>
231
232 PR 1013
233 * i386.h (i386_optab): Update comments for 64bit addressing on
234 mov. Allow 64bit addressing for mov and movq.
235
2362005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
237
238 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
239 respectively, in various floating-point load and store patterns.
240
2412005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
242
243 * hppa.h (FLAG_STRICT): Correct comment.
244 (pa_opcodes): Update load and store entries to allow both PA 1.X and
245 PA 2.0 mneumonics when equivalent. Entries with cache control
246 completers now require PA 1.1. Adjust whitespace.
247
2482005-05-19 Anton Blanchard <anton@samba.org>
249
250 * ppc.h (PPC_OPCODE_POWER5): Define.
251
2522005-05-10 Nick Clifton <nickc@redhat.com>
253
254 * Update the address and phone number of the FSF organization in
255 the GPL notices in the following files:
256 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
257 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
258 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
259 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
260 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
261 tic54x.h, tic80.h, v850.h, vax.h
262
2632005-05-09 Jan Beulich <jbeulich@novell.com>
264
265 * i386.h (i386_optab): Add ht and hnt.
266
2672005-04-18 Mark Kettenis <kettenis@gnu.org>
268
269 * i386.h: Insert hyphens into selected VIA PadLock extensions.
270 Add xcrypt-ctr. Provide aliases without hyphens.
271
2722005-04-13 H.J. Lu <hongjiu.lu@intel.com>
273
274 Moved from ../ChangeLog
275
276 2005-04-12 Paul Brook <paul@codesourcery.com>
277 * m88k.h: Rename psr macros to avoid conflicts.
278
279 2005-03-12 Zack Weinberg <zack@codesourcery.com>
280 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
281 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
282 and ARM_ARCH_V6ZKT2.
283
284 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
285 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
286 Remove redundant instruction types.
287 (struct argument): X_op - new field.
288 (struct cst4_entry): Remove.
289 (no_op_insn): Declare.
290
291 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
292 * crx.h (enum argtype): Rename types, remove unused types.
293
294 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
295 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
296 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
297 (enum operand_type): Rearrange operands, edit comments.
298 replace us<N> with ui<N> for unsigned immediate.
299 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
300 displacements (respectively).
301 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
302 (instruction type): Add NO_TYPE_INS.
303 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
304 (operand_entry): New field - 'flags'.
305 (operand flags): New.
306
307 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
308 * crx.h (operand_type): Remove redundant types i3, i4,
309 i5, i8, i12.
310 Add new unsigned immediate types us3, us4, us5, us16.
311
3122005-04-12 Mark Kettenis <kettenis@gnu.org>
313
314 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
315 adjust them accordingly.
316
3172005-04-01 Jan Beulich <jbeulich@novell.com>
318
319 * i386.h (i386_optab): Add rdtscp.
320
3212005-03-29 H.J. Lu <hongjiu.lu@intel.com>
322
323 * i386.h (i386_optab): Don't allow the `l' suffix for moving
324 between memory and segment register. Allow movq for moving between
325 general-purpose register and segment register.
326
3272005-02-09 Jan Beulich <jbeulich@novell.com>
328
329 PR gas/707
330 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
331 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
332 fnstsw.
333
3342006-02-07 Nathan Sidwell <nathan@codesourcery.com>
335
336 * m68k.h (m68008, m68ec030, m68882): Remove.
337 (m68k_mask): New.
338 (cpu_m68k, cpu_cf): New.
339 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
340 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
341
3422005-01-25 Alexandre Oliva <aoliva@redhat.com>
343
344 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
345 * cgen.h (enum cgen_parse_operand_type): Add
346 CGEN_PARSE_OPERAND_SYMBOLIC.
347
3482005-01-21 Fred Fish <fnf@specifixinc.com>
349
350 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
351 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
352 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
353
3542005-01-19 Fred Fish <fnf@specifixinc.com>
355
356 * mips.h (struct mips_opcode): Add new pinfo2 member.
357 (INSN_ALIAS): New define for opcode table entries that are
358 specific instances of another entry, such as 'move' for an 'or'
359 with a zero operand.
360 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
361 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
362
3632004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
364
365 * mips.h (CPU_RM9000): Define.
366 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
367
3682004-11-25 Jan Beulich <jbeulich@novell.com>
369
370 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
371 to/from test registers are illegal in 64-bit mode. Add missing
372 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
373 (previously one had to explicitly encode a rex64 prefix). Re-enable
374 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
375 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
376
3772004-11-23 Jan Beulich <jbeulich@novell.com>
378
379 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
380 available only with SSE2. Change the MMX additions introduced by SSE
381 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
382 instructions by their now designated identifier (since combining i686
383 and 3DNow! does not really imply 3DNow!A).
384
3852004-11-19 Alan Modra <amodra@bigpond.net.au>
386
387 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
388 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
389
3902004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
391 Vineet Sharma <vineets@noida.hcltech.com>
392
393 * maxq.h: New file: Disassembly information for the maxq port.
394
3952004-11-05 H.J. Lu <hongjiu.lu@intel.com>
396
397 * i386.h (i386_optab): Put back "movzb".
398
3992004-11-04 Hans-Peter Nilsson <hp@axis.com>
400
401 * cris.h (enum cris_insn_version_usage): Tweak formatting and
402 comments. Remove member cris_ver_sim. Add members
403 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
404 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
405 (struct cris_support_reg, struct cris_cond15): New types.
406 (cris_conds15): Declare.
407 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
408 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
409 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
410 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
411 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
412 SIZE_FIELD_UNSIGNED.
413
4142004-11-04 Jan Beulich <jbeulich@novell.com>
415
416 * i386.h (sldx_Suf): Remove.
417 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
418 (q_FP): Define, implying no REX64.
419 (x_FP, sl_FP): Imply FloatMF.
420 (i386_optab): Split reg and mem forms of moving from segment registers
421 so that the memory forms can ignore the 16-/32-bit operand size
422 distinction. Adjust a few others for Intel mode. Remove *FP uses from
423 all non-floating-point instructions. Unite 32- and 64-bit forms of
424 movsx, movzx, and movd. Adjust floating point operations for the above
425 changes to the *FP macros. Add DefaultSize to floating point control
426 insns operating on larger memory ranges. Remove left over comments
427 hinting at certain insns being Intel-syntax ones where the ones
428 actually meant are already gone.
429
4302004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
431
432 * crx.h: Add COPS_REG_INS - Coprocessor Special register
433 instruction type.
434
4352004-09-30 Paul Brook <paul@codesourcery.com>
436
437 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
438 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
439
4402004-09-11 Theodore A. Roth <troth@openavr.org>
441
442 * avr.h: Add support for
443 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
444
4452004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
446
447 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
448
4492004-08-24 Dmitry Diky <diwil@spec.ru>
450
451 * msp430.h (msp430_opc): Add new instructions.
452 (msp430_rcodes): Declare new instructions.
453 (msp430_hcodes): Likewise..
454
4552004-08-13 Nick Clifton <nickc@redhat.com>
456
457 PR/301
458 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
459 processors.
460
4612004-08-30 Michal Ludvig <mludvig@suse.cz>
462
463 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
464
4652004-07-22 H.J. Lu <hongjiu.lu@intel.com>
466
467 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
468
4692004-07-21 Jan Beulich <jbeulich@novell.com>
470
471 * i386.h: Adjust instruction descriptions to better match the
472 specification.
473
4742004-07-16 Richard Earnshaw <rearnsha@arm.com>
475
476 * arm.h: Remove all old content. Replace with architecture defines
477 from gas/config/tc-arm.c.
478
4792004-07-09 Andreas Schwab <schwab@suse.de>
480
481 * m68k.h: Fix comment.
482
4832004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
484
485 * crx.h: New file.
486
4872004-06-24 Alan Modra <amodra@bigpond.net.au>
488
489 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
490
4912004-05-24 Peter Barada <peter@the-baradas.com>
492
493 * m68k.h: Add 'size' to m68k_opcode.
494
4952004-05-05 Peter Barada <peter@the-baradas.com>
496
497 * m68k.h: Switch from ColdFire chip name to core variant.
498
4992004-04-22 Peter Barada <peter@the-baradas.com>
500
501 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
502 descriptions for new EMAC cases.
503 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
504 handle Motorola MAC syntax.
505 Allow disassembly of ColdFire V4e object files.
506
5072004-03-16 Alan Modra <amodra@bigpond.net.au>
508
509 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
510
5112004-03-12 Jakub Jelinek <jakub@redhat.com>
512
513 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
514
5152004-03-12 Michal Ludvig <mludvig@suse.cz>
516
517 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
518
5192004-03-12 Michal Ludvig <mludvig@suse.cz>
520
521 * i386.h (i386_optab): Added xstore/xcrypt insns.
522
5232004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
524
525 * h8300.h (32bit ldc/stc): Add relaxing support.
526
5272004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
528
529 * h8300.h (BITOP): Pass MEMRELAX flag.
530
5312004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
532
533 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
534 except for the H8S.
535
536For older changes see ChangeLog-9103
537\f
538Local Variables:
539mode: change-log
540left-margin: 8
541fill-column: 74
542version-control: never
543End:
GDB Binutils - Deliverables
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