projects / deliverable / binutils-gdb.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
[AArch64] Add ARMv8.2 command line option and feature flag.
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
... / ...
CommitLineData
12015-11-19 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64.h (AARCH64_FEATURE_V8_2): New.
4 (AARCH64_ARCH_V8_2): New.
5
62015-11-11 Alan Modra <amodra@gmail.com>
7 Peter Bergner <bergner@vnet.ibm.com>
8
9 * ppc.h (PPC_OPCODE_POWER9): New define.
10 (PPC_OPCODE_VSX3): Likewise.
11
122015-11-02 Nick Clifton <nickc@redhat.com>
13
14 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
15
162015-11-02 Nick Clifton <nickc@redhat.com>
17
18 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
19
202015-10-28 Yao Qi <yao.qi@linaro.org>
21
22 * aarch64.h (aarch64_decode_insn): Update declaration.
23
242015-10-07 Yao Qi <yao.qi@linaro.org>
25
26 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
27 <name>: New field.
28
292015-10-07 Yao Qi <yao.qi@linaro.org>
30
31 * aarch64.h [__cplusplus]: Wrap in extern "C".
32
332015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
34 Cupertino Miranda <cmiranda@synopsys.com>
35
36 * arc-func.h: New file.
37 * arc.h: Likewise.
38
392015-10-02 Yao Qi <yao.qi@linaro.org>
40
41 * aarch64.h (aarch64_zero_register_p): Move the declaration
42 to column one.
43
442015-10-02 Yao Qi <yao.qi@linaro.org>
45
46 * aarch64.h (aarch64_decode_insn): Declare it.
47
482015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
49
50 * s390.h (S390_INSTR_FLAG_HTM): New flag.
51 (S390_INSTR_FLAG_VX): New flag.
52 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
53
542015-09-23 Nick Clifton <nickc@redhat.com>
55
56 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
57 shifting.
58
592015-09-22 Nick Clifton <nickc@redhat.com>
60
61 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
62
632015-09-09 Daniel Santos <daniel.santos@pobox.com>
64
65 * visium.h (gen_reg_table): Make static.
66 (fp_reg_table): Likewise.
67 (cc_table): Likewise.
68
692015-07-20 Matthew Wahab <matthew.wahab@arm.com>
70
71 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
72 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
73 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
74 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
75
762015-07-03 Alan Modra <amodra@gmail.com>
77
78 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
79
802015-07-01 Sandra Loosemore <sandra@codesourcery.com>
81 Cesar Philippidis <cesar@codesourcery.com>
82
83 * nios2.h (enum iw_format_type): Add R2 formats.
84 (enum overflow_type): Add signed_immed12_overflow and
85 enumeration_overflow for R2.
86 (struct nios2_opcode): Document new argument letters for R2.
87 (REG_3BIT, REG_LDWM, REG_POP): Define.
88 (includes): Include nios2r2.h.
89 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
90 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
91 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
92 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
93 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
94 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
95 Declare.
96 * nios2r2.h: New file.
97
982015-06-19 Peter Bergner <bergner@vnet.ibm.com>
99
100 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
101 (ppc_optional_operand_value): New inline function.
102
1032015-06-04 Matthew Wahab <matthew.wahab@arm.com>
104
105 * aarch64.h (AARCH64_V8_1): New.
106
1072015-06-03 Matthew Wahab <matthew.wahab@arm.com>
108
109 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
110 (ARM_ARCH_V8_1A): New.
111 (ARM_ARCH_V8_1A_FP): New.
112 (ARM_ARCH_V8_1A_SIMD): New.
113 (ARM_ARCH_V8_1A_CRYPTOV1): New.
114 (ARM_FEATURE_CORE): New.
115
1162015-06-02 Matthew Wahab <matthew.wahab@arm.com>
117
118 * arm.h (ARM_EXT2_PAN): New.
119 (ARM_FEATURE_CORE_HIGH): New.
120
1212015-06-02 Matthew Wahab <matthew.wahab@arm.com>
122
123 * arm.h (ARM_FEATURE_ALL): New.
124
1252015-06-02 Matthew Wahab <matthew.wahab@arm.com>
126
127 * aarch64.h (AARCH64_FEATURE_RDMA): New.
128
1292015-06-02 Matthew Wahab <matthew.wahab@arm.com>
130
131 * aarch64.h (AARCH64_FEATURE_LOR): New.
132
1332015-06-01 Matthew Wahab <matthew.wahab@arm.com>
134
135 * aarch64.h (AARCH64_FEATURE_PAN): New.
136 (aarch64_sys_reg_supported_p): Declare.
137 (aarch64_pstatefield_supported_p): Declare.
138
1392015-04-30 DJ Delorie <dj@redhat.com>
140
141 * rl78.h (RL78_Dis_Isa): New.
142 (rl78_decode_opcode): Add ISA parameter.
143
1442015-03-24 Terry Guo <terry.guo@arm.com>
145
146 * arm.h (arm_feature_set): Extended to provide more available bits.
147 (ARM_ANY): Updated to follow above new definition.
148 (ARM_CPU_HAS_FEATURE): Likewise.
149 (ARM_CPU_IS_ANY): Likewise.
150 (ARM_MERGE_FEATURE_SETS): Likewise.
151 (ARM_CLEAR_FEATURE): Likewise.
152 (ARM_FEATURE): Likewise.
153 (ARM_FEATURE_COPY): New macro.
154 (ARM_FEATURE_EQUAL): Likewise.
155 (ARM_FEATURE_ZERO): Likewise.
156 (ARM_FEATURE_CORE_EQUAL): Likewise.
157 (ARM_FEATURE_LOW): Likewise.
158 (ARM_FEATURE_CORE_LOW): Likewise.
159 (ARM_FEATURE_CORE_COPROC): Likewise.
160
1612015-02-19 Pedro Alves <palves@redhat.com>
162
163 * cgen.h [__cplusplus]: Wrap in extern "C".
164 * msp430-decode.h [__cplusplus]: Likewise.
165 * nios2.h [__cplusplus]: Likewise.
166 * rl78.h [__cplusplus]: Likewise.
167 * rx.h [__cplusplus]: Likewise.
168 * tilegx.h [__cplusplus]: Likewise.
169
1702015-01-28 James Bowman <james.bowman@ftdichip.com>
171
172 * ft32.h: New file.
173
1742015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
175
176 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
177
1782015-01-01 Alan Modra <amodra@gmail.com>
179
180 Update year range in copyright notice of all files.
181
1822014-12-27 Anthony Green <green@moxielogic.com>
183
184 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
185 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
186
1872014-12-06 Eric Botcazou <ebotcazou@adacore.com>
188
189 * visium.h: New file.
190
1912014-11-28 Sandra Loosemore <sandra@codesourcery.com>
192
193 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
194 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
195 (NIOS2_INSN_OPTARG): Renumber.
196
1972014-11-06 Sandra Loosemore <sandra@codesourcery.com>
198
199 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
200 declaration. Fix obsolete comment.
201
2022014-10-23 Sandra Loosemore <sandra@codesourcery.com>
203
204 * nios2.h (enum iw_format_type): New.
205 (struct nios2_opcode): Update comments. Add size and format fields.
206 (NIOS2_INSN_OPTARG): New.
207 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
208 (struct nios2_reg): Add regtype field.
209 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
210 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
211 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
212 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
213 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
214 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
215 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
216 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
217 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
218 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
219 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
220 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
221 (OP_MASK_OP, OP_SH_OP): Delete.
222 (OP_MASK_IOP, OP_SH_IOP): Delete.
223 (OP_MASK_IRD, OP_SH_IRD): Delete.
224 (OP_MASK_IRT, OP_SH_IRT): Delete.
225 (OP_MASK_IRS, OP_SH_IRS): Delete.
226 (OP_MASK_ROP, OP_SH_ROP): Delete.
227 (OP_MASK_RRD, OP_SH_RRD): Delete.
228 (OP_MASK_RRT, OP_SH_RRT): Delete.
229 (OP_MASK_RRS, OP_SH_RRS): Delete.
230 (OP_MASK_JOP, OP_SH_JOP): Delete.
231 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
232 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
233 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
234 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
235 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
236 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
237 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
238 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
239 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
240 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
241 (OP_MASK_<insn>, OP_MASK): Delete.
242 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
243 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
244 Include nios2r1.h to define new instruction opcode constants
245 and accessors.
246 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
247 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
248 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
249 (NUMOPCODES, NUMREGISTERS): Delete.
250 * nios2r1.h: New file.
251
2522014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
253
254 * sparc.h (HWCAP2_VIS3B): Documentation improved.
255
2562014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
257
258 * sparc.h (sparc_opcode): new field `hwcaps2'.
259 (HWCAP2_FJATHPLUS): New define.
260 (HWCAP2_VIS3B): Likewise.
261 (HWCAP2_ADP): Likewise.
262 (HWCAP2_SPARC5): Likewise.
263 (HWCAP2_MWAIT): Likewise.
264 (HWCAP2_XMPMUL): Likewise.
265 (HWCAP2_XMONT): Likewise.
266 (HWCAP2_NSEC): Likewise.
267 (HWCAP2_FJATHHPC): Likewise.
268 (HWCAP2_FJDES): Likewise.
269 (HWCAP2_FJAES): Likewise.
270 Document the new operand kind `{', corresponding to the mcdper
271 ancillary state register.
272 Document the new operand kind }, which represents frsd floating
273 point registers (double precision) which must be the same than
274 frs1 in its containing instruction.
275
2762014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
277
278 * nds32.h: Add new opcode declaration.
279
2802014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
281 Matthew Fortune <matthew.fortune@imgtec.com>
282
283 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
284 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
285 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
286 +I, +O, +R, +:, +\, +", +;
287 (mips_check_prev_operand): New struct.
288 (INSN2_FORBIDDEN_SLOT): New define.
289 (INSN_ISA32R6): New define.
290 (INSN_ISA64R6): New define.
291 (INSN_UPTO32R6): New define.
292 (INSN_UPTO64R6): New define.
293 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
294 (ISA_MIPS32R6): New define.
295 (ISA_MIPS64R6): New define.
296 (CPU_MIPS32R6): New define.
297 (CPU_MIPS64R6): New define.
298 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
299
3002014-09-03 Jiong Wang <jiong.wang@arm.com>
301
302 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
303 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
304 (aarch64_insn_class): Add lse_atomic.
305 (F_LSE_SZ): New field added.
306 (opcode_has_special_coder): Recognize F_LSE_SZ.
307
3082014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
309
310 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
311 over to `+J'.
312
3132014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
314
315 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
316 (INSN_LOAD_COPROC): New define.
317 (INSN_COPROC_MOVE_DELAY): Rename to...
318 (INSN_COPROC_MOVE): New define.
319
3202014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
321 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
322 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
323 Soundararajan <Sounderarajan.D@atmel.com>
324
325 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
326 (AVR_ISA_2xxxa): Define ISA without LPM.
327 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
328 Add doc for contraint used in 16 bit lds/sts.
329 Adjust ISA group for icall, ijmp, pop and push.
330 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
331
3322014-05-19 Nick Clifton <nickc@redhat.com>
333
334 * msp430.h (struct msp430_operand_s): Add vshift field.
335
3362014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
337
338 * mips.h (INSN_ISA_MASK): Updated.
339 (INSN_ISA32R3): New define.
340 (INSN_ISA32R5): New define.
341 (INSN_ISA64R3): New define.
342 (INSN_ISA64R5): New define.
343 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
344 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
345 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
346 mips64r5.
347 (INSN_UPTO32R3): New define.
348 (INSN_UPTO32R5): New define.
349 (INSN_UPTO64R3): New define.
350 (INSN_UPTO64R5): New define.
351 (ISA_MIPS32R3): New define.
352 (ISA_MIPS32R5): New define.
353 (ISA_MIPS64R3): New define.
354 (ISA_MIPS64R5): New define.
355 (CPU_MIPS32R3): New define.
356 (CPU_MIPS32R5): New define.
357 (CPU_MIPS64R3): New define.
358 (CPU_MIPS64R5): New define.
359
3602014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
361
362 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
363
3642014-04-22 Christian Svensson <blue@cmd.nu>
365
366 * or32.h: Delete.
367
3682014-03-05 Alan Modra <amodra@gmail.com>
369
370 Update copyright years.
371
3722013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
373
374 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
375 microMIPS.
376
3772013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
378 Wei-Cheng Wang <cole945@gmail.com>
379
380 * nds32.h: New file for Andes NDS32.
381
3822013-12-07 Mike Frysinger <vapier@gentoo.org>
383
384 * bfin.h: Remove +x file mode.
385
3862013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
387
388 * aarch64.h (aarch64_pstatefields): Change element type to
389 aarch64_sys_reg.
390
3912013-11-18 Renlin Li <Renlin.Li@arm.com>
392
393 * arm.h (ARM_AEXT_V7VE): New define.
394 (ARM_ARCH_V7VE): New define.
395 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
396
3972013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
398
399 Revert
400
401 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
402
403 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
404 (aarch64_sys_reg_writeonly_p): Ditto.
405
4062013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
407
408 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
409 (aarch64_sys_reg_writeonly_p): Ditto.
410
4112013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
412
413 * aarch64.h (aarch64_sys_reg): New typedef.
414 (aarch64_sys_regs): Change to define with the new type.
415 (aarch64_sys_reg_deprecated_p): Declare.
416
4172013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
418
419 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
420 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
421
4222013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
423
424 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
425 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
426 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
427 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
428 For MIPS, update extension character sequences after +.
429 (ASE_MSA): New define.
430 (ASE_MSA64): New define.
431 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
432 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
433 For microMIPS, update extension character sequences after +.
434
4352013-08-23 Yuri Chornoivan <yurchor@ukr.net>
436
437 PR binutils/15834
438 * i960.h: Fix typos.
439
4402013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
441
442 * mips.h: Remove references to "+I" and imm2_expr.
443
4442013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
445
446 * mips.h (M_DEXT, M_DINS): Delete.
447
4482013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
449
450 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
451 (mips_optional_operand_p): New function.
452
4532013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
454 Richard Sandiford <rdsandiford@googlemail.com>
455
456 * mips.h: Document new VU0 operand characters.
457 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
458 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
459 (OP_REG_R5900_ACC): New mips_reg_operand_types.
460 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
461 (mips_vu0_channel_mask): Declare.
462
4632013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
464
465 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
466 (mips_int_operand_min, mips_int_operand_max): New functions.
467 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
468
4692013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
470
471 * mips.h (mips_decode_reg_operand): New function.
472 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
473 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
474 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
475 New macros.
476 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
477 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
478 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
479 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
480 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
481 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
482 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
483 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
484 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
485 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
486 macros to cover the gaps.
487 (INSN2_MOD_SP): Replace with...
488 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
489 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
490 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
491 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
492 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
493 Delete.
494
4952013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
496
497 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
498 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
499 (MIPS16_INSN_COND_BRANCH): Delete.
500
5012013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
502 Kirill Yukhin <kirill.yukhin@intel.com>
503 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
504
505 * i386.h (BND_PREFIX_OPCODE): New.
506
5072013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
508
509 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
510 OP_SAVE_RESTORE_LIST.
511 (decode_mips16_operand): Declare.
512
5132013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
514
515 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
516 (mips_operand, mips_int_operand, mips_mapped_int_operand)
517 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
518 (mips_pcrel_operand): New structures.
519 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
520 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
521 (decode_mips_operand, decode_micromips_operand): Declare.
522
5232013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
524
525 * mips.h: Document MIPS16 "I" opcode.
526
5272013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
528
529 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
530 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
531 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
532 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
533 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
534 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
535 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
536 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
537 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
538 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
539 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
540 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
541 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
542 Rename to...
543 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
544 (M_USD_AB): ...these.
545
5462013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
547
548 * mips.h: Remove documentation of "[" and "]". Update documentation
549 of "k" and the MDMX formats.
550
5512013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
552
553 * mips.h: Update documentation of "+s" and "+S".
554
5552013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
556
557 * mips.h: Document "+i".
558
5592013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
560
561 * mips.h: Remove "mi" documentation. Update "mh" documentation.
562 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
563 Delete.
564 (INSN2_WRITE_GPR_MHI): Rename to...
565 (INSN2_WRITE_GPR_MH): ...this.
566
5672013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
568
569 * mips.h: Remove documentation of "+D" and "+T".
570
5712013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
572
573 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
574 Use "source" rather than "destination" for microMIPS "G".
575
5762013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
577
578 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
579 values.
580
5812013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
582
583 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
584
5852013-06-17 Catherine Moore <clm@codesourcery.com>
586 Maciej W. Rozycki <macro@codesourcery.com>
587 Chao-Ying Fu <fu@mips.com>
588
589 * mips.h (OP_SH_EVAOFFSET): Define.
590 (OP_MASK_EVAOFFSET): Define.
591 (INSN_ASE_MASK): Delete.
592 (ASE_EVA): Define.
593 (M_CACHEE_AB, M_CACHEE_OB): New.
594 (M_LBE_OB, M_LBE_AB): New.
595 (M_LBUE_OB, M_LBUE_AB): New.
596 (M_LHE_OB, M_LHE_AB): New.
597 (M_LHUE_OB, M_LHUE_AB): New.
598 (M_LLE_AB, M_LLE_OB): New.
599 (M_LWE_OB, M_LWE_AB): New.
600 (M_LWLE_AB, M_LWLE_OB): New.
601 (M_LWRE_AB, M_LWRE_OB): New.
602 (M_PREFE_AB, M_PREFE_OB): New.
603 (M_SCE_AB, M_SCE_OB): New.
604 (M_SBE_OB, M_SBE_AB): New.
605 (M_SHE_OB, M_SHE_AB): New.
606 (M_SWE_OB, M_SWE_AB): New.
607 (M_SWLE_AB, M_SWLE_OB): New.
608 (M_SWRE_AB, M_SWRE_OB): New.
609 (MICROMIPSOP_SH_EVAOFFSET): Define.
610 (MICROMIPSOP_MASK_EVAOFFSET): Define.
611
6122013-06-12 Sandra Loosemore <sandra@codesourcery.com>
613
614 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
615
6162013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
617
618 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
619
6202013-05-09 Andrew Pinski <apinski@cavium.com>
621
622 * mips.h (OP_MASK_CODE10): Correct definition.
623 (OP_SH_CODE10): Likewise.
624 Add a comment that "+J" is used now for OP_*CODE10.
625 (INSN_ASE_MASK): Update.
626 (INSN_VIRT): New macro.
627 (INSN_VIRT64): New macro
628
6292013-05-02 Nick Clifton <nickc@redhat.com>
630
631 * msp430.h: Add patterns for MSP430X instructions.
632
6332013-04-06 David S. Miller <davem@davemloft.net>
634
635 * sparc.h (F_PREFERRED): Define.
636 (F_PREF_ALIAS): Define.
637
6382013-04-03 Nick Clifton <nickc@redhat.com>
639
640 * v850.h (V850_INVERSE_PCREL): Define.
641
6422013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
643
644 PR binutils/15068
645 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
646
6472013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
648
649 PR binutils/15068
650 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
651 Add 16-bit opcodes.
652 * tic6xc-opcode-table.h: Add 16-bit insns.
653 * tic6x.h: Add support for 16-bit insns.
654
6552013-03-21 Michael Schewe <michael.schewe@gmx.net>
656
657 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
658 and mov.b/w/l Rs,@(d:32,ERd).
659
6602013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
661
662 PR gas/15082
663 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
664 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
665 tic6x_operand_xregpair operand coding type.
666 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
667 opcode field, usu ORXREGD1324 for the src2 operand and remove the
668 TIC6X_FLAG_NO_CROSS.
669
6702013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
671
672 PR gas/15095
673 * tic6x.h (enum tic6x_coding_method): Add
674 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
675 separately the msb and lsb of a register pair. This is needed to
676 encode the opcodes in the same way as TI assembler does.
677 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
678 and rsqrdp opcodes to use the new field coding types.
679
6802013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
681
682 * arm.h (CRC_EXT_ARMV8): New constant.
683 (ARCH_CRC_ARMV8): New macro.
684
6852013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
686
687 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
688
6892013-02-06 Sandra Loosemore <sandra@codesourcery.com>
690 Andrew Jenner <andrew@codesourcery.com>
691
692 Based on patches from Altera Corporation.
693
694 * nios2.h: New file.
695
6962013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
697
698 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
699
7002013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
701
702 PR gas/15069
703 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
704
7052013-01-24 Nick Clifton <nickc@redhat.com>
706
707 * v850.h: Add e3v5 support.
708
7092013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
710
711 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
712
7132013-01-10 Peter Bergner <bergner@vnet.ibm.com>
714
715 * ppc.h (PPC_OPCODE_POWER8): New define.
716 (PPC_OPCODE_HTM): Likewise.
717
7182013-01-10 Will Newton <will.newton@imgtec.com>
719
720 * metag.h: New file.
721
7222013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
723
724 * cr16.h (make_instruction): Rename to cr16_make_instruction.
725 (match_opcode): Rename to cr16_match_opcode.
726
7272013-01-04 Juergen Urban <JuergenUrban@gmx.de>
728
729 * mips.h: Add support for r5900 instructions including lq and sq.
730
7312013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
732
733 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
734 (make_instruction,match_opcode): Added function prototypes.
735 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
736
7372012-11-23 Alan Modra <amodra@gmail.com>
738
739 * ppc.h (ppc_parse_cpu): Update prototype.
740
7412012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
742
743 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
744 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
745
7462012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
747
748 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
749
7502012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
751
752 * ia64.h (ia64_opnd): Add new operand types.
753
7542012-08-21 David S. Miller <davem@davemloft.net>
755
756 * sparc.h (F3F4): New macro.
757
7582012-08-13 Ian Bolton <ian.bolton@arm.com>
759 Laurent Desnogues <laurent.desnogues@arm.com>
760 Jim MacArthur <jim.macarthur@arm.com>
761 Marcus Shawcroft <marcus.shawcroft@arm.com>
762 Nigel Stephens <nigel.stephens@arm.com>
763 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
764 Richard Earnshaw <rearnsha@arm.com>
765 Sofiane Naci <sofiane.naci@arm.com>
766 Tejas Belagod <tejas.belagod@arm.com>
767 Yufeng Zhang <yufeng.zhang@arm.com>
768
769 * aarch64.h: New file.
770
7712012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
772 Maciej W. Rozycki <macro@codesourcery.com>
773
774 * mips.h (mips_opcode): Add the exclusions field.
775 (OPCODE_IS_MEMBER): Remove macro.
776 (cpu_is_member): New inline function.
777 (opcode_is_member): Likewise.
778
7792012-07-31 Chao-Ying Fu <fu@mips.com>
780 Catherine Moore <clm@codesourcery.com>
781 Maciej W. Rozycki <macro@codesourcery.com>
782
783 * mips.h: Document microMIPS DSP ASE usage.
784 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
785 microMIPS DSP ASE support.
786 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
787 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
788 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
789 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
790 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
791 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
792 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
793
7942012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
795
796 * mips.h: Fix a typo in description.
797
7982012-06-07 Georg-Johann Lay <avr@gjlay.de>
799
800 * avr.h: (AVR_ISA_XCH): New define.
801 (AVR_ISA_XMEGA): Use it.
802 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
803
8042012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
805
806 * m68hc11.h: Add XGate definitions.
807 (struct m68hc11_opcode): Add xg_mask field.
808
8092012-05-14 Catherine Moore <clm@codesourcery.com>
810 Maciej W. Rozycki <macro@codesourcery.com>
811 Rhonda Wittels <rhonda@codesourcery.com>
812
813 * ppc.h (PPC_OPCODE_VLE): New definition.
814 (PPC_OP_SA): New macro.
815 (PPC_OP_SE_VLE): New macro.
816 (PPC_OP): Use a variable shift amount.
817 (powerpc_operand): Update comments.
818 (PPC_OPSHIFT_INV): New macro.
819 (PPC_OPERAND_CR): Replace with...
820 (PPC_OPERAND_CR_BIT): ...this and
821 (PPC_OPERAND_CR_REG): ...this.
822
823
8242012-05-03 Sean Keys <skeys@ipdatasys.com>
825
826 * xgate.h: Header file for XGATE assembler.
827
8282012-04-27 David S. Miller <davem@davemloft.net>
829
830 * sparc.h: Document new arg code' )' for crypto RS3
831 immediates.
832
833 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
834 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
835 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
836 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
837 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
838 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
839 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
840 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
841 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
842 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
843 HWCAP_CBCOND, HWCAP_CRC32): New defines.
844
8452012-03-10 Edmar Wienskoski <edmar@freescale.com>
846
847 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
848
8492012-02-27 Alan Modra <amodra@gmail.com>
850
851 * crx.h (cst4_map): Update declaration.
852
8532012-02-25 Walter Lee <walt@tilera.com>
854
855 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
856 TILEGX_OPC_LD_TLS.
857 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
858 TILEPRO_OPC_LW_TLS_SN.
859
8602012-02-08 H.J. Lu <hongjiu.lu@intel.com>
861
862 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
863 (XRELEASE_PREFIX_OPCODE): Likewise.
864
8652011-12-08 Andrew Pinski <apinski@cavium.com>
866 Adam Nemet <anemet@caviumnetworks.com>
867
868 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
869 (INSN_OCTEON2): New macro.
870 (CPU_OCTEON2): New macro.
871 (OPCODE_IS_MEMBER): Add Octeon2.
872
8732011-11-29 Andrew Pinski <apinski@cavium.com>
874
875 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
876 (INSN_OCTEONP): New macro.
877 (CPU_OCTEONP): New macro.
878 (OPCODE_IS_MEMBER): Add Octeon+.
879 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
880
8812011-11-01 DJ Delorie <dj@redhat.com>
882
883 * rl78.h: New file.
884
8852011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
886
887 * mips.h: Fix a typo in description.
888
8892011-09-21 David S. Miller <davem@davemloft.net>
890
891 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
892 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
893 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
894 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
895
8962011-08-09 Chao-ying Fu <fu@mips.com>
897 Maciej W. Rozycki <macro@codesourcery.com>
898
899 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
900 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
901 (INSN_ASE_MASK): Add the MCU bit.
902 (INSN_MCU): New macro.
903 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
904 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
905
9062011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
907
908 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
909 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
910 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
911 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
912 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
913 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
914 (INSN2_READ_GPR_MMN): Likewise.
915 (INSN2_READ_FPR_D): Change the bit used.
916 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
917 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
918 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
919 (INSN2_COND_BRANCH): Likewise.
920 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
921 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
922 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
923 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
924 (INSN2_MOD_GPR_MN): Likewise.
925
9262011-08-05 David S. Miller <davem@davemloft.net>
927
928 * sparc.h: Document new format codes '4', '5', and '('.
929 (OPF_LOW4, RS3): New macros.
930
9312011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
932
933 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
934 order of flags documented.
935
9362011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
937
938 * mips.h: Clarify the description of microMIPS instruction
939 manipulation macros.
940 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
941
9422011-07-24 Chao-ying Fu <fu@mips.com>
943 Maciej W. Rozycki <macro@codesourcery.com>
944
945 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
946 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
947 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
948 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
949 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
950 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
951 (OP_MASK_RS3, OP_SH_RS3): Likewise.
952 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
953 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
954 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
955 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
956 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
957 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
958 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
959 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
960 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
961 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
962 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
963 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
964 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
965 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
966 (INSN_WRITE_GPR_S): New macro.
967 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
968 (INSN2_READ_FPR_D): Likewise.
969 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
970 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
971 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
972 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
973 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
974 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
975 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
976 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
977 (CPU_MICROMIPS): New macro.
978 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
979 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
980 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
981 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
982 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
983 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
984 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
985 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
986 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
987 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
988 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
989 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
990 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
991 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
992 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
993 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
994 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
995 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
996 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
997 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
998 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
999 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1000 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1001 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1002 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1003 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1004 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1005 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1006 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1007 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1008 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1009 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1010 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1011 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1012 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1013 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1014 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1015 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1016 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1017 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1018 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1019 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1020 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1021 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1022 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1023 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1024 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1025 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1026 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1027 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1028 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1029 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1030 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1031 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1032 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1033 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1034 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1035 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1036 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1037 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1038 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1039 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1040 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1041 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1042 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1043 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1044 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1045 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1046 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1047 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1048 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1049 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1050 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1051 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1052 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1053 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1054 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1055 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1056 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1057 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1058 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1059 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1060 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1061 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1062 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1063 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1064 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1065 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1066 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1067 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1068 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1069 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1070 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1071 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1072 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1073 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1074 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1075 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1076 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1077 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1078 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1079 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1080 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1081 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1082 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1083 (micromips_opcodes): New declaration.
1084 (bfd_micromips_num_opcodes): Likewise.
1085
10862011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1087
1088 * mips.h (INSN_TRAP): Rename to...
1089 (INSN_NO_DELAY_SLOT): ... this.
1090 (INSN_SYNC): Remove macro.
1091
10922011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1093
1094 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1095 a duplicate of AVR_ISA_SPM.
1096
10972011-07-01 Nick Clifton <nickc@redhat.com>
1098
1099 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1100
11012011-06-18 Robin Getz <robin.getz@analog.com>
1102
1103 * bfin.h (is_macmod_signed): New func
1104
11052011-06-18 Mike Frysinger <vapier@gentoo.org>
1106
1107 * bfin.h (is_macmod_pmove): Add missing space before func args.
1108 (is_macmod_hmove): Likewise.
1109
11102011-06-13 Walter Lee <walt@tilera.com>
1111
1112 * tilegx.h: New file.
1113 * tilepro.h: New file.
1114
11152011-05-31 Paul Brook <paul@codesourcery.com>
1116
1117 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1118
11192011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1120
1121 * s390.h: Replace S390_OPERAND_REG_EVEN with
1122 S390_OPERAND_REG_PAIR.
1123
11242011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1125
1126 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1127
11282011-04-18 Julian Brown <julian@codesourcery.com>
1129
1130 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1131
11322011-04-11 Dan McDonald <dan@wellkeeper.com>
1133
1134 PR gas/12296
1135 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1136
11372011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1138
1139 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1140 New instruction set flags.
1141 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1142
11432011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1144
1145 * mips.h (M_PREF_AB): New enum value.
1146
11472011-02-12 Mike Frysinger <vapier@gentoo.org>
1148
1149 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1150 M_IU): Define.
1151 (is_macmod_pmove, is_macmod_hmove): New functions.
1152
11532011-02-11 Mike Frysinger <vapier@gentoo.org>
1154
1155 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1156
11572011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1158
1159 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1160 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1161
11622010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1163
1164 PR gas/11395
1165 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1166 "bb" entries.
1167
11682010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1169
1170 PR gas/11395
1171 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1172
11732010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1174
1175 * mips.h: Update commentary after last commit.
1176
11772010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1178
1179 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1180 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1181 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1182
11832010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1184
1185 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1186
11872010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1188
1189 * mips.h: Fix previous commit.
1190
11912010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1192
1193 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1194 (INSN_LOONGSON_3A): Clear bit 31.
1195
11962010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1197
1198 PR gas/12198
1199 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1200 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1201 (ARM_ARCH_V6M_ONLY): New define.
1202
12032010-11-11 Mingming Sun <mingm.sun@gmail.com>
1204
1205 * mips.h (INSN_LOONGSON_3A): Defined.
1206 (CPU_LOONGSON_3A): Defined.
1207 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1208
12092010-10-09 Matt Rice <ratmice@gmail.com>
1210
1211 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1212 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1213
12142010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1215
1216 * arm.h (ARM_EXT_VIRT): New define.
1217 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1218 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1219 Extensions.
1220
12212010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1222
1223 * arm.h (ARM_AEXT_ADIV): New define.
1224 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1225
12262010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1227
1228 * arm.h (ARM_EXT_OS): New define.
1229 (ARM_AEXT_V6SM): Likewise.
1230 (ARM_ARCH_V6SM): Likewise.
1231
12322010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1233
1234 * arm.h (ARM_EXT_MP): Add.
1235 (ARM_ARCH_V7A_MP): Likewise.
1236
12372010-09-22 Mike Frysinger <vapier@gentoo.org>
1238
1239 * bfin.h: Declare pseudoChr structs/defines.
1240
12412010-09-21 Mike Frysinger <vapier@gentoo.org>
1242
1243 * bfin.h: Strip trailing whitespace.
1244
12452010-07-29 DJ Delorie <dj@redhat.com>
1246
1247 * rx.h (RX_Operand_Type): Add TwoReg.
1248 (RX_Opcode_ID): Remove ediv and ediv2.
1249
12502010-07-27 DJ Delorie <dj@redhat.com>
1251
1252 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1253
12542010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1255 Ina Pandit <ina.pandit@kpitcummins.com>
1256
1257 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1258 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1259 PROCESSOR_V850E2_ALL.
1260 Remove PROCESSOR_V850EA support.
1261 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1262 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1263 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1264 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1265 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1266 V850_OPERAND_PERCENT.
1267 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1268 V850_NOT_R0.
1269 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1270 and V850E_PUSH_POP
1271
12722010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1273
1274 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1275 (MIPS16_INSN_BRANCH): Rename to...
1276 (MIPS16_INSN_COND_BRANCH): ... this.
1277
12782010-07-03 Alan Modra <amodra@gmail.com>
1279
1280 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1281 Renumber other PPC_OPCODE defines.
1282
12832010-07-03 Alan Modra <amodra@gmail.com>
1284
1285 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1286
12872010-06-29 Alan Modra <amodra@gmail.com>
1288
1289 * maxq.h: Delete file.
1290
12912010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1292
1293 * ppc.h (PPC_OPCODE_E500): Define.
1294
12952010-05-26 Catherine Moore <clm@codesourcery.com>
1296
1297 * opcode/mips.h (INSN_MIPS16): Remove.
1298
12992010-04-21 Joseph Myers <joseph@codesourcery.com>
1300
1301 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1302
13032010-04-15 Nick Clifton <nickc@redhat.com>
1304
1305 * alpha.h: Update copyright notice to use GPLv3.
1306 * arc.h: Likewise.
1307 * arm.h: Likewise.
1308 * avr.h: Likewise.
1309 * bfin.h: Likewise.
1310 * cgen.h: Likewise.
1311 * convex.h: Likewise.
1312 * cr16.h: Likewise.
1313 * cris.h: Likewise.
1314 * crx.h: Likewise.
1315 * d10v.h: Likewise.
1316 * d30v.h: Likewise.
1317 * dlx.h: Likewise.
1318 * h8300.h: Likewise.
1319 * hppa.h: Likewise.
1320 * i370.h: Likewise.
1321 * i386.h: Likewise.
1322 * i860.h: Likewise.
1323 * i960.h: Likewise.
1324 * ia64.h: Likewise.
1325 * m68hc11.h: Likewise.
1326 * m68k.h: Likewise.
1327 * m88k.h: Likewise.
1328 * maxq.h: Likewise.
1329 * mips.h: Likewise.
1330 * mmix.h: Likewise.
1331 * mn10200.h: Likewise.
1332 * mn10300.h: Likewise.
1333 * msp430.h: Likewise.
1334 * np1.h: Likewise.
1335 * ns32k.h: Likewise.
1336 * or32.h: Likewise.
1337 * pdp11.h: Likewise.
1338 * pj.h: Likewise.
1339 * pn.h: Likewise.
1340 * ppc.h: Likewise.
1341 * pyr.h: Likewise.
1342 * rx.h: Likewise.
1343 * s390.h: Likewise.
1344 * score-datadep.h: Likewise.
1345 * score-inst.h: Likewise.
1346 * sparc.h: Likewise.
1347 * spu-insns.h: Likewise.
1348 * spu.h: Likewise.
1349 * tic30.h: Likewise.
1350 * tic4x.h: Likewise.
1351 * tic54x.h: Likewise.
1352 * tic80.h: Likewise.
1353 * v850.h: Likewise.
1354 * vax.h: Likewise.
1355
13562010-03-25 Joseph Myers <joseph@codesourcery.com>
1357
1358 * tic6x-control-registers.h, tic6x-insn-formats.h,
1359 tic6x-opcode-table.h, tic6x.h: New.
1360
13612010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1362
1363 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1364
13652010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1366
1367 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1368
13692010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1370
1371 * ia64.h (ia64_find_opcode): Remove argument name.
1372 (ia64_find_next_opcode): Likewise.
1373 (ia64_dis_opcode): Likewise.
1374 (ia64_free_opcode): Likewise.
1375 (ia64_find_dependency): Likewise.
1376
13772009-11-22 Doug Evans <dje@sebabeach.org>
1378
1379 * cgen.h: Include bfd_stdint.h.
1380 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1381
13822009-11-18 Paul Brook <paul@codesourcery.com>
1383
1384 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1385
13862009-11-17 Paul Brook <paul@codesourcery.com>
1387 Daniel Jacobowitz <dan@codesourcery.com>
1388
1389 * arm.h (ARM_EXT_V6_DSP): Define.
1390 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1391 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1392
13932009-11-04 DJ Delorie <dj@redhat.com>
1394
1395 * rx.h (rx_decode_opcode) (mvtipl): Add.
1396 (mvtcp, mvfcp, opecp): Remove.
1397
13982009-11-02 Paul Brook <paul@codesourcery.com>
1399
1400 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1401 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1402 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1403 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1404 FPU_ARCH_NEON_VFP_V4): Define.
1405
14062009-10-23 Doug Evans <dje@sebabeach.org>
1407
1408 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1409 * cgen.h: Update. Improve multi-inclusion macro name.
1410
14112009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1412
1413 * ppc.h (PPC_OPCODE_476): Define.
1414
14152009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1416
1417 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1418
14192009-09-29 DJ Delorie <dj@redhat.com>
1420
1421 * rx.h: New file.
1422
14232009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1424
1425 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1426
14272009-09-21 Ben Elliston <bje@au.ibm.com>
1428
1429 * ppc.h (PPC_OPCODE_PPCA2): New.
1430
14312009-09-05 Martin Thuresson <martin@mtme.org>
1432
1433 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1434
14352009-08-29 Martin Thuresson <martin@mtme.org>
1436
1437 * tic30.h (template): Rename type template to
1438 insn_template. Updated code to use new name.
1439 * tic54x.h (template): Rename type template to
1440 insn_template.
1441
14422009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1443
1444 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1445
14462009-06-11 Anthony Green <green@moxielogic.com>
1447
1448 * moxie.h (MOXIE_F3_PCREL): Define.
1449 (moxie_form3_opc_info): Grow.
1450
14512009-06-06 Anthony Green <green@moxielogic.com>
1452
1453 * moxie.h (MOXIE_F1_M): Define.
1454
14552009-04-15 Anthony Green <green@moxielogic.com>
1456
1457 * moxie.h: Created.
1458
14592009-04-06 DJ Delorie <dj@redhat.com>
1460
1461 * h8300.h: Add relaxation attributes to MOVA opcodes.
1462
14632009-03-10 Alan Modra <amodra@bigpond.net.au>
1464
1465 * ppc.h (ppc_parse_cpu): Declare.
1466
14672009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1468
1469 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1470 and _IMM11 for mbitclr and mbitset.
1471 * score-datadep.h: Update dependency information.
1472
14732009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1474
1475 * ppc.h (PPC_OPCODE_POWER7): New.
1476
14772009-02-06 Doug Evans <dje@google.com>
1478
1479 * i386.h: Add comment regarding sse* insns and prefixes.
1480
14812009-02-03 Sandip Matte <sandip@rmicorp.com>
1482
1483 * mips.h (INSN_XLR): Define.
1484 (INSN_CHIP_MASK): Update.
1485 (CPU_XLR): Define.
1486 (OPCODE_IS_MEMBER): Update.
1487 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1488
14892009-01-28 Doug Evans <dje@google.com>
1490
1491 * opcode/i386.h: Add multiple inclusion protection.
1492 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1493 (EDI_REG_NUM): New macros.
1494 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1495 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1496 (REX_PREFIX_P): New macro.
1497
14982009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1499
1500 * ppc.h (struct powerpc_opcode): New field "deprecated".
1501 (PPC_OPCODE_NOPOWER4): Delete.
1502
15032008-11-28 Joshua Kinard <kumba@gentoo.org>
1504
1505 * mips.h: Define CPU_R14000, CPU_R16000.
1506 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1507
15082008-11-18 Catherine Moore <clm@codesourcery.com>
1509
1510 * arm.h (FPU_NEON_FP16): New.
1511 (FPU_ARCH_NEON_FP16): New.
1512
15132008-11-06 Chao-ying Fu <fu@mips.com>
1514
1515 * mips.h: Doucument '1' for 5-bit sync type.
1516
15172008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1518
1519 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1520 IA64_RS_CR.
1521
15222008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1523
1524 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1525
15262008-07-30 Michael J. Eager <eager@eagercon.com>
1527
1528 * ppc.h (PPC_OPCODE_405): Define.
1529 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1530
15312008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1532
1533 * ppc.h (ppc_cpu_t): New typedef.
1534 (struct powerpc_opcode <flags>): Use it.
1535 (struct powerpc_operand <insert, extract>): Likewise.
1536 (struct powerpc_macro <flags>): Likewise.
1537
15382008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1539
1540 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1541 Update comment before MIPS16 field descriptors to mention MIPS16.
1542 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1543 BBIT.
1544 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1545 New bit masks and shift counts for cins and exts.
1546
1547 * mips.h: Document new field descriptors +Q.
1548 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1549
15502008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1551
1552 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1553 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1554
15552008-04-14 Edmar Wienskoski <edmar@freescale.com>
1556
1557 * ppc.h: (PPC_OPCODE_E500MC): New.
1558
15592008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1560
1561 * i386.h (MAX_OPERANDS): Set to 5.
1562 (MAX_MNEM_SIZE): Changed to 20.
1563
15642008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1565
1566 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1567
15682008-03-09 Paul Brook <paul@codesourcery.com>
1569
1570 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1571
15722008-03-04 Paul Brook <paul@codesourcery.com>
1573
1574 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1575 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1576 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1577
15782008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1579 Nick Clifton <nickc@redhat.com>
1580
1581 PR 3134
1582 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1583 with a 32-bit displacement but without the top bit of the 4th byte
1584 set.
1585
15862008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1587
1588 * cr16.h (cr16_num_optab): Declared.
1589
15902008-02-14 Hakan Ardo <hakan@debian.org>
1591
1592 PR gas/2626
1593 * avr.h (AVR_ISA_2xxe): Define.
1594
15952008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1596
1597 * mips.h: Update copyright.
1598 (INSN_CHIP_MASK): New macro.
1599 (INSN_OCTEON): New macro.
1600 (CPU_OCTEON): New macro.
1601 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1602
16032008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1604
1605 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1606
16072008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1608
1609 * avr.h (AVR_ISA_USB162): Add new opcode set.
1610 (AVR_ISA_AVR3): Likewise.
1611
16122007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1613
1614 * mips.h (INSN_LOONGSON_2E): New.
1615 (INSN_LOONGSON_2F): New.
1616 (CPU_LOONGSON_2E): New.
1617 (CPU_LOONGSON_2F): New.
1618 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1619
16202007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1621
1622 * mips.h (INSN_ISA*): Redefine certain values as an
1623 enumeration. Update comments.
1624 (mips_isa_table): New.
1625 (ISA_MIPS*): Redefine to match enumeration.
1626 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1627 values.
1628
16292007-08-08 Ben Elliston <bje@au.ibm.com>
1630
1631 * ppc.h (PPC_OPCODE_PPCPS): New.
1632
16332007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1634
1635 * m68k.h: Document j K & E.
1636
16372007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1638
1639 * cr16.h: New file for CR16 target.
1640
16412007-05-02 Alan Modra <amodra@bigpond.net.au>
1642
1643 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1644
16452007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1646
1647 * m68k.h (mcfisa_c): New.
1648 (mcfusp, mcf_mask): Adjust.
1649
16502007-04-20 Alan Modra <amodra@bigpond.net.au>
1651
1652 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1653 (num_powerpc_operands): Declare.
1654 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1655 (PPC_OPERAND_PLUS1): Define.
1656
16572007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1658
1659 * i386.h (REX_MODE64): Renamed to ...
1660 (REX_W): This.
1661 (REX_EXTX): Renamed to ...
1662 (REX_R): This.
1663 (REX_EXTY): Renamed to ...
1664 (REX_X): This.
1665 (REX_EXTZ): Renamed to ...
1666 (REX_B): This.
1667
16682007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1669
1670 * i386.h: Add entries from config/tc-i386.h and move tables
1671 to opcodes/i386-opc.h.
1672
16732007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1674
1675 * i386.h (FloatDR): Removed.
1676 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1677
16782007-03-01 Alan Modra <amodra@bigpond.net.au>
1679
1680 * spu-insns.h: Add soma double-float insns.
1681
16822007-02-20 Thiemo Seufer <ths@mips.com>
1683 Chao-Ying Fu <fu@mips.com>
1684
1685 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1686 (INSN_DSPR2): Add flag for DSP R2 instructions.
1687 (M_BALIGN): New macro.
1688
16892007-02-14 Alan Modra <amodra@bigpond.net.au>
1690
1691 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1692 and Seg3ShortFrom with Shortform.
1693
16942007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1695
1696 PR gas/4027
1697 * i386.h (i386_optab): Put the real "test" before the pseudo
1698 one.
1699
17002007-01-08 Kazu Hirata <kazu@codesourcery.com>
1701
1702 * m68k.h (m68010up): OR fido_a.
1703
17042006-12-25 Kazu Hirata <kazu@codesourcery.com>
1705
1706 * m68k.h (fido_a): New.
1707
17082006-12-24 Kazu Hirata <kazu@codesourcery.com>
1709
1710 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1711 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1712 values.
1713
17142006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1715
1716 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1717
17182006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1719
1720 * score-inst.h (enum score_insn_type): Add Insn_internal.
1721
17222006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1723 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1724 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1725 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1726 Alan Modra <amodra@bigpond.net.au>
1727
1728 * spu-insns.h: New file.
1729 * spu.h: New file.
1730
17312006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1732
1733 * ppc.h (PPC_OPCODE_CELL): Define.
1734
17352006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1736
1737 * i386.h : Modify opcode to support for the change in POPCNT opcode
1738 in amdfam10 architecture.
1739
17402006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1741
1742 * i386.h: Replace CpuMNI with CpuSSSE3.
1743
17442006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1745 Joseph Myers <joseph@codesourcery.com>
1746 Ian Lance Taylor <ian@wasabisystems.com>
1747 Ben Elliston <bje@wasabisystems.com>
1748
1749 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1750
17512006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1752
1753 * score-datadep.h: New file.
1754 * score-inst.h: New file.
1755
17562006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1757
1758 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1759 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1760 movdq2q and movq2dq.
1761
17622006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1763 Michael Meissner <michael.meissner@amd.com>
1764
1765 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1766
17672006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1768
1769 * i386.h (i386_optab): Add "nop" with memory reference.
1770
17712006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1772
1773 * i386.h (i386_optab): Update comment for 64bit NOP.
1774
17752006-06-06 Ben Elliston <bje@au.ibm.com>
1776 Anton Blanchard <anton@samba.org>
1777
1778 * ppc.h (PPC_OPCODE_POWER6): Define.
1779 Adjust whitespace.
1780
17812006-06-05 Thiemo Seufer <ths@mips.com>
1782
1783 * mips.h: Improve description of MT flags.
1784
17852006-05-25 Richard Sandiford <richard@codesourcery.com>
1786
1787 * m68k.h (mcf_mask): Define.
1788
17892006-05-05 Thiemo Seufer <ths@mips.com>
1790 David Ung <davidu@mips.com>
1791
1792 * mips.h (enum): Add macro M_CACHE_AB.
1793
17942006-05-04 Thiemo Seufer <ths@mips.com>
1795 Nigel Stephens <nigel@mips.com>
1796 David Ung <davidu@mips.com>
1797
1798 * mips.h: Add INSN_SMARTMIPS define.
1799
18002006-04-30 Thiemo Seufer <ths@mips.com>
1801 David Ung <davidu@mips.com>
1802
1803 * mips.h: Defines udi bits and masks. Add description of
1804 characters which may appear in the args field of udi
1805 instructions.
1806
18072006-04-26 Thiemo Seufer <ths@networkno.de>
1808
1809 * mips.h: Improve comments describing the bitfield instruction
1810 fields.
1811
18122006-04-26 Julian Brown <julian@codesourcery.com>
1813
1814 * arm.h (FPU_VFP_EXT_V3): Define constant.
1815 (FPU_NEON_EXT_V1): Likewise.
1816 (FPU_VFP_HARD): Update.
1817 (FPU_VFP_V3): Define macro.
1818 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1819
18202006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1821
1822 * avr.h (AVR_ISA_PWMx): New.
1823
18242006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1825
1826 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1827 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1828 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1829 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1830 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1831
18322006-03-10 Paul Brook <paul@codesourcery.com>
1833
1834 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1835
18362006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1837
1838 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1839 first. Correct mask of bb "B" opcode.
1840
18412006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1842
1843 * i386.h (i386_optab): Support Intel Merom New Instructions.
1844
18452006-02-24 Paul Brook <paul@codesourcery.com>
1846
1847 * arm.h: Add V7 feature bits.
1848
18492006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1850
1851 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1852
18532006-01-31 Paul Brook <paul@codesourcery.com>
1854 Richard Earnshaw <rearnsha@arm.com>
1855
1856 * arm.h: Use ARM_CPU_FEATURE.
1857 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1858 (arm_feature_set): Change to a structure.
1859 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1860 ARM_FEATURE): New macros.
1861
18622005-12-07 Hans-Peter Nilsson <hp@axis.com>
1863
1864 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1865 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1866 (ADD_PC_INCR_OPCODE): Don't define.
1867
18682005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1869
1870 PR gas/1874
1871 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1872
18732005-11-14 David Ung <davidu@mips.com>
1874
1875 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1876 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1877 save/restore encoding of the args field.
1878
18792005-10-28 Dave Brolley <brolley@redhat.com>
1880
1881 Contribute the following changes:
1882 2005-02-16 Dave Brolley <brolley@redhat.com>
1883
1884 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1885 cgen_isa_mask_* to cgen_bitset_*.
1886 * cgen.h: Likewise.
1887
1888 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1889
1890 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1891 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1892 (CGEN_CPU_TABLE): Make isas a ponter.
1893
1894 2003-09-29 Dave Brolley <brolley@redhat.com>
1895
1896 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1897 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1898 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1899
1900 2002-12-13 Dave Brolley <brolley@redhat.com>
1901
1902 * cgen.h (symcat.h): #include it.
1903 (cgen-bitset.h): #include it.
1904 (CGEN_ATTR_VALUE_TYPE): Now a union.
1905 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1906 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1907 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1908 * cgen-bitset.h: New file.
1909
19102005-09-30 Catherine Moore <clm@cm00re.com>
1911
1912 * bfin.h: New file.
1913
19142005-10-24 Jan Beulich <jbeulich@novell.com>
1915
1916 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1917 indirect operands.
1918
19192005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1920
1921 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1922 Add FLAG_STRICT to pa10 ftest opcode.
1923
19242005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1925
1926 * hppa.h (pa_opcodes): Remove lha entries.
1927
19282005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1929
1930 * hppa.h (FLAG_STRICT): Revise comment.
1931 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1932 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1933 entries for "fdc".
1934
19352005-09-30 Catherine Moore <clm@cm00re.com>
1936
1937 * bfin.h: New file.
1938
19392005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1940
1941 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1942
19432005-09-06 Chao-ying Fu <fu@mips.com>
1944
1945 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1946 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1947 define.
1948 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1949 (INSN_ASE_MASK): Update to include INSN_MT.
1950 (INSN_MT): New define for MT ASE.
1951
19522005-08-25 Chao-ying Fu <fu@mips.com>
1953
1954 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1955 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1956 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1957 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1958 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1959 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1960 instructions.
1961 (INSN_DSP): New define for DSP ASE.
1962
19632005-08-18 Alan Modra <amodra@bigpond.net.au>
1964
1965 * a29k.h: Delete.
1966
19672005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1968
1969 * ppc.h (PPC_OPCODE_E300): Define.
1970
19712005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1972
1973 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1974
19752005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1976
1977 PR gas/336
1978 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1979 and pitlb.
1980
19812005-07-27 Jan Beulich <jbeulich@novell.com>
1982
1983 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1984 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1985 Add movq-s as 64-bit variants of movd-s.
1986
19872005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1988
1989 * hppa.h: Fix punctuation in comment.
1990
1991 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1992 implicit space-register addressing. Set space-register bits on opcodes
1993 using implicit space-register addressing. Add various missing pa20
1994 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1995 space-register addressing. Use "fE" instead of "fe" in various
1996 fstw opcodes.
1997
19982005-07-18 Jan Beulich <jbeulich@novell.com>
1999
2000 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2001
20022007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2003
2004 * i386.h (i386_optab): Support Intel VMX Instructions.
2005
20062005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2007
2008 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2009
20102005-07-05 Jan Beulich <jbeulich@novell.com>
2011
2012 * i386.h (i386_optab): Add new insns.
2013
20142005-07-01 Nick Clifton <nickc@redhat.com>
2015
2016 * sparc.h: Add typedefs to structure declarations.
2017
20182005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2019
2020 PR 1013
2021 * i386.h (i386_optab): Update comments for 64bit addressing on
2022 mov. Allow 64bit addressing for mov and movq.
2023
20242005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2025
2026 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2027 respectively, in various floating-point load and store patterns.
2028
20292005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2030
2031 * hppa.h (FLAG_STRICT): Correct comment.
2032 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2033 PA 2.0 mneumonics when equivalent. Entries with cache control
2034 completers now require PA 1.1. Adjust whitespace.
2035
20362005-05-19 Anton Blanchard <anton@samba.org>
2037
2038 * ppc.h (PPC_OPCODE_POWER5): Define.
2039
20402005-05-10 Nick Clifton <nickc@redhat.com>
2041
2042 * Update the address and phone number of the FSF organization in
2043 the GPL notices in the following files:
2044 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2045 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2046 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2047 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2048 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2049 tic54x.h, tic80.h, v850.h, vax.h
2050
20512005-05-09 Jan Beulich <jbeulich@novell.com>
2052
2053 * i386.h (i386_optab): Add ht and hnt.
2054
20552005-04-18 Mark Kettenis <kettenis@gnu.org>
2056
2057 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2058 Add xcrypt-ctr. Provide aliases without hyphens.
2059
20602005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2061
2062 Moved from ../ChangeLog
2063
2064 2005-04-12 Paul Brook <paul@codesourcery.com>
2065 * m88k.h: Rename psr macros to avoid conflicts.
2066
2067 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2068 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2069 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2070 and ARM_ARCH_V6ZKT2.
2071
2072 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2073 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2074 Remove redundant instruction types.
2075 (struct argument): X_op - new field.
2076 (struct cst4_entry): Remove.
2077 (no_op_insn): Declare.
2078
2079 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2080 * crx.h (enum argtype): Rename types, remove unused types.
2081
2082 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2083 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2084 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2085 (enum operand_type): Rearrange operands, edit comments.
2086 replace us<N> with ui<N> for unsigned immediate.
2087 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2088 displacements (respectively).
2089 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2090 (instruction type): Add NO_TYPE_INS.
2091 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2092 (operand_entry): New field - 'flags'.
2093 (operand flags): New.
2094
2095 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2096 * crx.h (operand_type): Remove redundant types i3, i4,
2097 i5, i8, i12.
2098 Add new unsigned immediate types us3, us4, us5, us16.
2099
21002005-04-12 Mark Kettenis <kettenis@gnu.org>
2101
2102 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2103 adjust them accordingly.
2104
21052005-04-01 Jan Beulich <jbeulich@novell.com>
2106
2107 * i386.h (i386_optab): Add rdtscp.
2108
21092005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2110
2111 * i386.h (i386_optab): Don't allow the `l' suffix for moving
2112 between memory and segment register. Allow movq for moving between
2113 general-purpose register and segment register.
2114
21152005-02-09 Jan Beulich <jbeulich@novell.com>
2116
2117 PR gas/707
2118 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2119 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2120 fnstsw.
2121
21222006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2123
2124 * m68k.h (m68008, m68ec030, m68882): Remove.
2125 (m68k_mask): New.
2126 (cpu_m68k, cpu_cf): New.
2127 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2128 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2129
21302005-01-25 Alexandre Oliva <aoliva@redhat.com>
2131
2132 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2133 * cgen.h (enum cgen_parse_operand_type): Add
2134 CGEN_PARSE_OPERAND_SYMBOLIC.
2135
21362005-01-21 Fred Fish <fnf@specifixinc.com>
2137
2138 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2139 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2140 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2141
21422005-01-19 Fred Fish <fnf@specifixinc.com>
2143
2144 * mips.h (struct mips_opcode): Add new pinfo2 member.
2145 (INSN_ALIAS): New define for opcode table entries that are
2146 specific instances of another entry, such as 'move' for an 'or'
2147 with a zero operand.
2148 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2149 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2150
21512004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2152
2153 * mips.h (CPU_RM9000): Define.
2154 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2155
21562004-11-25 Jan Beulich <jbeulich@novell.com>
2157
2158 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2159 to/from test registers are illegal in 64-bit mode. Add missing
2160 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2161 (previously one had to explicitly encode a rex64 prefix). Re-enable
2162 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2163 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2164
21652004-11-23 Jan Beulich <jbeulich@novell.com>
2166
2167 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2168 available only with SSE2. Change the MMX additions introduced by SSE
2169 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2170 instructions by their now designated identifier (since combining i686
2171 and 3DNow! does not really imply 3DNow!A).
2172
21732004-11-19 Alan Modra <amodra@bigpond.net.au>
2174
2175 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2176 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2177
21782004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2179 Vineet Sharma <vineets@noida.hcltech.com>
2180
2181 * maxq.h: New file: Disassembly information for the maxq port.
2182
21832004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2184
2185 * i386.h (i386_optab): Put back "movzb".
2186
21872004-11-04 Hans-Peter Nilsson <hp@axis.com>
2188
2189 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2190 comments. Remove member cris_ver_sim. Add members
2191 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2192 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2193 (struct cris_support_reg, struct cris_cond15): New types.
2194 (cris_conds15): Declare.
2195 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2196 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2197 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2198 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2199 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2200 SIZE_FIELD_UNSIGNED.
2201
22022004-11-04 Jan Beulich <jbeulich@novell.com>
2203
2204 * i386.h (sldx_Suf): Remove.
2205 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2206 (q_FP): Define, implying no REX64.
2207 (x_FP, sl_FP): Imply FloatMF.
2208 (i386_optab): Split reg and mem forms of moving from segment registers
2209 so that the memory forms can ignore the 16-/32-bit operand size
2210 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2211 all non-floating-point instructions. Unite 32- and 64-bit forms of
2212 movsx, movzx, and movd. Adjust floating point operations for the above
2213 changes to the *FP macros. Add DefaultSize to floating point control
2214 insns operating on larger memory ranges. Remove left over comments
2215 hinting at certain insns being Intel-syntax ones where the ones
2216 actually meant are already gone.
2217
22182004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2219
2220 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2221 instruction type.
2222
22232004-09-30 Paul Brook <paul@codesourcery.com>
2224
2225 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2226 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2227
22282004-09-11 Theodore A. Roth <troth@openavr.org>
2229
2230 * avr.h: Add support for
2231 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2232
22332004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2234
2235 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2236
22372004-08-24 Dmitry Diky <diwil@spec.ru>
2238
2239 * msp430.h (msp430_opc): Add new instructions.
2240 (msp430_rcodes): Declare new instructions.
2241 (msp430_hcodes): Likewise..
2242
22432004-08-13 Nick Clifton <nickc@redhat.com>
2244
2245 PR/301
2246 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2247 processors.
2248
22492004-08-30 Michal Ludvig <mludvig@suse.cz>
2250
2251 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2252
22532004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2254
2255 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2256
22572004-07-21 Jan Beulich <jbeulich@novell.com>
2258
2259 * i386.h: Adjust instruction descriptions to better match the
2260 specification.
2261
22622004-07-16 Richard Earnshaw <rearnsha@arm.com>
2263
2264 * arm.h: Remove all old content. Replace with architecture defines
2265 from gas/config/tc-arm.c.
2266
22672004-07-09 Andreas Schwab <schwab@suse.de>
2268
2269 * m68k.h: Fix comment.
2270
22712004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2272
2273 * crx.h: New file.
2274
22752004-06-24 Alan Modra <amodra@bigpond.net.au>
2276
2277 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2278
22792004-05-24 Peter Barada <peter@the-baradas.com>
2280
2281 * m68k.h: Add 'size' to m68k_opcode.
2282
22832004-05-05 Peter Barada <peter@the-baradas.com>
2284
2285 * m68k.h: Switch from ColdFire chip name to core variant.
2286
22872004-04-22 Peter Barada <peter@the-baradas.com>
2288
2289 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2290 descriptions for new EMAC cases.
2291 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2292 handle Motorola MAC syntax.
2293 Allow disassembly of ColdFire V4e object files.
2294
22952004-03-16 Alan Modra <amodra@bigpond.net.au>
2296
2297 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2298
22992004-03-12 Jakub Jelinek <jakub@redhat.com>
2300
2301 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2302
23032004-03-12 Michal Ludvig <mludvig@suse.cz>
2304
2305 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2306
23072004-03-12 Michal Ludvig <mludvig@suse.cz>
2308
2309 * i386.h (i386_optab): Added xstore/xcrypt insns.
2310
23112004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2312
2313 * h8300.h (32bit ldc/stc): Add relaxing support.
2314
23152004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2316
2317 * h8300.h (BITOP): Pass MEMRELAX flag.
2318
23192004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2320
2321 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2322 except for the H8S.
2323
2324For older changes see ChangeLog-9103
2325\f
2326Copyright (C) 2004-2015 Free Software Foundation, Inc.
2327
2328Copying and distribution of this file, with or without modification,
2329are permitted in any medium without royalty provided the copyright
2330notice and this notice are preserved.
2331
2332Local Variables:
2333mode: change-log
2334left-margin: 8
2335fill-column: 74
2336version-control: never
2337End:
GDB Binutils - Deliverables
This page took 0.029597 seconds and 4 git commands to generate.