| | 1 | 2008-04-14 Edmar Wienskoski <edmar@freescale.com> |
| | 2 | |
| | 3 | * ppc.h: (PPC_OPCODE_E500MC): New. |
| | 4 | |
| | 5 | 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> |
| | 6 | |
| | 7 | * i386.h (MAX_OPERANDS): Set to 5. |
| | 8 | (MAX_MNEM_SIZE): Changed to 20. |
| | 9 | |
| | 10 | 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com> |
| | 11 | |
| | 12 | * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167. |
| | 13 | |
| | 14 | 2008-03-09 Paul Brook <paul@codesourcery.com> |
| | 15 | |
| | 16 | * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define. |
| | 17 | |
| | 18 | 2008-03-04 Paul Brook <paul@codesourcery.com> |
| | 19 | |
| | 20 | * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define. |
| | 21 | (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags. |
| | 22 | (ARM_AEXT_V6M, ARM_ARCH_V6M): Define. |
| | 23 | |
| | 24 | 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com> |
| | 25 | Nick Clifton <nickc@redhat.com> |
| | 26 | |
| | 27 | PR 3134 |
| | 28 | * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction |
| | 29 | with a 32-bit displacement but without the top bit of the 4th byte |
| | 30 | set. |
| | 31 | |
| | 32 | 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com> |
| | 33 | |
| | 34 | * cr16.h (cr16_num_optab): Declared. |
| | 35 | |
| | 36 | 2008-02-14 Hakan Ardo <hakan@debian.org> |
| | 37 | |
| | 38 | PR gas/2626 |
| | 39 | * avr.h (AVR_ISA_2xxe): Define. |
| | 40 | |
| | 41 | 2008-02-04 Adam Nemet <anemet@caviumnetworks.com> |
| | 42 | |
| | 43 | * mips.h: Update copyright. |
| | 44 | (INSN_CHIP_MASK): New macro. |
| | 45 | (INSN_OCTEON): New macro. |
| | 46 | (CPU_OCTEON): New macro. |
| | 47 | (OPCODE_IS_MEMBER): Handle Octeon instructions. |
| | 48 | |
| | 49 | 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com> |
| | 50 | |
| | 51 | * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401. |
| | 52 | |
| | 53 | 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com> |
| | 54 | |
| | 55 | * avr.h (AVR_ISA_USB162): Add new opcode set. |
| | 56 | (AVR_ISA_AVR3): Likewise. |
| | 57 | |
| | 58 | 2007-11-29 Mark Shinwell <shinwell@codesourcery.com> |
| | 59 | |
| | 60 | * mips.h (INSN_LOONGSON_2E): New. |
| | 61 | (INSN_LOONGSON_2F): New. |
| | 62 | (CPU_LOONGSON_2E): New. |
| | 63 | (CPU_LOONGSON_2F): New. |
| | 64 | (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags. |
| | 65 | |
| | 66 | 2007-11-29 Mark Shinwell <shinwell@codesourcery.com> |
| | 67 | |
| | 68 | * mips.h (INSN_ISA*): Redefine certain values as an |
| | 69 | enumeration. Update comments. |
| | 70 | (mips_isa_table): New. |
| | 71 | (ISA_MIPS*): Redefine to match enumeration. |
| | 72 | (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA* |
| | 73 | values. |
| | 74 | |
| | 75 | 2007-08-08 Ben Elliston <bje@au.ibm.com> |
| | 76 | |
| | 77 | * ppc.h (PPC_OPCODE_PPCPS): New. |
| | 78 | |
| | 79 | 2007-07-03 Nathan Sidwell <nathan@codesourcery.com> |
| | 80 | |
| | 81 | * m68k.h: Document j K & E. |
| | 82 | |
| | 83 | 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com> |
| | 84 | |
| | 85 | * cr16.h: New file for CR16 target. |
| | 86 | |
| | 87 | 2007-05-02 Alan Modra <amodra@bigpond.net.au> |
| | 88 | |
| | 89 | * ppc.h (PPC_OPERAND_PLUS1): Update comment. |
| | 90 | |
| | 91 | 2007-04-23 Nathan Sidwell <nathan@codesourcery.com> |
| | 92 | |
| | 93 | * m68k.h (mcfisa_c): New. |
| | 94 | (mcfusp, mcf_mask): Adjust. |
| | 95 | |
| | 96 | 2007-04-20 Alan Modra <amodra@bigpond.net.au> |
| | 97 | |
| | 98 | * ppc.h (struct powerpc_operand): Replace "bits" with "bitm". |
| | 99 | (num_powerpc_operands): Declare. |
| | 100 | (PPC_OPERAND_SIGNED et al): Redefine as hex. |
| | 101 | (PPC_OPERAND_PLUS1): Define. |
| | 102 | |
| | 103 | 2007-03-21 H.J. Lu <hongjiu.lu@intel.com> |
| | 104 | |
| | 105 | * i386.h (REX_MODE64): Renamed to ... |
| | 106 | (REX_W): This. |
| | 107 | (REX_EXTX): Renamed to ... |
| | 108 | (REX_R): This. |
| | 109 | (REX_EXTY): Renamed to ... |
| | 110 | (REX_X): This. |
| | 111 | (REX_EXTZ): Renamed to ... |
| | 112 | (REX_B): This. |
| | 113 | |
| | 114 | 2007-03-15 H.J. Lu <hongjiu.lu@intel.com> |
| | 115 | |
| | 116 | * i386.h: Add entries from config/tc-i386.h and move tables |
| | 117 | to opcodes/i386-opc.h. |
| | 118 | |
| | 119 | 2007-03-13 H.J. Lu <hongjiu.lu@intel.com> |
| | 120 | |
| | 121 | * i386.h (FloatDR): Removed. |
| | 122 | (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR. |
| | 123 | |
| | 124 | 2007-03-01 Alan Modra <amodra@bigpond.net.au> |
| | 125 | |
| | 126 | * spu-insns.h: Add soma double-float insns. |
| | 127 | |
| | 128 | 2007-02-20 Thiemo Seufer <ths@mips.com> |
| | 129 | Chao-Ying Fu <fu@mips.com> |
| | 130 | |
| | 131 | * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. |
| | 132 | (INSN_DSPR2): Add flag for DSP R2 instructions. |
| | 133 | (M_BALIGN): New macro. |
| | 134 | |
| | 135 | 2007-02-14 Alan Modra <amodra@bigpond.net.au> |
| | 136 | |
| | 137 | * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm |
| | 138 | and Seg3ShortFrom with Shortform. |
| | 139 | |
| | 140 | 2007-02-11 H.J. Lu <hongjiu.lu@intel.com> |
| | 141 | |
| | 142 | PR gas/4027 |
| | 143 | * i386.h (i386_optab): Put the real "test" before the pseudo |
| | 144 | one. |
| | 145 | |
| | 146 | 2007-01-08 Kazu Hirata <kazu@codesourcery.com> |
| | 147 | |
| | 148 | * m68k.h (m68010up): OR fido_a. |
| | 149 | |
| | 150 | 2006-12-25 Kazu Hirata <kazu@codesourcery.com> |
| | 151 | |
| | 152 | * m68k.h (fido_a): New. |
| | 153 | |
| | 154 | 2006-12-24 Kazu Hirata <kazu@codesourcery.com> |
| | 155 | |
| | 156 | * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a, |
| | 157 | mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined |
| | 158 | values. |
| | 159 | |
| | 160 | 2006-11-08 H.J. Lu <hongjiu.lu@intel.com> |
| | 161 | |
| | 162 | * i386.h (i386_optab): Replace CpuPNI with CpuSSE3. |
| | 163 | |
| | 164 | 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn> |
| | 165 | |
| | 166 | * score-inst.h (enum score_insn_type): Add Insn_internal. |
| | 167 | |
| | 168 | 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> |
| | 169 | Yukishige Shibata <shibata@rd.scei.sony.co.jp> |
| | 170 | Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp> |
| | 171 | Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp> |
| | 172 | Alan Modra <amodra@bigpond.net.au> |
| | 173 | |
| | 174 | * spu-insns.h: New file. |
| | 175 | * spu.h: New file. |
| | 176 | |
| | 177 | 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com> |
| | 178 | |
| | 179 | * ppc.h (PPC_OPCODE_CELL): Define. |
| | 180 | |
| | 181 | 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> |
| | 182 | |
| | 183 | * i386.h : Modify opcode to support for the change in POPCNT opcode |
| | 184 | in amdfam10 architecture. |
| | 185 | |
| | 186 | 2006-09-28 H.J. Lu <hongjiu.lu@intel.com> |
| | 187 | |
| | 188 | * i386.h: Replace CpuMNI with CpuSSSE3. |
| | 189 | |
| | 190 | 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> |
| | 191 | Joseph Myers <joseph@codesourcery.com> |
| | 192 | Ian Lance Taylor <ian@wasabisystems.com> |
| | 193 | Ben Elliston <bje@wasabisystems.com> |
| | 194 | |
| | 195 | * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. |
| | 196 | |
| | 197 | 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn> |
| | 198 | |
| | 199 | * score-datadep.h: New file. |
| | 200 | * score-inst.h: New file. |
| | 201 | |
| | 202 | 2006-07-14 H.J. Lu <hongjiu.lu@intel.com> |
| | 203 | |
| | 204 | * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps, |
| | 205 | movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu, |
| | 206 | movdq2q and movq2dq. |
| | 207 | |
| | 208 | 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> |
| | 209 | Michael Meissner <michael.meissner@amd.com> |
| | 210 | |
| | 211 | * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions). |
| | 212 | |
| | 213 | 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> |
| | 214 | |
| | 215 | * i386.h (i386_optab): Add "nop" with memory reference. |
| | 216 | |
| | 217 | 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> |
| | 218 | |
| | 219 | * i386.h (i386_optab): Update comment for 64bit NOP. |
| | 220 | |
| | 221 | 2006-06-06 Ben Elliston <bje@au.ibm.com> |
| | 222 | Anton Blanchard <anton@samba.org> |
| | 223 | |
| | 224 | * ppc.h (PPC_OPCODE_POWER6): Define. |
| | 225 | Adjust whitespace. |
| | 226 | |
| | 227 | 2006-06-05 Thiemo Seufer <ths@mips.com> |
| | 228 | |
| | 229 | * mips.h: Improve description of MT flags. |
| | 230 | |
| | 231 | 2006-05-25 Richard Sandiford <richard@codesourcery.com> |
| | 232 | |
| | 233 | * m68k.h (mcf_mask): Define. |
| | 234 | |
| | 235 | 2006-05-05 Thiemo Seufer <ths@mips.com> |
| | 236 | David Ung <davidu@mips.com> |
| | 237 | |
| | 238 | * mips.h (enum): Add macro M_CACHE_AB. |
| | 239 | |
| | 240 | 2006-05-04 Thiemo Seufer <ths@mips.com> |
| | 241 | Nigel Stephens <nigel@mips.com> |
| | 242 | David Ung <davidu@mips.com> |
| | 243 | |
| | 244 | * mips.h: Add INSN_SMARTMIPS define. |
| | 245 | |
| | 246 | 2006-04-30 Thiemo Seufer <ths@mips.com> |
| | 247 | David Ung <davidu@mips.com> |
| | 248 | |
| | 249 | * mips.h: Defines udi bits and masks. Add description of |
| | 250 | characters which may appear in the args field of udi |
| | 251 | instructions. |
| | 252 | |
| | 253 | 2006-04-26 Thiemo Seufer <ths@networkno.de> |
| | 254 | |
| | 255 | * mips.h: Improve comments describing the bitfield instruction |
| | 256 | fields. |
| | 257 | |
| | 258 | 2006-04-26 Julian Brown <julian@codesourcery.com> |
| | 259 | |
| | 260 | * arm.h (FPU_VFP_EXT_V3): Define constant. |
| | 261 | (FPU_NEON_EXT_V1): Likewise. |
| | 262 | (FPU_VFP_HARD): Update. |
| | 263 | (FPU_VFP_V3): Define macro. |
| | 264 | (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros. |
| | 265 | |
| | 266 | 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de> |
| | 267 | |
| | 268 | * avr.h (AVR_ISA_PWMx): New. |
| | 269 | |
| | 270 | 2006-03-28 Nathan Sidwell <nathan@codesourcery.com> |
| | 271 | |
| | 272 | * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010, |
| | 273 | cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851, |
| | 274 | cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e, |
| | 275 | cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x, |
| | 276 | cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove. |
| | 277 | |
| | 278 | 2006-03-10 Paul Brook <paul@codesourcery.com> |
| | 279 | |
| | 280 | * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions. |
| | 281 | |
| | 282 | 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| | 283 | |
| | 284 | * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come |
| | 285 | first. Correct mask of bb "B" opcode. |
| | 286 | |
| | 287 | 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> |
| | 288 | |
| | 289 | * i386.h (i386_optab): Support Intel Merom New Instructions. |
| | 290 | |
| | 291 | 2006-02-24 Paul Brook <paul@codesourcery.com> |
| | 292 | |
| | 293 | * arm.h: Add V7 feature bits. |
| | 294 | |
| | 295 | 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> |
| | 296 | |
| | 297 | * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. |
| | 298 | |
| | 299 | 2006-01-31 Paul Brook <paul@codesourcery.com> |
| | 300 | Richard Earnshaw <rearnsha@arm.com> |
| | 301 | |
| | 302 | * arm.h: Use ARM_CPU_FEATURE. |
| | 303 | (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New. |
| | 304 | (arm_feature_set): Change to a structure. |
| | 305 | (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, |
| | 306 | ARM_FEATURE): New macros. |
| | 307 | |
| | 308 | 2005-12-07 Hans-Peter Nilsson <hp@axis.com> |
| | 309 | |
| | 310 | * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS) |
| | 311 | (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros. |
| | 312 | (ADD_PC_INCR_OPCODE): Don't define. |
| | 313 | |
| | 314 | 2005-12-06 H.J. Lu <hongjiu.lu@intel.com> |
| | 315 | |
| | 316 | PR gas/1874 |
| | 317 | * i386.h (i386_optab): Add 64bit support for monitor and mwait. |
| | 318 | |
| | 319 | 2005-11-14 David Ung <davidu@mips.com> |
| | 320 | |
| | 321 | * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore |
| | 322 | instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for |
| | 323 | save/restore encoding of the args field. |
| | 324 | |
| | 325 | 2005-10-28 Dave Brolley <brolley@redhat.com> |
| | 326 | |
| | 327 | Contribute the following changes: |
| | 328 | 2005-02-16 Dave Brolley <brolley@redhat.com> |
| | 329 | |
| | 330 | * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename |
| | 331 | cgen_isa_mask_* to cgen_bitset_*. |
| | 332 | * cgen.h: Likewise. |
| | 333 | |
| | 334 | 2003-10-21 Richard Sandiford <rsandifo@redhat.com> |
| | 335 | |
| | 336 | * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition. |
| | 337 | (CGEN_ATTR_ENTRY): Change "value" to type "unsigned". |
| | 338 | (CGEN_CPU_TABLE): Make isas a ponter. |
| | 339 | |
| | 340 | 2003-09-29 Dave Brolley <brolley@redhat.com> |
| | 341 | |
| | 342 | * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef. |
| | 343 | (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto. |
| | 344 | (CGEN_ATTR_VALUE_TYPE): Use these new typedefs. |
| | 345 | |
| | 346 | 2002-12-13 Dave Brolley <brolley@redhat.com> |
| | 347 | |
| | 348 | * cgen.h (symcat.h): #include it. |
| | 349 | (cgen-bitset.h): #include it. |
| | 350 | (CGEN_ATTR_VALUE_TYPE): Now a union. |
| | 351 | (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h. |
| | 352 | (CGEN_ATTR_ENTRY): 'value' now unsigned. |
| | 353 | (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*). |
| | 354 | * cgen-bitset.h: New file. |
| | 355 | |
| | 356 | 2005-09-30 Catherine Moore <clm@cm00re.com> |
| | 357 | |
| | 358 | * bfin.h: New file. |
| | 359 | |
| | 360 | 2005-10-24 Jan Beulich <jbeulich@novell.com> |
| | 361 | |
| | 362 | * ia64.h (enum ia64_opnd): Move memory operand out of set of |
| | 363 | indirect operands. |
| | 364 | |
| | 365 | 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| | 366 | |
| | 367 | * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes. |
| | 368 | Add FLAG_STRICT to pa10 ftest opcode. |
| | 369 | |
| | 370 | 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| | 371 | |
| | 372 | * hppa.h (pa_opcodes): Remove lha entries. |
| | 373 | |
| | 374 | 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| | 375 | |
| | 376 | * hppa.h (FLAG_STRICT): Revise comment. |
| | 377 | (pa_opcode): Revise ordering rules. Add/move strict pa10 variants |
| | 378 | before corresponding pa11 opcodes. Add strict pa10 register-immediate |
| | 379 | entries for "fdc". |
| | 380 | |
| | 381 | 2005-09-30 Catherine Moore <clm@cm00re.com> |
| | 382 | |
| | 383 | * bfin.h: New file. |
| | 384 | |
| | 385 | 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| | 386 | |
| | 387 | * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries. |
| | 388 | |
| | 389 | 2005-09-06 Chao-ying Fu <fu@mips.com> |
| | 390 | |
| | 391 | * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H, |
| | 392 | OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New |
| | 393 | define. |
| | 394 | Document !, $, *, &, g, +t, +T operand formats for MT instructions. |
| | 395 | (INSN_ASE_MASK): Update to include INSN_MT. |
| | 396 | (INSN_MT): New define for MT ASE. |
| | 397 | |
| | 398 | 2005-08-25 Chao-ying Fu <fu@mips.com> |
| | 399 | |
| | 400 | * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S, |
| | 401 | OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7, |
| | 402 | OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4, |
| | 403 | OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP, |
| | 404 | OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define. |
| | 405 | Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP |
| | 406 | instructions. |
| | 407 | (INSN_DSP): New define for DSP ASE. |
| | 408 | |
| | 409 | 2005-08-18 Alan Modra <amodra@bigpond.net.au> |
| | 410 | |
| | 411 | * a29k.h: Delete. |
| | 412 | |
| | 413 | 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com> |
| | 414 | |
| | 415 | * ppc.h (PPC_OPCODE_E300): Define. |
| | 416 | |
| | 417 | 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com> |
| | 418 | |
| | 419 | * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109. |
| | 420 | |
| | 421 | 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| | 422 | |
| | 423 | PR gas/336 |
| | 424 | * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb |
| | 425 | and pitlb. |
| | 426 | |
| | 427 | 2005-07-27 Jan Beulich <jbeulich@novell.com> |
| | 428 | |
| | 429 | * i386.h (i386_optab): Add comment to movd. Use LongMem for all |
| | 430 | movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers. |
| | 431 | Add movq-s as 64-bit variants of movd-s. |
| | 432 | |
| | 433 | 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| | 434 | |
| | 435 | * hppa.h: Fix punctuation in comment. |
| | 436 | |
| | 437 | * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for |
| | 438 | implicit space-register addressing. Set space-register bits on opcodes |
| | 439 | using implicit space-register addressing. Add various missing pa20 |
| | 440 | long-immediate opcodes. Remove various opcodes using implicit 3-bit |
| | 441 | space-register addressing. Use "fE" instead of "fe" in various |
| | 442 | fstw opcodes. |
| | 443 | |
| | 444 | 2005-07-18 Jan Beulich <jbeulich@novell.com> |
| | 445 | |
| | 446 | * i386.h (i386_optab): Operands of aam and aad are unsigned. |
| | 447 | |
| | 448 | 2007-07-15 H.J. Lu <hongjiu.lu@intel.com> |
| | 449 | |
| | 450 | * i386.h (i386_optab): Support Intel VMX Instructions. |
| | 451 | |
| | 452 | 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| | 453 | |
| | 454 | * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores. |
| | 455 | |
| | 456 | 2005-07-05 Jan Beulich <jbeulich@novell.com> |
| | 457 | |
| | 458 | * i386.h (i386_optab): Add new insns. |
| | 459 | |
| | 460 | 2005-07-01 Nick Clifton <nickc@redhat.com> |
| | 461 | |
| | 462 | * sparc.h: Add typedefs to structure declarations. |
| | 463 | |
| | 464 | 2005-06-20 H.J. Lu <hongjiu.lu@intel.com> |
| | 465 | |
| | 466 | PR 1013 |
| | 467 | * i386.h (i386_optab): Update comments for 64bit addressing on |
| | 468 | mov. Allow 64bit addressing for mov and movq. |
| | 469 | |
| | 470 | 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| | 471 | |
| | 472 | * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx, |
| | 473 | respectively, in various floating-point load and store patterns. |
| | 474 | |
| | 475 | 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| | 476 | |
| | 477 | * hppa.h (FLAG_STRICT): Correct comment. |
| | 478 | (pa_opcodes): Update load and store entries to allow both PA 1.X and |
| | 479 | PA 2.0 mneumonics when equivalent. Entries with cache control |
| | 480 | completers now require PA 1.1. Adjust whitespace. |
| | 481 | |
| | 482 | 2005-05-19 Anton Blanchard <anton@samba.org> |
| | 483 | |
| | 484 | * ppc.h (PPC_OPCODE_POWER5): Define. |
| | 485 | |
| | 486 | 2005-05-10 Nick Clifton <nickc@redhat.com> |
| | 487 | |
| | 488 | * Update the address and phone number of the FSF organization in |
| | 489 | the GPL notices in the following files: |
| | 490 | a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h, |
| | 491 | crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h, |
| | 492 | i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h, |
| | 493 | mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h, |
| | 494 | pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h, |
| | 495 | tic54x.h, tic80.h, v850.h, vax.h |
| | 496 | |
| | 497 | 2005-05-09 Jan Beulich <jbeulich@novell.com> |
| | 498 | |
| | 499 | * i386.h (i386_optab): Add ht and hnt. |
| | 500 | |
| | 501 | 2005-04-18 Mark Kettenis <kettenis@gnu.org> |
| | 502 | |
| | 503 | * i386.h: Insert hyphens into selected VIA PadLock extensions. |
| | 504 | Add xcrypt-ctr. Provide aliases without hyphens. |
| | 505 | |
| | 506 | 2005-04-13 H.J. Lu <hongjiu.lu@intel.com> |
| | 507 | |
| | 508 | Moved from ../ChangeLog |
| | 509 | |
| | 510 | 2005-04-12 Paul Brook <paul@codesourcery.com> |
| | 511 | * m88k.h: Rename psr macros to avoid conflicts. |
| | 512 | |
| | 513 | 2005-03-12 Zack Weinberg <zack@codesourcery.com> |
| | 514 | * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. |
| | 515 | Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, |
| | 516 | and ARM_ARCH_V6ZKT2. |
| | 517 | |
| | 518 | 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com> |
| | 519 | * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4. |
| | 520 | Remove redundant instruction types. |
| | 521 | (struct argument): X_op - new field. |
| | 522 | (struct cst4_entry): Remove. |
| | 523 | (no_op_insn): Declare. |
| | 524 | |
| | 525 | 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com> |
| | 526 | * crx.h (enum argtype): Rename types, remove unused types. |
| | 527 | |
| | 528 | 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com> |
| | 529 | * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'. |
| | 530 | (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE. |
| | 531 | (enum operand_type): Rearrange operands, edit comments. |
| | 532 | replace us<N> with ui<N> for unsigned immediate. |
| | 533 | replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped |
| | 534 | displacements (respectively). |
| | 535 | replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index. |
| | 536 | (instruction type): Add NO_TYPE_INS. |
| | 537 | (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR. |
| | 538 | (operand_entry): New field - 'flags'. |
| | 539 | (operand flags): New. |
| | 540 | |
| | 541 | 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com> |
| | 542 | * crx.h (operand_type): Remove redundant types i3, i4, |
| | 543 | i5, i8, i12. |
| | 544 | Add new unsigned immediate types us3, us4, us5, us16. |
| | 545 | |
| | 546 | 2005-04-12 Mark Kettenis <kettenis@gnu.org> |
| | 547 | |
| | 548 | * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and |
| | 549 | adjust them accordingly. |
| | 550 | |
| | 551 | 2005-04-01 Jan Beulich <jbeulich@novell.com> |
| | 552 | |
| | 553 | * i386.h (i386_optab): Add rdtscp. |
| | 554 | |
| | 555 | 2005-03-29 H.J. Lu <hongjiu.lu@intel.com> |
| | 556 | |
| | 557 | * i386.h (i386_optab): Don't allow the `l' suffix for moving |
| | 558 | between memory and segment register. Allow movq for moving between |
| | 559 | general-purpose register and segment register. |
| | 560 | |
| | 561 | 2005-02-09 Jan Beulich <jbeulich@novell.com> |
| | 562 | |
| | 563 | PR gas/707 |
| | 564 | * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and |
| | 565 | FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and |
| | 566 | fnstsw. |
| | 567 | |
| | 568 | 2006-02-07 Nathan Sidwell <nathan@codesourcery.com> |
| | 569 | |
| | 570 | * m68k.h (m68008, m68ec030, m68882): Remove. |
| | 571 | (m68k_mask): New. |
| | 572 | (cpu_m68k, cpu_cf): New. |
| | 573 | (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407, |
| | 574 | mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants. |
| | 575 | |
| | 576 | 2005-01-25 Alexandre Oliva <aoliva@redhat.com> |
| | 577 | |
| | 578 | 2004-11-10 Alexandre Oliva <aoliva@redhat.com> |
| | 579 | * cgen.h (enum cgen_parse_operand_type): Add |
| | 580 | CGEN_PARSE_OPERAND_SYMBOLIC. |
| | 581 | |
| | 582 | 2005-01-21 Fred Fish <fnf@specifixinc.com> |
| | 583 | |
| | 584 | * mips.h: Change INSN_ALIAS to INSN2_ALIAS. |
| | 585 | Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. |
| | 586 | Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. |
| | 587 | |
| | 588 | 2005-01-19 Fred Fish <fnf@specifixinc.com> |
| | 589 | |
| | 590 | * mips.h (struct mips_opcode): Add new pinfo2 member. |
| | 591 | (INSN_ALIAS): New define for opcode table entries that are |
| | 592 | specific instances of another entry, such as 'move' for an 'or' |
| | 593 | with a zero operand. |
| | 594 | (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. |
| | 595 | (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. |
| | 596 | |
| | 597 | 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com> |
| | 598 | |
| | 599 | * mips.h (CPU_RM9000): Define. |
| | 600 | (OPCODE_IS_MEMBER): Handle CPU_RM9000. |
| | 601 | |
| | 602 | 2004-11-25 Jan Beulich <jbeulich@novell.com> |
| | 603 | |
| | 604 | * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves |
| | 605 | to/from test registers are illegal in 64-bit mode. Add missing |
| | 606 | NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix |
| | 607 | (previously one had to explicitly encode a rex64 prefix). Re-enable |
| | 608 | lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings |
| | 609 | support it there. Add cmpxchg16b as per Intel's 64-bit documentation. |
| | 610 | |
| | 611 | 2004-11-23 Jan Beulich <jbeulich@novell.com> |
| | 612 | |
| | 613 | * i386.h (i386_optab): paddq and psubq, even in their MMX form, are |
| | 614 | available only with SSE2. Change the MMX additions introduced by SSE |
| | 615 | and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A |
| | 616 | instructions by their now designated identifier (since combining i686 |
| | 617 | and 3DNow! does not really imply 3DNow!A). |
| | 618 | |
| | 619 | 2004-11-19 Alan Modra <amodra@bigpond.net.au> |
| | 620 | |
| | 621 | * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, |
| | 622 | struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. |
| | 623 | |
| | 624 | 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> |
| | 625 | Vineet Sharma <vineets@noida.hcltech.com> |
| | 626 | |
| | 627 | * maxq.h: New file: Disassembly information for the maxq port. |
| | 628 | |
| | 629 | 2004-11-05 H.J. Lu <hongjiu.lu@intel.com> |
| | 630 | |
| | 631 | * i386.h (i386_optab): Put back "movzb". |
| | 632 | |
| | 633 | 2004-11-04 Hans-Peter Nilsson <hp@axis.com> |
| | 634 | |
| | 635 | * cris.h (enum cris_insn_version_usage): Tweak formatting and |
| | 636 | comments. Remove member cris_ver_sim. Add members |
| | 637 | cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, |
| | 638 | cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. |
| | 639 | (struct cris_support_reg, struct cris_cond15): New types. |
| | 640 | (cris_conds15): Declare. |
| | 641 | (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) |
| | 642 | (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) |
| | 643 | (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. |
| | 644 | (NOP_Z_BITS): Define in terms of NOP_OPCODE. |
| | 645 | (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and |
| | 646 | SIZE_FIELD_UNSIGNED. |
| | 647 | |
| | 648 | 2004-11-04 Jan Beulich <jbeulich@novell.com> |
| | 649 | |
| | 650 | * i386.h (sldx_Suf): Remove. |
| | 651 | (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. |
| | 652 | (q_FP): Define, implying no REX64. |
| | 653 | (x_FP, sl_FP): Imply FloatMF. |
| | 654 | (i386_optab): Split reg and mem forms of moving from segment registers |
| | 655 | so that the memory forms can ignore the 16-/32-bit operand size |
| | 656 | distinction. Adjust a few others for Intel mode. Remove *FP uses from |
| | 657 | all non-floating-point instructions. Unite 32- and 64-bit forms of |
| | 658 | movsx, movzx, and movd. Adjust floating point operations for the above |
| | 659 | changes to the *FP macros. Add DefaultSize to floating point control |
| | 660 | insns operating on larger memory ranges. Remove left over comments |
| | 661 | hinting at certain insns being Intel-syntax ones where the ones |
| | 662 | actually meant are already gone. |
| | 663 | |
| | 664 | 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com> |
| | 665 | |
| | 666 | * crx.h: Add COPS_REG_INS - Coprocessor Special register |
| | 667 | instruction type. |
| | 668 | |
| | 669 | 2004-09-30 Paul Brook <paul@codesourcery.com> |
| | 670 | |
| | 671 | * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. |
| | 672 | (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. |
| | 673 | |
| | 674 | 2004-09-11 Theodore A. Roth <troth@openavr.org> |
| | 675 | |
| | 676 | * avr.h: Add support for |
| | 677 | atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. |
| | 678 | |
| | 679 | 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org> |
| | 680 | |
| | 681 | * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. |
| | 682 | |
| | 683 | 2004-08-24 Dmitry Diky <diwil@spec.ru> |
| | 684 | |
| | 685 | * msp430.h (msp430_opc): Add new instructions. |
| | 686 | (msp430_rcodes): Declare new instructions. |
| | 687 | (msp430_hcodes): Likewise.. |
| | 688 | |
| | 689 | 2004-08-13 Nick Clifton <nickc@redhat.com> |
| | 690 | |
| | 691 | PR/301 |
| | 692 | * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX |
| | 693 | processors. |
| | 694 | |
| | 695 | 2004-08-30 Michal Ludvig <mludvig@suse.cz> |
| | 696 | |
| | 697 | * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. |
| | 698 | |
| | 699 | 2004-07-22 H.J. Lu <hongjiu.lu@intel.com> |
| | 700 | |
| | 701 | * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. |
| | 702 | |
| | 703 | 2004-07-21 Jan Beulich <jbeulich@novell.com> |
| | 704 | |
| | 705 | * i386.h: Adjust instruction descriptions to better match the |
| | 706 | specification. |
| | 707 | |
| | 708 | 2004-07-16 Richard Earnshaw <rearnsha@arm.com> |
| | 709 | |
| | 710 | * arm.h: Remove all old content. Replace with architecture defines |
| | 711 | from gas/config/tc-arm.c. |
| | 712 | |
| | 713 | 2004-07-09 Andreas Schwab <schwab@suse.de> |
| | 714 | |
| | 715 | * m68k.h: Fix comment. |
| | 716 | |
| | 717 | 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com> |
| | 718 | |
| | 719 | * crx.h: New file. |
| | 720 | |
| | 721 | 2004-06-24 Alan Modra <amodra@bigpond.net.au> |
| | 722 | |
| | 723 | * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. |
| | 724 | |
| | 725 | 2004-05-24 Peter Barada <peter@the-baradas.com> |
| | 726 | |
| | 727 | * m68k.h: Add 'size' to m68k_opcode. |
| | 728 | |
| | 729 | 2004-05-05 Peter Barada <peter@the-baradas.com> |
| | 730 | |
| | 731 | * m68k.h: Switch from ColdFire chip name to core variant. |
| | 732 | |
| | 733 | 2004-04-22 Peter Barada <peter@the-baradas.com> |
| | 734 | |
| | 735 | * m68k.h: Add mcfmac/mcfemac definitions. Update operand |
| | 736 | descriptions for new EMAC cases. |
| | 737 | Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly |
| | 738 | handle Motorola MAC syntax. |
| | 739 | Allow disassembly of ColdFire V4e object files. |
| | 740 | |
| | 741 | 2004-03-16 Alan Modra <amodra@bigpond.net.au> |
| | 742 | |
| | 743 | * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. |
| | 744 | |
| | 745 | 2004-03-12 Jakub Jelinek <jakub@redhat.com> |
| | 746 | |
| | 747 | * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. |
| | 748 | |
| | 749 | 2004-03-12 Michal Ludvig <mludvig@suse.cz> |
| | 750 | |
| | 751 | * i386.h (i386_optab): Added xstore as an alias for xstorerng. |
| | 752 | |
| | 753 | 2004-03-12 Michal Ludvig <mludvig@suse.cz> |
| | 754 | |
| | 755 | * i386.h (i386_optab): Added xstore/xcrypt insns. |
| | 756 | |
| | 757 | 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> |
| | 758 | |
| | 759 | * h8300.h (32bit ldc/stc): Add relaxing support. |
| | 760 | |
| | 761 | 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> |
| | 762 | |
| | 763 | * h8300.h (BITOP): Pass MEMRELAX flag. |
| | 764 | |
| | 765 | 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com> |
| | 766 | |
| | 767 | * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 |
| | 768 | except for the H8S. |
| | 769 | |
| | 770 | For older changes see ChangeLog-9103 |
| | 771 | \f |
| | 772 | Local Variables: |
| | 773 | mode: change-log |
| | 774 | left-margin: 8 |
| | 775 | fill-column: 74 |
| | 776 | version-control: never |
| | 777 | End: |
projects / deliverable / binutils-gdb.git / blame_incremental