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Consolidate Thumb-1/Thumb-2 ISA detection
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
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CommitLineData
12015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
2
3 * arm.h (ARM_ARCH_THUMB2): Add comment explaining its meaning and
4 remove extension bit not including any Thumb-2 instruction.
5
62015-12-15 Matthew Wahab <matthew.wahab@arm.com>
7
8 * arm.h (ARM_ARCH_V8_1A): Add the CRC_EXT_ARMV8 co-processor
9 feature macro.
10 (ARM_ARCH_V8_2A): Likewise.
11
122015-12-14 Matthew Wahab <matthew.wahab@arm.com>
13
14 * aarch64.h (enum aarch64_opnd_qualifier): Add
15 AARCH64_OPND_QLF_V_2H.
16
172015-12-14 Yoshinori Sato <ysato@users.sourceforge.jp>
18
19 * rx.h: Add new instructions.
20
212015-12-11 Matthew Wahab <matthew.wahab@arm.com>
22
23 * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
24 * aarch64-asm-2.c: Regenerate.
25 * aarch64-dis-2.c: Regenerate.
26 * aarch64-opc-2.c: Regenerate.
27 * aarch64-opc.c (aarch64_hint_options): Add "csync".
28 (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB.
29 * aarch64-tbl.h (aarch64_feature_stat_profile): New.
30 (STAT_PROFILE): New.
31 (aarch64_opcode_table): Add "psb".
32 (AARCH64_OPERANDS): Add "BARRIER_PSB".
33
342015-12-11 Matthew Wahab <matthew.wahab@arm.com>
35
36 * aarch64.h (aarch64_hint_options): Declare.
37 (aarch64_opnd_info): Add field hint_option.
38
392015-12-11 Matthew Wahab <matthew.wahab@arm.com>
40
41 * aarch64.h (AARCH64_FEATURE_PROFILE): New.
42
432015-12-10 Matthew Wahab <matthew.wahab@arm.com>
44
45 * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
46
472015-12-10 Matthew Wahab <matthew.wahab@arm.com>
48
49 * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
50 (aarch64_sys_ins_reg_has_xt): Declare.
51
522015-12-10 Matthew Wahab <matthew.wahab@arm.com>
53
54 * aarch64.h (AARCH64_FEATURE_RAS): New.
55 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
56
572015-12-10 Matthew Wahab <matthew.wahab@arm.com>
58
59 * aarch64.h (AARCH64_FEATURE_F16): Fix clash with
60 AARCH64_FEATURE_V8_1.
61 (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
62 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
63 AARCH64_FEATURE_V8_1.
64
652015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
66
67 * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].
68
692015-11-27 Matthew Wahab <matthew.wahab@arm.com>
70
71 * aarch64.h (aarch64_op): Add OP_BFC.
72
732015-11-27 Matthew Wahab <matthew.wahab@arm.com>
74
75 * aarch64.h (AARCH64_FEATURE_F16): New.
76 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
77 features.
78
792015-11-20 Matthew Wahab <matthew.wahab@arm.com>
80
81 * aarch64.h (AARCH64_FEATURE_V8_1): New.
82 (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
83
842015-11-19 Matthew Wahab <matthew.wahab@arm.com>
85
86 * arm.h (ARM_EXT2_V8_2A): New.
87 (ARM_ARCH_V8_2A): New.
88
892015-11-19 Matthew Wahab <matthew.wahab@arm.com>
90
91 * aarch64.h (AARCH64_FEATURE_V8_2): New.
92 (AARCH64_ARCH_V8_2): New.
93
942015-11-11 Alan Modra <amodra@gmail.com>
95 Peter Bergner <bergner@vnet.ibm.com>
96
97 * ppc.h (PPC_OPCODE_POWER9): New define.
98 (PPC_OPCODE_VSX3): Likewise.
99
1002015-11-02 Nick Clifton <nickc@redhat.com>
101
102 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
103
1042015-11-02 Nick Clifton <nickc@redhat.com>
105
106 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
107
1082015-10-28 Yao Qi <yao.qi@linaro.org>
109
110 * aarch64.h (aarch64_decode_insn): Update declaration.
111
1122015-10-07 Yao Qi <yao.qi@linaro.org>
113
114 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
115 <name>: New field.
116
1172015-10-07 Yao Qi <yao.qi@linaro.org>
118
119 * aarch64.h [__cplusplus]: Wrap in extern "C".
120
1212015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
122 Cupertino Miranda <cmiranda@synopsys.com>
123
124 * arc-func.h: New file.
125 * arc.h: Likewise.
126
1272015-10-02 Yao Qi <yao.qi@linaro.org>
128
129 * aarch64.h (aarch64_zero_register_p): Move the declaration
130 to column one.
131
1322015-10-02 Yao Qi <yao.qi@linaro.org>
133
134 * aarch64.h (aarch64_decode_insn): Declare it.
135
1362015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
137
138 * s390.h (S390_INSTR_FLAG_HTM): New flag.
139 (S390_INSTR_FLAG_VX): New flag.
140 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
141
1422015-09-23 Nick Clifton <nickc@redhat.com>
143
144 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
145 shifting.
146
1472015-09-22 Nick Clifton <nickc@redhat.com>
148
149 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
150
1512015-09-09 Daniel Santos <daniel.santos@pobox.com>
152
153 * visium.h (gen_reg_table): Make static.
154 (fp_reg_table): Likewise.
155 (cc_table): Likewise.
156
1572015-07-20 Matthew Wahab <matthew.wahab@arm.com>
158
159 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
160 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
161 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
162 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
163
1642015-07-03 Alan Modra <amodra@gmail.com>
165
166 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
167
1682015-07-01 Sandra Loosemore <sandra@codesourcery.com>
169 Cesar Philippidis <cesar@codesourcery.com>
170
171 * nios2.h (enum iw_format_type): Add R2 formats.
172 (enum overflow_type): Add signed_immed12_overflow and
173 enumeration_overflow for R2.
174 (struct nios2_opcode): Document new argument letters for R2.
175 (REG_3BIT, REG_LDWM, REG_POP): Define.
176 (includes): Include nios2r2.h.
177 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
178 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
179 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
180 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
181 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
182 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
183 Declare.
184 * nios2r2.h: New file.
185
1862015-06-19 Peter Bergner <bergner@vnet.ibm.com>
187
188 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
189 (ppc_optional_operand_value): New inline function.
190
1912015-06-04 Matthew Wahab <matthew.wahab@arm.com>
192
193 * aarch64.h (AARCH64_V8_1): New.
194
1952015-06-03 Matthew Wahab <matthew.wahab@arm.com>
196
197 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
198 (ARM_ARCH_V8_1A): New.
199 (ARM_ARCH_V8_1A_FP): New.
200 (ARM_ARCH_V8_1A_SIMD): New.
201 (ARM_ARCH_V8_1A_CRYPTOV1): New.
202 (ARM_FEATURE_CORE): New.
203
2042015-06-02 Matthew Wahab <matthew.wahab@arm.com>
205
206 * arm.h (ARM_EXT2_PAN): New.
207 (ARM_FEATURE_CORE_HIGH): New.
208
2092015-06-02 Matthew Wahab <matthew.wahab@arm.com>
210
211 * arm.h (ARM_FEATURE_ALL): New.
212
2132015-06-02 Matthew Wahab <matthew.wahab@arm.com>
214
215 * aarch64.h (AARCH64_FEATURE_RDMA): New.
216
2172015-06-02 Matthew Wahab <matthew.wahab@arm.com>
218
219 * aarch64.h (AARCH64_FEATURE_LOR): New.
220
2212015-06-01 Matthew Wahab <matthew.wahab@arm.com>
222
223 * aarch64.h (AARCH64_FEATURE_PAN): New.
224 (aarch64_sys_reg_supported_p): Declare.
225 (aarch64_pstatefield_supported_p): Declare.
226
2272015-04-30 DJ Delorie <dj@redhat.com>
228
229 * rl78.h (RL78_Dis_Isa): New.
230 (rl78_decode_opcode): Add ISA parameter.
231
2322015-03-24 Terry Guo <terry.guo@arm.com>
233
234 * arm.h (arm_feature_set): Extended to provide more available bits.
235 (ARM_ANY): Updated to follow above new definition.
236 (ARM_CPU_HAS_FEATURE): Likewise.
237 (ARM_CPU_IS_ANY): Likewise.
238 (ARM_MERGE_FEATURE_SETS): Likewise.
239 (ARM_CLEAR_FEATURE): Likewise.
240 (ARM_FEATURE): Likewise.
241 (ARM_FEATURE_COPY): New macro.
242 (ARM_FEATURE_EQUAL): Likewise.
243 (ARM_FEATURE_ZERO): Likewise.
244 (ARM_FEATURE_CORE_EQUAL): Likewise.
245 (ARM_FEATURE_LOW): Likewise.
246 (ARM_FEATURE_CORE_LOW): Likewise.
247 (ARM_FEATURE_CORE_COPROC): Likewise.
248
2492015-02-19 Pedro Alves <palves@redhat.com>
250
251 * cgen.h [__cplusplus]: Wrap in extern "C".
252 * msp430-decode.h [__cplusplus]: Likewise.
253 * nios2.h [__cplusplus]: Likewise.
254 * rl78.h [__cplusplus]: Likewise.
255 * rx.h [__cplusplus]: Likewise.
256 * tilegx.h [__cplusplus]: Likewise.
257
2582015-01-28 James Bowman <james.bowman@ftdichip.com>
259
260 * ft32.h: New file.
261
2622015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
263
264 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
265
2662015-01-01 Alan Modra <amodra@gmail.com>
267
268 Update year range in copyright notice of all files.
269
2702014-12-27 Anthony Green <green@moxielogic.com>
271
272 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
273 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
274
2752014-12-06 Eric Botcazou <ebotcazou@adacore.com>
276
277 * visium.h: New file.
278
2792014-11-28 Sandra Loosemore <sandra@codesourcery.com>
280
281 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
282 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
283 (NIOS2_INSN_OPTARG): Renumber.
284
2852014-11-06 Sandra Loosemore <sandra@codesourcery.com>
286
287 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
288 declaration. Fix obsolete comment.
289
2902014-10-23 Sandra Loosemore <sandra@codesourcery.com>
291
292 * nios2.h (enum iw_format_type): New.
293 (struct nios2_opcode): Update comments. Add size and format fields.
294 (NIOS2_INSN_OPTARG): New.
295 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
296 (struct nios2_reg): Add regtype field.
297 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
298 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
299 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
300 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
301 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
302 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
303 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
304 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
305 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
306 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
307 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
308 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
309 (OP_MASK_OP, OP_SH_OP): Delete.
310 (OP_MASK_IOP, OP_SH_IOP): Delete.
311 (OP_MASK_IRD, OP_SH_IRD): Delete.
312 (OP_MASK_IRT, OP_SH_IRT): Delete.
313 (OP_MASK_IRS, OP_SH_IRS): Delete.
314 (OP_MASK_ROP, OP_SH_ROP): Delete.
315 (OP_MASK_RRD, OP_SH_RRD): Delete.
316 (OP_MASK_RRT, OP_SH_RRT): Delete.
317 (OP_MASK_RRS, OP_SH_RRS): Delete.
318 (OP_MASK_JOP, OP_SH_JOP): Delete.
319 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
320 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
321 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
322 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
323 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
324 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
325 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
326 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
327 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
328 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
329 (OP_MASK_<insn>, OP_MASK): Delete.
330 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
331 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
332 Include nios2r1.h to define new instruction opcode constants
333 and accessors.
334 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
335 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
336 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
337 (NUMOPCODES, NUMREGISTERS): Delete.
338 * nios2r1.h: New file.
339
3402014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
341
342 * sparc.h (HWCAP2_VIS3B): Documentation improved.
343
3442014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
345
346 * sparc.h (sparc_opcode): new field `hwcaps2'.
347 (HWCAP2_FJATHPLUS): New define.
348 (HWCAP2_VIS3B): Likewise.
349 (HWCAP2_ADP): Likewise.
350 (HWCAP2_SPARC5): Likewise.
351 (HWCAP2_MWAIT): Likewise.
352 (HWCAP2_XMPMUL): Likewise.
353 (HWCAP2_XMONT): Likewise.
354 (HWCAP2_NSEC): Likewise.
355 (HWCAP2_FJATHHPC): Likewise.
356 (HWCAP2_FJDES): Likewise.
357 (HWCAP2_FJAES): Likewise.
358 Document the new operand kind `{', corresponding to the mcdper
359 ancillary state register.
360 Document the new operand kind }, which represents frsd floating
361 point registers (double precision) which must be the same than
362 frs1 in its containing instruction.
363
3642014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
365
366 * nds32.h: Add new opcode declaration.
367
3682014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
369 Matthew Fortune <matthew.fortune@imgtec.com>
370
371 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
372 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
373 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
374 +I, +O, +R, +:, +\, +", +;
375 (mips_check_prev_operand): New struct.
376 (INSN2_FORBIDDEN_SLOT): New define.
377 (INSN_ISA32R6): New define.
378 (INSN_ISA64R6): New define.
379 (INSN_UPTO32R6): New define.
380 (INSN_UPTO64R6): New define.
381 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
382 (ISA_MIPS32R6): New define.
383 (ISA_MIPS64R6): New define.
384 (CPU_MIPS32R6): New define.
385 (CPU_MIPS64R6): New define.
386 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
387
3882014-09-03 Jiong Wang <jiong.wang@arm.com>
389
390 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
391 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
392 (aarch64_insn_class): Add lse_atomic.
393 (F_LSE_SZ): New field added.
394 (opcode_has_special_coder): Recognize F_LSE_SZ.
395
3962014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
397
398 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
399 over to `+J'.
400
4012014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
402
403 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
404 (INSN_LOAD_COPROC): New define.
405 (INSN_COPROC_MOVE_DELAY): Rename to...
406 (INSN_COPROC_MOVE): New define.
407
4082014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
409 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
410 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
411 Soundararajan <Sounderarajan.D@atmel.com>
412
413 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
414 (AVR_ISA_2xxxa): Define ISA without LPM.
415 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
416 Add doc for contraint used in 16 bit lds/sts.
417 Adjust ISA group for icall, ijmp, pop and push.
418 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
419
4202014-05-19 Nick Clifton <nickc@redhat.com>
421
422 * msp430.h (struct msp430_operand_s): Add vshift field.
423
4242014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
425
426 * mips.h (INSN_ISA_MASK): Updated.
427 (INSN_ISA32R3): New define.
428 (INSN_ISA32R5): New define.
429 (INSN_ISA64R3): New define.
430 (INSN_ISA64R5): New define.
431 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
432 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
433 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
434 mips64r5.
435 (INSN_UPTO32R3): New define.
436 (INSN_UPTO32R5): New define.
437 (INSN_UPTO64R3): New define.
438 (INSN_UPTO64R5): New define.
439 (ISA_MIPS32R3): New define.
440 (ISA_MIPS32R5): New define.
441 (ISA_MIPS64R3): New define.
442 (ISA_MIPS64R5): New define.
443 (CPU_MIPS32R3): New define.
444 (CPU_MIPS32R5): New define.
445 (CPU_MIPS64R3): New define.
446 (CPU_MIPS64R5): New define.
447
4482014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
449
450 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
451
4522014-04-22 Christian Svensson <blue@cmd.nu>
453
454 * or32.h: Delete.
455
4562014-03-05 Alan Modra <amodra@gmail.com>
457
458 Update copyright years.
459
4602013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
461
462 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
463 microMIPS.
464
4652013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
466 Wei-Cheng Wang <cole945@gmail.com>
467
468 * nds32.h: New file for Andes NDS32.
469
4702013-12-07 Mike Frysinger <vapier@gentoo.org>
471
472 * bfin.h: Remove +x file mode.
473
4742013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
475
476 * aarch64.h (aarch64_pstatefields): Change element type to
477 aarch64_sys_reg.
478
4792013-11-18 Renlin Li <Renlin.Li@arm.com>
480
481 * arm.h (ARM_AEXT_V7VE): New define.
482 (ARM_ARCH_V7VE): New define.
483 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
484
4852013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
486
487 Revert
488
489 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
490
491 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
492 (aarch64_sys_reg_writeonly_p): Ditto.
493
4942013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
495
496 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
497 (aarch64_sys_reg_writeonly_p): Ditto.
498
4992013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
500
501 * aarch64.h (aarch64_sys_reg): New typedef.
502 (aarch64_sys_regs): Change to define with the new type.
503 (aarch64_sys_reg_deprecated_p): Declare.
504
5052013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
506
507 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
508 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
509
5102013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
511
512 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
513 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
514 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
515 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
516 For MIPS, update extension character sequences after +.
517 (ASE_MSA): New define.
518 (ASE_MSA64): New define.
519 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
520 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
521 For microMIPS, update extension character sequences after +.
522
5232013-08-23 Yuri Chornoivan <yurchor@ukr.net>
524
525 PR binutils/15834
526 * i960.h: Fix typos.
527
5282013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
529
530 * mips.h: Remove references to "+I" and imm2_expr.
531
5322013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
533
534 * mips.h (M_DEXT, M_DINS): Delete.
535
5362013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
537
538 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
539 (mips_optional_operand_p): New function.
540
5412013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
542 Richard Sandiford <rdsandiford@googlemail.com>
543
544 * mips.h: Document new VU0 operand characters.
545 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
546 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
547 (OP_REG_R5900_ACC): New mips_reg_operand_types.
548 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
549 (mips_vu0_channel_mask): Declare.
550
5512013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
552
553 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
554 (mips_int_operand_min, mips_int_operand_max): New functions.
555 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
556
5572013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
558
559 * mips.h (mips_decode_reg_operand): New function.
560 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
561 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
562 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
563 New macros.
564 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
565 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
566 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
567 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
568 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
569 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
570 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
571 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
572 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
573 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
574 macros to cover the gaps.
575 (INSN2_MOD_SP): Replace with...
576 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
577 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
578 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
579 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
580 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
581 Delete.
582
5832013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
584
585 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
586 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
587 (MIPS16_INSN_COND_BRANCH): Delete.
588
5892013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
590 Kirill Yukhin <kirill.yukhin@intel.com>
591 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
592
593 * i386.h (BND_PREFIX_OPCODE): New.
594
5952013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
596
597 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
598 OP_SAVE_RESTORE_LIST.
599 (decode_mips16_operand): Declare.
600
6012013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
602
603 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
604 (mips_operand, mips_int_operand, mips_mapped_int_operand)
605 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
606 (mips_pcrel_operand): New structures.
607 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
608 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
609 (decode_mips_operand, decode_micromips_operand): Declare.
610
6112013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
612
613 * mips.h: Document MIPS16 "I" opcode.
614
6152013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
616
617 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
618 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
619 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
620 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
621 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
622 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
623 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
624 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
625 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
626 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
627 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
628 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
629 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
630 Rename to...
631 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
632 (M_USD_AB): ...these.
633
6342013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
635
636 * mips.h: Remove documentation of "[" and "]". Update documentation
637 of "k" and the MDMX formats.
638
6392013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
640
641 * mips.h: Update documentation of "+s" and "+S".
642
6432013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
644
645 * mips.h: Document "+i".
646
6472013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
648
649 * mips.h: Remove "mi" documentation. Update "mh" documentation.
650 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
651 Delete.
652 (INSN2_WRITE_GPR_MHI): Rename to...
653 (INSN2_WRITE_GPR_MH): ...this.
654
6552013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
656
657 * mips.h: Remove documentation of "+D" and "+T".
658
6592013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
660
661 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
662 Use "source" rather than "destination" for microMIPS "G".
663
6642013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
665
666 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
667 values.
668
6692013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
670
671 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
672
6732013-06-17 Catherine Moore <clm@codesourcery.com>
674 Maciej W. Rozycki <macro@codesourcery.com>
675 Chao-Ying Fu <fu@mips.com>
676
677 * mips.h (OP_SH_EVAOFFSET): Define.
678 (OP_MASK_EVAOFFSET): Define.
679 (INSN_ASE_MASK): Delete.
680 (ASE_EVA): Define.
681 (M_CACHEE_AB, M_CACHEE_OB): New.
682 (M_LBE_OB, M_LBE_AB): New.
683 (M_LBUE_OB, M_LBUE_AB): New.
684 (M_LHE_OB, M_LHE_AB): New.
685 (M_LHUE_OB, M_LHUE_AB): New.
686 (M_LLE_AB, M_LLE_OB): New.
687 (M_LWE_OB, M_LWE_AB): New.
688 (M_LWLE_AB, M_LWLE_OB): New.
689 (M_LWRE_AB, M_LWRE_OB): New.
690 (M_PREFE_AB, M_PREFE_OB): New.
691 (M_SCE_AB, M_SCE_OB): New.
692 (M_SBE_OB, M_SBE_AB): New.
693 (M_SHE_OB, M_SHE_AB): New.
694 (M_SWE_OB, M_SWE_AB): New.
695 (M_SWLE_AB, M_SWLE_OB): New.
696 (M_SWRE_AB, M_SWRE_OB): New.
697 (MICROMIPSOP_SH_EVAOFFSET): Define.
698 (MICROMIPSOP_MASK_EVAOFFSET): Define.
699
7002013-06-12 Sandra Loosemore <sandra@codesourcery.com>
701
702 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
703
7042013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
705
706 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
707
7082013-05-09 Andrew Pinski <apinski@cavium.com>
709
710 * mips.h (OP_MASK_CODE10): Correct definition.
711 (OP_SH_CODE10): Likewise.
712 Add a comment that "+J" is used now for OP_*CODE10.
713 (INSN_ASE_MASK): Update.
714 (INSN_VIRT): New macro.
715 (INSN_VIRT64): New macro
716
7172013-05-02 Nick Clifton <nickc@redhat.com>
718
719 * msp430.h: Add patterns for MSP430X instructions.
720
7212013-04-06 David S. Miller <davem@davemloft.net>
722
723 * sparc.h (F_PREFERRED): Define.
724 (F_PREF_ALIAS): Define.
725
7262013-04-03 Nick Clifton <nickc@redhat.com>
727
728 * v850.h (V850_INVERSE_PCREL): Define.
729
7302013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
731
732 PR binutils/15068
733 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
734
7352013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
736
737 PR binutils/15068
738 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
739 Add 16-bit opcodes.
740 * tic6xc-opcode-table.h: Add 16-bit insns.
741 * tic6x.h: Add support for 16-bit insns.
742
7432013-03-21 Michael Schewe <michael.schewe@gmx.net>
744
745 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
746 and mov.b/w/l Rs,@(d:32,ERd).
747
7482013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
749
750 PR gas/15082
751 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
752 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
753 tic6x_operand_xregpair operand coding type.
754 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
755 opcode field, usu ORXREGD1324 for the src2 operand and remove the
756 TIC6X_FLAG_NO_CROSS.
757
7582013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
759
760 PR gas/15095
761 * tic6x.h (enum tic6x_coding_method): Add
762 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
763 separately the msb and lsb of a register pair. This is needed to
764 encode the opcodes in the same way as TI assembler does.
765 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
766 and rsqrdp opcodes to use the new field coding types.
767
7682013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
769
770 * arm.h (CRC_EXT_ARMV8): New constant.
771 (ARCH_CRC_ARMV8): New macro.
772
7732013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
774
775 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
776
7772013-02-06 Sandra Loosemore <sandra@codesourcery.com>
778 Andrew Jenner <andrew@codesourcery.com>
779
780 Based on patches from Altera Corporation.
781
782 * nios2.h: New file.
783
7842013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
785
786 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
787
7882013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
789
790 PR gas/15069
791 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
792
7932013-01-24 Nick Clifton <nickc@redhat.com>
794
795 * v850.h: Add e3v5 support.
796
7972013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
798
799 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
800
8012013-01-10 Peter Bergner <bergner@vnet.ibm.com>
802
803 * ppc.h (PPC_OPCODE_POWER8): New define.
804 (PPC_OPCODE_HTM): Likewise.
805
8062013-01-10 Will Newton <will.newton@imgtec.com>
807
808 * metag.h: New file.
809
8102013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
811
812 * cr16.h (make_instruction): Rename to cr16_make_instruction.
813 (match_opcode): Rename to cr16_match_opcode.
814
8152013-01-04 Juergen Urban <JuergenUrban@gmx.de>
816
817 * mips.h: Add support for r5900 instructions including lq and sq.
818
8192013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
820
821 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
822 (make_instruction,match_opcode): Added function prototypes.
823 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
824
8252012-11-23 Alan Modra <amodra@gmail.com>
826
827 * ppc.h (ppc_parse_cpu): Update prototype.
828
8292012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
830
831 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
832 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
833
8342012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
835
836 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
837
8382012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
839
840 * ia64.h (ia64_opnd): Add new operand types.
841
8422012-08-21 David S. Miller <davem@davemloft.net>
843
844 * sparc.h (F3F4): New macro.
845
8462012-08-13 Ian Bolton <ian.bolton@arm.com>
847 Laurent Desnogues <laurent.desnogues@arm.com>
848 Jim MacArthur <jim.macarthur@arm.com>
849 Marcus Shawcroft <marcus.shawcroft@arm.com>
850 Nigel Stephens <nigel.stephens@arm.com>
851 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
852 Richard Earnshaw <rearnsha@arm.com>
853 Sofiane Naci <sofiane.naci@arm.com>
854 Tejas Belagod <tejas.belagod@arm.com>
855 Yufeng Zhang <yufeng.zhang@arm.com>
856
857 * aarch64.h: New file.
858
8592012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
860 Maciej W. Rozycki <macro@codesourcery.com>
861
862 * mips.h (mips_opcode): Add the exclusions field.
863 (OPCODE_IS_MEMBER): Remove macro.
864 (cpu_is_member): New inline function.
865 (opcode_is_member): Likewise.
866
8672012-07-31 Chao-Ying Fu <fu@mips.com>
868 Catherine Moore <clm@codesourcery.com>
869 Maciej W. Rozycki <macro@codesourcery.com>
870
871 * mips.h: Document microMIPS DSP ASE usage.
872 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
873 microMIPS DSP ASE support.
874 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
875 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
876 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
877 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
878 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
879 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
880 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
881
8822012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
883
884 * mips.h: Fix a typo in description.
885
8862012-06-07 Georg-Johann Lay <avr@gjlay.de>
887
888 * avr.h: (AVR_ISA_XCH): New define.
889 (AVR_ISA_XMEGA): Use it.
890 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
891
8922012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
893
894 * m68hc11.h: Add XGate definitions.
895 (struct m68hc11_opcode): Add xg_mask field.
896
8972012-05-14 Catherine Moore <clm@codesourcery.com>
898 Maciej W. Rozycki <macro@codesourcery.com>
899 Rhonda Wittels <rhonda@codesourcery.com>
900
901 * ppc.h (PPC_OPCODE_VLE): New definition.
902 (PPC_OP_SA): New macro.
903 (PPC_OP_SE_VLE): New macro.
904 (PPC_OP): Use a variable shift amount.
905 (powerpc_operand): Update comments.
906 (PPC_OPSHIFT_INV): New macro.
907 (PPC_OPERAND_CR): Replace with...
908 (PPC_OPERAND_CR_BIT): ...this and
909 (PPC_OPERAND_CR_REG): ...this.
910
911
9122012-05-03 Sean Keys <skeys@ipdatasys.com>
913
914 * xgate.h: Header file for XGATE assembler.
915
9162012-04-27 David S. Miller <davem@davemloft.net>
917
918 * sparc.h: Document new arg code' )' for crypto RS3
919 immediates.
920
921 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
922 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
923 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
924 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
925 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
926 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
927 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
928 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
929 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
930 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
931 HWCAP_CBCOND, HWCAP_CRC32): New defines.
932
9332012-03-10 Edmar Wienskoski <edmar@freescale.com>
934
935 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
936
9372012-02-27 Alan Modra <amodra@gmail.com>
938
939 * crx.h (cst4_map): Update declaration.
940
9412012-02-25 Walter Lee <walt@tilera.com>
942
943 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
944 TILEGX_OPC_LD_TLS.
945 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
946 TILEPRO_OPC_LW_TLS_SN.
947
9482012-02-08 H.J. Lu <hongjiu.lu@intel.com>
949
950 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
951 (XRELEASE_PREFIX_OPCODE): Likewise.
952
9532011-12-08 Andrew Pinski <apinski@cavium.com>
954 Adam Nemet <anemet@caviumnetworks.com>
955
956 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
957 (INSN_OCTEON2): New macro.
958 (CPU_OCTEON2): New macro.
959 (OPCODE_IS_MEMBER): Add Octeon2.
960
9612011-11-29 Andrew Pinski <apinski@cavium.com>
962
963 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
964 (INSN_OCTEONP): New macro.
965 (CPU_OCTEONP): New macro.
966 (OPCODE_IS_MEMBER): Add Octeon+.
967 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
968
9692011-11-01 DJ Delorie <dj@redhat.com>
970
971 * rl78.h: New file.
972
9732011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
974
975 * mips.h: Fix a typo in description.
976
9772011-09-21 David S. Miller <davem@davemloft.net>
978
979 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
980 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
981 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
982 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
983
9842011-08-09 Chao-ying Fu <fu@mips.com>
985 Maciej W. Rozycki <macro@codesourcery.com>
986
987 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
988 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
989 (INSN_ASE_MASK): Add the MCU bit.
990 (INSN_MCU): New macro.
991 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
992 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
993
9942011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
995
996 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
997 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
998 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
999 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
1000 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
1001 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
1002 (INSN2_READ_GPR_MMN): Likewise.
1003 (INSN2_READ_FPR_D): Change the bit used.
1004 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
1005 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
1006 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
1007 (INSN2_COND_BRANCH): Likewise.
1008 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
1009 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
1010 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
1011 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
1012 (INSN2_MOD_GPR_MN): Likewise.
1013
10142011-08-05 David S. Miller <davem@davemloft.net>
1015
1016 * sparc.h: Document new format codes '4', '5', and '('.
1017 (OPF_LOW4, RS3): New macros.
1018
10192011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
1020
1021 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
1022 order of flags documented.
1023
10242011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
1025
1026 * mips.h: Clarify the description of microMIPS instruction
1027 manipulation macros.
1028 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
1029
10302011-07-24 Chao-ying Fu <fu@mips.com>
1031 Maciej W. Rozycki <macro@codesourcery.com>
1032
1033 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
1034 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
1035 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
1036 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
1037 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
1038 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
1039 (OP_MASK_RS3, OP_SH_RS3): Likewise.
1040 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
1041 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
1042 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
1043 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
1044 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
1045 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
1046 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
1047 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
1048 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
1049 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
1050 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
1051 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
1052 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
1053 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
1054 (INSN_WRITE_GPR_S): New macro.
1055 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
1056 (INSN2_READ_FPR_D): Likewise.
1057 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
1058 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
1059 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
1060 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
1061 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
1062 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
1063 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
1064 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
1065 (CPU_MICROMIPS): New macro.
1066 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
1067 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
1068 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
1069 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
1070 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
1071 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
1072 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
1073 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
1074 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
1075 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
1076 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
1077 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
1078 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
1079 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
1080 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
1081 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
1082 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1083 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1084 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1085 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1086 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1087 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1088 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1089 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1090 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1091 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1092 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1093 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1094 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1095 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1096 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1097 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1098 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1099 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1100 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1101 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1102 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1103 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1104 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1105 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1106 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1107 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1108 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1109 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1110 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1111 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1112 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1113 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1114 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1115 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1116 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1117 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1118 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1119 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1120 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1121 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1122 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1123 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1124 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1125 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1126 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1127 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1128 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1129 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1130 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1131 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1132 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1133 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1134 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1135 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1136 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1137 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1138 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1139 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1140 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1141 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1142 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1143 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1144 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1145 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1146 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1147 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1148 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1149 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1150 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1151 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1152 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1153 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1154 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1155 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1156 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1157 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1158 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1159 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1160 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1161 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1162 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1163 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1164 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1165 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1166 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1167 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1168 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1169 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1170 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1171 (micromips_opcodes): New declaration.
1172 (bfd_micromips_num_opcodes): Likewise.
1173
11742011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1175
1176 * mips.h (INSN_TRAP): Rename to...
1177 (INSN_NO_DELAY_SLOT): ... this.
1178 (INSN_SYNC): Remove macro.
1179
11802011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1181
1182 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1183 a duplicate of AVR_ISA_SPM.
1184
11852011-07-01 Nick Clifton <nickc@redhat.com>
1186
1187 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1188
11892011-06-18 Robin Getz <robin.getz@analog.com>
1190
1191 * bfin.h (is_macmod_signed): New func
1192
11932011-06-18 Mike Frysinger <vapier@gentoo.org>
1194
1195 * bfin.h (is_macmod_pmove): Add missing space before func args.
1196 (is_macmod_hmove): Likewise.
1197
11982011-06-13 Walter Lee <walt@tilera.com>
1199
1200 * tilegx.h: New file.
1201 * tilepro.h: New file.
1202
12032011-05-31 Paul Brook <paul@codesourcery.com>
1204
1205 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1206
12072011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1208
1209 * s390.h: Replace S390_OPERAND_REG_EVEN with
1210 S390_OPERAND_REG_PAIR.
1211
12122011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1213
1214 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1215
12162011-04-18 Julian Brown <julian@codesourcery.com>
1217
1218 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1219
12202011-04-11 Dan McDonald <dan@wellkeeper.com>
1221
1222 PR gas/12296
1223 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1224
12252011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1226
1227 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1228 New instruction set flags.
1229 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1230
12312011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1232
1233 * mips.h (M_PREF_AB): New enum value.
1234
12352011-02-12 Mike Frysinger <vapier@gentoo.org>
1236
1237 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1238 M_IU): Define.
1239 (is_macmod_pmove, is_macmod_hmove): New functions.
1240
12412011-02-11 Mike Frysinger <vapier@gentoo.org>
1242
1243 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1244
12452011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1246
1247 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1248 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1249
12502010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1251
1252 PR gas/11395
1253 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1254 "bb" entries.
1255
12562010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1257
1258 PR gas/11395
1259 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1260
12612010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1262
1263 * mips.h: Update commentary after last commit.
1264
12652010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1266
1267 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1268 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1269 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1270
12712010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1272
1273 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1274
12752010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1276
1277 * mips.h: Fix previous commit.
1278
12792010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1280
1281 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1282 (INSN_LOONGSON_3A): Clear bit 31.
1283
12842010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1285
1286 PR gas/12198
1287 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1288 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1289 (ARM_ARCH_V6M_ONLY): New define.
1290
12912010-11-11 Mingming Sun <mingm.sun@gmail.com>
1292
1293 * mips.h (INSN_LOONGSON_3A): Defined.
1294 (CPU_LOONGSON_3A): Defined.
1295 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1296
12972010-10-09 Matt Rice <ratmice@gmail.com>
1298
1299 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1300 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1301
13022010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1303
1304 * arm.h (ARM_EXT_VIRT): New define.
1305 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1306 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1307 Extensions.
1308
13092010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1310
1311 * arm.h (ARM_AEXT_ADIV): New define.
1312 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1313
13142010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1315
1316 * arm.h (ARM_EXT_OS): New define.
1317 (ARM_AEXT_V6SM): Likewise.
1318 (ARM_ARCH_V6SM): Likewise.
1319
13202010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1321
1322 * arm.h (ARM_EXT_MP): Add.
1323 (ARM_ARCH_V7A_MP): Likewise.
1324
13252010-09-22 Mike Frysinger <vapier@gentoo.org>
1326
1327 * bfin.h: Declare pseudoChr structs/defines.
1328
13292010-09-21 Mike Frysinger <vapier@gentoo.org>
1330
1331 * bfin.h: Strip trailing whitespace.
1332
13332010-07-29 DJ Delorie <dj@redhat.com>
1334
1335 * rx.h (RX_Operand_Type): Add TwoReg.
1336 (RX_Opcode_ID): Remove ediv and ediv2.
1337
13382010-07-27 DJ Delorie <dj@redhat.com>
1339
1340 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1341
13422010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1343 Ina Pandit <ina.pandit@kpitcummins.com>
1344
1345 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1346 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1347 PROCESSOR_V850E2_ALL.
1348 Remove PROCESSOR_V850EA support.
1349 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1350 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1351 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1352 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1353 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1354 V850_OPERAND_PERCENT.
1355 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1356 V850_NOT_R0.
1357 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1358 and V850E_PUSH_POP
1359
13602010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1361
1362 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1363 (MIPS16_INSN_BRANCH): Rename to...
1364 (MIPS16_INSN_COND_BRANCH): ... this.
1365
13662010-07-03 Alan Modra <amodra@gmail.com>
1367
1368 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1369 Renumber other PPC_OPCODE defines.
1370
13712010-07-03 Alan Modra <amodra@gmail.com>
1372
1373 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1374
13752010-06-29 Alan Modra <amodra@gmail.com>
1376
1377 * maxq.h: Delete file.
1378
13792010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1380
1381 * ppc.h (PPC_OPCODE_E500): Define.
1382
13832010-05-26 Catherine Moore <clm@codesourcery.com>
1384
1385 * opcode/mips.h (INSN_MIPS16): Remove.
1386
13872010-04-21 Joseph Myers <joseph@codesourcery.com>
1388
1389 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1390
13912010-04-15 Nick Clifton <nickc@redhat.com>
1392
1393 * alpha.h: Update copyright notice to use GPLv3.
1394 * arc.h: Likewise.
1395 * arm.h: Likewise.
1396 * avr.h: Likewise.
1397 * bfin.h: Likewise.
1398 * cgen.h: Likewise.
1399 * convex.h: Likewise.
1400 * cr16.h: Likewise.
1401 * cris.h: Likewise.
1402 * crx.h: Likewise.
1403 * d10v.h: Likewise.
1404 * d30v.h: Likewise.
1405 * dlx.h: Likewise.
1406 * h8300.h: Likewise.
1407 * hppa.h: Likewise.
1408 * i370.h: Likewise.
1409 * i386.h: Likewise.
1410 * i860.h: Likewise.
1411 * i960.h: Likewise.
1412 * ia64.h: Likewise.
1413 * m68hc11.h: Likewise.
1414 * m68k.h: Likewise.
1415 * m88k.h: Likewise.
1416 * maxq.h: Likewise.
1417 * mips.h: Likewise.
1418 * mmix.h: Likewise.
1419 * mn10200.h: Likewise.
1420 * mn10300.h: Likewise.
1421 * msp430.h: Likewise.
1422 * np1.h: Likewise.
1423 * ns32k.h: Likewise.
1424 * or32.h: Likewise.
1425 * pdp11.h: Likewise.
1426 * pj.h: Likewise.
1427 * pn.h: Likewise.
1428 * ppc.h: Likewise.
1429 * pyr.h: Likewise.
1430 * rx.h: Likewise.
1431 * s390.h: Likewise.
1432 * score-datadep.h: Likewise.
1433 * score-inst.h: Likewise.
1434 * sparc.h: Likewise.
1435 * spu-insns.h: Likewise.
1436 * spu.h: Likewise.
1437 * tic30.h: Likewise.
1438 * tic4x.h: Likewise.
1439 * tic54x.h: Likewise.
1440 * tic80.h: Likewise.
1441 * v850.h: Likewise.
1442 * vax.h: Likewise.
1443
14442010-03-25 Joseph Myers <joseph@codesourcery.com>
1445
1446 * tic6x-control-registers.h, tic6x-insn-formats.h,
1447 tic6x-opcode-table.h, tic6x.h: New.
1448
14492010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1450
1451 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1452
14532010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1454
1455 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1456
14572010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1458
1459 * ia64.h (ia64_find_opcode): Remove argument name.
1460 (ia64_find_next_opcode): Likewise.
1461 (ia64_dis_opcode): Likewise.
1462 (ia64_free_opcode): Likewise.
1463 (ia64_find_dependency): Likewise.
1464
14652009-11-22 Doug Evans <dje@sebabeach.org>
1466
1467 * cgen.h: Include bfd_stdint.h.
1468 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1469
14702009-11-18 Paul Brook <paul@codesourcery.com>
1471
1472 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1473
14742009-11-17 Paul Brook <paul@codesourcery.com>
1475 Daniel Jacobowitz <dan@codesourcery.com>
1476
1477 * arm.h (ARM_EXT_V6_DSP): Define.
1478 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1479 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1480
14812009-11-04 DJ Delorie <dj@redhat.com>
1482
1483 * rx.h (rx_decode_opcode) (mvtipl): Add.
1484 (mvtcp, mvfcp, opecp): Remove.
1485
14862009-11-02 Paul Brook <paul@codesourcery.com>
1487
1488 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1489 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1490 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1491 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1492 FPU_ARCH_NEON_VFP_V4): Define.
1493
14942009-10-23 Doug Evans <dje@sebabeach.org>
1495
1496 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1497 * cgen.h: Update. Improve multi-inclusion macro name.
1498
14992009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1500
1501 * ppc.h (PPC_OPCODE_476): Define.
1502
15032009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1504
1505 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1506
15072009-09-29 DJ Delorie <dj@redhat.com>
1508
1509 * rx.h: New file.
1510
15112009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1512
1513 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1514
15152009-09-21 Ben Elliston <bje@au.ibm.com>
1516
1517 * ppc.h (PPC_OPCODE_PPCA2): New.
1518
15192009-09-05 Martin Thuresson <martin@mtme.org>
1520
1521 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1522
15232009-08-29 Martin Thuresson <martin@mtme.org>
1524
1525 * tic30.h (template): Rename type template to
1526 insn_template. Updated code to use new name.
1527 * tic54x.h (template): Rename type template to
1528 insn_template.
1529
15302009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1531
1532 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1533
15342009-06-11 Anthony Green <green@moxielogic.com>
1535
1536 * moxie.h (MOXIE_F3_PCREL): Define.
1537 (moxie_form3_opc_info): Grow.
1538
15392009-06-06 Anthony Green <green@moxielogic.com>
1540
1541 * moxie.h (MOXIE_F1_M): Define.
1542
15432009-04-15 Anthony Green <green@moxielogic.com>
1544
1545 * moxie.h: Created.
1546
15472009-04-06 DJ Delorie <dj@redhat.com>
1548
1549 * h8300.h: Add relaxation attributes to MOVA opcodes.
1550
15512009-03-10 Alan Modra <amodra@bigpond.net.au>
1552
1553 * ppc.h (ppc_parse_cpu): Declare.
1554
15552009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1556
1557 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1558 and _IMM11 for mbitclr and mbitset.
1559 * score-datadep.h: Update dependency information.
1560
15612009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1562
1563 * ppc.h (PPC_OPCODE_POWER7): New.
1564
15652009-02-06 Doug Evans <dje@google.com>
1566
1567 * i386.h: Add comment regarding sse* insns and prefixes.
1568
15692009-02-03 Sandip Matte <sandip@rmicorp.com>
1570
1571 * mips.h (INSN_XLR): Define.
1572 (INSN_CHIP_MASK): Update.
1573 (CPU_XLR): Define.
1574 (OPCODE_IS_MEMBER): Update.
1575 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1576
15772009-01-28 Doug Evans <dje@google.com>
1578
1579 * opcode/i386.h: Add multiple inclusion protection.
1580 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1581 (EDI_REG_NUM): New macros.
1582 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1583 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1584 (REX_PREFIX_P): New macro.
1585
15862009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1587
1588 * ppc.h (struct powerpc_opcode): New field "deprecated".
1589 (PPC_OPCODE_NOPOWER4): Delete.
1590
15912008-11-28 Joshua Kinard <kumba@gentoo.org>
1592
1593 * mips.h: Define CPU_R14000, CPU_R16000.
1594 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1595
15962008-11-18 Catherine Moore <clm@codesourcery.com>
1597
1598 * arm.h (FPU_NEON_FP16): New.
1599 (FPU_ARCH_NEON_FP16): New.
1600
16012008-11-06 Chao-ying Fu <fu@mips.com>
1602
1603 * mips.h: Doucument '1' for 5-bit sync type.
1604
16052008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1606
1607 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1608 IA64_RS_CR.
1609
16102008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1611
1612 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1613
16142008-07-30 Michael J. Eager <eager@eagercon.com>
1615
1616 * ppc.h (PPC_OPCODE_405): Define.
1617 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1618
16192008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1620
1621 * ppc.h (ppc_cpu_t): New typedef.
1622 (struct powerpc_opcode <flags>): Use it.
1623 (struct powerpc_operand <insert, extract>): Likewise.
1624 (struct powerpc_macro <flags>): Likewise.
1625
16262008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1627
1628 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1629 Update comment before MIPS16 field descriptors to mention MIPS16.
1630 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1631 BBIT.
1632 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1633 New bit masks and shift counts for cins and exts.
1634
1635 * mips.h: Document new field descriptors +Q.
1636 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1637
16382008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1639
1640 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1641 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1642
16432008-04-14 Edmar Wienskoski <edmar@freescale.com>
1644
1645 * ppc.h: (PPC_OPCODE_E500MC): New.
1646
16472008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1648
1649 * i386.h (MAX_OPERANDS): Set to 5.
1650 (MAX_MNEM_SIZE): Changed to 20.
1651
16522008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1653
1654 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1655
16562008-03-09 Paul Brook <paul@codesourcery.com>
1657
1658 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1659
16602008-03-04 Paul Brook <paul@codesourcery.com>
1661
1662 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1663 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1664 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1665
16662008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1667 Nick Clifton <nickc@redhat.com>
1668
1669 PR 3134
1670 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1671 with a 32-bit displacement but without the top bit of the 4th byte
1672 set.
1673
16742008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1675
1676 * cr16.h (cr16_num_optab): Declared.
1677
16782008-02-14 Hakan Ardo <hakan@debian.org>
1679
1680 PR gas/2626
1681 * avr.h (AVR_ISA_2xxe): Define.
1682
16832008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1684
1685 * mips.h: Update copyright.
1686 (INSN_CHIP_MASK): New macro.
1687 (INSN_OCTEON): New macro.
1688 (CPU_OCTEON): New macro.
1689 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1690
16912008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1692
1693 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1694
16952008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1696
1697 * avr.h (AVR_ISA_USB162): Add new opcode set.
1698 (AVR_ISA_AVR3): Likewise.
1699
17002007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1701
1702 * mips.h (INSN_LOONGSON_2E): New.
1703 (INSN_LOONGSON_2F): New.
1704 (CPU_LOONGSON_2E): New.
1705 (CPU_LOONGSON_2F): New.
1706 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1707
17082007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1709
1710 * mips.h (INSN_ISA*): Redefine certain values as an
1711 enumeration. Update comments.
1712 (mips_isa_table): New.
1713 (ISA_MIPS*): Redefine to match enumeration.
1714 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1715 values.
1716
17172007-08-08 Ben Elliston <bje@au.ibm.com>
1718
1719 * ppc.h (PPC_OPCODE_PPCPS): New.
1720
17212007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1722
1723 * m68k.h: Document j K & E.
1724
17252007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1726
1727 * cr16.h: New file for CR16 target.
1728
17292007-05-02 Alan Modra <amodra@bigpond.net.au>
1730
1731 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1732
17332007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1734
1735 * m68k.h (mcfisa_c): New.
1736 (mcfusp, mcf_mask): Adjust.
1737
17382007-04-20 Alan Modra <amodra@bigpond.net.au>
1739
1740 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1741 (num_powerpc_operands): Declare.
1742 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1743 (PPC_OPERAND_PLUS1): Define.
1744
17452007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1746
1747 * i386.h (REX_MODE64): Renamed to ...
1748 (REX_W): This.
1749 (REX_EXTX): Renamed to ...
1750 (REX_R): This.
1751 (REX_EXTY): Renamed to ...
1752 (REX_X): This.
1753 (REX_EXTZ): Renamed to ...
1754 (REX_B): This.
1755
17562007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1757
1758 * i386.h: Add entries from config/tc-i386.h and move tables
1759 to opcodes/i386-opc.h.
1760
17612007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1762
1763 * i386.h (FloatDR): Removed.
1764 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1765
17662007-03-01 Alan Modra <amodra@bigpond.net.au>
1767
1768 * spu-insns.h: Add soma double-float insns.
1769
17702007-02-20 Thiemo Seufer <ths@mips.com>
1771 Chao-Ying Fu <fu@mips.com>
1772
1773 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1774 (INSN_DSPR2): Add flag for DSP R2 instructions.
1775 (M_BALIGN): New macro.
1776
17772007-02-14 Alan Modra <amodra@bigpond.net.au>
1778
1779 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1780 and Seg3ShortFrom with Shortform.
1781
17822007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1783
1784 PR gas/4027
1785 * i386.h (i386_optab): Put the real "test" before the pseudo
1786 one.
1787
17882007-01-08 Kazu Hirata <kazu@codesourcery.com>
1789
1790 * m68k.h (m68010up): OR fido_a.
1791
17922006-12-25 Kazu Hirata <kazu@codesourcery.com>
1793
1794 * m68k.h (fido_a): New.
1795
17962006-12-24 Kazu Hirata <kazu@codesourcery.com>
1797
1798 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1799 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1800 values.
1801
18022006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1803
1804 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1805
18062006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1807
1808 * score-inst.h (enum score_insn_type): Add Insn_internal.
1809
18102006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1811 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1812 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1813 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1814 Alan Modra <amodra@bigpond.net.au>
1815
1816 * spu-insns.h: New file.
1817 * spu.h: New file.
1818
18192006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1820
1821 * ppc.h (PPC_OPCODE_CELL): Define.
1822
18232006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1824
1825 * i386.h : Modify opcode to support for the change in POPCNT opcode
1826 in amdfam10 architecture.
1827
18282006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1829
1830 * i386.h: Replace CpuMNI with CpuSSSE3.
1831
18322006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1833 Joseph Myers <joseph@codesourcery.com>
1834 Ian Lance Taylor <ian@wasabisystems.com>
1835 Ben Elliston <bje@wasabisystems.com>
1836
1837 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1838
18392006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1840
1841 * score-datadep.h: New file.
1842 * score-inst.h: New file.
1843
18442006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1845
1846 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1847 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1848 movdq2q and movq2dq.
1849
18502006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1851 Michael Meissner <michael.meissner@amd.com>
1852
1853 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1854
18552006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1856
1857 * i386.h (i386_optab): Add "nop" with memory reference.
1858
18592006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1860
1861 * i386.h (i386_optab): Update comment for 64bit NOP.
1862
18632006-06-06 Ben Elliston <bje@au.ibm.com>
1864 Anton Blanchard <anton@samba.org>
1865
1866 * ppc.h (PPC_OPCODE_POWER6): Define.
1867 Adjust whitespace.
1868
18692006-06-05 Thiemo Seufer <ths@mips.com>
1870
1871 * mips.h: Improve description of MT flags.
1872
18732006-05-25 Richard Sandiford <richard@codesourcery.com>
1874
1875 * m68k.h (mcf_mask): Define.
1876
18772006-05-05 Thiemo Seufer <ths@mips.com>
1878 David Ung <davidu@mips.com>
1879
1880 * mips.h (enum): Add macro M_CACHE_AB.
1881
18822006-05-04 Thiemo Seufer <ths@mips.com>
1883 Nigel Stephens <nigel@mips.com>
1884 David Ung <davidu@mips.com>
1885
1886 * mips.h: Add INSN_SMARTMIPS define.
1887
18882006-04-30 Thiemo Seufer <ths@mips.com>
1889 David Ung <davidu@mips.com>
1890
1891 * mips.h: Defines udi bits and masks. Add description of
1892 characters which may appear in the args field of udi
1893 instructions.
1894
18952006-04-26 Thiemo Seufer <ths@networkno.de>
1896
1897 * mips.h: Improve comments describing the bitfield instruction
1898 fields.
1899
19002006-04-26 Julian Brown <julian@codesourcery.com>
1901
1902 * arm.h (FPU_VFP_EXT_V3): Define constant.
1903 (FPU_NEON_EXT_V1): Likewise.
1904 (FPU_VFP_HARD): Update.
1905 (FPU_VFP_V3): Define macro.
1906 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1907
19082006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1909
1910 * avr.h (AVR_ISA_PWMx): New.
1911
19122006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1913
1914 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1915 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1916 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1917 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1918 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1919
19202006-03-10 Paul Brook <paul@codesourcery.com>
1921
1922 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1923
19242006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1925
1926 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1927 first. Correct mask of bb "B" opcode.
1928
19292006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1930
1931 * i386.h (i386_optab): Support Intel Merom New Instructions.
1932
19332006-02-24 Paul Brook <paul@codesourcery.com>
1934
1935 * arm.h: Add V7 feature bits.
1936
19372006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1938
1939 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1940
19412006-01-31 Paul Brook <paul@codesourcery.com>
1942 Richard Earnshaw <rearnsha@arm.com>
1943
1944 * arm.h: Use ARM_CPU_FEATURE.
1945 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1946 (arm_feature_set): Change to a structure.
1947 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1948 ARM_FEATURE): New macros.
1949
19502005-12-07 Hans-Peter Nilsson <hp@axis.com>
1951
1952 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1953 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1954 (ADD_PC_INCR_OPCODE): Don't define.
1955
19562005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1957
1958 PR gas/1874
1959 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1960
19612005-11-14 David Ung <davidu@mips.com>
1962
1963 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1964 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1965 save/restore encoding of the args field.
1966
19672005-10-28 Dave Brolley <brolley@redhat.com>
1968
1969 Contribute the following changes:
1970 2005-02-16 Dave Brolley <brolley@redhat.com>
1971
1972 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1973 cgen_isa_mask_* to cgen_bitset_*.
1974 * cgen.h: Likewise.
1975
1976 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1977
1978 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1979 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1980 (CGEN_CPU_TABLE): Make isas a ponter.
1981
1982 2003-09-29 Dave Brolley <brolley@redhat.com>
1983
1984 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1985 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1986 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1987
1988 2002-12-13 Dave Brolley <brolley@redhat.com>
1989
1990 * cgen.h (symcat.h): #include it.
1991 (cgen-bitset.h): #include it.
1992 (CGEN_ATTR_VALUE_TYPE): Now a union.
1993 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1994 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1995 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1996 * cgen-bitset.h: New file.
1997
19982005-09-30 Catherine Moore <clm@cm00re.com>
1999
2000 * bfin.h: New file.
2001
20022005-10-24 Jan Beulich <jbeulich@novell.com>
2003
2004 * ia64.h (enum ia64_opnd): Move memory operand out of set of
2005 indirect operands.
2006
20072005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2008
2009 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
2010 Add FLAG_STRICT to pa10 ftest opcode.
2011
20122005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2013
2014 * hppa.h (pa_opcodes): Remove lha entries.
2015
20162005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2017
2018 * hppa.h (FLAG_STRICT): Revise comment.
2019 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
2020 before corresponding pa11 opcodes. Add strict pa10 register-immediate
2021 entries for "fdc".
2022
20232005-09-30 Catherine Moore <clm@cm00re.com>
2024
2025 * bfin.h: New file.
2026
20272005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2028
2029 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
2030
20312005-09-06 Chao-ying Fu <fu@mips.com>
2032
2033 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
2034 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
2035 define.
2036 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
2037 (INSN_ASE_MASK): Update to include INSN_MT.
2038 (INSN_MT): New define for MT ASE.
2039
20402005-08-25 Chao-ying Fu <fu@mips.com>
2041
2042 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
2043 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
2044 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
2045 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
2046 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
2047 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
2048 instructions.
2049 (INSN_DSP): New define for DSP ASE.
2050
20512005-08-18 Alan Modra <amodra@bigpond.net.au>
2052
2053 * a29k.h: Delete.
2054
20552005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
2056
2057 * ppc.h (PPC_OPCODE_E300): Define.
2058
20592005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
2060
2061 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
2062
20632005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2064
2065 PR gas/336
2066 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
2067 and pitlb.
2068
20692005-07-27 Jan Beulich <jbeulich@novell.com>
2070
2071 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
2072 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
2073 Add movq-s as 64-bit variants of movd-s.
2074
20752005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2076
2077 * hppa.h: Fix punctuation in comment.
2078
2079 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
2080 implicit space-register addressing. Set space-register bits on opcodes
2081 using implicit space-register addressing. Add various missing pa20
2082 long-immediate opcodes. Remove various opcodes using implicit 3-bit
2083 space-register addressing. Use "fE" instead of "fe" in various
2084 fstw opcodes.
2085
20862005-07-18 Jan Beulich <jbeulich@novell.com>
2087
2088 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2089
20902007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2091
2092 * i386.h (i386_optab): Support Intel VMX Instructions.
2093
20942005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2095
2096 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2097
20982005-07-05 Jan Beulich <jbeulich@novell.com>
2099
2100 * i386.h (i386_optab): Add new insns.
2101
21022005-07-01 Nick Clifton <nickc@redhat.com>
2103
2104 * sparc.h: Add typedefs to structure declarations.
2105
21062005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2107
2108 PR 1013
2109 * i386.h (i386_optab): Update comments for 64bit addressing on
2110 mov. Allow 64bit addressing for mov and movq.
2111
21122005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2113
2114 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2115 respectively, in various floating-point load and store patterns.
2116
21172005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2118
2119 * hppa.h (FLAG_STRICT): Correct comment.
2120 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2121 PA 2.0 mneumonics when equivalent. Entries with cache control
2122 completers now require PA 1.1. Adjust whitespace.
2123
21242005-05-19 Anton Blanchard <anton@samba.org>
2125
2126 * ppc.h (PPC_OPCODE_POWER5): Define.
2127
21282005-05-10 Nick Clifton <nickc@redhat.com>
2129
2130 * Update the address and phone number of the FSF organization in
2131 the GPL notices in the following files:
2132 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2133 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2134 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2135 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2136 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2137 tic54x.h, tic80.h, v850.h, vax.h
2138
21392005-05-09 Jan Beulich <jbeulich@novell.com>
2140
2141 * i386.h (i386_optab): Add ht and hnt.
2142
21432005-04-18 Mark Kettenis <kettenis@gnu.org>
2144
2145 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2146 Add xcrypt-ctr. Provide aliases without hyphens.
2147
21482005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2149
2150 Moved from ../ChangeLog
2151
2152 2005-04-12 Paul Brook <paul@codesourcery.com>
2153 * m88k.h: Rename psr macros to avoid conflicts.
2154
2155 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2156 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2157 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2158 and ARM_ARCH_V6ZKT2.
2159
2160 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2161 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2162 Remove redundant instruction types.
2163 (struct argument): X_op - new field.
2164 (struct cst4_entry): Remove.
2165 (no_op_insn): Declare.
2166
2167 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2168 * crx.h (enum argtype): Rename types, remove unused types.
2169
2170 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2171 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2172 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2173 (enum operand_type): Rearrange operands, edit comments.
2174 replace us<N> with ui<N> for unsigned immediate.
2175 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2176 displacements (respectively).
2177 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2178 (instruction type): Add NO_TYPE_INS.
2179 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2180 (operand_entry): New field - 'flags'.
2181 (operand flags): New.
2182
2183 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2184 * crx.h (operand_type): Remove redundant types i3, i4,
2185 i5, i8, i12.
2186 Add new unsigned immediate types us3, us4, us5, us16.
2187
21882005-04-12 Mark Kettenis <kettenis@gnu.org>
2189
2190 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2191 adjust them accordingly.
2192
21932005-04-01 Jan Beulich <jbeulich@novell.com>
2194
2195 * i386.h (i386_optab): Add rdtscp.
2196
21972005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2198
2199 * i386.h (i386_optab): Don't allow the `l' suffix for moving
2200 between memory and segment register. Allow movq for moving between
2201 general-purpose register and segment register.
2202
22032005-02-09 Jan Beulich <jbeulich@novell.com>
2204
2205 PR gas/707
2206 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2207 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2208 fnstsw.
2209
22102006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2211
2212 * m68k.h (m68008, m68ec030, m68882): Remove.
2213 (m68k_mask): New.
2214 (cpu_m68k, cpu_cf): New.
2215 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2216 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2217
22182005-01-25 Alexandre Oliva <aoliva@redhat.com>
2219
2220 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2221 * cgen.h (enum cgen_parse_operand_type): Add
2222 CGEN_PARSE_OPERAND_SYMBOLIC.
2223
22242005-01-21 Fred Fish <fnf@specifixinc.com>
2225
2226 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2227 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2228 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2229
22302005-01-19 Fred Fish <fnf@specifixinc.com>
2231
2232 * mips.h (struct mips_opcode): Add new pinfo2 member.
2233 (INSN_ALIAS): New define for opcode table entries that are
2234 specific instances of another entry, such as 'move' for an 'or'
2235 with a zero operand.
2236 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2237 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2238
22392004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2240
2241 * mips.h (CPU_RM9000): Define.
2242 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2243
22442004-11-25 Jan Beulich <jbeulich@novell.com>
2245
2246 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2247 to/from test registers are illegal in 64-bit mode. Add missing
2248 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2249 (previously one had to explicitly encode a rex64 prefix). Re-enable
2250 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2251 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2252
22532004-11-23 Jan Beulich <jbeulich@novell.com>
2254
2255 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2256 available only with SSE2. Change the MMX additions introduced by SSE
2257 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2258 instructions by their now designated identifier (since combining i686
2259 and 3DNow! does not really imply 3DNow!A).
2260
22612004-11-19 Alan Modra <amodra@bigpond.net.au>
2262
2263 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2264 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2265
22662004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2267 Vineet Sharma <vineets@noida.hcltech.com>
2268
2269 * maxq.h: New file: Disassembly information for the maxq port.
2270
22712004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2272
2273 * i386.h (i386_optab): Put back "movzb".
2274
22752004-11-04 Hans-Peter Nilsson <hp@axis.com>
2276
2277 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2278 comments. Remove member cris_ver_sim. Add members
2279 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2280 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2281 (struct cris_support_reg, struct cris_cond15): New types.
2282 (cris_conds15): Declare.
2283 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2284 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2285 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2286 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2287 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2288 SIZE_FIELD_UNSIGNED.
2289
22902004-11-04 Jan Beulich <jbeulich@novell.com>
2291
2292 * i386.h (sldx_Suf): Remove.
2293 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2294 (q_FP): Define, implying no REX64.
2295 (x_FP, sl_FP): Imply FloatMF.
2296 (i386_optab): Split reg and mem forms of moving from segment registers
2297 so that the memory forms can ignore the 16-/32-bit operand size
2298 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2299 all non-floating-point instructions. Unite 32- and 64-bit forms of
2300 movsx, movzx, and movd. Adjust floating point operations for the above
2301 changes to the *FP macros. Add DefaultSize to floating point control
2302 insns operating on larger memory ranges. Remove left over comments
2303 hinting at certain insns being Intel-syntax ones where the ones
2304 actually meant are already gone.
2305
23062004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2307
2308 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2309 instruction type.
2310
23112004-09-30 Paul Brook <paul@codesourcery.com>
2312
2313 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2314 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2315
23162004-09-11 Theodore A. Roth <troth@openavr.org>
2317
2318 * avr.h: Add support for
2319 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2320
23212004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2322
2323 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2324
23252004-08-24 Dmitry Diky <diwil@spec.ru>
2326
2327 * msp430.h (msp430_opc): Add new instructions.
2328 (msp430_rcodes): Declare new instructions.
2329 (msp430_hcodes): Likewise..
2330
23312004-08-13 Nick Clifton <nickc@redhat.com>
2332
2333 PR/301
2334 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2335 processors.
2336
23372004-08-30 Michal Ludvig <mludvig@suse.cz>
2338
2339 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2340
23412004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2342
2343 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2344
23452004-07-21 Jan Beulich <jbeulich@novell.com>
2346
2347 * i386.h: Adjust instruction descriptions to better match the
2348 specification.
2349
23502004-07-16 Richard Earnshaw <rearnsha@arm.com>
2351
2352 * arm.h: Remove all old content. Replace with architecture defines
2353 from gas/config/tc-arm.c.
2354
23552004-07-09 Andreas Schwab <schwab@suse.de>
2356
2357 * m68k.h: Fix comment.
2358
23592004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2360
2361 * crx.h: New file.
2362
23632004-06-24 Alan Modra <amodra@bigpond.net.au>
2364
2365 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2366
23672004-05-24 Peter Barada <peter@the-baradas.com>
2368
2369 * m68k.h: Add 'size' to m68k_opcode.
2370
23712004-05-05 Peter Barada <peter@the-baradas.com>
2372
2373 * m68k.h: Switch from ColdFire chip name to core variant.
2374
23752004-04-22 Peter Barada <peter@the-baradas.com>
2376
2377 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2378 descriptions for new EMAC cases.
2379 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2380 handle Motorola MAC syntax.
2381 Allow disassembly of ColdFire V4e object files.
2382
23832004-03-16 Alan Modra <amodra@bigpond.net.au>
2384
2385 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2386
23872004-03-12 Jakub Jelinek <jakub@redhat.com>
2388
2389 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2390
23912004-03-12 Michal Ludvig <mludvig@suse.cz>
2392
2393 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2394
23952004-03-12 Michal Ludvig <mludvig@suse.cz>
2396
2397 * i386.h (i386_optab): Added xstore/xcrypt insns.
2398
23992004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2400
2401 * h8300.h (32bit ldc/stc): Add relaxing support.
2402
24032004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2404
2405 * h8300.h (BITOP): Pass MEMRELAX flag.
2406
24072004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2408
2409 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2410 except for the H8S.
2411
2412For older changes see ChangeLog-9103
2413\f
2414Copyright (C) 2004-2015 Free Software Foundation, Inc.
2415
2416Copying and distribution of this file, with or without modification,
2417are permitted in any medium without royalty provided the copyright
2418notice and this notice are preserved.
2419
2420Local Variables:
2421mode: change-log
2422left-margin: 8
2423fill-column: 74
2424version-control: never
2425End:
GDB Binutils - Deliverables
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