| 1 | /* crx.h -- Header file for CRX opcode and register tables. |
| 2 | Copyright 2004 Free Software Foundation, Inc. |
| 3 | Contributed by Tomer Levi, NSC, Israel. |
| 4 | Originally written for GAS 2.12 by Tomer Levi, NSC, Israel. |
| 5 | Updates, BFDizing, GNUifying and ELF support by Tomer Levi. |
| 6 | |
| 7 | This file is part of GAS, GDB and the GNU binutils. |
| 8 | |
| 9 | GAS, GDB, and GNU binutils is free software; you can redistribute it |
| 10 | and/or modify it under the terms of the GNU General Public License as |
| 11 | published by the Free Software Foundation; either version 2, or (at your |
| 12 | option) any later version. |
| 13 | |
| 14 | GAS, GDB, and GNU binutils are distributed in the hope that they will be |
| 15 | useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program; if not, write to the Free Software |
| 21 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
| 22 | |
| 23 | #ifndef _CRX_H_ |
| 24 | #define _CRX_H_ |
| 25 | |
| 26 | /* CRX core/debug Registers : |
| 27 | The enums are used as indices to CRX registers table (crx_regtab). |
| 28 | Therefore, order MUST be preserved. */ |
| 29 | |
| 30 | typedef enum |
| 31 | { |
| 32 | /* 32-bit general purpose registers. */ |
| 33 | r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, |
| 34 | r10, r11, r12, r13, r14, r15, ra, sp, |
| 35 | /* 32-bit user registers. */ |
| 36 | u0, u1, u2, u3, u4, u5, u6, u7, u8, u9, |
| 37 | u10, u11, u12, u13, u14, u15, ura, usp, |
| 38 | /* hi and lo registers. */ |
| 39 | hi, lo, |
| 40 | /* hi and lo user registers. */ |
| 41 | uhi, ulo, |
| 42 | /* Processor Status Register. */ |
| 43 | psr, |
| 44 | /* Interrupt Base Register. */ |
| 45 | intbase, |
| 46 | /* Interrupt Stack Pointer Register. */ |
| 47 | isp, |
| 48 | /* Configuration Register. */ |
| 49 | cfg, |
| 50 | /* Coprocessor Configuration Register. */ |
| 51 | cpcfg, |
| 52 | /* Coprocessor Enable Register. */ |
| 53 | cen, |
| 54 | /* Not a register. */ |
| 55 | nullregister, |
| 56 | MAX_REG |
| 57 | } |
| 58 | reg; |
| 59 | |
| 60 | /* CRX Coprocessor registers and special registers : |
| 61 | The enums are used as indices to CRX coprocessor registers table |
| 62 | (crx_copregtab). Therefore, order MUST be preserved. */ |
| 63 | |
| 64 | typedef enum |
| 65 | { |
| 66 | /* Coprocessor registers. */ |
| 67 | c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8, |
| 68 | c9, c10, c11, c12, c13, c14, c15, |
| 69 | /* Coprocessor special registers. */ |
| 70 | cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8, |
| 71 | cs9, cs10, cs11, cs12, cs13, cs14, cs15, |
| 72 | /* Not a Coprocessor register. */ |
| 73 | nullcopregister, |
| 74 | MAX_COPREG |
| 75 | } |
| 76 | copreg; |
| 77 | |
| 78 | /* CRX Register types. */ |
| 79 | |
| 80 | typedef enum |
| 81 | { |
| 82 | CRX_R_REGTYPE, /* r<N> */ |
| 83 | CRX_U_REGTYPE, /* u<N> */ |
| 84 | CRX_C_REGTYPE, /* c<N> */ |
| 85 | CRX_CS_REGTYPE, /* cs<N> */ |
| 86 | CRX_CFG_REGTYPE /* configuration register */ |
| 87 | } |
| 88 | reg_type; |
| 89 | |
| 90 | /* CRX argument types : |
| 91 | The argument types correspond to instructions operands |
| 92 | |
| 93 | Argument types : |
| 94 | r - register |
| 95 | c - constant |
| 96 | i - immediate |
| 97 | idxr - index register |
| 98 | rbase - register base |
| 99 | s - star ('*') |
| 100 | copr - coprocessor register |
| 101 | copsr - coprocessor special register. */ |
| 102 | |
| 103 | typedef enum |
| 104 | { |
| 105 | arg_r, arg_c, arg_cr, arg_ic, arg_icr, arg_sc, |
| 106 | arg_idxr, arg_rbase, arg_copr, arg_copsr, |
| 107 | /* Not an argument. */ |
| 108 | nullargs |
| 109 | } |
| 110 | argtype; |
| 111 | |
| 112 | /* CRX operand types : |
| 113 | The operand types correspond to instructions operands. */ |
| 114 | |
| 115 | typedef enum |
| 116 | { |
| 117 | dummy, |
| 118 | /* 4-bit encoded constant. */ |
| 119 | cst4, |
| 120 | /* N-bit immediate. */ |
| 121 | i16, i32, |
| 122 | /* N-bit unsigned immediate. */ |
| 123 | ui3, ui4, ui5, ui16, |
| 124 | /* N-bit signed displacement. */ |
| 125 | disps9, disps17, disps25, disps32, |
| 126 | /* N-bit unsigned displacement. */ |
| 127 | dispu5, |
| 128 | /* N-bit escaped displacement. */ |
| 129 | dispe9, |
| 130 | /* N-bit absolute address. */ |
| 131 | abs16, abs32, |
| 132 | /* Register relative. */ |
| 133 | rbase, rbase_dispu4, |
| 134 | rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32, |
| 135 | /* Register index. */ |
| 136 | rindex_disps6, rindex_disps22, |
| 137 | /* 4-bit genaral-purpose register specifier. */ |
| 138 | regr, |
| 139 | /* 8-bit register address space. */ |
| 140 | regr8, |
| 141 | /* coprocessor register. */ |
| 142 | copregr, |
| 143 | /* coprocessor special register. */ |
| 144 | copsregr, |
| 145 | /* Not an operand. */ |
| 146 | nulloperand, |
| 147 | /* Maximum supported operand. */ |
| 148 | MAX_OPRD |
| 149 | } |
| 150 | operand_type; |
| 151 | |
| 152 | /* CRX instruction types. */ |
| 153 | |
| 154 | #define NO_TYPE_INS 0 |
| 155 | #define ARITH_INS 1 |
| 156 | #define LD_STOR_INS 2 |
| 157 | #define BRANCH_INS 3 |
| 158 | #define ARITH_BYTE_INS 4 |
| 159 | #define CMPBR_INS 5 |
| 160 | #define SHIFT_INS 6 |
| 161 | #define BRANCH_NEQ_INS 7 |
| 162 | #define LD_STOR_INS_INC 8 |
| 163 | #define STOR_IMM_INS 9 |
| 164 | #define CSTBIT_INS 10 |
| 165 | #define COP_BRANCH_INS 11 |
| 166 | #define COP_REG_INS 12 |
| 167 | #define COPS_REG_INS 13 |
| 168 | #define DCR_BRANCH_INS 14 |
| 169 | |
| 170 | /* Maximum value supported for instruction types. */ |
| 171 | #define CRX_INS_MAX (1 << 4) |
| 172 | /* Mask to record an instruction type. */ |
| 173 | #define CRX_INS_MASK (CRX_INS_MAX - 1) |
| 174 | /* Return instruction type, given instruction's attributes. */ |
| 175 | #define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK) |
| 176 | |
| 177 | /* Indicates whether this instruction has a register list as parameter. */ |
| 178 | #define REG_LIST CRX_INS_MAX |
| 179 | /* The operands in binary and assembly are placed in reverse order. |
| 180 | load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */ |
| 181 | #define REVERSE_MATCH (1 << 5) |
| 182 | |
| 183 | /* Kind of displacement map used DISPU[BWD]4. */ |
| 184 | #define DISPUB4 (1 << 6) |
| 185 | #define DISPUW4 (1 << 7) |
| 186 | #define DISPUD4 (1 << 8) |
| 187 | #define DISPU4MAP (DISPUB4 | DISPUW4 | DISPUD4) |
| 188 | |
| 189 | /* Printing formats, where the instruction prefix isn't consecutive. */ |
| 190 | #define FMT_1 (1 << 9) /* 0xF0F00000 */ |
| 191 | #define FMT_2 (1 << 10) /* 0xFFF0FF00 */ |
| 192 | #define FMT_3 (1 << 11) /* 0xFFF00F00 */ |
| 193 | #define FMT_4 (1 << 12) /* 0xFFF0F000 */ |
| 194 | #define FMT_5 (1 << 13) /* 0xFFF0FFF0 */ |
| 195 | #define FMT_CRX (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5) |
| 196 | |
| 197 | /* Indicates whether this instruction can be relaxed. */ |
| 198 | #define RELAXABLE (1 << 14) |
| 199 | |
| 200 | /* Indicates that instruction uses user registers (and not |
| 201 | general-purpose registers) as operands. */ |
| 202 | #define USER_REG (1 << 15) |
| 203 | |
| 204 | /* Indicates that instruction can perfom a cst4 mapping. */ |
| 205 | #define CST4MAP (1 << 16) |
| 206 | |
| 207 | /* Instruction shouldn't allow 'sp' usage. */ |
| 208 | #define NO_SP (1 << 17) |
| 209 | |
| 210 | /* Instruction shouldn't allow to push a register which is used as a rptr. */ |
| 211 | #define NO_RPTR (1 << 18) |
| 212 | |
| 213 | /* Maximum operands per instruction. */ |
| 214 | #define MAX_OPERANDS 5 |
| 215 | /* Maximum register name length. */ |
| 216 | #define MAX_REGNAME_LEN 10 |
| 217 | /* Maximum instruction length. */ |
| 218 | #define MAX_INST_LEN 256 |
| 219 | |
| 220 | |
| 221 | /* Values defined for the flags field of a struct operand_entry. */ |
| 222 | |
| 223 | /* Operand must be an unsigned number. */ |
| 224 | #define OP_UNSIGNED (1 << 0) |
| 225 | /* Operand must be a signed number. */ |
| 226 | #define OP_SIGNED (1 << 1) |
| 227 | /* A special arithmetic 4-bit constant operand. */ |
| 228 | #define OP_CST4 (1 << 2) |
| 229 | /* A special load/stor 4-bit unsigned displacement operand. */ |
| 230 | #define OP_DISPU4 (1 << 3) |
| 231 | /* Operand must be an even number. */ |
| 232 | #define OP_EVEN (1 << 4) |
| 233 | /* Operand is shifted right. */ |
| 234 | #define OP_SHIFT (1 << 5) |
| 235 | /* Operand is shifted right and decremented. */ |
| 236 | #define OP_SHIFT_DEC (1 << 6) |
| 237 | /* Operand has reserved escape sequences. */ |
| 238 | #define OP_ESC (1 << 7) |
| 239 | /* Operand is used only for the upper 64 KB (FFFF0000 to FFFFFFFF). */ |
| 240 | #define OP_UPPER_64KB (1 << 8) |
| 241 | |
| 242 | /* Single operand description. */ |
| 243 | |
| 244 | typedef struct |
| 245 | { |
| 246 | /* Operand type. */ |
| 247 | operand_type op_type; |
| 248 | /* Operand location within the opcode. */ |
| 249 | unsigned int shift; |
| 250 | } |
| 251 | operand_desc; |
| 252 | |
| 253 | /* Instruction data structure used in instruction table. */ |
| 254 | |
| 255 | typedef struct |
| 256 | { |
| 257 | /* Name. */ |
| 258 | const char *mnemonic; |
| 259 | /* Size (in words). */ |
| 260 | unsigned int size; |
| 261 | /* Constant prefix (matched by the disassembler). */ |
| 262 | unsigned long match; |
| 263 | /* Match size (in bits). */ |
| 264 | int match_bits; |
| 265 | /* Attributes. */ |
| 266 | unsigned int flags; |
| 267 | /* Operands (always last, so unreferenced operands are initialized). */ |
| 268 | operand_desc operands[MAX_OPERANDS]; |
| 269 | } |
| 270 | inst; |
| 271 | |
| 272 | /* Data structure for a single instruction's arguments (Operands). */ |
| 273 | |
| 274 | typedef struct |
| 275 | { |
| 276 | /* Register or base register. */ |
| 277 | reg r; |
| 278 | /* Index register. */ |
| 279 | reg i_r; |
| 280 | /* Coprocessor register. */ |
| 281 | copreg cr; |
| 282 | /* Constant/immediate/absolute value. */ |
| 283 | long constant; |
| 284 | /* Scaled index mode. */ |
| 285 | unsigned int scale; |
| 286 | /* Argument type. */ |
| 287 | argtype type; |
| 288 | /* Size of the argument (in bits) required to represent. */ |
| 289 | int size; |
| 290 | /* The type of the expression. */ |
| 291 | unsigned char X_op; |
| 292 | } |
| 293 | argument; |
| 294 | |
| 295 | /* Internal structure to hold the various entities |
| 296 | corresponding to the current assembling instruction. */ |
| 297 | |
| 298 | typedef struct |
| 299 | { |
| 300 | /* Number of arguments. */ |
| 301 | int nargs; |
| 302 | /* The argument data structure for storing args (operands). */ |
| 303 | argument arg[MAX_OPERANDS]; |
| 304 | /* The following fields are required only by CRX-assembler. */ |
| 305 | #ifdef TC_CRX |
| 306 | /* Expression used for setting the fixups (if any). */ |
| 307 | expressionS exp; |
| 308 | bfd_reloc_code_real_type rtype; |
| 309 | #endif /* TC_CRX */ |
| 310 | /* Instruction size (in bytes). */ |
| 311 | int size; |
| 312 | } |
| 313 | ins; |
| 314 | |
| 315 | /* Structure to hold information about predefined operands. */ |
| 316 | |
| 317 | typedef struct |
| 318 | { |
| 319 | /* Size (in bits). */ |
| 320 | unsigned int bit_size; |
| 321 | /* Argument type. */ |
| 322 | argtype arg_type; |
| 323 | /* One bit syntax flags. */ |
| 324 | int flags; |
| 325 | } |
| 326 | operand_entry; |
| 327 | |
| 328 | /* Structure to hold trap handler information. */ |
| 329 | |
| 330 | typedef struct |
| 331 | { |
| 332 | /* Trap name. */ |
| 333 | char *name; |
| 334 | /* Index in dispatch table. */ |
| 335 | unsigned int entry; |
| 336 | } |
| 337 | trap_entry; |
| 338 | |
| 339 | /* Structure to hold information about predefined registers. */ |
| 340 | |
| 341 | typedef struct |
| 342 | { |
| 343 | /* Name (string representation). */ |
| 344 | char *name; |
| 345 | /* Value (enum representation). */ |
| 346 | union |
| 347 | { |
| 348 | /* Register. */ |
| 349 | reg reg_val; |
| 350 | /* Coprocessor register. */ |
| 351 | copreg copreg_val; |
| 352 | } value; |
| 353 | /* Register image. */ |
| 354 | int image; |
| 355 | /* Register type. */ |
| 356 | reg_type type; |
| 357 | } |
| 358 | reg_entry; |
| 359 | |
| 360 | /* Structure to hold a cst4 operand mapping. */ |
| 361 | |
| 362 | /* CRX opcode table. */ |
| 363 | extern const inst crx_instruction[]; |
| 364 | extern const int crx_num_opcodes; |
| 365 | #define NUMOPCODES crx_num_opcodes |
| 366 | |
| 367 | /* CRX operands table. */ |
| 368 | extern const operand_entry crx_optab[]; |
| 369 | |
| 370 | /* CRX registers table. */ |
| 371 | extern const reg_entry crx_regtab[]; |
| 372 | extern const int crx_num_regs; |
| 373 | #define NUMREGS crx_num_regs |
| 374 | |
| 375 | /* CRX coprocessor registers table. */ |
| 376 | extern const reg_entry crx_copregtab[]; |
| 377 | extern const int crx_num_copregs; |
| 378 | #define NUMCOPREGS crx_num_copregs |
| 379 | |
| 380 | /* CRX trap/interrupt table. */ |
| 381 | extern const trap_entry crx_traps[]; |
| 382 | extern const int crx_num_traps; |
| 383 | #define NUMTRAPS crx_num_traps |
| 384 | |
| 385 | /* cst4 operand mapping. */ |
| 386 | extern const long cst4_map[]; |
| 387 | extern const int cst4_maps; |
| 388 | |
| 389 | /* Table of instructions with no operands. */ |
| 390 | extern const char* no_op_insn[]; |
| 391 | |
| 392 | /* Current instruction we're assembling. */ |
| 393 | extern const inst *instruction; |
| 394 | |
| 395 | /* A macro for representing the instruction "constant" opcode, that is, |
| 396 | the FIXED part of the instruction. The "constant" opcode is represented |
| 397 | as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT) |
| 398 | over that range. */ |
| 399 | #define BIN(OPC,SHIFT) (OPC << SHIFT) |
| 400 | |
| 401 | /* Is the current instruction type is TYPE ? */ |
| 402 | #define IS_INSN_TYPE(TYPE) \ |
| 403 | (CRX_INS_TYPE(instruction->flags) == TYPE) |
| 404 | |
| 405 | /* Is the current instruction mnemonic is MNEMONIC ? */ |
| 406 | #define IS_INSN_MNEMONIC(MNEMONIC) \ |
| 407 | (strcmp(instruction->mnemonic,MNEMONIC) == 0) |
| 408 | |
| 409 | /* Does the current instruction has register list ? */ |
| 410 | #define INST_HAS_REG_LIST \ |
| 411 | (instruction->flags & REG_LIST) |
| 412 | |
| 413 | /* Long long type handling. */ |
| 414 | /* Replace all appearances of 'long long int' with LONGLONG. */ |
| 415 | typedef long long int LONGLONG; |
| 416 | typedef unsigned long long ULONGLONG; |
| 417 | |
| 418 | #endif /* _CRX_H_ */ |