| 1 | /* i386-opcode.h -- Intel 80386 opcode table |
| 2 | Copyright 1989, 91, 92, 93, 94, 95, 96, 1997 Free Software Foundation. |
| 3 | |
| 4 | This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 2 of the License, or |
| 9 | (at your option) any later version. |
| 10 | |
| 11 | This program is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | GNU General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with this program; if not, write to the Free Software |
| 18 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
| 19 | |
| 20 | /* The NON_BROKEN_OPCODES cases use the operands in the reverse order |
| 21 | from that documented in the Intel manuals. The opcode values are |
| 22 | such that they actually generate different instructions. These |
| 23 | values must not be changed, as they are the values generated by the |
| 24 | UnixWare assembler, and possibly other ix86 assemblers. */ |
| 25 | |
| 26 | static const template i386_optab[] = { |
| 27 | |
| 28 | #define _ None |
| 29 | /* move instructions */ |
| 30 | #define MOV_AX_DISP32 0xa0 |
| 31 | { "mov", 2, 0xa0, _, DW|NoModrm, { Disp32, Acc, 0 } }, |
| 32 | { "mov", 2, 0x88, _, DW|Modrm, { Reg, Reg|Mem, 0 } }, |
| 33 | { "mov", 2, 0xb0, _, ShortFormW, { Imm, Reg, 0 } }, |
| 34 | { "mov", 2, 0xc6, _, W|Modrm, { Imm, Reg|Mem, 0 } }, |
| 35 | { "mov", 2, 0x8c, _, D|Modrm, { SReg3|SReg2, Reg16|Mem, 0 } }, |
| 36 | /* move to/from control debug registers */ |
| 37 | { "mov", 2, 0x0f20, _, D|Modrm, { Control, Reg32, 0} }, |
| 38 | { "mov", 2, 0x0f21, _, D|Modrm, { Debug, Reg32, 0} }, |
| 39 | { "mov", 2, 0x0f24, _, D|Modrm, { Test, Reg32, 0} }, |
| 40 | |
| 41 | /* move with sign extend */ |
| 42 | /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid |
| 43 | conflict with the "movs" string move instruction. Thus, |
| 44 | {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} }, |
| 45 | is not kosher; we must seperate the two instructions. */ |
| 46 | {"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data32, { Reg8|Mem, Reg32, 0} }, |
| 47 | {"movsbw", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data16, { Reg8|Mem, Reg16, 0} }, |
| 48 | {"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} }, |
| 49 | |
| 50 | /* move with zero extend */ |
| 51 | {"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} }, |
| 52 | {"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} }, |
| 53 | |
| 54 | /* push instructions */ |
| 55 | {"push", 1, 0x50, _, ShortForm, { WordReg,0,0 } }, |
| 56 | {"push", 1, 0xff, 0x6, Modrm, { WordReg|WordMem, 0, 0 } }, |
| 57 | {"push", 1, 0x6a, _, NoModrm, { Imm8S, 0, 0} }, |
| 58 | {"push", 1, 0x68, _, NoModrm, { Imm16|Imm32, 0, 0} }, |
| 59 | {"push", 1, 0x06, _, Seg2ShortForm, { SReg2,0,0 } }, |
| 60 | {"push", 1, 0x0fa0, _, Seg3ShortForm, { SReg3,0,0 } }, |
| 61 | /* push all */ |
| 62 | {"pusha", 0, 0x60, _, NoModrm, { 0, 0, 0 } }, |
| 63 | |
| 64 | /* pop instructions */ |
| 65 | {"pop", 1, 0x58, _, ShortForm, { WordReg,0,0 } }, |
| 66 | {"pop", 1, 0x8f, 0x0, Modrm, { WordReg|WordMem, 0, 0 } }, |
| 67 | #define POP_SEG_SHORT 0x7 |
| 68 | {"pop", 1, 0x07, _, Seg2ShortForm, { SReg2,0,0 } }, |
| 69 | {"pop", 1, 0x0fa1, _, Seg3ShortForm, { SReg3,0,0 } }, |
| 70 | /* pop all */ |
| 71 | {"popa", 0, 0x61, _, NoModrm, { 0, 0, 0 } }, |
| 72 | |
| 73 | /* xchg exchange instructions |
| 74 | xchg commutes: we allow both operand orders */ |
| 75 | {"xchg", 2, 0x90, _, ShortForm, { WordReg, Acc, 0 } }, |
| 76 | {"xchg", 2, 0x90, _, ShortForm, { Acc, WordReg, 0 } }, |
| 77 | {"xchg", 2, 0x86, _, W|Modrm, { Reg, Reg|Mem, 0 } }, |
| 78 | {"xchg", 2, 0x86, _, W|Modrm, { Reg|Mem, Reg, 0 } }, |
| 79 | |
| 80 | /* in/out from ports */ |
| 81 | {"in", 2, 0xe4, _, W|NoModrm, { Imm8, Acc, 0 } }, |
| 82 | {"in", 2, 0xec, _, W|NoModrm, { InOutPortReg, Acc, 0 } }, |
| 83 | {"in", 1, 0xe4, _, W|NoModrm, { Imm8, 0, 0 } }, |
| 84 | {"in", 1, 0xec, _, W|NoModrm, { InOutPortReg, 0, 0 } }, |
| 85 | {"out", 2, 0xe6, _, W|NoModrm, { Acc, Imm8, 0 } }, |
| 86 | {"out", 2, 0xee, _, W|NoModrm, { Acc, InOutPortReg, 0 } }, |
| 87 | {"out", 1, 0xe6, _, W|NoModrm, { Imm8, 0, 0 } }, |
| 88 | {"out", 1, 0xee, _, W|NoModrm, { InOutPortReg, 0, 0 } }, |
| 89 | |
| 90 | /* load effective address */ |
| 91 | {"lea", 2, 0x8d, _, Modrm, { WordMem, WordReg, 0 } }, |
| 92 | |
| 93 | /* load segment registers from memory */ |
| 94 | {"lds", 2, 0xc5, _, Modrm, { Mem, Reg32, 0} }, |
| 95 | {"les", 2, 0xc4, _, Modrm, { Mem, Reg32, 0} }, |
| 96 | {"lfs", 2, 0x0fb4, _, Modrm, { Mem, Reg32, 0} }, |
| 97 | {"lgs", 2, 0x0fb5, _, Modrm, { Mem, Reg32, 0} }, |
| 98 | {"lss", 2, 0x0fb2, _, Modrm, { Mem, Reg32, 0} }, |
| 99 | |
| 100 | /* flags register instructions */ |
| 101 | {"clc", 0, 0xf8, _, NoModrm, { 0, 0, 0} }, |
| 102 | {"cld", 0, 0xfc, _, NoModrm, { 0, 0, 0} }, |
| 103 | {"cli", 0, 0xfa, _, NoModrm, { 0, 0, 0} }, |
| 104 | {"clts", 0, 0x0f06, _, NoModrm, { 0, 0, 0} }, |
| 105 | {"cmc", 0, 0xf5, _, NoModrm, { 0, 0, 0} }, |
| 106 | {"lahf", 0, 0x9f, _, NoModrm, { 0, 0, 0} }, |
| 107 | {"sahf", 0, 0x9e, _, NoModrm, { 0, 0, 0} }, |
| 108 | {"pushfl", 0, 0x9c, _, NoModrm|Data32, { 0, 0, 0} }, |
| 109 | {"popfl", 0, 0x9d, _, NoModrm|Data32, { 0, 0, 0} }, |
| 110 | {"pushfw", 0, 0x9c, _, NoModrm|Data16, { 0, 0, 0} }, |
| 111 | {"popfw", 0, 0x9d, _, NoModrm|Data16, { 0, 0, 0} }, |
| 112 | {"pushf", 0, 0x9c, _, NoModrm, { 0, 0, 0} }, |
| 113 | {"popf", 0, 0x9d, _, NoModrm, { 0, 0, 0} }, |
| 114 | {"stc", 0, 0xf9, _, NoModrm, { 0, 0, 0} }, |
| 115 | {"std", 0, 0xfd, _, NoModrm, { 0, 0, 0} }, |
| 116 | {"sti", 0, 0xfb, _, NoModrm, { 0, 0, 0} }, |
| 117 | |
| 118 | {"add", 2, 0x0, _, DW|Modrm, { Reg, Reg|Mem, 0} }, |
| 119 | {"add", 2, 0x83, 0, Modrm, { Imm8S, WordReg|WordMem, 0} }, |
| 120 | {"add", 2, 0x4, _, W|NoModrm, { Imm, Acc, 0} }, |
| 121 | {"add", 2, 0x80, 0, W|Modrm, { Imm, Reg|Mem, 0} }, |
| 122 | |
| 123 | {"inc", 1, 0x40, _, ShortForm, { WordReg, 0, 0} }, |
| 124 | {"inc", 1, 0xfe, 0, W|Modrm, { Reg|Mem, 0, 0} }, |
| 125 | |
| 126 | {"sub", 2, 0x28, _, DW|Modrm, { Reg, Reg|Mem, 0} }, |
| 127 | {"sub", 2, 0x83, 5, Modrm, { Imm8S, WordReg|WordMem, 0} }, |
| 128 | {"sub", 2, 0x2c, _, W|NoModrm, { Imm, Acc, 0} }, |
| 129 | {"sub", 2, 0x80, 5, W|Modrm, { Imm, Reg|Mem, 0} }, |
| 130 | |
| 131 | {"dec", 1, 0x48, _, ShortForm, { WordReg, 0, 0} }, |
| 132 | {"dec", 1, 0xfe, 1, W|Modrm, { Reg|Mem, 0, 0} }, |
| 133 | |
| 134 | {"sbb", 2, 0x18, _, DW|Modrm, { Reg, Reg|Mem, 0} }, |
| 135 | {"sbb", 2, 0x83, 3, Modrm, { Imm8S, WordReg|WordMem, 0} }, |
| 136 | {"sbb", 2, 0x1c, _, W|NoModrm, { Imm, Acc, 0} }, |
| 137 | {"sbb", 2, 0x80, 3, W|Modrm, { Imm, Reg|Mem, 0} }, |
| 138 | |
| 139 | {"cmp", 2, 0x38, _, DW|Modrm, { Reg, Reg|Mem, 0} }, |
| 140 | {"cmp", 2, 0x83, 7, Modrm, { Imm8S, WordReg|WordMem, 0} }, |
| 141 | {"cmp", 2, 0x3c, _, W|NoModrm, { Imm, Acc, 0} }, |
| 142 | {"cmp", 2, 0x80, 7, W|Modrm, { Imm, Reg|Mem, 0} }, |
| 143 | |
| 144 | {"test", 2, 0x84, _, W|Modrm, { Reg|Mem, Reg, 0} }, |
| 145 | {"test", 2, 0x84, _, W|Modrm, { Reg, Reg|Mem, 0} }, |
| 146 | {"test", 2, 0xa8, _, W|NoModrm, { Imm, Acc, 0} }, |
| 147 | {"test", 2, 0xf6, 0, W|Modrm, { Imm, Reg|Mem, 0} }, |
| 148 | |
| 149 | {"and", 2, 0x20, _, DW|Modrm, { Reg, Reg|Mem, 0} }, |
| 150 | {"and", 2, 0x83, 4, Modrm, { Imm8S, WordReg|WordMem, 0} }, |
| 151 | {"and", 2, 0x24, _, W|NoModrm, { Imm, Acc, 0} }, |
| 152 | {"and", 2, 0x80, 4, W|Modrm, { Imm, Reg|Mem, 0} }, |
| 153 | |
| 154 | {"or", 2, 0x08, _, DW|Modrm, { Reg, Reg|Mem, 0} }, |
| 155 | {"or", 2, 0x83, 1, Modrm, { Imm8S, WordReg|WordMem, 0} }, |
| 156 | {"or", 2, 0x0c, _, W|NoModrm, { Imm, Acc, 0} }, |
| 157 | {"or", 2, 0x80, 1, W|Modrm, { Imm, Reg|Mem, 0} }, |
| 158 | |
| 159 | {"xor", 2, 0x30, _, DW|Modrm, { Reg, Reg|Mem, 0} }, |
| 160 | {"xor", 2, 0x83, 6, Modrm, { Imm8S, WordReg|WordMem, 0} }, |
| 161 | {"xor", 2, 0x34, _, W|NoModrm, { Imm, Acc, 0} }, |
| 162 | {"xor", 2, 0x80, 6, W|Modrm, { Imm, Reg|Mem, 0} }, |
| 163 | |
| 164 | /* iclr with 1 operand is really xor with 2 operands. */ |
| 165 | {"clr", 1, 0x30, _, W|Modrm|iclrKludge, { Reg } }, |
| 166 | |
| 167 | {"adc", 2, 0x10, _, DW|Modrm, { Reg, Reg|Mem, 0} }, |
| 168 | {"adc", 2, 0x83, 2, Modrm, { Imm8S, WordReg|WordMem, 0} }, |
| 169 | {"adc", 2, 0x14, _, W|NoModrm, { Imm, Acc, 0} }, |
| 170 | {"adc", 2, 0x80, 2, W|Modrm, { Imm, Reg|Mem, 0} }, |
| 171 | |
| 172 | {"neg", 1, 0xf6, 3, W|Modrm, { Reg|Mem, 0, 0} }, |
| 173 | {"not", 1, 0xf6, 2, W|Modrm, { Reg|Mem, 0, 0} }, |
| 174 | |
| 175 | {"aaa", 0, 0x37, _, NoModrm, { 0, 0, 0} }, |
| 176 | {"aas", 0, 0x3f, _, NoModrm, { 0, 0, 0} }, |
| 177 | {"daa", 0, 0x27, _, NoModrm, { 0, 0, 0} }, |
| 178 | {"das", 0, 0x2f, _, NoModrm, { 0, 0, 0} }, |
| 179 | {"aad", 0, 0xd50a, _, NoModrm, { 0, 0, 0} }, |
| 180 | {"aam", 0, 0xd40a, _, NoModrm, { 0, 0, 0} }, |
| 181 | |
| 182 | /* conversion insns */ |
| 183 | /* conversion: intel naming */ |
| 184 | {"cbw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} }, |
| 185 | {"cwd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} }, |
| 186 | {"cwde", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} }, |
| 187 | {"cdq", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} }, |
| 188 | /* att naming */ |
| 189 | {"cbtw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} }, |
| 190 | {"cwtl", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} }, |
| 191 | {"cwtd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} }, |
| 192 | {"cltd", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} }, |
| 193 | |
| 194 | /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are |
| 195 | expanding 64-bit multiplies, and *cannot* be selected to accomplish |
| 196 | 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) |
| 197 | These multiplies can only be selected with single operand forms. */ |
| 198 | {"mul", 1, 0xf6, 4, W|Modrm, { Reg|Mem, 0, 0} }, |
| 199 | {"imul", 1, 0xf6, 5, W|Modrm, { Reg|Mem, 0, 0} }, |
| 200 | |
| 201 | |
| 202 | |
| 203 | |
| 204 | /* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields. |
| 205 | These instructions are exceptions: 'imul $2, %eax, %ecx' would put |
| 206 | '%eax' in the reg field and '%ecx' in the regmem field if we did not |
| 207 | switch them. */ |
| 208 | {"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} }, |
| 209 | {"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, { Imm8S, WordReg|Mem, WordReg} }, |
| 210 | {"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, { Imm16|Imm32, WordReg|Mem, WordReg} }, |
| 211 | /* |
| 212 | imul with 2 operands mimicks imul with 3 by puting register both |
| 213 | in i.rm.reg & i.rm.regmem fields |
| 214 | */ |
| 215 | {"imul", 2, 0x6b, _, Modrm|imulKludge, { Imm8S, WordReg, 0} }, |
| 216 | {"imul", 2, 0x69, _, Modrm|imulKludge, { Imm16|Imm32, WordReg, 0} }, |
| 217 | {"div", 1, 0xf6, 6, W|Modrm, { Reg|Mem, 0, 0} }, |
| 218 | {"div", 2, 0xf6, 6, W|Modrm, { Reg|Mem, Acc, 0} }, |
| 219 | {"idiv", 1, 0xf6, 7, W|Modrm, { Reg|Mem, 0, 0} }, |
| 220 | {"idiv", 2, 0xf6, 7, W|Modrm, { Reg|Mem, Acc, 0} }, |
| 221 | |
| 222 | {"rol", 2, 0xd0, 0, W|Modrm, { Imm1, Reg|Mem, 0} }, |
| 223 | {"rol", 2, 0xc0, 0, W|Modrm, { Imm8, Reg|Mem, 0} }, |
| 224 | {"rol", 2, 0xd2, 0, W|Modrm, { ShiftCount, Reg|Mem, 0} }, |
| 225 | {"rol", 1, 0xd0, 0, W|Modrm, { Reg|Mem, 0, 0} }, |
| 226 | |
| 227 | {"ror", 2, 0xd0, 1, W|Modrm, { Imm1, Reg|Mem, 0} }, |
| 228 | {"ror", 2, 0xc0, 1, W|Modrm, { Imm8, Reg|Mem, 0} }, |
| 229 | {"ror", 2, 0xd2, 1, W|Modrm, { ShiftCount, Reg|Mem, 0} }, |
| 230 | {"ror", 1, 0xd0, 1, W|Modrm, { Reg|Mem, 0, 0} }, |
| 231 | |
| 232 | {"rcl", 2, 0xd0, 2, W|Modrm, { Imm1, Reg|Mem, 0} }, |
| 233 | {"rcl", 2, 0xc0, 2, W|Modrm, { Imm8, Reg|Mem, 0} }, |
| 234 | {"rcl", 2, 0xd2, 2, W|Modrm, { ShiftCount, Reg|Mem, 0} }, |
| 235 | {"rcl", 1, 0xd0, 2, W|Modrm, { Reg|Mem, 0, 0} }, |
| 236 | |
| 237 | {"rcr", 2, 0xd0, 3, W|Modrm, { Imm1, Reg|Mem, 0} }, |
| 238 | {"rcr", 2, 0xc0, 3, W|Modrm, { Imm8, Reg|Mem, 0} }, |
| 239 | {"rcr", 2, 0xd2, 3, W|Modrm, { ShiftCount, Reg|Mem, 0} }, |
| 240 | {"rcr", 1, 0xd0, 3, W|Modrm, { Reg|Mem, 0, 0} }, |
| 241 | |
| 242 | {"sal", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} }, |
| 243 | {"sal", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} }, |
| 244 | {"sal", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} }, |
| 245 | {"sal", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} }, |
| 246 | {"shl", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} }, |
| 247 | {"shl", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} }, |
| 248 | {"shl", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} }, |
| 249 | {"shl", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} }, |
| 250 | |
| 251 | {"shld", 3, 0x0fa4, _, Modrm, { Imm8, WordReg, WordReg|Mem} }, |
| 252 | {"shld", 3, 0x0fa5, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} }, |
| 253 | {"shld", 2, 0x0fa5, _, Modrm, { WordReg, WordReg|Mem, 0} }, |
| 254 | |
| 255 | {"shr", 2, 0xd0, 5, W|Modrm, { Imm1, Reg|Mem, 0} }, |
| 256 | {"shr", 2, 0xc0, 5, W|Modrm, { Imm8, Reg|Mem, 0} }, |
| 257 | {"shr", 2, 0xd2, 5, W|Modrm, { ShiftCount, Reg|Mem, 0} }, |
| 258 | {"shr", 1, 0xd0, 5, W|Modrm, { Reg|Mem, 0, 0} }, |
| 259 | |
| 260 | {"shrd", 3, 0x0fac, _, Modrm, { Imm8, WordReg, WordReg|Mem} }, |
| 261 | {"shrd", 3, 0x0fad, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} }, |
| 262 | {"shrd", 2, 0x0fad, _, Modrm, { WordReg, WordReg|Mem, 0} }, |
| 263 | |
| 264 | {"sar", 2, 0xd0, 7, W|Modrm, { Imm1, Reg|Mem, 0} }, |
| 265 | {"sar", 2, 0xc0, 7, W|Modrm, { Imm8, Reg|Mem, 0} }, |
| 266 | {"sar", 2, 0xd2, 7, W|Modrm, { ShiftCount, Reg|Mem, 0} }, |
| 267 | {"sar", 1, 0xd0, 7, W|Modrm, { Reg|Mem, 0, 0} }, |
| 268 | |
| 269 | /* control transfer instructions */ |
| 270 | #define CALL_PC_RELATIVE 0xe8 |
| 271 | {"call", 1, 0xe8, _, JumpDword, { Disp32, 0, 0} }, |
| 272 | {"call", 1, 0xff, 2, Modrm|Data32, { Reg|Mem|JumpAbsolute, 0, 0} }, |
| 273 | {"callw", 1, 0xff, 2, Modrm|Data16, { Reg|Mem|JumpAbsolute, 0, 0} }, |
| 274 | #define CALL_FAR_IMMEDIATE 0x9a |
| 275 | {"lcall", 2, 0x9a, _, JumpInterSegment, { Imm16, Imm32, 0} }, |
| 276 | {"lcall", 1, 0xff, 3, Modrm|Data32, { Mem, 0, 0} }, |
| 277 | {"lcallw", 1, 0xff, 3, Modrm|Data16, { Mem, 0, 0} }, |
| 278 | |
| 279 | #define JUMP_PC_RELATIVE 0xeb |
| 280 | {"jmp", 1, 0xeb, _, Jump, { Disp, 0, 0} }, |
| 281 | {"jmp", 1, 0xff, 4, Modrm, { Reg32|Mem|JumpAbsolute, 0, 0} }, |
| 282 | #define JUMP_FAR_IMMEDIATE 0xea |
| 283 | {"ljmp", 2, 0xea, _, JumpInterSegment, { Imm16, Imm32, 0} }, |
| 284 | {"ljmp", 1, 0xff, 5, Modrm|Data32, { Mem, 0, 0} }, |
| 285 | |
| 286 | {"ret", 0, 0xc3, _, NoModrm|Data32, { 0, 0, 0} }, |
| 287 | {"ret", 1, 0xc2, _, NoModrm|Data32, { Imm16, 0, 0} }, |
| 288 | {"retw", 0, 0xc3, _, NoModrm|Data16, { 0, 0, 0} }, |
| 289 | {"retw", 1, 0xc2, _, NoModrm|Data16, { Imm16, 0, 0} }, |
| 290 | {"lret", 0, 0xcb, _, NoModrm|Data32, { 0, 0, 0} }, |
| 291 | {"lret", 1, 0xca, _, NoModrm|Data32, { Imm16, 0, 0} }, |
| 292 | {"lretw", 0, 0xcb, _, NoModrm|Data16, { 0, 0, 0} }, |
| 293 | {"lretw", 1, 0xca, _, NoModrm|Data16, { Imm16, 0, 0} }, |
| 294 | {"enter", 2, 0xc8, _, NoModrm|Data32, { Imm16, Imm8, 0} }, |
| 295 | {"leave", 0, 0xc9, _, NoModrm|Data32, { 0, 0, 0} }, |
| 296 | {"enterw", 2, 0xc8, _, NoModrm|Data16, { Imm16, Imm8, 0} }, |
| 297 | {"leavew", 0, 0xc9, _, NoModrm|Data16, { 0, 0, 0} }, |
| 298 | |
| 299 | /* conditional jumps */ |
| 300 | {"jo", 1, 0x70, _, Jump, { Disp, 0, 0} }, |
| 301 | |
| 302 | {"jno", 1, 0x71, _, Jump, { Disp, 0, 0} }, |
| 303 | |
| 304 | {"jb", 1, 0x72, _, Jump, { Disp, 0, 0} }, |
| 305 | {"jc", 1, 0x72, _, Jump, { Disp, 0, 0} }, |
| 306 | {"jnae", 1, 0x72, _, Jump, { Disp, 0, 0} }, |
| 307 | |
| 308 | {"jnb", 1, 0x73, _, Jump, { Disp, 0, 0} }, |
| 309 | {"jnc", 1, 0x73, _, Jump, { Disp, 0, 0} }, |
| 310 | {"jae", 1, 0x73, _, Jump, { Disp, 0, 0} }, |
| 311 | |
| 312 | {"je", 1, 0x74, _, Jump, { Disp, 0, 0} }, |
| 313 | {"jz", 1, 0x74, _, Jump, { Disp, 0, 0} }, |
| 314 | |
| 315 | {"jne", 1, 0x75, _, Jump, { Disp, 0, 0} }, |
| 316 | {"jnz", 1, 0x75, _, Jump, { Disp, 0, 0} }, |
| 317 | |
| 318 | {"jbe", 1, 0x76, _, Jump, { Disp, 0, 0} }, |
| 319 | {"jna", 1, 0x76, _, Jump, { Disp, 0, 0} }, |
| 320 | |
| 321 | {"jnbe", 1, 0x77, _, Jump, { Disp, 0, 0} }, |
| 322 | {"ja", 1, 0x77, _, Jump, { Disp, 0, 0} }, |
| 323 | |
| 324 | {"js", 1, 0x78, _, Jump, { Disp, 0, 0} }, |
| 325 | |
| 326 | {"jns", 1, 0x79, _, Jump, { Disp, 0, 0} }, |
| 327 | |
| 328 | {"jp", 1, 0x7a, _, Jump, { Disp, 0, 0} }, |
| 329 | {"jpe", 1, 0x7a, _, Jump, { Disp, 0, 0} }, |
| 330 | |
| 331 | {"jnp", 1, 0x7b, _, Jump, { Disp, 0, 0} }, |
| 332 | {"jpo", 1, 0x7b, _, Jump, { Disp, 0, 0} }, |
| 333 | |
| 334 | {"jl", 1, 0x7c, _, Jump, { Disp, 0, 0} }, |
| 335 | {"jnge", 1, 0x7c, _, Jump, { Disp, 0, 0} }, |
| 336 | |
| 337 | {"jnl", 1, 0x7d, _, Jump, { Disp, 0, 0} }, |
| 338 | {"jge", 1, 0x7d, _, Jump, { Disp, 0, 0} }, |
| 339 | |
| 340 | {"jle", 1, 0x7e, _, Jump, { Disp, 0, 0} }, |
| 341 | {"jng", 1, 0x7e, _, Jump, { Disp, 0, 0} }, |
| 342 | |
| 343 | {"jnle", 1, 0x7f, _, Jump, { Disp, 0, 0} }, |
| 344 | {"jg", 1, 0x7f, _, Jump, { Disp, 0, 0} }, |
| 345 | |
| 346 | #define IS_JUMP_ON_CX_ZERO(o) \ |
| 347 | (o == 0xe3) |
| 348 | |
| 349 | /* jcxz vs. jecxz is chosen on the basis of the address size prefix. */ |
| 350 | {"jcxz", 1, 0xe3, _, JumpByte|Data16, { Disp, 0, 0} }, |
| 351 | {"jecxz", 1, 0xe3, _, JumpByte|Data32, { Disp, 0, 0} }, |
| 352 | |
| 353 | #define IS_LOOP_ECX_TIMES(o) \ |
| 354 | (o == 0xe2 || o == 0xe1 || o == 0xe0) |
| 355 | |
| 356 | {"loop", 1, 0xe2, _, JumpByte, { Disp, 0, 0} }, |
| 357 | |
| 358 | {"loopz", 1, 0xe1, _, JumpByte, { Disp, 0, 0} }, |
| 359 | {"loope", 1, 0xe1, _, JumpByte, { Disp, 0, 0} }, |
| 360 | |
| 361 | {"loopnz", 1, 0xe0, _, JumpByte, { Disp, 0, 0} }, |
| 362 | {"loopne", 1, 0xe0, _, JumpByte, { Disp, 0, 0} }, |
| 363 | |
| 364 | /* set byte on flag instructions */ |
| 365 | {"seto", 1, 0x0f90, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 366 | |
| 367 | {"setno", 1, 0x0f91, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 368 | |
| 369 | {"setb", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 370 | {"setc", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 371 | {"setnae", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 372 | |
| 373 | {"setnb", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 374 | {"setnc", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 375 | {"setae", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 376 | |
| 377 | {"sete", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 378 | {"setz", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 379 | |
| 380 | {"setne", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 381 | {"setnz", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 382 | |
| 383 | {"setbe", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 384 | {"setna", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 385 | |
| 386 | {"setnbe", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 387 | {"seta", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 388 | |
| 389 | {"sets", 1, 0x0f98, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 390 | |
| 391 | {"setns", 1, 0x0f99, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 392 | |
| 393 | {"setp", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 394 | {"setpe", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 395 | |
| 396 | {"setnp", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 397 | {"setpo", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 398 | |
| 399 | {"setl", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 400 | {"setnge", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 401 | |
| 402 | {"setnl", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 403 | {"setge", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 404 | |
| 405 | {"setle", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 406 | {"setng", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 407 | |
| 408 | {"setnle", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 409 | {"setg", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} }, |
| 410 | |
| 411 | #define IS_STRING_INSTRUCTION(o) \ |
| 412 | ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \ |
| 413 | (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \ |
| 414 | (o) == 0xd7) |
| 415 | |
| 416 | /* string manipulation */ |
| 417 | {"cmps", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} }, |
| 418 | {"scmp", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} }, |
| 419 | {"ins", 0, 0x6c, _, W|NoModrm, { 0, 0, 0} }, |
| 420 | {"outs", 0, 0x6e, _, W|NoModrm, { 0, 0, 0} }, |
| 421 | {"lods", 0, 0xac, _, W|NoModrm, { 0, 0, 0} }, |
| 422 | {"slod", 0, 0xac, _, W|NoModrm, { 0, 0, 0} }, |
| 423 | {"movs", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} }, |
| 424 | {"smov", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} }, |
| 425 | {"scas", 0, 0xae, _, W|NoModrm, { 0, 0, 0} }, |
| 426 | {"ssca", 0, 0xae, _, W|NoModrm, { 0, 0, 0} }, |
| 427 | {"stos", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} }, |
| 428 | {"ssto", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} }, |
| 429 | {"xlat", 0, 0xd7, _, NoModrm, { 0, 0, 0} }, |
| 430 | |
| 431 | /* bit manipulation */ |
| 432 | {"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} }, |
| 433 | {"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} }, |
| 434 | {"bt", 2, 0x0fa3, _, Modrm, { Reg, Reg|Mem, 0} }, |
| 435 | {"bt", 2, 0x0fba, 4, Modrm, { Imm8, Reg|Mem, 0} }, |
| 436 | {"btc", 2, 0x0fbb, _, Modrm, { Reg, Reg|Mem, 0} }, |
| 437 | {"btc", 2, 0x0fba, 7, Modrm, { Imm8, Reg|Mem, 0} }, |
| 438 | {"btr", 2, 0x0fb3, _, Modrm, { Reg, Reg|Mem, 0} }, |
| 439 | {"btr", 2, 0x0fba, 6, Modrm, { Imm8, Reg|Mem, 0} }, |
| 440 | {"bts", 2, 0x0fab, _, Modrm, { Reg, Reg|Mem, 0} }, |
| 441 | {"bts", 2, 0x0fba, 5, Modrm, { Imm8, Reg|Mem, 0} }, |
| 442 | |
| 443 | /* interrupts & op. sys insns */ |
| 444 | /* See gas/config/tc-i386.c for conversion of 'int $3' into the special |
| 445 | int 3 insn. */ |
| 446 | #define INT_OPCODE 0xcd |
| 447 | #define INT3_OPCODE 0xcc |
| 448 | {"int", 1, 0xcd, _, NoModrm, { Imm8, 0, 0} }, |
| 449 | {"int3", 0, 0xcc, _, NoModrm, { 0, 0, 0} }, |
| 450 | {"into", 0, 0xce, _, NoModrm, { 0, 0, 0} }, |
| 451 | {"iret", 0, 0xcf, _, NoModrm|Data32, { 0, 0, 0} }, |
| 452 | {"iretw", 0, 0xcf, _, NoModrm|Data16, { 0, 0, 0} }, |
| 453 | /* i386sl, i486sl, later 486, and Pentium */ |
| 454 | {"rsm", 0, 0x0faa, _, NoModrm,{ 0, 0, 0} }, |
| 455 | |
| 456 | {"boundl", 2, 0x62, _, Modrm|Data32, { Reg32, Mem, 0} }, |
| 457 | {"boundw", 2, 0x62, _, Modrm|Data16, { Reg16, Mem, 0} }, |
| 458 | |
| 459 | {"hlt", 0, 0xf4, _, NoModrm, { 0, 0, 0} }, |
| 460 | {"wait", 0, 0x9b, _, NoModrm, { 0, 0, 0} }, |
| 461 | /* nop is actually 'xchgl %eax, %eax' */ |
| 462 | {"nop", 0, 0x90, _, NoModrm, { 0, 0, 0} }, |
| 463 | |
| 464 | /* protection control */ |
| 465 | {"arpl", 2, 0x63, _, Modrm, { Reg16, Reg16|Mem, 0} }, |
| 466 | {"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} }, |
| 467 | {"lgdt", 1, 0x0f01, 2, Modrm, { Mem, 0, 0} }, |
| 468 | {"lidt", 1, 0x0f01, 3, Modrm, { Mem, 0, 0} }, |
| 469 | {"lldt", 1, 0x0f00, 2, Modrm, { WordReg|Mem, 0, 0} }, |
| 470 | {"lmsw", 1, 0x0f01, 6, Modrm, { WordReg|Mem, 0, 0} }, |
| 471 | {"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} }, |
| 472 | {"ltr", 1, 0x0f00, 3, Modrm, { WordReg|Mem, 0, 0} }, |
| 473 | |
| 474 | {"sgdt", 1, 0x0f01, 0, Modrm, { Mem, 0, 0} }, |
| 475 | {"sidt", 1, 0x0f01, 1, Modrm, { Mem, 0, 0} }, |
| 476 | {"sldt", 1, 0x0f00, 0, Modrm, { WordReg|Mem, 0, 0} }, |
| 477 | {"smsw", 1, 0x0f01, 4, Modrm, { WordReg|Mem, 0, 0} }, |
| 478 | {"str", 1, 0x0f00, 1, Modrm, { Reg16|Mem, 0, 0} }, |
| 479 | |
| 480 | {"verr", 1, 0x0f00, 4, Modrm, { WordReg|Mem, 0, 0} }, |
| 481 | {"verw", 1, 0x0f00, 5, Modrm, { WordReg|Mem, 0, 0} }, |
| 482 | |
| 483 | /* floating point instructions */ |
| 484 | |
| 485 | /* load */ |
| 486 | {"fld", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ |
| 487 | {"flds", 1, 0xd9, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem float */ |
| 488 | {"fldl", 1, 0xdd, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem double */ |
| 489 | {"fldl", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ |
| 490 | {"fild", 1, 0xdf, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem word (16) */ |
| 491 | {"fildl", 1, 0xdb, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem dword (32) */ |
| 492 | {"fildq",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */ |
| 493 | {"fildll",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */ |
| 494 | {"fldt", 1, 0xdb, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem efloat */ |
| 495 | {"fbld", 1, 0xdf, 4, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem bcd */ |
| 496 | |
| 497 | /* store (no pop) */ |
| 498 | {"fst", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ |
| 499 | {"fsts", 1, 0xd9, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */ |
| 500 | {"fstl", 1, 0xdd, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */ |
| 501 | {"fstl", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ |
| 502 | {"fist", 1, 0xdf, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */ |
| 503 | {"fistl", 1, 0xdb, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */ |
| 504 | |
| 505 | /* store (with pop) */ |
| 506 | {"fstp", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */ |
| 507 | {"fstps", 1, 0xd9, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */ |
| 508 | {"fstpl", 1, 0xdd, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */ |
| 509 | {"fstpl", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */ |
| 510 | {"fistp", 1, 0xdf, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */ |
| 511 | {"fistpl",1, 0xdb, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */ |
| 512 | {"fistpq",1, 0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */ |
| 513 | {"fistpll",1,0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */ |
| 514 | {"fstpt", 1, 0xdb, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem efloat */ |
| 515 | {"fbstp", 1, 0xdf, 6, Modrm, { Mem, 0, 0} }, /* %st0 --> mem bcd */ |
| 516 | |
| 517 | /* exchange %st<n> with %st0 */ |
| 518 | {"fxch", 1, 0xd9c8, _, ShortForm, { FloatReg, 0, 0} }, |
| 519 | {"fxch", 0, 0xd9c9, _, NoModrm, { 0, 0, 0} }, /* alias for fxch %st, %st(1) */ |
| 520 | |
| 521 | /* comparison (without pop) */ |
| 522 | {"fcom", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} }, |
| 523 | {"fcoms", 1, 0xd8, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */ |
| 524 | {"ficoml", 1, 0xda, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */ |
| 525 | {"fcoml", 1, 0xdc, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */ |
| 526 | {"fcoml", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} }, |
| 527 | {"ficoms", 1, 0xde, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */ |
| 528 | |
| 529 | /* comparison (with pop) */ |
| 530 | {"fcomp", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} }, |
| 531 | {"fcomp", 0, 0xd8d9, _, NoModrm, {0, 0, 0} }, /* fcomp %st, %st(1) */ |
| 532 | {"fcomps", 1, 0xd8, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */ |
| 533 | {"ficompl", 1, 0xda, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */ |
| 534 | {"fcompl", 1, 0xdc, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */ |
| 535 | {"fcompl", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} }, |
| 536 | {"ficomps", 1, 0xde, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */ |
| 537 | {"fcompp", 0, 0xded9, _, NoModrm, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */ |
| 538 | |
| 539 | /* unordered comparison (with pop) */ |
| 540 | {"fucom", 1, 0xdde0, _, ShortForm, { FloatReg, 0, 0} }, |
| 541 | {"fucomp", 1, 0xdde8, _, ShortForm, { FloatReg, 0, 0} }, |
| 542 | {"fucompp", 0, 0xdae9, _, NoModrm, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */ |
| 543 | |
| 544 | {"ftst", 0, 0xd9e4, _, NoModrm, { 0, 0, 0} }, /* test %st0 */ |
| 545 | {"fxam", 0, 0xd9e5, _, NoModrm, { 0, 0, 0} }, /* examine %st0 */ |
| 546 | |
| 547 | /* load constants into %st0 */ |
| 548 | {"fld1", 0, 0xd9e8, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 1.0 */ |
| 549 | {"fldl2t", 0, 0xd9e9, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(10) */ |
| 550 | {"fldl2e", 0, 0xd9ea, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(e) */ |
| 551 | {"fldpi", 0, 0xd9eb, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- pi */ |
| 552 | {"fldlg2", 0, 0xd9ec, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log10(2) */ |
| 553 | {"fldln2", 0, 0xd9ed, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- ln(2) */ |
| 554 | {"fldz", 0, 0xd9ee, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 0.0 */ |
| 555 | |
| 556 | /* arithmetic */ |
| 557 | |
| 558 | /* add */ |
| 559 | {"fadd", 1, 0xd8c0, _, ShortForm, { FloatReg, 0, 0} }, |
| 560 | {"fadd", 2, 0xd8c0, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, |
| 561 | {"fadd", 0, 0xdcc1, _, NoModrm, { 0, 0, 0} }, /* alias for fadd %st, %st(1) */ |
| 562 | {"faddp", 1, 0xdec0, _, ShortForm, { FloatReg, 0, 0} }, |
| 563 | {"faddp", 2, 0xdec0, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 564 | {"faddp", 2, 0xdec0, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
| 565 | {"faddp", 0, 0xdec1, _, NoModrm, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */ |
| 566 | {"fadds", 1, 0xd8, 0, Modrm, { Mem, 0, 0} }, |
| 567 | {"fiaddl", 1, 0xda, 0, Modrm, { Mem, 0, 0} }, |
| 568 | {"faddl", 1, 0xdc, 0, Modrm, { Mem, 0, 0} }, |
| 569 | {"fiadds", 1, 0xde, 0, Modrm, { Mem, 0, 0} }, |
| 570 | |
| 571 | /* sub */ |
| 572 | /* Note: intel has decided that certain of these operations are reversed |
| 573 | in assembler syntax. */ |
| 574 | {"fsub", 1, 0xd8e0, _, ShortForm, { FloatReg, 0, 0} }, |
| 575 | {"fsub", 2, 0xd8e0, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 576 | #ifdef NON_BROKEN_OPCODES |
| 577 | {"fsub", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
| 578 | #else |
| 579 | {"fsub", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
| 580 | #endif |
| 581 | {"fsub", 0, 0xdce1, _, NoModrm, { 0, 0, 0} }, |
| 582 | {"fsubp", 1, 0xdee8, _, ShortForm, { FloatReg, 0, 0} }, |
| 583 | {"fsubp", 2, 0xdee8, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 584 | #ifdef NON_BROKEN_OPCODES |
| 585 | {"fsubp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
| 586 | {"fsubp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} }, |
| 587 | #else |
| 588 | {"fsubp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
| 589 | {"fsubp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} }, |
| 590 | #endif |
| 591 | {"fsubs", 1, 0xd8, 4, Modrm, { Mem, 0, 0} }, |
| 592 | {"fisubl", 1, 0xda, 4, Modrm, { Mem, 0, 0} }, |
| 593 | {"fsubl", 1, 0xdc, 4, Modrm, { Mem, 0, 0} }, |
| 594 | {"fisubs", 1, 0xde, 4, Modrm, { Mem, 0, 0} }, |
| 595 | |
| 596 | /* sub reverse */ |
| 597 | {"fsubr", 1, 0xd8e8, _, ShortForm, { FloatReg, 0, 0} }, |
| 598 | {"fsubr", 2, 0xd8e8, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 599 | #ifdef NON_BROKEN_OPCODES |
| 600 | {"fsubr", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
| 601 | #else |
| 602 | {"fsubr", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
| 603 | #endif |
| 604 | {"fsubr", 0, 0xdce9, _, NoModrm, { 0, 0, 0} }, |
| 605 | {"fsubrp", 1, 0xdee0, _, ShortForm, { FloatReg, 0, 0} }, |
| 606 | {"fsubrp", 2, 0xdee0, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 607 | #ifdef NON_BROKEN_OPCODES |
| 608 | {"fsubrp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
| 609 | {"fsubrp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} }, |
| 610 | #else |
| 611 | {"fsubrp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
| 612 | {"fsubrp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} }, |
| 613 | #endif |
| 614 | {"fsubrs", 1, 0xd8, 5, Modrm, { Mem, 0, 0} }, |
| 615 | {"fisubrl", 1, 0xda, 5, Modrm, { Mem, 0, 0} }, |
| 616 | {"fsubrl", 1, 0xdc, 5, Modrm, { Mem, 0, 0} }, |
| 617 | {"fisubrs", 1, 0xde, 5, Modrm, { Mem, 0, 0} }, |
| 618 | |
| 619 | /* mul */ |
| 620 | {"fmul", 1, 0xd8c8, _, ShortForm, { FloatReg, 0, 0} }, |
| 621 | {"fmul", 2, 0xd8c8, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, |
| 622 | {"fmul", 0, 0xdcc9, _, NoModrm, { 0, 0, 0} }, |
| 623 | {"fmulp", 1, 0xdec8, _, ShortForm, { FloatReg, 0, 0} }, |
| 624 | {"fmulp", 2, 0xdec8, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 625 | {"fmulp", 2, 0xdec8, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
| 626 | {"fmulp", 0, 0xdec9, _, NoModrm, { 0, 0, 0} }, |
| 627 | {"fmuls", 1, 0xd8, 1, Modrm, { Mem, 0, 0} }, |
| 628 | {"fimull", 1, 0xda, 1, Modrm, { Mem, 0, 0} }, |
| 629 | {"fmull", 1, 0xdc, 1, Modrm, { Mem, 0, 0} }, |
| 630 | {"fimuls", 1, 0xde, 1, Modrm, { Mem, 0, 0} }, |
| 631 | |
| 632 | /* div */ |
| 633 | /* Note: intel has decided that certain of these operations are reversed |
| 634 | in assembler syntax. */ |
| 635 | {"fdiv", 1, 0xd8f0, _, ShortForm, { FloatReg, 0, 0} }, |
| 636 | {"fdiv", 2, 0xd8f0, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 637 | #ifdef NON_BROKEN_OPCODES |
| 638 | {"fdiv", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
| 639 | #else |
| 640 | {"fdiv", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
| 641 | #endif |
| 642 | {"fdiv", 0, 0xdcf1, _, NoModrm, { 0, 0, 0} }, |
| 643 | {"fdivp", 1, 0xdef8, _, ShortForm, { FloatReg, 0, 0} }, |
| 644 | {"fdivp", 2, 0xdef8, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 645 | #ifdef NON_BROKEN_OPCODES |
| 646 | {"fdivp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
| 647 | {"fdivp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} }, |
| 648 | #else |
| 649 | {"fdivp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
| 650 | {"fdivp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} }, |
| 651 | #endif |
| 652 | {"fdivs", 1, 0xd8, 6, Modrm, { Mem, 0, 0} }, |
| 653 | {"fidivl", 1, 0xda, 6, Modrm, { Mem, 0, 0} }, |
| 654 | {"fdivl", 1, 0xdc, 6, Modrm, { Mem, 0, 0} }, |
| 655 | {"fidivs", 1, 0xde, 6, Modrm, { Mem, 0, 0} }, |
| 656 | |
| 657 | /* div reverse */ |
| 658 | {"fdivr", 1, 0xd8f8, _, ShortForm, { FloatReg, 0, 0} }, |
| 659 | {"fdivr", 2, 0xd8f8, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 660 | #ifdef NON_BROKEN_OPCODES |
| 661 | {"fdivr", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
| 662 | #else |
| 663 | {"fdivr", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
| 664 | #endif |
| 665 | {"fdivr", 0, 0xdcf9, _, NoModrm, { 0, 0, 0} }, |
| 666 | {"fdivrp", 1, 0xdef0, _, ShortForm, { FloatReg, 0, 0} }, |
| 667 | {"fdivrp", 2, 0xdef0, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 668 | #ifdef NON_BROKEN_OPCODES |
| 669 | {"fdivrp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
| 670 | {"fdivrp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} }, |
| 671 | #else |
| 672 | {"fdivrp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
| 673 | {"fdivrp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} }, |
| 674 | #endif |
| 675 | {"fdivrs", 1, 0xd8, 7, Modrm, { Mem, 0, 0} }, |
| 676 | {"fidivrl", 1, 0xda, 7, Modrm, { Mem, 0, 0} }, |
| 677 | {"fdivrl", 1, 0xdc, 7, Modrm, { Mem, 0, 0} }, |
| 678 | {"fidivrs", 1, 0xde, 7, Modrm, { Mem, 0, 0} }, |
| 679 | |
| 680 | {"f2xm1", 0, 0xd9f0, _, NoModrm, { 0, 0, 0} }, |
| 681 | {"fyl2x", 0, 0xd9f1, _, NoModrm, { 0, 0, 0} }, |
| 682 | {"fptan", 0, 0xd9f2, _, NoModrm, { 0, 0, 0} }, |
| 683 | {"fpatan", 0, 0xd9f3, _, NoModrm, { 0, 0, 0} }, |
| 684 | {"fxtract", 0, 0xd9f4, _, NoModrm, { 0, 0, 0} }, |
| 685 | {"fprem1", 0, 0xd9f5, _, NoModrm, { 0, 0, 0} }, |
| 686 | {"fdecstp", 0, 0xd9f6, _, NoModrm, { 0, 0, 0} }, |
| 687 | {"fincstp", 0, 0xd9f7, _, NoModrm, { 0, 0, 0} }, |
| 688 | {"fprem", 0, 0xd9f8, _, NoModrm, { 0, 0, 0} }, |
| 689 | {"fyl2xp1", 0, 0xd9f9, _, NoModrm, { 0, 0, 0} }, |
| 690 | {"fsqrt", 0, 0xd9fa, _, NoModrm, { 0, 0, 0} }, |
| 691 | {"fsincos", 0, 0xd9fb, _, NoModrm, { 0, 0, 0} }, |
| 692 | {"frndint", 0, 0xd9fc, _, NoModrm, { 0, 0, 0} }, |
| 693 | {"fscale", 0, 0xd9fd, _, NoModrm, { 0, 0, 0} }, |
| 694 | {"fsin", 0, 0xd9fe, _, NoModrm, { 0, 0, 0} }, |
| 695 | {"fcos", 0, 0xd9ff, _, NoModrm, { 0, 0, 0} }, |
| 696 | |
| 697 | {"fchs", 0, 0xd9e0, _, NoModrm, { 0, 0, 0} }, |
| 698 | {"fabs", 0, 0xd9e1, _, NoModrm, { 0, 0, 0} }, |
| 699 | |
| 700 | /* processor control */ |
| 701 | {"fninit", 0, 0xdbe3, _, NoModrm, { 0, 0, 0} }, |
| 702 | {"finit", 0, 0x9bdbe3, _, NoModrm, { 0, 0, 0} }, |
| 703 | {"fldcw", 1, 0xd9, 5, Modrm, { Mem, 0, 0} }, |
| 704 | {"fnstcw", 1, 0xd9, 7, Modrm, { Mem, 0, 0} }, |
| 705 | {"fstcw", 1, 0x9bd9, 7, Modrm, { Mem, 0, 0} }, |
| 706 | {"fnstsw", 1, 0xdfe0, _, NoModrm, { Acc, 0, 0} }, |
| 707 | {"fnstsw", 1, 0xdd, 7, Modrm, { Mem, 0, 0} }, |
| 708 | {"fnstsw", 0, 0xdfe0, _, NoModrm, { 0, 0, 0} }, |
| 709 | {"fstsw", 1, 0x9bdfe0, _, NoModrm, { Acc, 0, 0} }, |
| 710 | {"fstsw", 1, 0x9bdd, 7, Modrm, { Mem, 0, 0} }, |
| 711 | {"fstsw", 0, 0x9bdfe0, _, NoModrm, { 0, 0, 0} }, |
| 712 | {"fnclex", 0, 0xdbe2, _, NoModrm, { 0, 0, 0} }, |
| 713 | {"fclex", 0, 0x9bdbe2, _, NoModrm, { 0, 0, 0} }, |
| 714 | /* |
| 715 | We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor |
| 716 | instructions; i'm not sure how to add them or how they are different. |
| 717 | My 386/387 book offers no details about this. |
| 718 | */ |
| 719 | {"fnstenv", 1, 0xd9, 6, Modrm, { Mem, 0, 0} }, |
| 720 | {"fstenv", 1, 0x9bd9, 6, Modrm, { Mem, 0, 0} }, |
| 721 | {"fldenv", 1, 0xd9, 4, Modrm, { Mem, 0, 0} }, |
| 722 | {"fnsave", 1, 0xdd, 6, Modrm, { Mem, 0, 0} }, |
| 723 | {"fsave", 1, 0x9bdd, 6, Modrm, { Mem, 0, 0} }, |
| 724 | {"frstor", 1, 0xdd, 4, Modrm, { Mem, 0, 0} }, |
| 725 | |
| 726 | {"ffree", 1, 0xddc0, _, ShortForm, { FloatReg, 0, 0} }, |
| 727 | /* P6:free st(i), pop st */ |
| 728 | {"ffreep", 1, 0xdfc0, _, ShortForm, { FloatReg, 0, 0} }, |
| 729 | {"fnop", 0, 0xd9d0, _, NoModrm, { 0, 0, 0} }, |
| 730 | {"fwait", 0, 0x9b, _, NoModrm, { 0, 0, 0} }, |
| 731 | |
| 732 | /* |
| 733 | opcode prefixes; we allow them as seperate insns too |
| 734 | (see prefix table below) |
| 735 | */ |
| 736 | {"aword", 0, 0x67, _, NoModrm, { 0, 0, 0} }, |
| 737 | {"addr16", 0, 0x67, _, NoModrm, { 0, 0, 0} }, |
| 738 | {"word", 0, 0x66, _, NoModrm, { 0, 0, 0} }, |
| 739 | {"data16", 0, 0x66, _, NoModrm, { 0, 0, 0} }, |
| 740 | {"lock", 0, 0xf0, _, NoModrm, { 0, 0, 0} }, |
| 741 | {"cs", 0, 0x2e, _, NoModrm, { 0, 0, 0} }, |
| 742 | {"ds", 0, 0x3e, _, NoModrm, { 0, 0, 0} }, |
| 743 | {"es", 0, 0x26, _, NoModrm, { 0, 0, 0} }, |
| 744 | {"fs", 0, 0x64, _, NoModrm, { 0, 0, 0} }, |
| 745 | {"gs", 0, 0x65, _, NoModrm, { 0, 0, 0} }, |
| 746 | {"ss", 0, 0x36, _, NoModrm, { 0, 0, 0} }, |
| 747 | {"rep", 0, 0xf3, _, NoModrm, { 0, 0, 0} }, |
| 748 | {"repe", 0, 0xf3, _, NoModrm, { 0, 0, 0} }, |
| 749 | {"repz", 0, 0xf3, _, NoModrm, { 0, 0, 0} }, |
| 750 | {"repne", 0, 0xf2, _, NoModrm, { 0, 0, 0} }, |
| 751 | {"repnz", 0, 0xf2, _, NoModrm, { 0, 0, 0} }, |
| 752 | |
| 753 | /* 486 extensions */ |
| 754 | |
| 755 | {"bswap", 1, 0x0fc8, _, ShortForm, { Reg32,0,0 } }, |
| 756 | {"xadd", 2, 0x0fc0, _, W|Modrm, { Reg, Reg|Mem, 0 } }, |
| 757 | {"cmpxchg", 2, 0x0fb0, _, W|Modrm, { Reg, Reg|Mem, 0 } }, |
| 758 | {"invd", 0, 0x0f08, _, NoModrm, { 0, 0, 0} }, |
| 759 | {"wbinvd", 0, 0x0f09, _, NoModrm, { 0, 0, 0} }, |
| 760 | {"invlpg", 1, 0x0f01, 7, Modrm, { Mem, 0, 0} }, |
| 761 | |
| 762 | /* 586 and late 486 extensions */ |
| 763 | {"cpuid", 0, 0x0fa2, _, NoModrm, { 0, 0, 0} }, |
| 764 | |
| 765 | /* Pentium extensions */ |
| 766 | {"wrmsr", 0, 0x0f30, _, NoModrm, { 0, 0, 0} }, |
| 767 | {"rdtsc", 0, 0x0f31, _, NoModrm, { 0, 0, 0} }, |
| 768 | {"rdmsr", 0, 0x0f32, _, NoModrm, { 0, 0, 0} }, |
| 769 | {"cmpxchg8b", 1, 0x0fc7, 1, Modrm, { Mem, 0, 0} }, |
| 770 | |
| 771 | /* Pentium Pro extensions */ |
| 772 | {"rdpmc", 0, 0x0f33, _, NoModrm, { 0, 0, 0} }, |
| 773 | |
| 774 | {"ud2", 0, 0x0f0b, _, NoModrm, {0, 0, 0} }, /* official undefined instr. */ |
| 775 | |
| 776 | {"cmovo", 2, 0x0f40, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, |
| 777 | {"cmovno", 2, 0x0f41, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, |
| 778 | {"cmovb", 2, 0x0f42, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, |
| 779 | {"cmovae", 2, 0x0f43, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, |
| 780 | {"cmove", 2, 0x0f44, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, |
| 781 | {"cmovne", 2, 0x0f45, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, |
| 782 | {"cmovbe", 2, 0x0f46, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, |
| 783 | {"cmova", 2, 0x0f47, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, |
| 784 | {"cmovs", 2, 0x0f48, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, |
| 785 | {"cmovns", 2, 0x0f49, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, |
| 786 | {"cmovp", 2, 0x0f4a, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, |
| 787 | {"cmovnp", 2, 0x0f4b, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, |
| 788 | {"cmovl", 2, 0x0f4c, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, |
| 789 | {"cmovge", 2, 0x0f4d, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, |
| 790 | {"cmovle", 2, 0x0f4e, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, |
| 791 | {"cmovg", 2, 0x0f4f, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, |
| 792 | |
| 793 | {"fcmovb", 2, 0xdac0, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 794 | {"fcmove", 2, 0xdac8, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 795 | {"fcmovbe",2, 0xdad0, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 796 | {"fcmovu", 2, 0xdad8, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 797 | {"fcmovnb", 2, 0xdbc0, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 798 | {"fcmovne", 2, 0xdbc8, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 799 | {"fcmovnbe",2, 0xdbd0, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 800 | {"fcmovnu", 2, 0xdbd8, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 801 | |
| 802 | {"fcomi", 2, 0xdbf0, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 803 | {"fucomi", 2, 0xdbe8, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 804 | {"fcomip", 2, 0xdff0, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 805 | {"fucomip",2, 0xdfe8, _, ShortForm, { FloatReg, FloatAcc, 0} }, |
| 806 | |
| 807 | /* MMX instructions. */ |
| 808 | |
| 809 | {"emms", 0, 0x0f77, _, NoModrm, { 0, 0, 0 } }, |
| 810 | {"movd", 2, 0x0f6e, _, Modrm, { Reg32|WordMem, RegMMX, 0 } }, |
| 811 | {"movd", 2, 0x0f7e, _, Modrm, { RegMMX, Reg32|WordMem, 0 } }, |
| 812 | {"movq", 2, 0x0f6f, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 813 | {"movq", 2, 0x0f7f, _, Modrm, { RegMMX, RegMMX|WordMem, 0 } }, |
| 814 | {"packssdw", 2, 0x0f6b, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 815 | {"packsswb", 2, 0x0f63, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 816 | {"packuswb", 2, 0x0f67, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 817 | {"paddb", 2, 0x0ffc, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 818 | {"paddw", 2, 0x0ffd, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 819 | {"paddd", 2, 0x0ffe, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 820 | {"paddsb", 2, 0x0fec, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 821 | {"paddsw", 2, 0x0fed, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 822 | {"paddusb", 2, 0x0fdc, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 823 | {"paddusw", 2, 0x0fdd, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 824 | {"pand", 2, 0x0fdb, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 825 | {"pandn", 2, 0x0fdf, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 826 | {"pcmpeqb", 2, 0x0f74, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 827 | {"pcmpeqw", 2, 0x0f75, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 828 | {"pcmpeqd", 2, 0x0f76, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 829 | {"pcmpgtb", 2, 0x0f64, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 830 | {"pcmpgtw", 2, 0x0f65, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 831 | {"pcmpgtd", 2, 0x0f66, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 832 | {"pmaddwd", 2, 0x0ff5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 833 | {"pmulhw", 2, 0x0fe5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 834 | {"pmullw", 2, 0x0fd5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 835 | {"por", 2, 0x0feb, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 836 | {"psllw", 2, 0x0ff1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 837 | {"psllw", 2, 0x0f71, 6, Modrm, { Imm8, RegMMX, 0 } }, |
| 838 | {"pslld", 2, 0x0ff2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 839 | {"pslld", 2, 0x0f72, 6, Modrm, { Imm8, RegMMX, 0 } }, |
| 840 | {"psllq", 2, 0x0ff3, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 841 | {"psllq", 2, 0x0f73, 6, Modrm, { Imm8, RegMMX, 0 } }, |
| 842 | {"psraw", 2, 0x0fe1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 843 | {"psraw", 2, 0x0f71, 4, Modrm, { Imm8, RegMMX, 0 } }, |
| 844 | {"psrad", 2, 0x0fe2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 845 | {"psrad", 2, 0x0f72, 4, Modrm, { Imm8, RegMMX, 0 } }, |
| 846 | {"psrlw", 2, 0x0fd1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 847 | {"psrlw", 2, 0x0f71, 2, Modrm, { Imm8, RegMMX, 0 } }, |
| 848 | {"psrld", 2, 0x0fd2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 849 | {"psrld", 2, 0x0f72, 2, Modrm, { Imm8, RegMMX, 0 } }, |
| 850 | {"psrlq", 2, 0x0fd3, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 851 | {"psrlq", 2, 0x0f73, 2, Modrm, { Imm8, RegMMX, 0 } }, |
| 852 | {"psubb", 2, 0x0ff8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 853 | {"psubw", 2, 0x0ff9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 854 | {"psubd", 2, 0x0ffa, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 855 | {"psubsb", 2, 0x0fe8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 856 | {"psubsw", 2, 0x0fe9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 857 | {"psubusb", 2, 0x0fd8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 858 | {"psubusw", 2, 0x0fd9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 859 | {"punpckhbw", 2, 0x0f68, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 860 | {"punpckhwd", 2, 0x0f69, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 861 | {"punpckhdq", 2, 0x0f6a, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 862 | {"punpcklbw", 2, 0x0f60, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 863 | {"punpcklwd", 2, 0x0f61, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 864 | {"punpckldq", 2, 0x0f62, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 865 | {"pxor", 2, 0x0fef, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
| 866 | |
| 867 | {"", 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */ |
| 868 | }; |
| 869 | #undef _ |
| 870 | |
| 871 | static const template *const i386_optab_end |
| 872 | = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]); |
| 873 | |
| 874 | /* 386 register table */ |
| 875 | |
| 876 | static const reg_entry i386_regtab[] = { |
| 877 | /* 8 bit regs */ |
| 878 | {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2}, |
| 879 | {"bl", Reg8, 3}, |
| 880 | {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7}, |
| 881 | /* 16 bit regs */ |
| 882 | {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3}, |
| 883 | {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7}, |
| 884 | /* 32 bit regs */ |
| 885 | {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3}, |
| 886 | {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7}, |
| 887 | /* segment registers */ |
| 888 | {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2}, |
| 889 | {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5}, |
| 890 | /* control registers */ |
| 891 | {"cr0", Control, 0}, {"cr2", Control, 2}, {"cr3", Control, 3}, |
| 892 | {"cr4", Control, 4}, |
| 893 | /* debug registers */ |
| 894 | {"db0", Debug, 0}, {"db1", Debug, 1}, {"db2", Debug, 2}, |
| 895 | {"db3", Debug, 3}, {"db6", Debug, 6}, {"db7", Debug, 7}, |
| 896 | {"dr0", Debug, 0}, {"dr1", Debug, 1}, {"dr2", Debug, 2}, |
| 897 | {"dr3", Debug, 3}, {"dr6", Debug, 6}, {"dr7", Debug, 7}, |
| 898 | /* test registers */ |
| 899 | {"tr3", Test, 3}, {"tr4", Test, 4}, {"tr5", Test, 5}, |
| 900 | {"tr6", Test, 6}, {"tr7", Test, 7}, |
| 901 | /* float registers */ |
| 902 | {"st(0)", FloatReg|FloatAcc, 0}, |
| 903 | {"st", FloatReg|FloatAcc, 0}, |
| 904 | {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2}, |
| 905 | {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5}, |
| 906 | {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7}, |
| 907 | {"mm0", RegMMX, 0}, {"mm1", RegMMX, 1}, {"mm2", RegMMX, 2}, |
| 908 | {"mm3", RegMMX, 3}, {"mm4", RegMMX, 4}, {"mm5", RegMMX, 5}, |
| 909 | {"mm6", RegMMX, 6}, {"mm7", RegMMX, 7} |
| 910 | }; |
| 911 | |
| 912 | #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ |
| 913 | |
| 914 | static const reg_entry *const i386_regtab_end |
| 915 | = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]); |
| 916 | |
| 917 | /* segment stuff */ |
| 918 | static const seg_entry cs = { "cs", 0x2e }; |
| 919 | static const seg_entry ds = { "ds", 0x3e }; |
| 920 | static const seg_entry ss = { "ss", 0x36 }; |
| 921 | static const seg_entry es = { "es", 0x26 }; |
| 922 | static const seg_entry fs = { "fs", 0x64 }; |
| 923 | static const seg_entry gs = { "gs", 0x65 }; |
| 924 | static const seg_entry null = { "", 0x0 }; |
| 925 | |
| 926 | /* |
| 927 | This table is used to store the default segment register implied by all |
| 928 | possible memory addressing modes. |
| 929 | It is indexed by the mode & modrm entries of the modrm byte as follows: |
| 930 | index = (mode<<3) | modrm; |
| 931 | */ |
| 932 | static const seg_entry *const one_byte_segment_defaults[] = { |
| 933 | /* mode 0 */ |
| 934 | &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds, |
| 935 | /* mode 1 */ |
| 936 | &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds, |
| 937 | /* mode 2 */ |
| 938 | &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds, |
| 939 | /* mode 3 --- not a memory reference; never referenced */ |
| 940 | }; |
| 941 | |
| 942 | static const seg_entry *const two_byte_segment_defaults[] = { |
| 943 | /* mode 0 */ |
| 944 | &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, |
| 945 | /* mode 1 */ |
| 946 | &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, |
| 947 | /* mode 2 */ |
| 948 | &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, |
| 949 | /* mode 3 --- not a memory reference; never referenced */ |
| 950 | }; |
| 951 | |
| 952 | static const prefix_entry i386_prefixtab[] = { |
| 953 | #define ADDR_PREFIX_OPCODE 0x67 |
| 954 | { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing |
| 955 | * (How is this useful?) */ |
| 956 | #define WORD_PREFIX_OPCODE 0x66 |
| 957 | { "data16", 0x66 }, /* operand size prefix */ |
| 958 | { "lock", 0xf0 }, /* bus lock prefix */ |
| 959 | { "wait", 0x9b }, /* wait for coprocessor */ |
| 960 | { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */ |
| 961 | { "es", 0x26 }, { "fs", 0x64 }, |
| 962 | { "gs", 0x65 }, { "ss", 0x36 }, |
| 963 | /* REPE & REPNE used to detect rep/repne with a non-string instruction */ |
| 964 | #define REPNE 0xf2 |
| 965 | #define REPE 0xf3 |
| 966 | { "rep", 0xf3 }, /* repeat string instructions */ |
| 967 | { "repe", 0xf3 }, { "repz", 0xf3 }, |
| 968 | { "repne", 0xf2 }, { "repnz", 0xf2 } |
| 969 | }; |
| 970 | |
| 971 | static const prefix_entry *const i386_prefixtab_end |
| 972 | = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]); |
| 973 | |
| 974 | /* end of i386-opcode.h */ |