| 1 | /* mips.h. Mips opcode list for GDB, the GNU debugger. |
| 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
| 3 | 2003, 2004, 2005, 2008, 2009, 2010, 2013 |
| 4 | Free Software Foundation, Inc. |
| 5 | Contributed by Ralph Campbell and OSF |
| 6 | Commented and modified by Ian Lance Taylor, Cygnus Support |
| 7 | |
| 8 | This file is part of GDB, GAS, and the GNU binutils. |
| 9 | |
| 10 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
| 11 | them and/or modify them under the terms of the GNU General Public |
| 12 | License as published by the Free Software Foundation; either version 3, |
| 13 | or (at your option) any later version. |
| 14 | |
| 15 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
| 16 | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
| 17 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
| 18 | the GNU General Public License for more details. |
| 19 | |
| 20 | You should have received a copy of the GNU General Public License |
| 21 | along with this file; see the file COPYING3. If not, write to the Free |
| 22 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
| 23 | MA 02110-1301, USA. */ |
| 24 | |
| 25 | #ifndef _MIPS_H_ |
| 26 | #define _MIPS_H_ |
| 27 | |
| 28 | #include "bfd.h" |
| 29 | |
| 30 | /* These are bit masks and shift counts to use to access the various |
| 31 | fields of an instruction. To retrieve the X field of an |
| 32 | instruction, use the expression |
| 33 | (i >> OP_SH_X) & OP_MASK_X |
| 34 | To set the same field (to j), use |
| 35 | i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) |
| 36 | |
| 37 | Make sure you use fields that are appropriate for the instruction, |
| 38 | of course. |
| 39 | |
| 40 | The 'i' format uses OP, RS, RT and IMMEDIATE. |
| 41 | |
| 42 | The 'j' format uses OP and TARGET. |
| 43 | |
| 44 | The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. |
| 45 | |
| 46 | The 'b' format uses OP, RS, RT and DELTA. |
| 47 | |
| 48 | The floating point 'i' format uses OP, RS, RT and IMMEDIATE. |
| 49 | |
| 50 | The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. |
| 51 | |
| 52 | A breakpoint instruction uses OP, CODE and SPEC (10 bits of the |
| 53 | breakpoint instruction are not defined; Kane says the breakpoint |
| 54 | code field in BREAK is 20 bits; yet MIPS assemblers and debuggers |
| 55 | only use ten bits). An optional two-operand form of break/sdbbp |
| 56 | allows the lower ten bits to be set too, and MIPS32 and later |
| 57 | architectures allow 20 bits to be set with a signal operand |
| 58 | (using CODE20). |
| 59 | |
| 60 | The syscall instruction uses CODE20. |
| 61 | |
| 62 | The general coprocessor instructions use COPZ. */ |
| 63 | |
| 64 | #define OP_MASK_OP 0x3f |
| 65 | #define OP_SH_OP 26 |
| 66 | #define OP_MASK_RS 0x1f |
| 67 | #define OP_SH_RS 21 |
| 68 | #define OP_MASK_FR 0x1f |
| 69 | #define OP_SH_FR 21 |
| 70 | #define OP_MASK_FMT 0x1f |
| 71 | #define OP_SH_FMT 21 |
| 72 | #define OP_MASK_BCC 0x7 |
| 73 | #define OP_SH_BCC 18 |
| 74 | #define OP_MASK_CODE 0x3ff |
| 75 | #define OP_SH_CODE 16 |
| 76 | #define OP_MASK_CODE2 0x3ff |
| 77 | #define OP_SH_CODE2 6 |
| 78 | #define OP_MASK_RT 0x1f |
| 79 | #define OP_SH_RT 16 |
| 80 | #define OP_MASK_FT 0x1f |
| 81 | #define OP_SH_FT 16 |
| 82 | #define OP_MASK_CACHE 0x1f |
| 83 | #define OP_SH_CACHE 16 |
| 84 | #define OP_MASK_RD 0x1f |
| 85 | #define OP_SH_RD 11 |
| 86 | #define OP_MASK_FS 0x1f |
| 87 | #define OP_SH_FS 11 |
| 88 | #define OP_MASK_PREFX 0x1f |
| 89 | #define OP_SH_PREFX 11 |
| 90 | #define OP_MASK_CCC 0x7 |
| 91 | #define OP_SH_CCC 8 |
| 92 | #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ |
| 93 | #define OP_SH_CODE20 6 |
| 94 | #define OP_MASK_SHAMT 0x1f |
| 95 | #define OP_SH_SHAMT 6 |
| 96 | #define OP_MASK_EXTLSB OP_MASK_SHAMT |
| 97 | #define OP_SH_EXTLSB OP_SH_SHAMT |
| 98 | #define OP_MASK_STYPE OP_MASK_SHAMT |
| 99 | #define OP_SH_STYPE OP_SH_SHAMT |
| 100 | #define OP_MASK_FD 0x1f |
| 101 | #define OP_SH_FD 6 |
| 102 | #define OP_MASK_TARGET 0x3ffffff |
| 103 | #define OP_SH_TARGET 0 |
| 104 | #define OP_MASK_COPZ 0x1ffffff |
| 105 | #define OP_SH_COPZ 0 |
| 106 | #define OP_MASK_IMMEDIATE 0xffff |
| 107 | #define OP_SH_IMMEDIATE 0 |
| 108 | #define OP_MASK_DELTA 0xffff |
| 109 | #define OP_SH_DELTA 0 |
| 110 | #define OP_MASK_FUNCT 0x3f |
| 111 | #define OP_SH_FUNCT 0 |
| 112 | #define OP_MASK_SPEC 0x3f |
| 113 | #define OP_SH_SPEC 0 |
| 114 | #define OP_SH_LOCC 8 /* FP condition code. */ |
| 115 | #define OP_SH_HICC 18 /* FP condition code. */ |
| 116 | #define OP_MASK_CC 0x7 |
| 117 | #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ |
| 118 | #define OP_MASK_COP1NORM 0x1 /* a single bit. */ |
| 119 | #define OP_SH_COP1SPEC 21 /* COP1 encodings. */ |
| 120 | #define OP_MASK_COP1SPEC 0xf |
| 121 | #define OP_MASK_COP1SCLR 0x4 |
| 122 | #define OP_MASK_COP1CMP 0x3 |
| 123 | #define OP_SH_COP1CMP 4 |
| 124 | #define OP_SH_FORMAT 21 /* FP short format field. */ |
| 125 | #define OP_MASK_FORMAT 0x7 |
| 126 | #define OP_SH_TRUE 16 |
| 127 | #define OP_MASK_TRUE 0x1 |
| 128 | #define OP_SH_GE 17 |
| 129 | #define OP_MASK_GE 0x01 |
| 130 | #define OP_SH_UNSIGNED 16 |
| 131 | #define OP_MASK_UNSIGNED 0x1 |
| 132 | #define OP_SH_HINT 16 |
| 133 | #define OP_MASK_HINT 0x1f |
| 134 | #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ |
| 135 | #define OP_MASK_MMI 0x3f |
| 136 | #define OP_SH_MMISUB 6 |
| 137 | #define OP_MASK_MMISUB 0x1f |
| 138 | #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ |
| 139 | #define OP_SH_PERFREG 1 |
| 140 | #define OP_SH_SEL 0 /* Coprocessor select field. */ |
| 141 | #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ |
| 142 | #define OP_SH_CODE19 6 /* 19 bit wait code. */ |
| 143 | #define OP_MASK_CODE19 0x7ffff |
| 144 | #define OP_SH_ALN 21 |
| 145 | #define OP_MASK_ALN 0x7 |
| 146 | #define OP_SH_VSEL 21 |
| 147 | #define OP_MASK_VSEL 0x1f |
| 148 | #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, |
| 149 | but 0x8-0xf don't select bytes. */ |
| 150 | #define OP_SH_VECBYTE 22 |
| 151 | #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ |
| 152 | #define OP_SH_VECALIGN 21 |
| 153 | #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ |
| 154 | #define OP_SH_INSMSB 11 |
| 155 | #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ |
| 156 | #define OP_SH_EXTMSBD 11 |
| 157 | |
| 158 | /* MIPS DSP ASE */ |
| 159 | #define OP_SH_DSPACC 11 |
| 160 | #define OP_MASK_DSPACC 0x3 |
| 161 | #define OP_SH_DSPACC_S 21 |
| 162 | #define OP_MASK_DSPACC_S 0x3 |
| 163 | #define OP_SH_DSPSFT 20 |
| 164 | #define OP_MASK_DSPSFT 0x3f |
| 165 | #define OP_SH_DSPSFT_7 19 |
| 166 | #define OP_MASK_DSPSFT_7 0x7f |
| 167 | #define OP_SH_SA3 21 |
| 168 | #define OP_MASK_SA3 0x7 |
| 169 | #define OP_SH_SA4 21 |
| 170 | #define OP_MASK_SA4 0xf |
| 171 | #define OP_SH_IMM8 16 |
| 172 | #define OP_MASK_IMM8 0xff |
| 173 | #define OP_SH_IMM10 16 |
| 174 | #define OP_MASK_IMM10 0x3ff |
| 175 | #define OP_SH_WRDSP 11 |
| 176 | #define OP_MASK_WRDSP 0x3f |
| 177 | #define OP_SH_RDDSP 16 |
| 178 | #define OP_MASK_RDDSP 0x3f |
| 179 | #define OP_SH_BP 11 |
| 180 | #define OP_MASK_BP 0x3 |
| 181 | |
| 182 | /* MIPS MT ASE */ |
| 183 | #define OP_SH_MT_U 5 |
| 184 | #define OP_MASK_MT_U 0x1 |
| 185 | #define OP_SH_MT_H 4 |
| 186 | #define OP_MASK_MT_H 0x1 |
| 187 | #define OP_SH_MTACC_T 18 |
| 188 | #define OP_MASK_MTACC_T 0x3 |
| 189 | #define OP_SH_MTACC_D 13 |
| 190 | #define OP_MASK_MTACC_D 0x3 |
| 191 | |
| 192 | /* MIPS MCU ASE */ |
| 193 | #define OP_MASK_3BITPOS 0x7 |
| 194 | #define OP_SH_3BITPOS 12 |
| 195 | #define OP_MASK_OFFSET12 0xfff |
| 196 | #define OP_SH_OFFSET12 0 |
| 197 | |
| 198 | #define OP_OP_COP0 0x10 |
| 199 | #define OP_OP_COP1 0x11 |
| 200 | #define OP_OP_COP2 0x12 |
| 201 | #define OP_OP_COP3 0x13 |
| 202 | #define OP_OP_LWC1 0x31 |
| 203 | #define OP_OP_LWC2 0x32 |
| 204 | #define OP_OP_LWC3 0x33 /* a.k.a. pref */ |
| 205 | #define OP_OP_LDC1 0x35 |
| 206 | #define OP_OP_LDC2 0x36 |
| 207 | #define OP_OP_LDC3 0x37 /* a.k.a. ld */ |
| 208 | #define OP_OP_SWC1 0x39 |
| 209 | #define OP_OP_SWC2 0x3a |
| 210 | #define OP_OP_SWC3 0x3b |
| 211 | #define OP_OP_SDC1 0x3d |
| 212 | #define OP_OP_SDC2 0x3e |
| 213 | #define OP_OP_SDC3 0x3f /* a.k.a. sd */ |
| 214 | |
| 215 | /* MIPS VIRT ASE */ |
| 216 | #define OP_MASK_CODE10 0x3ff |
| 217 | #define OP_SH_CODE10 11 |
| 218 | |
| 219 | /* Values in the 'VSEL' field. */ |
| 220 | #define MDMX_FMTSEL_IMM_QH 0x1d |
| 221 | #define MDMX_FMTSEL_IMM_OB 0x1e |
| 222 | #define MDMX_FMTSEL_VEC_QH 0x15 |
| 223 | #define MDMX_FMTSEL_VEC_OB 0x16 |
| 224 | |
| 225 | /* UDI */ |
| 226 | #define OP_SH_UDI1 6 |
| 227 | #define OP_MASK_UDI1 0x1f |
| 228 | #define OP_SH_UDI2 6 |
| 229 | #define OP_MASK_UDI2 0x3ff |
| 230 | #define OP_SH_UDI3 6 |
| 231 | #define OP_MASK_UDI3 0x7fff |
| 232 | #define OP_SH_UDI4 6 |
| 233 | #define OP_MASK_UDI4 0xfffff |
| 234 | |
| 235 | /* Octeon */ |
| 236 | #define OP_SH_BBITIND 16 |
| 237 | #define OP_MASK_BBITIND 0x1f |
| 238 | #define OP_SH_CINSPOS 6 |
| 239 | #define OP_MASK_CINSPOS 0x1f |
| 240 | #define OP_SH_CINSLM1 11 |
| 241 | #define OP_MASK_CINSLM1 0x1f |
| 242 | #define OP_SH_SEQI 6 |
| 243 | #define OP_MASK_SEQI 0x3ff |
| 244 | |
| 245 | /* Loongson */ |
| 246 | #define OP_SH_OFFSET_A 6 |
| 247 | #define OP_MASK_OFFSET_A 0xff |
| 248 | #define OP_SH_OFFSET_B 3 |
| 249 | #define OP_MASK_OFFSET_B 0xff |
| 250 | #define OP_SH_OFFSET_C 6 |
| 251 | #define OP_MASK_OFFSET_C 0x1ff |
| 252 | #define OP_SH_RZ 0 |
| 253 | #define OP_MASK_RZ 0x1f |
| 254 | #define OP_SH_FZ 0 |
| 255 | #define OP_MASK_FZ 0x1f |
| 256 | |
| 257 | /* Every MICROMIPSOP_X definition requires a corresponding OP_X |
| 258 | definition, and vice versa. This simplifies various parts |
| 259 | of the operand handling in GAS. The fields below only exist |
| 260 | in the microMIPS encoding, so define each one to have an empty |
| 261 | range. */ |
| 262 | #define OP_MASK_TRAP 0 |
| 263 | #define OP_SH_TRAP 0 |
| 264 | #define OP_MASK_OFFSET10 0 |
| 265 | #define OP_SH_OFFSET10 0 |
| 266 | #define OP_MASK_RS3 0 |
| 267 | #define OP_SH_RS3 0 |
| 268 | #define OP_MASK_MB 0 |
| 269 | #define OP_SH_MB 0 |
| 270 | #define OP_MASK_MC 0 |
| 271 | #define OP_SH_MC 0 |
| 272 | #define OP_MASK_MD 0 |
| 273 | #define OP_SH_MD 0 |
| 274 | #define OP_MASK_ME 0 |
| 275 | #define OP_SH_ME 0 |
| 276 | #define OP_MASK_MF 0 |
| 277 | #define OP_SH_MF 0 |
| 278 | #define OP_MASK_MG 0 |
| 279 | #define OP_SH_MG 0 |
| 280 | #define OP_MASK_MH 0 |
| 281 | #define OP_SH_MH 0 |
| 282 | #define OP_MASK_MJ 0 |
| 283 | #define OP_SH_MJ 0 |
| 284 | #define OP_MASK_ML 0 |
| 285 | #define OP_SH_ML 0 |
| 286 | #define OP_MASK_MM 0 |
| 287 | #define OP_SH_MM 0 |
| 288 | #define OP_MASK_MN 0 |
| 289 | #define OP_SH_MN 0 |
| 290 | #define OP_MASK_MP 0 |
| 291 | #define OP_SH_MP 0 |
| 292 | #define OP_MASK_MQ 0 |
| 293 | #define OP_SH_MQ 0 |
| 294 | #define OP_MASK_IMMA 0 |
| 295 | #define OP_SH_IMMA 0 |
| 296 | #define OP_MASK_IMMB 0 |
| 297 | #define OP_SH_IMMB 0 |
| 298 | #define OP_MASK_IMMC 0 |
| 299 | #define OP_SH_IMMC 0 |
| 300 | #define OP_MASK_IMMF 0 |
| 301 | #define OP_SH_IMMF 0 |
| 302 | #define OP_MASK_IMMG 0 |
| 303 | #define OP_SH_IMMG 0 |
| 304 | #define OP_MASK_IMMH 0 |
| 305 | #define OP_SH_IMMH 0 |
| 306 | #define OP_MASK_IMMI 0 |
| 307 | #define OP_SH_IMMI 0 |
| 308 | #define OP_MASK_IMMJ 0 |
| 309 | #define OP_SH_IMMJ 0 |
| 310 | #define OP_MASK_IMML 0 |
| 311 | #define OP_SH_IMML 0 |
| 312 | #define OP_MASK_IMMM 0 |
| 313 | #define OP_SH_IMMM 0 |
| 314 | #define OP_MASK_IMMN 0 |
| 315 | #define OP_SH_IMMN 0 |
| 316 | #define OP_MASK_IMMO 0 |
| 317 | #define OP_SH_IMMO 0 |
| 318 | #define OP_MASK_IMMP 0 |
| 319 | #define OP_SH_IMMP 0 |
| 320 | #define OP_MASK_IMMQ 0 |
| 321 | #define OP_SH_IMMQ 0 |
| 322 | #define OP_MASK_IMMU 0 |
| 323 | #define OP_SH_IMMU 0 |
| 324 | #define OP_MASK_IMMW 0 |
| 325 | #define OP_SH_IMMW 0 |
| 326 | #define OP_MASK_IMMX 0 |
| 327 | #define OP_SH_IMMX 0 |
| 328 | #define OP_MASK_IMMY 0 |
| 329 | #define OP_SH_IMMY 0 |
| 330 | |
| 331 | /* Enhanced VA Scheme */ |
| 332 | #define OP_SH_EVAOFFSET 7 |
| 333 | #define OP_MASK_EVAOFFSET 0x1ff |
| 334 | |
| 335 | /* Enumerates the various types of MIPS operand. */ |
| 336 | enum mips_operand_type { |
| 337 | /* Described by mips_int_operand. */ |
| 338 | OP_INT, |
| 339 | |
| 340 | /* Described by mips_mapped_int_operand. */ |
| 341 | OP_MAPPED_INT, |
| 342 | |
| 343 | /* Described by mips_msb_operand. */ |
| 344 | OP_MSB, |
| 345 | |
| 346 | /* Described by mips_reg_operand. */ |
| 347 | OP_REG, |
| 348 | |
| 349 | /* Described by mips_reg_pair_operand. */ |
| 350 | OP_REG_PAIR, |
| 351 | |
| 352 | /* Described by mips_pcrel_operand. */ |
| 353 | OP_PCREL, |
| 354 | |
| 355 | /* A performance register. The field is 5 bits in size, but the supported |
| 356 | values are much more restricted. */ |
| 357 | OP_PERF_REG, |
| 358 | |
| 359 | /* The final operand in a microMIPS ADDIUSP instruction. It mostly acts |
| 360 | as a normal 9-bit signed offset that is multiplied by four, but there |
| 361 | are four special cases: |
| 362 | |
| 363 | -2 * 4 => -258 * 4 |
| 364 | -1 * 4 => -257 * 4 |
| 365 | 0 * 4 => 256 * 4 |
| 366 | 1 * 4 => 257 * 4. */ |
| 367 | OP_ADDIUSP_INT, |
| 368 | |
| 369 | /* The target of a (D)CLO or (D)CLZ instruction. The operand spans two |
| 370 | 5-bit register fields, both of which must be set to the destination |
| 371 | register. */ |
| 372 | OP_CLO_CLZ_DEST, |
| 373 | |
| 374 | /* A register list for a microMIPS LWM or SWM instruction. The operand |
| 375 | size determines whether the 16-bit or 32-bit encoding is required. */ |
| 376 | OP_LWM_SWM_LIST, |
| 377 | |
| 378 | /* The register list for an emulated MIPS16 ENTRY or EXIT instruction. */ |
| 379 | OP_ENTRY_EXIT_LIST, |
| 380 | |
| 381 | /* The register list and frame size for a MIPS16 SAVE or RESTORE |
| 382 | instruction. */ |
| 383 | OP_SAVE_RESTORE_LIST, |
| 384 | |
| 385 | /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions: |
| 386 | |
| 387 | V Meaning |
| 388 | ----- ------- |
| 389 | 0EEE0 8 copies of $vN[E], OB format |
| 390 | 0EE01 4 copies of $vN[E], QH format |
| 391 | 10110 all 8 elements of $vN, OB format |
| 392 | 10101 all 4 elements of $vN, QH format |
| 393 | 11110 8 copies of immediate N, OB format |
| 394 | 11101 4 copies of immediate N, QH format. */ |
| 395 | OP_MDMX_IMM_REG, |
| 396 | |
| 397 | /* A register operand that must match the destination register. */ |
| 398 | OP_REPEAT_DEST_REG, |
| 399 | |
| 400 | /* A register operand that must match the previous register. */ |
| 401 | OP_REPEAT_PREV_REG, |
| 402 | |
| 403 | /* $pc, which has no encoding in the architectural instruction. */ |
| 404 | OP_PC |
| 405 | }; |
| 406 | |
| 407 | /* Enumerates the types of MIPS register. */ |
| 408 | enum mips_reg_operand_type { |
| 409 | /* General registers $0-$31. Software names like $at can also be used. */ |
| 410 | OP_REG_GP, |
| 411 | |
| 412 | /* Floating-point registers $f0-$f31. */ |
| 413 | OP_REG_FP, |
| 414 | |
| 415 | /* Coprocessor condition code registers $cc0-$cc7. FPU condition codes |
| 416 | can also be written $fcc0-$fcc7. */ |
| 417 | OP_REG_CCC, |
| 418 | |
| 419 | /* FPRs used in a vector capacity. They can be written $f0-$f31 |
| 420 | or $v0-$v31, although the latter form is not used for the VR5400 |
| 421 | vector instructions. */ |
| 422 | OP_REG_VEC, |
| 423 | |
| 424 | /* DSP accumulator registers $ac0-$ac3. */ |
| 425 | OP_REG_ACC, |
| 426 | |
| 427 | /* Coprocessor registers $0-$31. Mnemonic names like c0_cause can |
| 428 | also be used in some contexts. */ |
| 429 | OP_REG_COPRO, |
| 430 | |
| 431 | /* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can |
| 432 | also be used in some contexts. */ |
| 433 | OP_REG_HW |
| 434 | }; |
| 435 | |
| 436 | /* Base class for all operands. */ |
| 437 | struct mips_operand |
| 438 | { |
| 439 | /* The type of the operand. */ |
| 440 | enum mips_operand_type type; |
| 441 | |
| 442 | /* The operand occupies SIZE bits of the instruction, starting at LSB. */ |
| 443 | unsigned short size; |
| 444 | unsigned short lsb; |
| 445 | }; |
| 446 | |
| 447 | /* Describes an integer operand with a regular encoding pattern. */ |
| 448 | struct mips_int_operand |
| 449 | { |
| 450 | struct mips_operand root; |
| 451 | |
| 452 | /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT. |
| 453 | The cyclically previous field value encodes 1 << SHIFT less than that, |
| 454 | and so on. E.g. |
| 455 | |
| 456 | - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves, |
| 457 | but 15 encodes -1. |
| 458 | |
| 459 | - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is |
| 460 | shifted left two places. |
| 461 | |
| 462 | - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except |
| 463 | that 0 encodes 8. |
| 464 | |
| 465 | - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3. */ |
| 466 | unsigned int max_val; |
| 467 | int bias; |
| 468 | unsigned int shift; |
| 469 | |
| 470 | /* True if the operand should be printed as hex rather than decimal. */ |
| 471 | bfd_boolean print_hex; |
| 472 | }; |
| 473 | |
| 474 | /* Uses a lookup table to describe a small integer operand. */ |
| 475 | struct mips_mapped_int_operand |
| 476 | { |
| 477 | struct mips_operand root; |
| 478 | |
| 479 | /* Maps each encoding value to the integer that it represents. */ |
| 480 | const int *int_map; |
| 481 | |
| 482 | /* True if the operand should be printed as hex rather than decimal. */ |
| 483 | bfd_boolean print_hex; |
| 484 | }; |
| 485 | |
| 486 | /* An operand that encodes the most significant bit position of a bitfield. |
| 487 | Given a bitfield that spans bits [MSB, LSB], some operands of this type |
| 488 | encode MSB directly while others encode MSB - LSB. Each operand of this |
| 489 | type is preceded by an integer operand that specifies LSB. |
| 490 | |
| 491 | The assembly form varies between instructions. For some instructions, |
| 492 | such as EXT, the operand is written as the bitfield size. For others, |
| 493 | such as EXTS, it is written in raw MSB - LSB form. */ |
| 494 | struct mips_msb_operand |
| 495 | { |
| 496 | struct mips_operand root; |
| 497 | |
| 498 | /* The assembly-level operand encoded by a field value of 0. */ |
| 499 | int bias; |
| 500 | |
| 501 | /* True if the operand encodes MSB directly, false if it encodes |
| 502 | MSB - LSB. */ |
| 503 | bfd_boolean add_lsb; |
| 504 | |
| 505 | /* The maximum value of MSB + 1. */ |
| 506 | unsigned int opsize; |
| 507 | }; |
| 508 | |
| 509 | /* Describes a single register operand. */ |
| 510 | struct mips_reg_operand |
| 511 | { |
| 512 | struct mips_operand root; |
| 513 | |
| 514 | /* The type of register. */ |
| 515 | enum mips_reg_operand_type reg_type; |
| 516 | |
| 517 | /* If nonnull, REG_MAP[N] gives the register associated with encoding N, |
| 518 | otherwise the encoding is the same as the register number. */ |
| 519 | const unsigned char *reg_map; |
| 520 | }; |
| 521 | |
| 522 | /* Describes an operand that encodes a pair of registers. */ |
| 523 | struct mips_reg_pair_operand |
| 524 | { |
| 525 | struct mips_operand root; |
| 526 | |
| 527 | /* The type of register. */ |
| 528 | enum mips_reg_operand_type reg_type; |
| 529 | |
| 530 | /* Encoding N represents REG1_MAP[N], REG2_MAP[N]. */ |
| 531 | unsigned char *reg1_map; |
| 532 | unsigned char *reg2_map; |
| 533 | }; |
| 534 | |
| 535 | /* Describes an operand that is calculated relative to a base PC. |
| 536 | The base PC is usually the address of the following instruction, |
| 537 | but the rules for MIPS16 instructions like ADDIUPC are more complicated. */ |
| 538 | struct mips_pcrel_operand |
| 539 | { |
| 540 | struct mips_operand root; |
| 541 | |
| 542 | /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC'. */ |
| 543 | unsigned int align_log2 : 8; |
| 544 | |
| 545 | /* The operand is shifted left SHIFT places and added to PC'. |
| 546 | The operand is signed if IS_SIGNED. */ |
| 547 | unsigned int shift : 8; |
| 548 | unsigned int is_signed : 1; |
| 549 | |
| 550 | /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then |
| 551 | reinstated. This is true for jumps and branches and false for |
| 552 | PC-relative data instructions. */ |
| 553 | unsigned int include_isa_bit : 1; |
| 554 | |
| 555 | /* If FLIP_ISA_BIT, the ISA bit of the result is inverted. |
| 556 | This is true for JALX and false otherwise. */ |
| 557 | unsigned int flip_isa_bit : 1; |
| 558 | }; |
| 559 | |
| 560 | /* Return a version of INSN in which the field specified by OPERAND |
| 561 | has value UVAL. */ |
| 562 | |
| 563 | static inline unsigned int |
| 564 | mips_insert_operand (const struct mips_operand *operand, unsigned int insn, |
| 565 | unsigned int uval) |
| 566 | { |
| 567 | unsigned int mask; |
| 568 | |
| 569 | mask = (1 << operand->size) - 1; |
| 570 | insn &= ~(mask << operand->lsb); |
| 571 | insn |= (uval & mask) << operand->lsb; |
| 572 | return insn; |
| 573 | } |
| 574 | |
| 575 | /* Extract OPERAND from instruction INSN. */ |
| 576 | |
| 577 | static inline unsigned int |
| 578 | mips_extract_operand (const struct mips_operand *operand, unsigned int insn) |
| 579 | { |
| 580 | return (insn >> operand->lsb) & ((1 << operand->size) - 1); |
| 581 | } |
| 582 | |
| 583 | /* UVAL is the value encoded by OPERAND. Return it in signed form. */ |
| 584 | |
| 585 | static inline int |
| 586 | mips_signed_operand (const struct mips_operand *operand, unsigned int uval) |
| 587 | { |
| 588 | unsigned int sign_bit, mask; |
| 589 | |
| 590 | mask = (1 << operand->size) - 1; |
| 591 | sign_bit = 1 << (operand->size - 1); |
| 592 | return ((uval + sign_bit) & mask) - sign_bit; |
| 593 | } |
| 594 | |
| 595 | /* Return the integer that OPERAND encodes as UVAL. */ |
| 596 | |
| 597 | static inline int |
| 598 | mips_decode_int_operand (const struct mips_int_operand *operand, |
| 599 | unsigned int uval) |
| 600 | { |
| 601 | uval |= (operand->max_val - uval) & -(1 << operand->root.size); |
| 602 | uval += operand->bias; |
| 603 | uval <<= operand->shift; |
| 604 | return uval; |
| 605 | } |
| 606 | |
| 607 | /* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC. |
| 608 | Return the address that it encodes. */ |
| 609 | |
| 610 | static inline bfd_vma |
| 611 | mips_decode_pcrel_operand (const struct mips_pcrel_operand *operand, |
| 612 | bfd_vma base_pc, unsigned int uval) |
| 613 | { |
| 614 | bfd_vma addr; |
| 615 | |
| 616 | addr = base_pc & -(1 << operand->align_log2); |
| 617 | if (operand->is_signed) |
| 618 | addr += mips_signed_operand (&operand->root, uval) * (1 << operand->shift); |
| 619 | else |
| 620 | addr += uval << operand->shift; |
| 621 | if (operand->include_isa_bit) |
| 622 | addr |= base_pc & 1; |
| 623 | if (operand->flip_isa_bit) |
| 624 | addr ^= 1; |
| 625 | return addr; |
| 626 | } |
| 627 | |
| 628 | /* This structure holds information for a particular instruction. */ |
| 629 | |
| 630 | struct mips_opcode |
| 631 | { |
| 632 | /* The name of the instruction. */ |
| 633 | const char *name; |
| 634 | /* A string describing the arguments for this instruction. */ |
| 635 | const char *args; |
| 636 | /* The basic opcode for the instruction. When assembling, this |
| 637 | opcode is modified by the arguments to produce the actual opcode |
| 638 | that is used. If pinfo is INSN_MACRO, then this is 0. */ |
| 639 | unsigned long match; |
| 640 | /* If pinfo is not INSN_MACRO, then this is a bit mask for the |
| 641 | relevant portions of the opcode when disassembling. If the |
| 642 | actual opcode anded with the match field equals the opcode field, |
| 643 | then we have found the correct instruction. If pinfo is |
| 644 | INSN_MACRO, then this field is the macro identifier. */ |
| 645 | unsigned long mask; |
| 646 | /* For a macro, this is INSN_MACRO. Otherwise, it is a collection |
| 647 | of bits describing the instruction, notably any relevant hazard |
| 648 | information. */ |
| 649 | unsigned long pinfo; |
| 650 | /* A collection of additional bits describing the instruction. */ |
| 651 | unsigned long pinfo2; |
| 652 | /* A collection of bits describing the instruction sets of which this |
| 653 | instruction or macro is a member. */ |
| 654 | unsigned long membership; |
| 655 | /* A collection of bits describing the ASE of which this instruction |
| 656 | or macro is a member. */ |
| 657 | unsigned long ase; |
| 658 | /* A collection of bits describing the instruction sets of which this |
| 659 | instruction or macro is not a member. */ |
| 660 | unsigned long exclusions; |
| 661 | }; |
| 662 | |
| 663 | /* These are the characters which may appear in the args field of an |
| 664 | instruction. They appear in the order in which the fields appear |
| 665 | when the instruction is used. Commas and parentheses in the args |
| 666 | string are ignored when assembling, and written into the output |
| 667 | when disassembling. |
| 668 | |
| 669 | Each of these characters corresponds to a mask field defined above. |
| 670 | |
| 671 | "1" 5 bit sync type (OP_*_STYPE) |
| 672 | "<" 5 bit shift amount (OP_*_SHAMT) |
| 673 | ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) |
| 674 | "a" 26 bit target address (OP_*_TARGET) |
| 675 | "+i" likewise, but flips bit 0 |
| 676 | "b" 5 bit base register (OP_*_RS) |
| 677 | "c" 10 bit breakpoint code (OP_*_CODE) |
| 678 | "d" 5 bit destination register specifier (OP_*_RD) |
| 679 | "h" 5 bit prefx hint (OP_*_PREFX) |
| 680 | "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) |
| 681 | "j" 16 bit signed immediate (OP_*_DELTA) |
| 682 | "k" 5 bit cache opcode in target register position (OP_*_CACHE) |
| 683 | "o" 16 bit signed offset (OP_*_DELTA) |
| 684 | "p" 16 bit PC relative branch target address (OP_*_DELTA) |
| 685 | "q" 10 bit extra breakpoint code (OP_*_CODE2) |
| 686 | "r" 5 bit same register used as both source and target (OP_*_RS) |
| 687 | "s" 5 bit source register specifier (OP_*_RS) |
| 688 | "t" 5 bit target register (OP_*_RT) |
| 689 | "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) |
| 690 | "v" 5 bit same register used as both source and destination (OP_*_RS) |
| 691 | "w" 5 bit same register used as both target and destination (OP_*_RT) |
| 692 | "U" 5 bit same destination register in both OP_*_RD and OP_*_RT |
| 693 | (used by clo and clz) |
| 694 | "C" 25 bit coprocessor function code (OP_*_COPZ) |
| 695 | "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) |
| 696 | "J" 19 bit wait function code (OP_*_CODE19) |
| 697 | "x" accept and ignore register name |
| 698 | "z" must be zero register |
| 699 | "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) |
| 700 | "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes |
| 701 | LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for |
| 702 | microMIPS compatibility). |
| 703 | Enforces: 0 <= pos < 32. |
| 704 | "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). |
| 705 | Requires that "+A" or "+E" occur first to set position. |
| 706 | Enforces: 0 < (pos+size) <= 32. |
| 707 | "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). |
| 708 | Requires that "+A" or "+E" occur first to set position. |
| 709 | Enforces: 0 < (pos+size) <= 32. |
| 710 | (Also used by "dext" w/ different limits, but limits for |
| 711 | that are checked by the M_DEXT macro.) |
| 712 | "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). |
| 713 | Enforces: 32 <= pos < 64. |
| 714 | "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). |
| 715 | Requires that "+A" or "+E" occur first to set position. |
| 716 | Enforces: 32 < (pos+size) <= 64. |
| 717 | "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). |
| 718 | Requires that "+A" or "+E" occur first to set position. |
| 719 | Enforces: 32 < (pos+size) <= 64. |
| 720 | "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). |
| 721 | Requires that "+A" or "+E" occur first to set position. |
| 722 | Enforces: 32 < (pos+size) <= 64. |
| 723 | |
| 724 | Floating point instructions: |
| 725 | "D" 5 bit destination register (OP_*_FD) |
| 726 | "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) |
| 727 | "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) |
| 728 | "S" 5 bit fs source 1 register (OP_*_FS) |
| 729 | "T" 5 bit ft source 2 register (OP_*_FT) |
| 730 | "R" 5 bit fr source 3 register (OP_*_FR) |
| 731 | "V" 5 bit same register used as floating source and destination (OP_*_FS) |
| 732 | "W" 5 bit same register used as floating target and destination (OP_*_FT) |
| 733 | |
| 734 | Coprocessor instructions: |
| 735 | "E" 5 bit target register (OP_*_RT) |
| 736 | "G" 5 bit destination register (OP_*_RD) |
| 737 | "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) |
| 738 | "P" 5 bit performance-monitor register (OP_*_PERFREG) |
| 739 | "e" 5 bit vector register byte specifier (OP_*_VECBYTE) |
| 740 | "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) |
| 741 | |
| 742 | Macro instructions: |
| 743 | "A" General 32 bit expression |
| 744 | "I" 32 bit immediate (value placed in imm_expr). |
| 745 | "+I" 32 bit immediate (value placed in imm2_expr). |
| 746 | "F" 64 bit floating point constant in .rdata |
| 747 | "L" 64 bit floating point constant in .lit8 |
| 748 | "f" 32 bit floating point constant |
| 749 | "l" 32 bit floating point constant in .lit4 |
| 750 | |
| 751 | MDMX and VR5400 instruction operands (note that while these use the |
| 752 | FP register fields, the MDMX instructions accept both $fN and $vN names |
| 753 | for the registers): |
| 754 | "O" alignment offset (OP_*_ALN) |
| 755 | "Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) |
| 756 | "X" destination register (OP_*_FD) |
| 757 | "Y" source register (OP_*_FS) |
| 758 | "Z" source register (OP_*_FT) |
| 759 | |
| 760 | DSP ASE usage: |
| 761 | "2" 2 bit unsigned immediate for byte align (OP_*_BP) |
| 762 | "3" 3 bit unsigned immediate (OP_*_SA3) |
| 763 | "4" 4 bit unsigned immediate (OP_*_SA4) |
| 764 | "5" 8 bit unsigned immediate (OP_*_IMM8) |
| 765 | "6" 5 bit unsigned immediate (OP_*_RS) |
| 766 | "7" 2 bit dsp accumulator register (OP_*_DSPACC) |
| 767 | "8" 6 bit unsigned immediate (OP_*_WRDSP) |
| 768 | "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) |
| 769 | "0" 6 bit signed immediate (OP_*_DSPSFT) |
| 770 | ":" 7 bit signed immediate (OP_*_DSPSFT_7) |
| 771 | "'" 6 bit unsigned immediate (OP_*_RDDSP) |
| 772 | "@" 10 bit signed immediate (OP_*_IMM10) |
| 773 | |
| 774 | MT ASE usage: |
| 775 | "!" 1 bit usermode flag (OP_*_MT_U) |
| 776 | "$" 1 bit load high flag (OP_*_MT_H) |
| 777 | "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) |
| 778 | "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) |
| 779 | "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) |
| 780 | "+t" 5 bit coprocessor 0 destination register (OP_*_RT) |
| 781 | |
| 782 | MCU ASE usage: |
| 783 | "~" 12 bit offset (OP_*_OFFSET12) |
| 784 | "\" 3 bit position for aset and aclr (OP_*_3BITPOS) |
| 785 | |
| 786 | VIRT ASE usage: |
| 787 | "+J" 10-bit hypcall code (OP_*CODE10) |
| 788 | |
| 789 | UDI immediates: |
| 790 | "+1" UDI immediate bits 6-10 |
| 791 | "+2" UDI immediate bits 6-15 |
| 792 | "+3" UDI immediate bits 6-20 |
| 793 | "+4" UDI immediate bits 6-25 |
| 794 | |
| 795 | Octeon: |
| 796 | "+x" Bit index field of bbit. Enforces: 0 <= index < 32. |
| 797 | "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64, |
| 798 | otherwise skips to next candidate. |
| 799 | "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32. |
| 800 | "+P" Position field of cins/exts aliasing cins32/exts32. Matches if |
| 801 | 32 <= pos < 64, otherwise skips to next candidate. |
| 802 | "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512. |
| 803 | "+s" Length-minus-one field of cins32/exts32. Requires msb position |
| 804 | of the field to be <= 31. |
| 805 | "+S" Length-minus-one field of cins/exts. Requires msb position |
| 806 | of the field to be <= 63. |
| 807 | |
| 808 | Loongson-3A: |
| 809 | "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A) |
| 810 | "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B) |
| 811 | "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C) |
| 812 | "+z" 5-bit rz register (OP_*_RZ) |
| 813 | "+Z" 5-bit fz register (OP_*_FZ) |
| 814 | |
| 815 | Enhanced VA Scheme: |
| 816 | "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET) |
| 817 | |
| 818 | Other: |
| 819 | "()" parens surrounding optional value |
| 820 | "," separates operands |
| 821 | "+" Start of extension sequence. |
| 822 | |
| 823 | Characters used so far, for quick reference when adding more: |
| 824 | "1234567890" |
| 825 | "%[]<>(),+:'@!$*&\~" |
| 826 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" |
| 827 | "abcdefghijklopqrstuvwxz" |
| 828 | |
| 829 | Extension character sequences used so far ("+" followed by the |
| 830 | following), for quick reference when adding more: |
| 831 | "1234" |
| 832 | "ABCEFGHIJPQSXZ" |
| 833 | "abcijpstxz" |
| 834 | */ |
| 835 | |
| 836 | /* These are the bits which may be set in the pinfo field of an |
| 837 | instructions, if it is not equal to INSN_MACRO. */ |
| 838 | |
| 839 | /* Modifies the general purpose register in OP_*_RD. */ |
| 840 | #define INSN_WRITE_GPR_D 0x00000001 |
| 841 | /* Modifies the general purpose register in OP_*_RT. */ |
| 842 | #define INSN_WRITE_GPR_T 0x00000002 |
| 843 | /* Modifies general purpose register 31. */ |
| 844 | #define INSN_WRITE_GPR_31 0x00000004 |
| 845 | /* Modifies the floating point register in OP_*_FD. */ |
| 846 | #define INSN_WRITE_FPR_D 0x00000008 |
| 847 | /* Modifies the floating point register in OP_*_FS. */ |
| 848 | #define INSN_WRITE_FPR_S 0x00000010 |
| 849 | /* Modifies the floating point register in OP_*_FT. */ |
| 850 | #define INSN_WRITE_FPR_T 0x00000020 |
| 851 | /* Reads the general purpose register in OP_*_RS. */ |
| 852 | #define INSN_READ_GPR_S 0x00000040 |
| 853 | /* Reads the general purpose register in OP_*_RT. */ |
| 854 | #define INSN_READ_GPR_T 0x00000080 |
| 855 | /* Reads the floating point register in OP_*_FS. */ |
| 856 | #define INSN_READ_FPR_S 0x00000100 |
| 857 | /* Reads the floating point register in OP_*_FT. */ |
| 858 | #define INSN_READ_FPR_T 0x00000200 |
| 859 | /* Reads the floating point register in OP_*_FR. */ |
| 860 | #define INSN_READ_FPR_R 0x00000400 |
| 861 | /* Modifies coprocessor condition code. */ |
| 862 | #define INSN_WRITE_COND_CODE 0x00000800 |
| 863 | /* Reads coprocessor condition code. */ |
| 864 | #define INSN_READ_COND_CODE 0x00001000 |
| 865 | /* TLB operation. */ |
| 866 | #define INSN_TLB 0x00002000 |
| 867 | /* Reads coprocessor register other than floating point register. */ |
| 868 | #define INSN_COP 0x00004000 |
| 869 | /* Instruction loads value from memory, requiring delay. */ |
| 870 | #define INSN_LOAD_MEMORY_DELAY 0x00008000 |
| 871 | /* Instruction loads value from coprocessor, requiring delay. */ |
| 872 | #define INSN_LOAD_COPROC_DELAY 0x00010000 |
| 873 | /* Instruction has unconditional branch delay slot. */ |
| 874 | #define INSN_UNCOND_BRANCH_DELAY 0x00020000 |
| 875 | /* Instruction has conditional branch delay slot. */ |
| 876 | #define INSN_COND_BRANCH_DELAY 0x00040000 |
| 877 | /* Conditional branch likely: if branch not taken, insn nullified. */ |
| 878 | #define INSN_COND_BRANCH_LIKELY 0x00080000 |
| 879 | /* Moves to coprocessor register, requiring delay. */ |
| 880 | #define INSN_COPROC_MOVE_DELAY 0x00100000 |
| 881 | /* Loads coprocessor register from memory, requiring delay. */ |
| 882 | #define INSN_COPROC_MEMORY_DELAY 0x00200000 |
| 883 | /* Reads the HI register. */ |
| 884 | #define INSN_READ_HI 0x00400000 |
| 885 | /* Reads the LO register. */ |
| 886 | #define INSN_READ_LO 0x00800000 |
| 887 | /* Modifies the HI register. */ |
| 888 | #define INSN_WRITE_HI 0x01000000 |
| 889 | /* Modifies the LO register. */ |
| 890 | #define INSN_WRITE_LO 0x02000000 |
| 891 | /* Not to be placed in a branch delay slot, either architecturally |
| 892 | or for ease of handling (such as with instructions that take a trap). */ |
| 893 | #define INSN_NO_DELAY_SLOT 0x04000000 |
| 894 | /* Instruction stores value into memory. */ |
| 895 | #define INSN_STORE_MEMORY 0x08000000 |
| 896 | /* Instruction uses single precision floating point. */ |
| 897 | #define FP_S 0x10000000 |
| 898 | /* Instruction uses double precision floating point. */ |
| 899 | #define FP_D 0x20000000 |
| 900 | /* Instruction is part of the tx39's integer multiply family. */ |
| 901 | #define INSN_MULT 0x40000000 |
| 902 | /* Modifies the general purpose register in MICROMIPSOP_*_RS. */ |
| 903 | #define INSN_WRITE_GPR_S 0x80000000 |
| 904 | /* Instruction is actually a macro. It should be ignored by the |
| 905 | disassembler, and requires special treatment by the assembler. */ |
| 906 | #define INSN_MACRO 0xffffffff |
| 907 | |
| 908 | /* These are the bits which may be set in the pinfo2 field of an |
| 909 | instruction. */ |
| 910 | |
| 911 | /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ |
| 912 | #define INSN2_ALIAS 0x00000001 |
| 913 | /* Instruction reads MDMX accumulator. */ |
| 914 | #define INSN2_READ_MDMX_ACC 0x00000002 |
| 915 | /* Instruction writes MDMX accumulator. */ |
| 916 | #define INSN2_WRITE_MDMX_ACC 0x00000004 |
| 917 | /* Macro uses single-precision floating-point instructions. This should |
| 918 | only be set for macros. For instructions, FP_S in pinfo carries the |
| 919 | same information. */ |
| 920 | #define INSN2_M_FP_S 0x00000008 |
| 921 | /* Macro uses double-precision floating-point instructions. This should |
| 922 | only be set for macros. For instructions, FP_D in pinfo carries the |
| 923 | same information. */ |
| 924 | #define INSN2_M_FP_D 0x00000010 |
| 925 | /* Modifies the general purpose register in OP_*_RZ. */ |
| 926 | #define INSN2_WRITE_GPR_Z 0x00000020 |
| 927 | /* Modifies the floating point register in OP_*_FZ. */ |
| 928 | #define INSN2_WRITE_FPR_Z 0x00000040 |
| 929 | /* Reads the general purpose register in OP_*_RZ. */ |
| 930 | #define INSN2_READ_GPR_Z 0x00000080 |
| 931 | /* Reads the floating point register in OP_*_FZ. */ |
| 932 | #define INSN2_READ_FPR_Z 0x00000100 |
| 933 | /* Reads the general purpose register in OP_*_RD. */ |
| 934 | #define INSN2_READ_GPR_D 0x00000200 |
| 935 | |
| 936 | |
| 937 | /* Instruction has a branch delay slot that requires a 16-bit instruction. */ |
| 938 | #define INSN2_BRANCH_DELAY_16BIT 0x00000400 |
| 939 | /* Instruction has a branch delay slot that requires a 32-bit instruction. */ |
| 940 | #define INSN2_BRANCH_DELAY_32BIT 0x00000800 |
| 941 | /* Reads the floating point register in MICROMIPSOP_*_FD. */ |
| 942 | #define INSN2_READ_FPR_D 0x00001000 |
| 943 | /* Modifies the general purpose register in MICROMIPSOP_*_MB. */ |
| 944 | #define INSN2_WRITE_GPR_MB 0x00002000 |
| 945 | /* Reads the general purpose register in MICROMIPSOP_*_MC. */ |
| 946 | #define INSN2_READ_GPR_MC 0x00004000 |
| 947 | /* Reads/writes the general purpose register in MICROMIPSOP_*_MD. */ |
| 948 | #define INSN2_MOD_GPR_MD 0x00008000 |
| 949 | /* Reads the general purpose register in MICROMIPSOP_*_ME. */ |
| 950 | #define INSN2_READ_GPR_ME 0x00010000 |
| 951 | /* Reads/writes the general purpose register in MICROMIPSOP_*_MF. */ |
| 952 | #define INSN2_MOD_GPR_MF 0x00020000 |
| 953 | /* Reads the general purpose register in MICROMIPSOP_*_MG. */ |
| 954 | #define INSN2_READ_GPR_MG 0x00040000 |
| 955 | /* Reads the general purpose register in MICROMIPSOP_*_MJ. */ |
| 956 | #define INSN2_READ_GPR_MJ 0x00080000 |
| 957 | /* Modifies the general purpose register in MICROMIPSOP_*_MJ. */ |
| 958 | #define INSN2_WRITE_GPR_MJ 0x00100000 |
| 959 | /* Reads the general purpose register in MICROMIPSOP_*_MP. */ |
| 960 | #define INSN2_READ_GPR_MP 0x00200000 |
| 961 | /* Modifies the general purpose register in MICROMIPSOP_*_MP. */ |
| 962 | #define INSN2_WRITE_GPR_MP 0x00400000 |
| 963 | /* Reads the general purpose register in MICROMIPSOP_*_MQ. */ |
| 964 | #define INSN2_READ_GPR_MQ 0x00800000 |
| 965 | /* Reads/Writes the stack pointer ($29). */ |
| 966 | #define INSN2_MOD_SP 0x01000000 |
| 967 | /* Reads the RA ($31) register. */ |
| 968 | #define INSN2_READ_GPR_31 0x02000000 |
| 969 | /* Reads the global pointer ($28). */ |
| 970 | #define INSN2_READ_GP 0x04000000 |
| 971 | /* Reads the program counter ($pc). */ |
| 972 | #define INSN2_READ_PC 0x08000000 |
| 973 | /* Is an unconditional branch insn. */ |
| 974 | #define INSN2_UNCOND_BRANCH 0x10000000 |
| 975 | /* Is a conditional branch insn. */ |
| 976 | #define INSN2_COND_BRANCH 0x20000000 |
| 977 | /* Modifies the general purpose registers in MICROMIPSOP_*_MH. */ |
| 978 | #define INSN2_WRITE_GPR_MH 0x40000000 |
| 979 | /* Reads the general purpose registers in MICROMIPSOP_*_MM/N. */ |
| 980 | #define INSN2_READ_GPR_MMN 0x80000000 |
| 981 | |
| 982 | /* Masks used to mark instructions to indicate which MIPS ISA level |
| 983 | they were introduced in. INSN_ISA_MASK masks an enumeration that |
| 984 | specifies the base ISA level(s). The remainder of a 32-bit |
| 985 | word constructed using these macros is a bitmask of the remaining |
| 986 | INSN_* values below. */ |
| 987 | |
| 988 | #define INSN_ISA_MASK 0x0000000ful |
| 989 | |
| 990 | /* We cannot start at zero due to ISA_UNKNOWN below. */ |
| 991 | #define INSN_ISA1 1 |
| 992 | #define INSN_ISA2 2 |
| 993 | #define INSN_ISA3 3 |
| 994 | #define INSN_ISA4 4 |
| 995 | #define INSN_ISA5 5 |
| 996 | #define INSN_ISA32 6 |
| 997 | #define INSN_ISA32R2 7 |
| 998 | #define INSN_ISA64 8 |
| 999 | #define INSN_ISA64R2 9 |
| 1000 | /* Below this point the INSN_* values correspond to combinations of ISAs. |
| 1001 | They are only for use in the opcodes table to indicate membership of |
| 1002 | a combination of ISAs that cannot be expressed using the usual inclusion |
| 1003 | ordering on the above INSN_* values. */ |
| 1004 | #define INSN_ISA3_32 10 |
| 1005 | #define INSN_ISA3_32R2 11 |
| 1006 | #define INSN_ISA4_32 12 |
| 1007 | #define INSN_ISA4_32R2 13 |
| 1008 | #define INSN_ISA5_32R2 14 |
| 1009 | |
| 1010 | /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through |
| 1011 | INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2, |
| 1012 | this table describes whether at least one of the ISAs described by X |
| 1013 | is/are implemented by ISA Y. (Think of Y as the ISA level supported by |
| 1014 | a particular core and X as the ISA level(s) at which a certain instruction |
| 1015 | is defined.) The ISA(s) described by X is/are implemented by Y iff |
| 1016 | (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1 |
| 1017 | is non-zero. */ |
| 1018 | static const unsigned int mips_isa_table[] = |
| 1019 | { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; |
| 1020 | |
| 1021 | /* Masks used for Chip specific instructions. */ |
| 1022 | #define INSN_CHIP_MASK 0xc3ff0f20 |
| 1023 | |
| 1024 | /* Cavium Networks Octeon instructions. */ |
| 1025 | #define INSN_OCTEON 0x00000800 |
| 1026 | #define INSN_OCTEONP 0x00000200 |
| 1027 | #define INSN_OCTEON2 0x00000100 |
| 1028 | |
| 1029 | /* MIPS R5900 instruction */ |
| 1030 | #define INSN_5900 0x00004000 |
| 1031 | |
| 1032 | /* MIPS R4650 instruction. */ |
| 1033 | #define INSN_4650 0x00010000 |
| 1034 | /* LSI R4010 instruction. */ |
| 1035 | #define INSN_4010 0x00020000 |
| 1036 | /* NEC VR4100 instruction. */ |
| 1037 | #define INSN_4100 0x00040000 |
| 1038 | /* Toshiba R3900 instruction. */ |
| 1039 | #define INSN_3900 0x00080000 |
| 1040 | /* MIPS R10000 instruction. */ |
| 1041 | #define INSN_10000 0x00100000 |
| 1042 | /* Broadcom SB-1 instruction. */ |
| 1043 | #define INSN_SB1 0x00200000 |
| 1044 | /* NEC VR4111/VR4181 instruction. */ |
| 1045 | #define INSN_4111 0x00400000 |
| 1046 | /* NEC VR4120 instruction. */ |
| 1047 | #define INSN_4120 0x00800000 |
| 1048 | /* NEC VR5400 instruction. */ |
| 1049 | #define INSN_5400 0x01000000 |
| 1050 | /* NEC VR5500 instruction. */ |
| 1051 | #define INSN_5500 0x02000000 |
| 1052 | |
| 1053 | /* ST Microelectronics Loongson 2E. */ |
| 1054 | #define INSN_LOONGSON_2E 0x40000000 |
| 1055 | /* ST Microelectronics Loongson 2F. */ |
| 1056 | #define INSN_LOONGSON_2F 0x80000000 |
| 1057 | /* Loongson 3A. */ |
| 1058 | #define INSN_LOONGSON_3A 0x00000400 |
| 1059 | /* RMI Xlr instruction */ |
| 1060 | #define INSN_XLR 0x00000020 |
| 1061 | |
| 1062 | /* DSP ASE */ |
| 1063 | #define ASE_DSP 0x00000001 |
| 1064 | #define ASE_DSP64 0x00000002 |
| 1065 | /* DSP R2 ASE */ |
| 1066 | #define ASE_DSPR2 0x00000004 |
| 1067 | /* Enhanced VA Scheme */ |
| 1068 | #define ASE_EVA 0x00000008 |
| 1069 | /* MCU (MicroController) ASE */ |
| 1070 | #define ASE_MCU 0x00000010 |
| 1071 | /* MDMX ASE */ |
| 1072 | #define ASE_MDMX 0x00000020 |
| 1073 | /* MIPS-3D ASE */ |
| 1074 | #define ASE_MIPS3D 0x00000040 |
| 1075 | /* MT ASE */ |
| 1076 | #define ASE_MT 0x00000080 |
| 1077 | /* SmartMIPS ASE */ |
| 1078 | #define ASE_SMARTMIPS 0x00000100 |
| 1079 | /* Virtualization ASE */ |
| 1080 | #define ASE_VIRT 0x00000200 |
| 1081 | #define ASE_VIRT64 0x00000400 |
| 1082 | |
| 1083 | /* MIPS ISA defines, use instead of hardcoding ISA level. */ |
| 1084 | |
| 1085 | #define ISA_UNKNOWN 0 /* Gas internal use. */ |
| 1086 | #define ISA_MIPS1 INSN_ISA1 |
| 1087 | #define ISA_MIPS2 INSN_ISA2 |
| 1088 | #define ISA_MIPS3 INSN_ISA3 |
| 1089 | #define ISA_MIPS4 INSN_ISA4 |
| 1090 | #define ISA_MIPS5 INSN_ISA5 |
| 1091 | |
| 1092 | #define ISA_MIPS32 INSN_ISA32 |
| 1093 | #define ISA_MIPS64 INSN_ISA64 |
| 1094 | |
| 1095 | #define ISA_MIPS32R2 INSN_ISA32R2 |
| 1096 | #define ISA_MIPS64R2 INSN_ISA64R2 |
| 1097 | |
| 1098 | |
| 1099 | /* CPU defines, use instead of hardcoding processor number. Keep this |
| 1100 | in sync with bfd/archures.c in order for machine selection to work. */ |
| 1101 | #define CPU_UNKNOWN 0 /* Gas internal use. */ |
| 1102 | #define CPU_R3000 3000 |
| 1103 | #define CPU_R3900 3900 |
| 1104 | #define CPU_R4000 4000 |
| 1105 | #define CPU_R4010 4010 |
| 1106 | #define CPU_VR4100 4100 |
| 1107 | #define CPU_R4111 4111 |
| 1108 | #define CPU_VR4120 4120 |
| 1109 | #define CPU_R4300 4300 |
| 1110 | #define CPU_R4400 4400 |
| 1111 | #define CPU_R4600 4600 |
| 1112 | #define CPU_R4650 4650 |
| 1113 | #define CPU_R5000 5000 |
| 1114 | #define CPU_VR5400 5400 |
| 1115 | #define CPU_VR5500 5500 |
| 1116 | #define CPU_R5900 5900 |
| 1117 | #define CPU_R6000 6000 |
| 1118 | #define CPU_RM7000 7000 |
| 1119 | #define CPU_R8000 8000 |
| 1120 | #define CPU_RM9000 9000 |
| 1121 | #define CPU_R10000 10000 |
| 1122 | #define CPU_R12000 12000 |
| 1123 | #define CPU_R14000 14000 |
| 1124 | #define CPU_R16000 16000 |
| 1125 | #define CPU_MIPS16 16 |
| 1126 | #define CPU_MIPS32 32 |
| 1127 | #define CPU_MIPS32R2 33 |
| 1128 | #define CPU_MIPS5 5 |
| 1129 | #define CPU_MIPS64 64 |
| 1130 | #define CPU_MIPS64R2 65 |
| 1131 | #define CPU_SB1 12310201 /* octal 'SB', 01. */ |
| 1132 | #define CPU_LOONGSON_2E 3001 |
| 1133 | #define CPU_LOONGSON_2F 3002 |
| 1134 | #define CPU_LOONGSON_3A 3003 |
| 1135 | #define CPU_OCTEON 6501 |
| 1136 | #define CPU_OCTEONP 6601 |
| 1137 | #define CPU_OCTEON2 6502 |
| 1138 | #define CPU_XLR 887682 /* decimal 'XLR' */ |
| 1139 | |
| 1140 | /* Return true if the given CPU is included in INSN_* mask MASK. */ |
| 1141 | |
| 1142 | static inline bfd_boolean |
| 1143 | cpu_is_member (int cpu, unsigned int mask) |
| 1144 | { |
| 1145 | switch (cpu) |
| 1146 | { |
| 1147 | case CPU_R4650: |
| 1148 | case CPU_RM7000: |
| 1149 | case CPU_RM9000: |
| 1150 | return (mask & INSN_4650) != 0; |
| 1151 | |
| 1152 | case CPU_R4010: |
| 1153 | return (mask & INSN_4010) != 0; |
| 1154 | |
| 1155 | case CPU_VR4100: |
| 1156 | return (mask & INSN_4100) != 0; |
| 1157 | |
| 1158 | case CPU_R3900: |
| 1159 | return (mask & INSN_3900) != 0; |
| 1160 | |
| 1161 | case CPU_R10000: |
| 1162 | case CPU_R12000: |
| 1163 | case CPU_R14000: |
| 1164 | case CPU_R16000: |
| 1165 | return (mask & INSN_10000) != 0; |
| 1166 | |
| 1167 | case CPU_SB1: |
| 1168 | return (mask & INSN_SB1) != 0; |
| 1169 | |
| 1170 | case CPU_R4111: |
| 1171 | return (mask & INSN_4111) != 0; |
| 1172 | |
| 1173 | case CPU_VR4120: |
| 1174 | return (mask & INSN_4120) != 0; |
| 1175 | |
| 1176 | case CPU_VR5400: |
| 1177 | return (mask & INSN_5400) != 0; |
| 1178 | |
| 1179 | case CPU_VR5500: |
| 1180 | return (mask & INSN_5500) != 0; |
| 1181 | |
| 1182 | case CPU_R5900: |
| 1183 | return (mask & INSN_5900) != 0; |
| 1184 | |
| 1185 | case CPU_LOONGSON_2E: |
| 1186 | return (mask & INSN_LOONGSON_2E) != 0; |
| 1187 | |
| 1188 | case CPU_LOONGSON_2F: |
| 1189 | return (mask & INSN_LOONGSON_2F) != 0; |
| 1190 | |
| 1191 | case CPU_LOONGSON_3A: |
| 1192 | return (mask & INSN_LOONGSON_3A) != 0; |
| 1193 | |
| 1194 | case CPU_OCTEON: |
| 1195 | return (mask & INSN_OCTEON) != 0; |
| 1196 | |
| 1197 | case CPU_OCTEONP: |
| 1198 | return (mask & INSN_OCTEONP) != 0; |
| 1199 | |
| 1200 | case CPU_OCTEON2: |
| 1201 | return (mask & INSN_OCTEON2) != 0; |
| 1202 | |
| 1203 | case CPU_XLR: |
| 1204 | return (mask & INSN_XLR) != 0; |
| 1205 | |
| 1206 | default: |
| 1207 | return FALSE; |
| 1208 | } |
| 1209 | } |
| 1210 | |
| 1211 | /* Test for membership in an ISA including chip specific ISAs. INSN |
| 1212 | is pointer to an element of the opcode table; ISA is the specified |
| 1213 | ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to |
| 1214 | test, or zero if no CPU specific ISA test is desired. Return true |
| 1215 | if instruction INSN is available to the given ISA and CPU. */ |
| 1216 | |
| 1217 | static inline bfd_boolean |
| 1218 | opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu) |
| 1219 | { |
| 1220 | if (!cpu_is_member (cpu, insn->exclusions)) |
| 1221 | { |
| 1222 | /* Test for ISA level compatibility. */ |
| 1223 | if ((isa & INSN_ISA_MASK) != 0 |
| 1224 | && (insn->membership & INSN_ISA_MASK) != 0 |
| 1225 | && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1] |
| 1226 | >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0) |
| 1227 | return TRUE; |
| 1228 | |
| 1229 | /* Test for ASE compatibility. */ |
| 1230 | if ((ase & insn->ase) != 0) |
| 1231 | return TRUE; |
| 1232 | |
| 1233 | /* Test for processor-specific extensions. */ |
| 1234 | if (cpu_is_member (cpu, insn->membership)) |
| 1235 | return TRUE; |
| 1236 | } |
| 1237 | return FALSE; |
| 1238 | } |
| 1239 | |
| 1240 | /* This is a list of macro expanded instructions. |
| 1241 | |
| 1242 | _I appended means immediate |
| 1243 | _A appended means target address of a jump |
| 1244 | _AB appended means address with (possibly zero) base register |
| 1245 | _D appended means 64 bit floating point constant |
| 1246 | _S appended means 32 bit floating point constant. */ |
| 1247 | |
| 1248 | enum |
| 1249 | { |
| 1250 | M_ABS, |
| 1251 | M_ACLR_AB, |
| 1252 | M_ADD_I, |
| 1253 | M_ADDU_I, |
| 1254 | M_AND_I, |
| 1255 | M_ASET_AB, |
| 1256 | M_BALIGN, |
| 1257 | M_BC1FL, |
| 1258 | M_BC1TL, |
| 1259 | M_BC2FL, |
| 1260 | M_BC2TL, |
| 1261 | M_BEQ, |
| 1262 | M_BEQ_I, |
| 1263 | M_BEQL, |
| 1264 | M_BEQL_I, |
| 1265 | M_BGE, |
| 1266 | M_BGEL, |
| 1267 | M_BGE_I, |
| 1268 | M_BGEL_I, |
| 1269 | M_BGEU, |
| 1270 | M_BGEUL, |
| 1271 | M_BGEU_I, |
| 1272 | M_BGEUL_I, |
| 1273 | M_BGEZ, |
| 1274 | M_BGEZL, |
| 1275 | M_BGEZALL, |
| 1276 | M_BGT, |
| 1277 | M_BGTL, |
| 1278 | M_BGT_I, |
| 1279 | M_BGTL_I, |
| 1280 | M_BGTU, |
| 1281 | M_BGTUL, |
| 1282 | M_BGTU_I, |
| 1283 | M_BGTUL_I, |
| 1284 | M_BGTZ, |
| 1285 | M_BGTZL, |
| 1286 | M_BLE, |
| 1287 | M_BLEL, |
| 1288 | M_BLE_I, |
| 1289 | M_BLEL_I, |
| 1290 | M_BLEU, |
| 1291 | M_BLEUL, |
| 1292 | M_BLEU_I, |
| 1293 | M_BLEUL_I, |
| 1294 | M_BLEZ, |
| 1295 | M_BLEZL, |
| 1296 | M_BLT, |
| 1297 | M_BLTL, |
| 1298 | M_BLT_I, |
| 1299 | M_BLTL_I, |
| 1300 | M_BLTU, |
| 1301 | M_BLTUL, |
| 1302 | M_BLTU_I, |
| 1303 | M_BLTUL_I, |
| 1304 | M_BLTZ, |
| 1305 | M_BLTZL, |
| 1306 | M_BLTZALL, |
| 1307 | M_BNE, |
| 1308 | M_BNEL, |
| 1309 | M_BNE_I, |
| 1310 | M_BNEL_I, |
| 1311 | M_CACHE_AB, |
| 1312 | M_CACHEE_AB, |
| 1313 | M_DABS, |
| 1314 | M_DADD_I, |
| 1315 | M_DADDU_I, |
| 1316 | M_DDIV_3, |
| 1317 | M_DDIV_3I, |
| 1318 | M_DDIVU_3, |
| 1319 | M_DDIVU_3I, |
| 1320 | M_DEXT, |
| 1321 | M_DINS, |
| 1322 | M_DIV_3, |
| 1323 | M_DIV_3I, |
| 1324 | M_DIVU_3, |
| 1325 | M_DIVU_3I, |
| 1326 | M_DLA_AB, |
| 1327 | M_DLCA_AB, |
| 1328 | M_DLI, |
| 1329 | M_DMUL, |
| 1330 | M_DMUL_I, |
| 1331 | M_DMULO, |
| 1332 | M_DMULO_I, |
| 1333 | M_DMULOU, |
| 1334 | M_DMULOU_I, |
| 1335 | M_DREM_3, |
| 1336 | M_DREM_3I, |
| 1337 | M_DREMU_3, |
| 1338 | M_DREMU_3I, |
| 1339 | M_DSUB_I, |
| 1340 | M_DSUBU_I, |
| 1341 | M_DSUBU_I_2, |
| 1342 | M_J_A, |
| 1343 | M_JAL_1, |
| 1344 | M_JAL_2, |
| 1345 | M_JAL_A, |
| 1346 | M_JALS_1, |
| 1347 | M_JALS_2, |
| 1348 | M_JALS_A, |
| 1349 | M_JRADDIUSP, |
| 1350 | M_JRC, |
| 1351 | M_L_DAB, |
| 1352 | M_LA_AB, |
| 1353 | M_LB_AB, |
| 1354 | M_LBE_AB, |
| 1355 | M_LBU_AB, |
| 1356 | M_LBUE_AB, |
| 1357 | M_LCA_AB, |
| 1358 | M_LD_AB, |
| 1359 | M_LDC1_AB, |
| 1360 | M_LDC2_AB, |
| 1361 | M_LQC2_AB, |
| 1362 | M_LDC3_AB, |
| 1363 | M_LDL_AB, |
| 1364 | M_LDM_AB, |
| 1365 | M_LDP_AB, |
| 1366 | M_LDR_AB, |
| 1367 | M_LH_AB, |
| 1368 | M_LHE_AB, |
| 1369 | M_LHU_AB, |
| 1370 | M_LHUE_AB, |
| 1371 | M_LI, |
| 1372 | M_LI_D, |
| 1373 | M_LI_DD, |
| 1374 | M_LI_S, |
| 1375 | M_LI_SS, |
| 1376 | M_LL_AB, |
| 1377 | M_LLD_AB, |
| 1378 | M_LLE_AB, |
| 1379 | M_LQ_AB, |
| 1380 | M_LW_AB, |
| 1381 | M_LWE_AB, |
| 1382 | M_LWC0_AB, |
| 1383 | M_LWC1_AB, |
| 1384 | M_LWC2_AB, |
| 1385 | M_LWC3_AB, |
| 1386 | M_LWL_AB, |
| 1387 | M_LWLE_AB, |
| 1388 | M_LWM_AB, |
| 1389 | M_LWP_AB, |
| 1390 | M_LWR_AB, |
| 1391 | M_LWRE_AB, |
| 1392 | M_LWU_AB, |
| 1393 | M_MSGSND, |
| 1394 | M_MSGLD, |
| 1395 | M_MSGLD_T, |
| 1396 | M_MSGWAIT, |
| 1397 | M_MSGWAIT_T, |
| 1398 | M_MOVE, |
| 1399 | M_MOVEP, |
| 1400 | M_MUL, |
| 1401 | M_MUL_I, |
| 1402 | M_MULO, |
| 1403 | M_MULO_I, |
| 1404 | M_MULOU, |
| 1405 | M_MULOU_I, |
| 1406 | M_NOR_I, |
| 1407 | M_OR_I, |
| 1408 | M_PREF_AB, |
| 1409 | M_PREFE_AB, |
| 1410 | M_REM_3, |
| 1411 | M_REM_3I, |
| 1412 | M_REMU_3, |
| 1413 | M_REMU_3I, |
| 1414 | M_DROL, |
| 1415 | M_ROL, |
| 1416 | M_DROL_I, |
| 1417 | M_ROL_I, |
| 1418 | M_DROR, |
| 1419 | M_ROR, |
| 1420 | M_DROR_I, |
| 1421 | M_ROR_I, |
| 1422 | M_S_DA, |
| 1423 | M_S_DAB, |
| 1424 | M_S_S, |
| 1425 | M_SAA_AB, |
| 1426 | M_SAAD_AB, |
| 1427 | M_SC_AB, |
| 1428 | M_SCD_AB, |
| 1429 | M_SCE_AB, |
| 1430 | M_SD_AB, |
| 1431 | M_SDC1_AB, |
| 1432 | M_SDC2_AB, |
| 1433 | M_SQC2_AB, |
| 1434 | M_SDC3_AB, |
| 1435 | M_SDL_AB, |
| 1436 | M_SDM_AB, |
| 1437 | M_SDP_AB, |
| 1438 | M_SDR_AB, |
| 1439 | M_SEQ, |
| 1440 | M_SEQ_I, |
| 1441 | M_SGE, |
| 1442 | M_SGE_I, |
| 1443 | M_SGEU, |
| 1444 | M_SGEU_I, |
| 1445 | M_SGT, |
| 1446 | M_SGT_I, |
| 1447 | M_SGTU, |
| 1448 | M_SGTU_I, |
| 1449 | M_SLE, |
| 1450 | M_SLE_I, |
| 1451 | M_SLEU, |
| 1452 | M_SLEU_I, |
| 1453 | M_SLT_I, |
| 1454 | M_SLTU_I, |
| 1455 | M_SNE, |
| 1456 | M_SNE_I, |
| 1457 | M_SB_AB, |
| 1458 | M_SBE_AB, |
| 1459 | M_SH_AB, |
| 1460 | M_SHE_AB, |
| 1461 | M_SQ_AB, |
| 1462 | M_SW_AB, |
| 1463 | M_SWE_AB, |
| 1464 | M_SWC0_AB, |
| 1465 | M_SWC1_AB, |
| 1466 | M_SWC2_AB, |
| 1467 | M_SWC3_AB, |
| 1468 | M_SWL_AB, |
| 1469 | M_SWLE_AB, |
| 1470 | M_SWM_AB, |
| 1471 | M_SWP_AB, |
| 1472 | M_SWR_AB, |
| 1473 | M_SWRE_AB, |
| 1474 | M_SUB_I, |
| 1475 | M_SUBU_I, |
| 1476 | M_SUBU_I_2, |
| 1477 | M_TEQ_I, |
| 1478 | M_TGE_I, |
| 1479 | M_TGEU_I, |
| 1480 | M_TLT_I, |
| 1481 | M_TLTU_I, |
| 1482 | M_TNE_I, |
| 1483 | M_TRUNCWD, |
| 1484 | M_TRUNCWS, |
| 1485 | M_ULD_AB, |
| 1486 | M_ULH_AB, |
| 1487 | M_ULHU_AB, |
| 1488 | M_ULW_AB, |
| 1489 | M_USH_AB, |
| 1490 | M_USW_AB, |
| 1491 | M_USD_AB, |
| 1492 | M_XOR_I, |
| 1493 | M_COP0, |
| 1494 | M_COP1, |
| 1495 | M_COP2, |
| 1496 | M_COP3, |
| 1497 | M_NUM_MACROS |
| 1498 | }; |
| 1499 | |
| 1500 | |
| 1501 | /* The order of overloaded instructions matters. Label arguments and |
| 1502 | register arguments look the same. Instructions that can have either |
| 1503 | for arguments must apear in the correct order in this table for the |
| 1504 | assembler to pick the right one. In other words, entries with |
| 1505 | immediate operands must apear after the same instruction with |
| 1506 | registers. |
| 1507 | |
| 1508 | Many instructions are short hand for other instructions (i.e., The |
| 1509 | jal <register> instruction is short for jalr <register>). */ |
| 1510 | |
| 1511 | extern const struct mips_operand *decode_mips_operand (const char *); |
| 1512 | extern const struct mips_opcode mips_builtin_opcodes[]; |
| 1513 | extern const int bfd_mips_num_builtin_opcodes; |
| 1514 | extern struct mips_opcode *mips_opcodes; |
| 1515 | extern int bfd_mips_num_opcodes; |
| 1516 | #define NUMOPCODES bfd_mips_num_opcodes |
| 1517 | |
| 1518 | \f |
| 1519 | /* The rest of this file adds definitions for the mips16 TinyRISC |
| 1520 | processor. */ |
| 1521 | |
| 1522 | /* These are the bitmasks and shift counts used for the different |
| 1523 | fields in the instruction formats. Other than OP, no masks are |
| 1524 | provided for the fixed portions of an instruction, since they are |
| 1525 | not needed. |
| 1526 | |
| 1527 | The I format uses IMM11. |
| 1528 | |
| 1529 | The RI format uses RX and IMM8. |
| 1530 | |
| 1531 | The RR format uses RX, and RY. |
| 1532 | |
| 1533 | The RRI format uses RX, RY, and IMM5. |
| 1534 | |
| 1535 | The RRR format uses RX, RY, and RZ. |
| 1536 | |
| 1537 | The RRI_A format uses RX, RY, and IMM4. |
| 1538 | |
| 1539 | The SHIFT format uses RX, RY, and SHAMT. |
| 1540 | |
| 1541 | The I8 format uses IMM8. |
| 1542 | |
| 1543 | The I8_MOVR32 format uses RY and REGR32. |
| 1544 | |
| 1545 | The IR_MOV32R format uses REG32R and MOV32Z. |
| 1546 | |
| 1547 | The I64 format uses IMM8. |
| 1548 | |
| 1549 | The RI64 format uses RY and IMM5. |
| 1550 | */ |
| 1551 | |
| 1552 | #define MIPS16OP_MASK_OP 0x1f |
| 1553 | #define MIPS16OP_SH_OP 11 |
| 1554 | #define MIPS16OP_MASK_IMM11 0x7ff |
| 1555 | #define MIPS16OP_SH_IMM11 0 |
| 1556 | #define MIPS16OP_MASK_RX 0x7 |
| 1557 | #define MIPS16OP_SH_RX 8 |
| 1558 | #define MIPS16OP_MASK_IMM8 0xff |
| 1559 | #define MIPS16OP_SH_IMM8 0 |
| 1560 | #define MIPS16OP_MASK_RY 0x7 |
| 1561 | #define MIPS16OP_SH_RY 5 |
| 1562 | #define MIPS16OP_MASK_IMM5 0x1f |
| 1563 | #define MIPS16OP_SH_IMM5 0 |
| 1564 | #define MIPS16OP_MASK_RZ 0x7 |
| 1565 | #define MIPS16OP_SH_RZ 2 |
| 1566 | #define MIPS16OP_MASK_IMM4 0xf |
| 1567 | #define MIPS16OP_SH_IMM4 0 |
| 1568 | #define MIPS16OP_MASK_REGR32 0x1f |
| 1569 | #define MIPS16OP_SH_REGR32 0 |
| 1570 | #define MIPS16OP_MASK_REG32R 0x1f |
| 1571 | #define MIPS16OP_SH_REG32R 3 |
| 1572 | #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) |
| 1573 | #define MIPS16OP_MASK_MOVE32Z 0x7 |
| 1574 | #define MIPS16OP_SH_MOVE32Z 0 |
| 1575 | #define MIPS16OP_MASK_IMM6 0x3f |
| 1576 | #define MIPS16OP_SH_IMM6 5 |
| 1577 | |
| 1578 | /* These are the characters which may appears in the args field of a MIPS16 |
| 1579 | instruction. They appear in the order in which the fields appear when the |
| 1580 | instruction is used. Commas and parentheses in the args string are ignored |
| 1581 | when assembling, and written into the output when disassembling. |
| 1582 | |
| 1583 | "y" 3 bit register (MIPS16OP_*_RY) |
| 1584 | "x" 3 bit register (MIPS16OP_*_RX) |
| 1585 | "z" 3 bit register (MIPS16OP_*_RZ) |
| 1586 | "Z" 3 bit register (MIPS16OP_*_MOVE32Z) |
| 1587 | "v" 3 bit same register as source and destination (MIPS16OP_*_RX) |
| 1588 | "w" 3 bit same register as source and destination (MIPS16OP_*_RY) |
| 1589 | "0" zero register ($0) |
| 1590 | "S" stack pointer ($sp or $29) |
| 1591 | "P" program counter |
| 1592 | "R" return address register ($ra or $31) |
| 1593 | "X" 5 bit MIPS register (MIPS16OP_*_REGR32) |
| 1594 | "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) |
| 1595 | "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) |
| 1596 | "a" 26 bit jump address |
| 1597 | "i" likewise, but flips bit 0 |
| 1598 | "e" 11 bit extension value |
| 1599 | "l" register list for entry instruction |
| 1600 | "L" register list for exit instruction |
| 1601 | |
| 1602 | "I" an immediate value used for macros |
| 1603 | |
| 1604 | The remaining codes may be extended. Except as otherwise noted, |
| 1605 | the full extended operand is a 16 bit signed value. |
| 1606 | "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) |
| 1607 | ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) |
| 1608 | "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) |
| 1609 | "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) |
| 1610 | "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) |
| 1611 | "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) |
| 1612 | "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) |
| 1613 | "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) |
| 1614 | "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) |
| 1615 | "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) |
| 1616 | "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) |
| 1617 | "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) |
| 1618 | "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) |
| 1619 | "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) |
| 1620 | "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) |
| 1621 | "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) |
| 1622 | "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) |
| 1623 | "q" 11 bit branch address (MIPS16OP_*_IMM11) |
| 1624 | "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) |
| 1625 | "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) |
| 1626 | "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) |
| 1627 | "m" 7 bit register list for save instruction (18 bit extended) |
| 1628 | "M" 7 bit register list for restore instruction (18 bit extended) |
| 1629 | */ |
| 1630 | |
| 1631 | /* Save/restore encoding for the args field when all 4 registers are |
| 1632 | either saved as arguments or saved/restored as statics. */ |
| 1633 | #define MIPS16_ALL_ARGS 0xe |
| 1634 | #define MIPS16_ALL_STATICS 0xb |
| 1635 | |
| 1636 | /* For the mips16, we use the same opcode table format and a few of |
| 1637 | the same flags. However, most of the flags are different. */ |
| 1638 | |
| 1639 | /* Modifies the register in MIPS16OP_*_RX. */ |
| 1640 | #define MIPS16_INSN_WRITE_X 0x00000001 |
| 1641 | /* Modifies the register in MIPS16OP_*_RY. */ |
| 1642 | #define MIPS16_INSN_WRITE_Y 0x00000002 |
| 1643 | /* Modifies the register in MIPS16OP_*_RZ. */ |
| 1644 | #define MIPS16_INSN_WRITE_Z 0x00000004 |
| 1645 | /* Modifies the T ($24) register. */ |
| 1646 | #define MIPS16_INSN_WRITE_T 0x00000008 |
| 1647 | /* Modifies the RA ($31) register. */ |
| 1648 | #define MIPS16_INSN_WRITE_31 0x00000020 |
| 1649 | /* Modifies the general purpose register in MIPS16OP_*_REG32R. */ |
| 1650 | #define MIPS16_INSN_WRITE_GPR_Y 0x00000040 |
| 1651 | /* Reads the register in MIPS16OP_*_RX. */ |
| 1652 | #define MIPS16_INSN_READ_X 0x00000080 |
| 1653 | /* Reads the register in MIPS16OP_*_RY. */ |
| 1654 | #define MIPS16_INSN_READ_Y 0x00000100 |
| 1655 | /* Reads the register in MIPS16OP_*_MOVE32Z. */ |
| 1656 | #define MIPS16_INSN_READ_Z 0x00000200 |
| 1657 | /* Reads the T ($24) register. */ |
| 1658 | #define MIPS16_INSN_READ_T 0x00000400 |
| 1659 | /* Reads the SP ($29) register. */ |
| 1660 | #define MIPS16_INSN_READ_SP 0x00000800 |
| 1661 | /* Reads the general purpose register in MIPS16OP_*_REGR32. */ |
| 1662 | #define MIPS16_INSN_READ_GPR_X 0x00004000 |
| 1663 | |
| 1664 | /* The following flags have the same value for the mips16 opcode |
| 1665 | table: |
| 1666 | |
| 1667 | INSN_ISA3 |
| 1668 | |
| 1669 | INSN_UNCOND_BRANCH_DELAY |
| 1670 | INSN_COND_BRANCH_DELAY |
| 1671 | INSN_COND_BRANCH_LIKELY (never used) |
| 1672 | INSN_READ_HI |
| 1673 | INSN_READ_LO |
| 1674 | INSN_WRITE_HI |
| 1675 | INSN_WRITE_LO |
| 1676 | INSN_TRAP |
| 1677 | FP_D (never used) |
| 1678 | */ |
| 1679 | |
| 1680 | extern const struct mips_operand *decode_mips16_operand (char, bfd_boolean); |
| 1681 | extern const struct mips_opcode mips16_opcodes[]; |
| 1682 | extern const int bfd_mips16_num_opcodes; |
| 1683 | |
| 1684 | /* These are the bit masks and shift counts used for the different fields |
| 1685 | in the microMIPS instruction formats. No masks are provided for the |
| 1686 | fixed portions of an instruction, since they are not needed. */ |
| 1687 | |
| 1688 | #define MICROMIPSOP_MASK_IMMEDIATE 0xffff |
| 1689 | #define MICROMIPSOP_SH_IMMEDIATE 0 |
| 1690 | #define MICROMIPSOP_MASK_DELTA 0xffff |
| 1691 | #define MICROMIPSOP_SH_DELTA 0 |
| 1692 | #define MICROMIPSOP_MASK_CODE10 0x3ff |
| 1693 | #define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */ |
| 1694 | #define MICROMIPSOP_MASK_TRAP 0xf |
| 1695 | #define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */ |
| 1696 | #define MICROMIPSOP_MASK_SHAMT 0x1f |
| 1697 | #define MICROMIPSOP_SH_SHAMT 11 |
| 1698 | #define MICROMIPSOP_MASK_TARGET 0x3ffffff |
| 1699 | #define MICROMIPSOP_SH_TARGET 0 |
| 1700 | #define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */ |
| 1701 | #define MICROMIPSOP_SH_EXTLSB 6 |
| 1702 | #define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ |
| 1703 | #define MICROMIPSOP_SH_EXTMSBD 11 |
| 1704 | #define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */ |
| 1705 | #define MICROMIPSOP_SH_INSMSB 11 |
| 1706 | #define MICROMIPSOP_MASK_CODE 0x3ff |
| 1707 | #define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */ |
| 1708 | #define MICROMIPSOP_MASK_CODE2 0x3ff |
| 1709 | #define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */ |
| 1710 | #define MICROMIPSOP_MASK_CACHE 0x1f |
| 1711 | #define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */ |
| 1712 | #define MICROMIPSOP_MASK_SEL 0x7 |
| 1713 | #define MICROMIPSOP_SH_SEL 11 |
| 1714 | #define MICROMIPSOP_MASK_OFFSET12 0xfff |
| 1715 | #define MICROMIPSOP_SH_OFFSET12 0 |
| 1716 | #define MICROMIPSOP_MASK_3BITPOS 0x7 |
| 1717 | #define MICROMIPSOP_SH_3BITPOS 21 |
| 1718 | #define MICROMIPSOP_MASK_STYPE 0x1f |
| 1719 | #define MICROMIPSOP_SH_STYPE 16 |
| 1720 | #define MICROMIPSOP_MASK_OFFSET10 0x3ff |
| 1721 | #define MICROMIPSOP_SH_OFFSET10 6 |
| 1722 | #define MICROMIPSOP_MASK_RS 0x1f |
| 1723 | #define MICROMIPSOP_SH_RS 16 |
| 1724 | #define MICROMIPSOP_MASK_RT 0x1f |
| 1725 | #define MICROMIPSOP_SH_RT 21 |
| 1726 | #define MICROMIPSOP_MASK_RD 0x1f |
| 1727 | #define MICROMIPSOP_SH_RD 11 |
| 1728 | #define MICROMIPSOP_MASK_FS 0x1f |
| 1729 | #define MICROMIPSOP_SH_FS 16 |
| 1730 | #define MICROMIPSOP_MASK_FT 0x1f |
| 1731 | #define MICROMIPSOP_SH_FT 21 |
| 1732 | #define MICROMIPSOP_MASK_FD 0x1f |
| 1733 | #define MICROMIPSOP_SH_FD 11 |
| 1734 | #define MICROMIPSOP_MASK_FR 0x1f |
| 1735 | #define MICROMIPSOP_SH_FR 6 |
| 1736 | #define MICROMIPSOP_MASK_RS3 0x1f |
| 1737 | #define MICROMIPSOP_SH_RS3 6 |
| 1738 | #define MICROMIPSOP_MASK_PREFX 0x1f |
| 1739 | #define MICROMIPSOP_SH_PREFX 11 |
| 1740 | #define MICROMIPSOP_MASK_BCC 0x7 |
| 1741 | #define MICROMIPSOP_SH_BCC 18 |
| 1742 | #define MICROMIPSOP_MASK_CCC 0x7 |
| 1743 | #define MICROMIPSOP_SH_CCC 13 |
| 1744 | #define MICROMIPSOP_MASK_COPZ 0x7fffff |
| 1745 | #define MICROMIPSOP_SH_COPZ 3 |
| 1746 | |
| 1747 | #define MICROMIPSOP_MASK_MB 0x7 |
| 1748 | #define MICROMIPSOP_SH_MB 23 |
| 1749 | #define MICROMIPSOP_MASK_MC 0x7 |
| 1750 | #define MICROMIPSOP_SH_MC 4 |
| 1751 | #define MICROMIPSOP_MASK_MD 0x7 |
| 1752 | #define MICROMIPSOP_SH_MD 7 |
| 1753 | #define MICROMIPSOP_MASK_ME 0x7 |
| 1754 | #define MICROMIPSOP_SH_ME 1 |
| 1755 | #define MICROMIPSOP_MASK_MF 0x7 |
| 1756 | #define MICROMIPSOP_SH_MF 3 |
| 1757 | #define MICROMIPSOP_MASK_MG 0x7 |
| 1758 | #define MICROMIPSOP_SH_MG 0 |
| 1759 | #define MICROMIPSOP_MASK_MH 0x7 |
| 1760 | #define MICROMIPSOP_SH_MH 7 |
| 1761 | #define MICROMIPSOP_MASK_MJ 0x1f |
| 1762 | #define MICROMIPSOP_SH_MJ 0 |
| 1763 | #define MICROMIPSOP_MASK_ML 0x7 |
| 1764 | #define MICROMIPSOP_SH_ML 4 |
| 1765 | #define MICROMIPSOP_MASK_MM 0x7 |
| 1766 | #define MICROMIPSOP_SH_MM 1 |
| 1767 | #define MICROMIPSOP_MASK_MN 0x7 |
| 1768 | #define MICROMIPSOP_SH_MN 4 |
| 1769 | #define MICROMIPSOP_MASK_MP 0x1f |
| 1770 | #define MICROMIPSOP_SH_MP 5 |
| 1771 | #define MICROMIPSOP_MASK_MQ 0x7 |
| 1772 | #define MICROMIPSOP_SH_MQ 7 |
| 1773 | |
| 1774 | #define MICROMIPSOP_MASK_IMMA 0x7f |
| 1775 | #define MICROMIPSOP_SH_IMMA 0 |
| 1776 | #define MICROMIPSOP_MASK_IMMB 0x7 |
| 1777 | #define MICROMIPSOP_SH_IMMB 1 |
| 1778 | #define MICROMIPSOP_MASK_IMMC 0xf |
| 1779 | #define MICROMIPSOP_SH_IMMC 0 |
| 1780 | #define MICROMIPSOP_MASK_IMMD 0x3ff |
| 1781 | #define MICROMIPSOP_SH_IMMD 0 |
| 1782 | #define MICROMIPSOP_MASK_IMME 0x7f |
| 1783 | #define MICROMIPSOP_SH_IMME 0 |
| 1784 | #define MICROMIPSOP_MASK_IMMF 0xf |
| 1785 | #define MICROMIPSOP_SH_IMMF 0 |
| 1786 | #define MICROMIPSOP_MASK_IMMG 0xf |
| 1787 | #define MICROMIPSOP_SH_IMMG 0 |
| 1788 | #define MICROMIPSOP_MASK_IMMH 0xf |
| 1789 | #define MICROMIPSOP_SH_IMMH 0 |
| 1790 | #define MICROMIPSOP_MASK_IMMI 0x7f |
| 1791 | #define MICROMIPSOP_SH_IMMI 0 |
| 1792 | #define MICROMIPSOP_MASK_IMMJ 0xf |
| 1793 | #define MICROMIPSOP_SH_IMMJ 0 |
| 1794 | #define MICROMIPSOP_MASK_IMML 0xf |
| 1795 | #define MICROMIPSOP_SH_IMML 0 |
| 1796 | #define MICROMIPSOP_MASK_IMMM 0x7 |
| 1797 | #define MICROMIPSOP_SH_IMMM 1 |
| 1798 | #define MICROMIPSOP_MASK_IMMN 0x3 |
| 1799 | #define MICROMIPSOP_SH_IMMN 4 |
| 1800 | #define MICROMIPSOP_MASK_IMMO 0xf |
| 1801 | #define MICROMIPSOP_SH_IMMO 0 |
| 1802 | #define MICROMIPSOP_MASK_IMMP 0x1f |
| 1803 | #define MICROMIPSOP_SH_IMMP 0 |
| 1804 | #define MICROMIPSOP_MASK_IMMQ 0x7fffff |
| 1805 | #define MICROMIPSOP_SH_IMMQ 0 |
| 1806 | #define MICROMIPSOP_MASK_IMMU 0x1f |
| 1807 | #define MICROMIPSOP_SH_IMMU 0 |
| 1808 | #define MICROMIPSOP_MASK_IMMW 0x3f |
| 1809 | #define MICROMIPSOP_SH_IMMW 1 |
| 1810 | #define MICROMIPSOP_MASK_IMMX 0xf |
| 1811 | #define MICROMIPSOP_SH_IMMX 1 |
| 1812 | #define MICROMIPSOP_MASK_IMMY 0x1ff |
| 1813 | #define MICROMIPSOP_SH_IMMY 1 |
| 1814 | |
| 1815 | /* MIPS DSP ASE */ |
| 1816 | #define MICROMIPSOP_MASK_DSPACC 0x3 |
| 1817 | #define MICROMIPSOP_SH_DSPACC 14 |
| 1818 | #define MICROMIPSOP_MASK_DSPSFT 0x3f |
| 1819 | #define MICROMIPSOP_SH_DSPSFT 16 |
| 1820 | #define MICROMIPSOP_MASK_SA3 0x7 |
| 1821 | #define MICROMIPSOP_SH_SA3 13 |
| 1822 | #define MICROMIPSOP_MASK_SA4 0xf |
| 1823 | #define MICROMIPSOP_SH_SA4 12 |
| 1824 | #define MICROMIPSOP_MASK_IMM8 0xff |
| 1825 | #define MICROMIPSOP_SH_IMM8 13 |
| 1826 | #define MICROMIPSOP_MASK_IMM10 0x3ff |
| 1827 | #define MICROMIPSOP_SH_IMM10 16 |
| 1828 | #define MICROMIPSOP_MASK_WRDSP 0x3f |
| 1829 | #define MICROMIPSOP_SH_WRDSP 14 |
| 1830 | #define MICROMIPSOP_MASK_BP 0x3 |
| 1831 | #define MICROMIPSOP_SH_BP 14 |
| 1832 | |
| 1833 | /* Placeholders for fields that only exist in the traditional 32-bit |
| 1834 | instruction encoding; see the comment above for details. */ |
| 1835 | #define MICROMIPSOP_MASK_CODE20 0 |
| 1836 | #define MICROMIPSOP_SH_CODE20 0 |
| 1837 | #define MICROMIPSOP_MASK_PERFREG 0 |
| 1838 | #define MICROMIPSOP_SH_PERFREG 0 |
| 1839 | #define MICROMIPSOP_MASK_CODE19 0 |
| 1840 | #define MICROMIPSOP_SH_CODE19 0 |
| 1841 | #define MICROMIPSOP_MASK_ALN 0 |
| 1842 | #define MICROMIPSOP_SH_ALN 0 |
| 1843 | #define MICROMIPSOP_MASK_VECBYTE 0 |
| 1844 | #define MICROMIPSOP_SH_VECBYTE 0 |
| 1845 | #define MICROMIPSOP_MASK_VECALIGN 0 |
| 1846 | #define MICROMIPSOP_SH_VECALIGN 0 |
| 1847 | #define MICROMIPSOP_MASK_DSPACC_S 0 |
| 1848 | #define MICROMIPSOP_SH_DSPACC_S 0 |
| 1849 | #define MICROMIPSOP_MASK_DSPSFT_7 0 |
| 1850 | #define MICROMIPSOP_SH_DSPSFT_7 0 |
| 1851 | #define MICROMIPSOP_MASK_RDDSP 0 |
| 1852 | #define MICROMIPSOP_SH_RDDSP 0 |
| 1853 | #define MICROMIPSOP_MASK_MT_U 0 |
| 1854 | #define MICROMIPSOP_SH_MT_U 0 |
| 1855 | #define MICROMIPSOP_MASK_MT_H 0 |
| 1856 | #define MICROMIPSOP_SH_MT_H 0 |
| 1857 | #define MICROMIPSOP_MASK_MTACC_T 0 |
| 1858 | #define MICROMIPSOP_SH_MTACC_T 0 |
| 1859 | #define MICROMIPSOP_MASK_MTACC_D 0 |
| 1860 | #define MICROMIPSOP_SH_MTACC_D 0 |
| 1861 | #define MICROMIPSOP_MASK_BBITIND 0 |
| 1862 | #define MICROMIPSOP_SH_BBITIND 0 |
| 1863 | #define MICROMIPSOP_MASK_CINSPOS 0 |
| 1864 | #define MICROMIPSOP_SH_CINSPOS 0 |
| 1865 | #define MICROMIPSOP_MASK_CINSLM1 0 |
| 1866 | #define MICROMIPSOP_SH_CINSLM1 0 |
| 1867 | #define MICROMIPSOP_MASK_SEQI 0 |
| 1868 | #define MICROMIPSOP_SH_SEQI 0 |
| 1869 | #define MICROMIPSOP_SH_OFFSET_A 0 |
| 1870 | #define MICROMIPSOP_MASK_OFFSET_A 0 |
| 1871 | #define MICROMIPSOP_SH_OFFSET_B 0 |
| 1872 | #define MICROMIPSOP_MASK_OFFSET_B 0 |
| 1873 | #define MICROMIPSOP_SH_OFFSET_C 0 |
| 1874 | #define MICROMIPSOP_MASK_OFFSET_C 0 |
| 1875 | #define MICROMIPSOP_SH_RZ 0 |
| 1876 | #define MICROMIPSOP_MASK_RZ 0 |
| 1877 | #define MICROMIPSOP_SH_FZ 0 |
| 1878 | #define MICROMIPSOP_MASK_FZ 0 |
| 1879 | |
| 1880 | /* microMIPS Enhanced VA Scheme */ |
| 1881 | #define MICROMIPSOP_SH_EVAOFFSET 0 |
| 1882 | #define MICROMIPSOP_MASK_EVAOFFSET 0x1ff |
| 1883 | |
| 1884 | /* These are the characters which may appears in the args field of a microMIPS |
| 1885 | instruction. They appear in the order in which the fields appear |
| 1886 | when the instruction is used. Commas and parentheses in the args |
| 1887 | string are ignored when assembling, and written into the output |
| 1888 | when disassembling. |
| 1889 | |
| 1890 | The followings are for 16-bit microMIPS instructions. |
| 1891 | |
| 1892 | "ma" must be $28 |
| 1893 | "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4 |
| 1894 | The same register used as both source and target. |
| 1895 | "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7 |
| 1896 | "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1 |
| 1897 | The same register used as both source and target. |
| 1898 | "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3 |
| 1899 | "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0 |
| 1900 | "mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7 |
| 1901 | "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0 |
| 1902 | "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4 |
| 1903 | "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1 |
| 1904 | "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4 |
| 1905 | "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5 |
| 1906 | "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7 |
| 1907 | "mr" must be program counter |
| 1908 | "ms" must be $29 |
| 1909 | "mt" must be the same as the previous register |
| 1910 | "mx" must be the same as the destination register |
| 1911 | "my" must be $31 |
| 1912 | "mz" must be $0 |
| 1913 | |
| 1914 | "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA) |
| 1915 | "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB) |
| 1916 | "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255, |
| 1917 | 32768, 65535) (MICROMIPSOP_*_IMMC) |
| 1918 | "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD) |
| 1919 | "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME) |
| 1920 | "mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF) |
| 1921 | "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG) |
| 1922 | "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH) |
| 1923 | "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI) |
| 1924 | "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ) |
| 1925 | "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML) |
| 1926 | "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM) |
| 1927 | "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN) |
| 1928 | "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML) |
| 1929 | "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP) |
| 1930 | "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU) |
| 1931 | "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW) |
| 1932 | "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX) |
| 1933 | "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY) |
| 1934 | "mZ" must be zero |
| 1935 | |
| 1936 | In most cases 32-bit microMIPS instructions use the same characters |
| 1937 | as MIPS (with ADDIUPC being a notable exception, but there are some |
| 1938 | others too). |
| 1939 | |
| 1940 | "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10) |
| 1941 | "1" 5-bit sync type (MICROMIPSOP_*_STYPE) |
| 1942 | "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT) |
| 1943 | ">" shift amount between 32 and 63, stored after subtracting 32 |
| 1944 | (MICROMIPSOP_*_SHAMT) |
| 1945 | "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS) |
| 1946 | "|" 4-bit trap code (MICROMIPSOP_*_TRAP) |
| 1947 | "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12) |
| 1948 | "a" 26-bit target address (MICROMIPSOP_*_TARGET) |
| 1949 | "+i" likewise, but flips bit 0 |
| 1950 | "b" 5-bit base register (MICROMIPSOP_*_RS) |
| 1951 | "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE) |
| 1952 | "d" 5-bit destination register specifier (MICROMIPSOP_*_RD) |
| 1953 | "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX) |
| 1954 | "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE) |
| 1955 | "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA) |
| 1956 | "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE) |
| 1957 | "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT) |
| 1958 | "o" 16-bit signed offset (MICROMIPSOP_*_DELTA) |
| 1959 | "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA) |
| 1960 | "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2) |
| 1961 | "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS) |
| 1962 | "s" 5-bit source register specifier (MICROMIPSOP_*_RS) |
| 1963 | "t" 5-bit target register (MICROMIPSOP_*_RT) |
| 1964 | "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE) |
| 1965 | "v" 5-bit same register used as both source and destination |
| 1966 | (MICROMIPSOP_*_RS) |
| 1967 | "w" 5-bit same register used as both target and destination |
| 1968 | (MICROMIPSOP_*_RT) |
| 1969 | "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3) |
| 1970 | "z" must be zero register |
| 1971 | "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ) |
| 1972 | "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10) |
| 1973 | "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS) |
| 1974 | |
| 1975 | "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes |
| 1976 | LSB (MICROMIPSOP_*_EXTLSB). |
| 1977 | Enforces: 0 <= pos < 32. |
| 1978 | "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB). |
| 1979 | Requires that "+A" or "+E" occur first to set position. |
| 1980 | Enforces: 0 < (pos+size) <= 32. |
| 1981 | "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). |
| 1982 | Requires that "+A" or "+E" occur first to set position. |
| 1983 | Enforces: 0 < (pos+size) <= 32. |
| 1984 | (Also used by DEXT w/ different limits, but limits for |
| 1985 | that are checked by the M_DEXT macro.) |
| 1986 | "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB). |
| 1987 | Enforces: 32 <= pos < 64. |
| 1988 | "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB). |
| 1989 | Requires that "+A" or "+E" occur first to set position. |
| 1990 | Enforces: 32 < (pos+size) <= 64. |
| 1991 | "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD). |
| 1992 | Requires that "+A" or "+E" occur first to set position. |
| 1993 | Enforces: 32 < (pos+size) <= 64. |
| 1994 | "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). |
| 1995 | Requires that "+A" or "+E" occur first to set position. |
| 1996 | Enforces: 32 < (pos+size) <= 64. |
| 1997 | |
| 1998 | PC-relative addition (ADDIUPC) instruction: |
| 1999 | "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ) |
| 2000 | "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23 |
| 2001 | |
| 2002 | Floating point instructions: |
| 2003 | "D" 5-bit destination register (MICROMIPSOP_*_FD) |
| 2004 | "M" 3-bit compare condition code (MICROMIPSOP_*_CCC) |
| 2005 | "N" 3-bit branch condition code (MICROMIPSOP_*_BCC) |
| 2006 | "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR) |
| 2007 | "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS) |
| 2008 | "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT) |
| 2009 | "V" 5-bit same register used as floating source and destination or target |
| 2010 | (MICROMIPSOP_*_FS) |
| 2011 | |
| 2012 | Coprocessor instructions: |
| 2013 | "E" 5-bit target register (MICROMIPSOP_*_RT) |
| 2014 | "G" 5-bit source register (MICROMIPSOP_*_RS) |
| 2015 | "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) |
| 2016 | |
| 2017 | Macro instructions: |
| 2018 | "A" general 32 bit expression |
| 2019 | "I" 32-bit immediate (value placed in imm_expr). |
| 2020 | "+I" 32-bit immediate (value placed in imm2_expr). |
| 2021 | "F" 64-bit floating point constant in .rdata |
| 2022 | "L" 64-bit floating point constant in .lit8 |
| 2023 | "f" 32-bit floating point constant |
| 2024 | "l" 32-bit floating point constant in .lit4 |
| 2025 | |
| 2026 | DSP ASE usage: |
| 2027 | "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP) |
| 2028 | "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3) |
| 2029 | "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4) |
| 2030 | "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8) |
| 2031 | "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS) |
| 2032 | "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC) |
| 2033 | "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP) |
| 2034 | "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT) |
| 2035 | "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10) |
| 2036 | "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD) |
| 2037 | |
| 2038 | microMIPS Enhanced VA Scheme: |
| 2039 | "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET) |
| 2040 | |
| 2041 | Other: |
| 2042 | "()" parens surrounding optional value |
| 2043 | "," separates operands |
| 2044 | "+" start of extension sequence |
| 2045 | "m" start of microMIPS extension sequence |
| 2046 | |
| 2047 | Characters used so far, for quick reference when adding more: |
| 2048 | "12345678 0" |
| 2049 | "<>(),+.@\^|~" |
| 2050 | "ABCDEFGHI KLMN RST V " |
| 2051 | "abcd f hijklmnopqrstuvw yz" |
| 2052 | |
| 2053 | Extension character sequences used so far ("+" followed by the |
| 2054 | following), for quick reference when adding more: |
| 2055 | "" |
| 2056 | "" |
| 2057 | "ABCEFGHI" |
| 2058 | "ij" |
| 2059 | |
| 2060 | Extension character sequences used so far ("m" followed by the |
| 2061 | following), for quick reference when adding more: |
| 2062 | "" |
| 2063 | "" |
| 2064 | " BCDEFGHIJ LMNOPQ U WXYZ" |
| 2065 | " bcdefghij lmn pq st xyz" |
| 2066 | */ |
| 2067 | |
| 2068 | extern const struct mips_operand *decode_micromips_operand (const char *); |
| 2069 | extern const struct mips_opcode micromips_opcodes[]; |
| 2070 | extern const int bfd_micromips_num_opcodes; |
| 2071 | |
| 2072 | /* A NOP insn impemented as "or at,at,zero". |
| 2073 | Used to implement -mfix-loongson2f. */ |
| 2074 | #define LOONGSON2F_NOP_INSN 0x00200825 |
| 2075 | |
| 2076 | #endif /* _MIPS_H_ */ |