| 1 | /* Automatically generated by parse-opcodes. */ |
| 2 | #ifndef RISCV_ENCODING_H |
| 3 | #define RISCV_ENCODING_H |
| 4 | #define MATCH_SLLI_RV32 0x1013 |
| 5 | #define MASK_SLLI_RV32 0xfe00707f |
| 6 | #define MATCH_SRLI_RV32 0x5013 |
| 7 | #define MASK_SRLI_RV32 0xfe00707f |
| 8 | #define MATCH_SRAI_RV32 0x40005013 |
| 9 | #define MASK_SRAI_RV32 0xfe00707f |
| 10 | #define MATCH_FRFLAGS 0x102073 |
| 11 | #define MASK_FRFLAGS 0xfffff07f |
| 12 | #define MATCH_FSFLAGS 0x101073 |
| 13 | #define MASK_FSFLAGS 0xfff0707f |
| 14 | #define MATCH_FSFLAGSI 0x105073 |
| 15 | #define MASK_FSFLAGSI 0xfff0707f |
| 16 | #define MATCH_FRRM 0x202073 |
| 17 | #define MASK_FRRM 0xfffff07f |
| 18 | #define MATCH_FSRM 0x201073 |
| 19 | #define MASK_FSRM 0xfff0707f |
| 20 | #define MATCH_FSRMI 0x205073 |
| 21 | #define MASK_FSRMI 0xfff0707f |
| 22 | #define MATCH_FSCSR 0x301073 |
| 23 | #define MASK_FSCSR 0xfff0707f |
| 24 | #define MATCH_FRCSR 0x302073 |
| 25 | #define MASK_FRCSR 0xfffff07f |
| 26 | #define MATCH_RDCYCLE 0xc0002073 |
| 27 | #define MASK_RDCYCLE 0xfffff07f |
| 28 | #define MATCH_RDTIME 0xc0102073 |
| 29 | #define MASK_RDTIME 0xfffff07f |
| 30 | #define MATCH_RDINSTRET 0xc0202073 |
| 31 | #define MASK_RDINSTRET 0xfffff07f |
| 32 | #define MATCH_RDCYCLEH 0xc8002073 |
| 33 | #define MASK_RDCYCLEH 0xfffff07f |
| 34 | #define MATCH_RDTIMEH 0xc8102073 |
| 35 | #define MASK_RDTIMEH 0xfffff07f |
| 36 | #define MATCH_RDINSTRETH 0xc8202073 |
| 37 | #define MASK_RDINSTRETH 0xfffff07f |
| 38 | #define MATCH_SCALL 0x73 |
| 39 | #define MASK_SCALL 0xffffffff |
| 40 | #define MATCH_SBREAK 0x100073 |
| 41 | #define MASK_SBREAK 0xffffffff |
| 42 | #define MATCH_BEQ 0x63 |
| 43 | #define MASK_BEQ 0x707f |
| 44 | #define MATCH_BNE 0x1063 |
| 45 | #define MASK_BNE 0x707f |
| 46 | #define MATCH_BLT 0x4063 |
| 47 | #define MASK_BLT 0x707f |
| 48 | #define MATCH_BGE 0x5063 |
| 49 | #define MASK_BGE 0x707f |
| 50 | #define MATCH_BLTU 0x6063 |
| 51 | #define MASK_BLTU 0x707f |
| 52 | #define MATCH_BGEU 0x7063 |
| 53 | #define MASK_BGEU 0x707f |
| 54 | #define MATCH_JALR 0x67 |
| 55 | #define MASK_JALR 0x707f |
| 56 | #define MATCH_JAL 0x6f |
| 57 | #define MASK_JAL 0x7f |
| 58 | #define MATCH_LUI 0x37 |
| 59 | #define MASK_LUI 0x7f |
| 60 | #define MATCH_AUIPC 0x17 |
| 61 | #define MASK_AUIPC 0x7f |
| 62 | #define MATCH_ADDI 0x13 |
| 63 | #define MASK_ADDI 0x707f |
| 64 | #define MATCH_SLLI 0x1013 |
| 65 | #define MASK_SLLI 0xfc00707f |
| 66 | #define MATCH_SLTI 0x2013 |
| 67 | #define MASK_SLTI 0x707f |
| 68 | #define MATCH_SLTIU 0x3013 |
| 69 | #define MASK_SLTIU 0x707f |
| 70 | #define MATCH_XORI 0x4013 |
| 71 | #define MASK_XORI 0x707f |
| 72 | #define MATCH_SRLI 0x5013 |
| 73 | #define MASK_SRLI 0xfc00707f |
| 74 | #define MATCH_SRAI 0x40005013 |
| 75 | #define MASK_SRAI 0xfc00707f |
| 76 | #define MATCH_ORI 0x6013 |
| 77 | #define MASK_ORI 0x707f |
| 78 | #define MATCH_ANDI 0x7013 |
| 79 | #define MASK_ANDI 0x707f |
| 80 | #define MATCH_ADD 0x33 |
| 81 | #define MASK_ADD 0xfe00707f |
| 82 | #define MATCH_SUB 0x40000033 |
| 83 | #define MASK_SUB 0xfe00707f |
| 84 | #define MATCH_SLL 0x1033 |
| 85 | #define MASK_SLL 0xfe00707f |
| 86 | #define MATCH_SLT 0x2033 |
| 87 | #define MASK_SLT 0xfe00707f |
| 88 | #define MATCH_SLTU 0x3033 |
| 89 | #define MASK_SLTU 0xfe00707f |
| 90 | #define MATCH_XOR 0x4033 |
| 91 | #define MASK_XOR 0xfe00707f |
| 92 | #define MATCH_SRL 0x5033 |
| 93 | #define MASK_SRL 0xfe00707f |
| 94 | #define MATCH_SRA 0x40005033 |
| 95 | #define MASK_SRA 0xfe00707f |
| 96 | #define MATCH_OR 0x6033 |
| 97 | #define MASK_OR 0xfe00707f |
| 98 | #define MATCH_AND 0x7033 |
| 99 | #define MASK_AND 0xfe00707f |
| 100 | #define MATCH_ADDIW 0x1b |
| 101 | #define MASK_ADDIW 0x707f |
| 102 | #define MATCH_SLLIW 0x101b |
| 103 | #define MASK_SLLIW 0xfe00707f |
| 104 | #define MATCH_SRLIW 0x501b |
| 105 | #define MASK_SRLIW 0xfe00707f |
| 106 | #define MATCH_SRAIW 0x4000501b |
| 107 | #define MASK_SRAIW 0xfe00707f |
| 108 | #define MATCH_ADDW 0x3b |
| 109 | #define MASK_ADDW 0xfe00707f |
| 110 | #define MATCH_SUBW 0x4000003b |
| 111 | #define MASK_SUBW 0xfe00707f |
| 112 | #define MATCH_SLLW 0x103b |
| 113 | #define MASK_SLLW 0xfe00707f |
| 114 | #define MATCH_SRLW 0x503b |
| 115 | #define MASK_SRLW 0xfe00707f |
| 116 | #define MATCH_SRAW 0x4000503b |
| 117 | #define MASK_SRAW 0xfe00707f |
| 118 | #define MATCH_LB 0x3 |
| 119 | #define MASK_LB 0x707f |
| 120 | #define MATCH_LH 0x1003 |
| 121 | #define MASK_LH 0x707f |
| 122 | #define MATCH_LW 0x2003 |
| 123 | #define MASK_LW 0x707f |
| 124 | #define MATCH_LD 0x3003 |
| 125 | #define MASK_LD 0x707f |
| 126 | #define MATCH_LBU 0x4003 |
| 127 | #define MASK_LBU 0x707f |
| 128 | #define MATCH_LHU 0x5003 |
| 129 | #define MASK_LHU 0x707f |
| 130 | #define MATCH_LWU 0x6003 |
| 131 | #define MASK_LWU 0x707f |
| 132 | #define MATCH_SB 0x23 |
| 133 | #define MASK_SB 0x707f |
| 134 | #define MATCH_SH 0x1023 |
| 135 | #define MASK_SH 0x707f |
| 136 | #define MATCH_SW 0x2023 |
| 137 | #define MASK_SW 0x707f |
| 138 | #define MATCH_SD 0x3023 |
| 139 | #define MASK_SD 0x707f |
| 140 | #define MATCH_FENCE 0xf |
| 141 | #define MASK_FENCE 0x707f |
| 142 | #define MATCH_FENCE_I 0x100f |
| 143 | #define MASK_FENCE_I 0x707f |
| 144 | #define MATCH_FENCE_TSO 0x8330000f |
| 145 | #define MASK_FENCE_TSO 0xfff0707f |
| 146 | #define MATCH_MUL 0x2000033 |
| 147 | #define MASK_MUL 0xfe00707f |
| 148 | #define MATCH_MULH 0x2001033 |
| 149 | #define MASK_MULH 0xfe00707f |
| 150 | #define MATCH_MULHSU 0x2002033 |
| 151 | #define MASK_MULHSU 0xfe00707f |
| 152 | #define MATCH_MULHU 0x2003033 |
| 153 | #define MASK_MULHU 0xfe00707f |
| 154 | #define MATCH_DIV 0x2004033 |
| 155 | #define MASK_DIV 0xfe00707f |
| 156 | #define MATCH_DIVU 0x2005033 |
| 157 | #define MASK_DIVU 0xfe00707f |
| 158 | #define MATCH_REM 0x2006033 |
| 159 | #define MASK_REM 0xfe00707f |
| 160 | #define MATCH_REMU 0x2007033 |
| 161 | #define MASK_REMU 0xfe00707f |
| 162 | #define MATCH_MULW 0x200003b |
| 163 | #define MASK_MULW 0xfe00707f |
| 164 | #define MATCH_DIVW 0x200403b |
| 165 | #define MASK_DIVW 0xfe00707f |
| 166 | #define MATCH_DIVUW 0x200503b |
| 167 | #define MASK_DIVUW 0xfe00707f |
| 168 | #define MATCH_REMW 0x200603b |
| 169 | #define MASK_REMW 0xfe00707f |
| 170 | #define MATCH_REMUW 0x200703b |
| 171 | #define MASK_REMUW 0xfe00707f |
| 172 | #define MATCH_AMOADD_W 0x202f |
| 173 | #define MASK_AMOADD_W 0xf800707f |
| 174 | #define MATCH_AMOXOR_W 0x2000202f |
| 175 | #define MASK_AMOXOR_W 0xf800707f |
| 176 | #define MATCH_AMOOR_W 0x4000202f |
| 177 | #define MASK_AMOOR_W 0xf800707f |
| 178 | #define MATCH_AMOAND_W 0x6000202f |
| 179 | #define MASK_AMOAND_W 0xf800707f |
| 180 | #define MATCH_AMOMIN_W 0x8000202f |
| 181 | #define MASK_AMOMIN_W 0xf800707f |
| 182 | #define MATCH_AMOMAX_W 0xa000202f |
| 183 | #define MASK_AMOMAX_W 0xf800707f |
| 184 | #define MATCH_AMOMINU_W 0xc000202f |
| 185 | #define MASK_AMOMINU_W 0xf800707f |
| 186 | #define MATCH_AMOMAXU_W 0xe000202f |
| 187 | #define MASK_AMOMAXU_W 0xf800707f |
| 188 | #define MATCH_AMOSWAP_W 0x800202f |
| 189 | #define MASK_AMOSWAP_W 0xf800707f |
| 190 | #define MATCH_LR_W 0x1000202f |
| 191 | #define MASK_LR_W 0xf9f0707f |
| 192 | #define MATCH_SC_W 0x1800202f |
| 193 | #define MASK_SC_W 0xf800707f |
| 194 | #define MATCH_AMOADD_D 0x302f |
| 195 | #define MASK_AMOADD_D 0xf800707f |
| 196 | #define MATCH_AMOXOR_D 0x2000302f |
| 197 | #define MASK_AMOXOR_D 0xf800707f |
| 198 | #define MATCH_AMOOR_D 0x4000302f |
| 199 | #define MASK_AMOOR_D 0xf800707f |
| 200 | #define MATCH_AMOAND_D 0x6000302f |
| 201 | #define MASK_AMOAND_D 0xf800707f |
| 202 | #define MATCH_AMOMIN_D 0x8000302f |
| 203 | #define MASK_AMOMIN_D 0xf800707f |
| 204 | #define MATCH_AMOMAX_D 0xa000302f |
| 205 | #define MASK_AMOMAX_D 0xf800707f |
| 206 | #define MATCH_AMOMINU_D 0xc000302f |
| 207 | #define MASK_AMOMINU_D 0xf800707f |
| 208 | #define MATCH_AMOMAXU_D 0xe000302f |
| 209 | #define MASK_AMOMAXU_D 0xf800707f |
| 210 | #define MATCH_AMOSWAP_D 0x800302f |
| 211 | #define MASK_AMOSWAP_D 0xf800707f |
| 212 | #define MATCH_LR_D 0x1000302f |
| 213 | #define MASK_LR_D 0xf9f0707f |
| 214 | #define MATCH_SC_D 0x1800302f |
| 215 | #define MASK_SC_D 0xf800707f |
| 216 | #define MATCH_ECALL 0x73 |
| 217 | #define MASK_ECALL 0xffffffff |
| 218 | #define MATCH_EBREAK 0x100073 |
| 219 | #define MASK_EBREAK 0xffffffff |
| 220 | #define MATCH_URET 0x200073 |
| 221 | #define MASK_URET 0xffffffff |
| 222 | #define MATCH_SRET 0x10200073 |
| 223 | #define MASK_SRET 0xffffffff |
| 224 | #define MATCH_HRET 0x20200073 |
| 225 | #define MASK_HRET 0xffffffff |
| 226 | #define MATCH_MRET 0x30200073 |
| 227 | #define MASK_MRET 0xffffffff |
| 228 | #define MATCH_DRET 0x7b200073 |
| 229 | #define MASK_DRET 0xffffffff |
| 230 | #define MATCH_SFENCE_VM 0x10400073 |
| 231 | #define MASK_SFENCE_VM 0xfff07fff |
| 232 | #define MATCH_SFENCE_VMA 0x12000073 |
| 233 | #define MASK_SFENCE_VMA 0xfe007fff |
| 234 | #define MATCH_WFI 0x10500073 |
| 235 | #define MASK_WFI 0xffffffff |
| 236 | #define MATCH_CSRRW 0x1073 |
| 237 | #define MASK_CSRRW 0x707f |
| 238 | #define MATCH_CSRRS 0x2073 |
| 239 | #define MASK_CSRRS 0x707f |
| 240 | #define MATCH_CSRRC 0x3073 |
| 241 | #define MASK_CSRRC 0x707f |
| 242 | #define MATCH_CSRRWI 0x5073 |
| 243 | #define MASK_CSRRWI 0x707f |
| 244 | #define MATCH_CSRRSI 0x6073 |
| 245 | #define MASK_CSRRSI 0x707f |
| 246 | #define MATCH_CSRRCI 0x7073 |
| 247 | #define MASK_CSRRCI 0x707f |
| 248 | #define MATCH_FADD_S 0x53 |
| 249 | #define MASK_FADD_S 0xfe00007f |
| 250 | #define MATCH_FSUB_S 0x8000053 |
| 251 | #define MASK_FSUB_S 0xfe00007f |
| 252 | #define MATCH_FMUL_S 0x10000053 |
| 253 | #define MASK_FMUL_S 0xfe00007f |
| 254 | #define MATCH_FDIV_S 0x18000053 |
| 255 | #define MASK_FDIV_S 0xfe00007f |
| 256 | #define MATCH_FSGNJ_S 0x20000053 |
| 257 | #define MASK_FSGNJ_S 0xfe00707f |
| 258 | #define MATCH_FSGNJN_S 0x20001053 |
| 259 | #define MASK_FSGNJN_S 0xfe00707f |
| 260 | #define MATCH_FSGNJX_S 0x20002053 |
| 261 | #define MASK_FSGNJX_S 0xfe00707f |
| 262 | #define MATCH_FMIN_S 0x28000053 |
| 263 | #define MASK_FMIN_S 0xfe00707f |
| 264 | #define MATCH_FMAX_S 0x28001053 |
| 265 | #define MASK_FMAX_S 0xfe00707f |
| 266 | #define MATCH_FSQRT_S 0x58000053 |
| 267 | #define MASK_FSQRT_S 0xfff0007f |
| 268 | #define MATCH_FADD_D 0x2000053 |
| 269 | #define MASK_FADD_D 0xfe00007f |
| 270 | #define MATCH_FSUB_D 0xa000053 |
| 271 | #define MASK_FSUB_D 0xfe00007f |
| 272 | #define MATCH_FMUL_D 0x12000053 |
| 273 | #define MASK_FMUL_D 0xfe00007f |
| 274 | #define MATCH_FDIV_D 0x1a000053 |
| 275 | #define MASK_FDIV_D 0xfe00007f |
| 276 | #define MATCH_FSGNJ_D 0x22000053 |
| 277 | #define MASK_FSGNJ_D 0xfe00707f |
| 278 | #define MATCH_FSGNJN_D 0x22001053 |
| 279 | #define MASK_FSGNJN_D 0xfe00707f |
| 280 | #define MATCH_FSGNJX_D 0x22002053 |
| 281 | #define MASK_FSGNJX_D 0xfe00707f |
| 282 | #define MATCH_FMIN_D 0x2a000053 |
| 283 | #define MASK_FMIN_D 0xfe00707f |
| 284 | #define MATCH_FMAX_D 0x2a001053 |
| 285 | #define MASK_FMAX_D 0xfe00707f |
| 286 | #define MATCH_FCVT_S_D 0x40100053 |
| 287 | #define MASK_FCVT_S_D 0xfff0007f |
| 288 | #define MATCH_FCVT_D_S 0x42000053 |
| 289 | #define MASK_FCVT_D_S 0xfff0007f |
| 290 | #define MATCH_FSQRT_D 0x5a000053 |
| 291 | #define MASK_FSQRT_D 0xfff0007f |
| 292 | #define MATCH_FADD_Q 0x6000053 |
| 293 | #define MASK_FADD_Q 0xfe00007f |
| 294 | #define MATCH_FSUB_Q 0xe000053 |
| 295 | #define MASK_FSUB_Q 0xfe00007f |
| 296 | #define MATCH_FMUL_Q 0x16000053 |
| 297 | #define MASK_FMUL_Q 0xfe00007f |
| 298 | #define MATCH_FDIV_Q 0x1e000053 |
| 299 | #define MASK_FDIV_Q 0xfe00007f |
| 300 | #define MATCH_FSGNJ_Q 0x26000053 |
| 301 | #define MASK_FSGNJ_Q 0xfe00707f |
| 302 | #define MATCH_FSGNJN_Q 0x26001053 |
| 303 | #define MASK_FSGNJN_Q 0xfe00707f |
| 304 | #define MATCH_FSGNJX_Q 0x26002053 |
| 305 | #define MASK_FSGNJX_Q 0xfe00707f |
| 306 | #define MATCH_FMIN_Q 0x2e000053 |
| 307 | #define MASK_FMIN_Q 0xfe00707f |
| 308 | #define MATCH_FMAX_Q 0x2e001053 |
| 309 | #define MASK_FMAX_Q 0xfe00707f |
| 310 | #define MATCH_FCVT_S_Q 0x40300053 |
| 311 | #define MASK_FCVT_S_Q 0xfff0007f |
| 312 | #define MATCH_FCVT_Q_S 0x46000053 |
| 313 | #define MASK_FCVT_Q_S 0xfff0007f |
| 314 | #define MATCH_FCVT_D_Q 0x42300053 |
| 315 | #define MASK_FCVT_D_Q 0xfff0007f |
| 316 | #define MATCH_FCVT_Q_D 0x46100053 |
| 317 | #define MASK_FCVT_Q_D 0xfff0007f |
| 318 | #define MATCH_FSQRT_Q 0x5e000053 |
| 319 | #define MASK_FSQRT_Q 0xfff0007f |
| 320 | #define MATCH_FLE_S 0xa0000053 |
| 321 | #define MASK_FLE_S 0xfe00707f |
| 322 | #define MATCH_FLT_S 0xa0001053 |
| 323 | #define MASK_FLT_S 0xfe00707f |
| 324 | #define MATCH_FEQ_S 0xa0002053 |
| 325 | #define MASK_FEQ_S 0xfe00707f |
| 326 | #define MATCH_FLE_D 0xa2000053 |
| 327 | #define MASK_FLE_D 0xfe00707f |
| 328 | #define MATCH_FLT_D 0xa2001053 |
| 329 | #define MASK_FLT_D 0xfe00707f |
| 330 | #define MATCH_FEQ_D 0xa2002053 |
| 331 | #define MASK_FEQ_D 0xfe00707f |
| 332 | #define MATCH_FLE_Q 0xa6000053 |
| 333 | #define MASK_FLE_Q 0xfe00707f |
| 334 | #define MATCH_FLT_Q 0xa6001053 |
| 335 | #define MASK_FLT_Q 0xfe00707f |
| 336 | #define MATCH_FEQ_Q 0xa6002053 |
| 337 | #define MASK_FEQ_Q 0xfe00707f |
| 338 | #define MATCH_FCVT_W_S 0xc0000053 |
| 339 | #define MASK_FCVT_W_S 0xfff0007f |
| 340 | #define MATCH_FCVT_WU_S 0xc0100053 |
| 341 | #define MASK_FCVT_WU_S 0xfff0007f |
| 342 | #define MATCH_FCVT_L_S 0xc0200053 |
| 343 | #define MASK_FCVT_L_S 0xfff0007f |
| 344 | #define MATCH_FCVT_LU_S 0xc0300053 |
| 345 | #define MASK_FCVT_LU_S 0xfff0007f |
| 346 | #define MATCH_FMV_X_S 0xe0000053 |
| 347 | #define MASK_FMV_X_S 0xfff0707f |
| 348 | #define MATCH_FCLASS_S 0xe0001053 |
| 349 | #define MASK_FCLASS_S 0xfff0707f |
| 350 | #define MATCH_FCVT_W_D 0xc2000053 |
| 351 | #define MASK_FCVT_W_D 0xfff0007f |
| 352 | #define MATCH_FCVT_WU_D 0xc2100053 |
| 353 | #define MASK_FCVT_WU_D 0xfff0007f |
| 354 | #define MATCH_FCVT_L_D 0xc2200053 |
| 355 | #define MASK_FCVT_L_D 0xfff0007f |
| 356 | #define MATCH_FCVT_LU_D 0xc2300053 |
| 357 | #define MASK_FCVT_LU_D 0xfff0007f |
| 358 | #define MATCH_FMV_X_D 0xe2000053 |
| 359 | #define MASK_FMV_X_D 0xfff0707f |
| 360 | #define MATCH_FCLASS_D 0xe2001053 |
| 361 | #define MASK_FCLASS_D 0xfff0707f |
| 362 | #define MATCH_FCVT_W_Q 0xc6000053 |
| 363 | #define MASK_FCVT_W_Q 0xfff0007f |
| 364 | #define MATCH_FCVT_WU_Q 0xc6100053 |
| 365 | #define MASK_FCVT_WU_Q 0xfff0007f |
| 366 | #define MATCH_FCVT_L_Q 0xc6200053 |
| 367 | #define MASK_FCVT_L_Q 0xfff0007f |
| 368 | #define MATCH_FCVT_LU_Q 0xc6300053 |
| 369 | #define MASK_FCVT_LU_Q 0xfff0007f |
| 370 | #define MATCH_FMV_X_Q 0xe6000053 |
| 371 | #define MASK_FMV_X_Q 0xfff0707f |
| 372 | #define MATCH_FCLASS_Q 0xe6001053 |
| 373 | #define MASK_FCLASS_Q 0xfff0707f |
| 374 | #define MATCH_FCVT_S_W 0xd0000053 |
| 375 | #define MASK_FCVT_S_W 0xfff0007f |
| 376 | #define MATCH_FCVT_S_WU 0xd0100053 |
| 377 | #define MASK_FCVT_S_WU 0xfff0007f |
| 378 | #define MATCH_FCVT_S_L 0xd0200053 |
| 379 | #define MASK_FCVT_S_L 0xfff0007f |
| 380 | #define MATCH_FCVT_S_LU 0xd0300053 |
| 381 | #define MASK_FCVT_S_LU 0xfff0007f |
| 382 | #define MATCH_FMV_S_X 0xf0000053 |
| 383 | #define MASK_FMV_S_X 0xfff0707f |
| 384 | #define MATCH_FCVT_D_W 0xd2000053 |
| 385 | #define MASK_FCVT_D_W 0xfff0007f |
| 386 | #define MATCH_FCVT_D_WU 0xd2100053 |
| 387 | #define MASK_FCVT_D_WU 0xfff0007f |
| 388 | #define MATCH_FCVT_D_L 0xd2200053 |
| 389 | #define MASK_FCVT_D_L 0xfff0007f |
| 390 | #define MATCH_FCVT_D_LU 0xd2300053 |
| 391 | #define MASK_FCVT_D_LU 0xfff0007f |
| 392 | #define MATCH_FMV_D_X 0xf2000053 |
| 393 | #define MASK_FMV_D_X 0xfff0707f |
| 394 | #define MATCH_FCVT_Q_W 0xd6000053 |
| 395 | #define MASK_FCVT_Q_W 0xfff0007f |
| 396 | #define MATCH_FCVT_Q_WU 0xd6100053 |
| 397 | #define MASK_FCVT_Q_WU 0xfff0007f |
| 398 | #define MATCH_FCVT_Q_L 0xd6200053 |
| 399 | #define MASK_FCVT_Q_L 0xfff0007f |
| 400 | #define MATCH_FCVT_Q_LU 0xd6300053 |
| 401 | #define MASK_FCVT_Q_LU 0xfff0007f |
| 402 | #define MATCH_FMV_Q_X 0xf6000053 |
| 403 | #define MASK_FMV_Q_X 0xfff0707f |
| 404 | #define MATCH_FLW 0x2007 |
| 405 | #define MASK_FLW 0x707f |
| 406 | #define MATCH_FLD 0x3007 |
| 407 | #define MASK_FLD 0x707f |
| 408 | #define MATCH_FLQ 0x4007 |
| 409 | #define MASK_FLQ 0x707f |
| 410 | #define MATCH_FSW 0x2027 |
| 411 | #define MASK_FSW 0x707f |
| 412 | #define MATCH_FSD 0x3027 |
| 413 | #define MASK_FSD 0x707f |
| 414 | #define MATCH_FSQ 0x4027 |
| 415 | #define MASK_FSQ 0x707f |
| 416 | #define MATCH_FMADD_S 0x43 |
| 417 | #define MASK_FMADD_S 0x600007f |
| 418 | #define MATCH_FMSUB_S 0x47 |
| 419 | #define MASK_FMSUB_S 0x600007f |
| 420 | #define MATCH_FNMSUB_S 0x4b |
| 421 | #define MASK_FNMSUB_S 0x600007f |
| 422 | #define MATCH_FNMADD_S 0x4f |
| 423 | #define MASK_FNMADD_S 0x600007f |
| 424 | #define MATCH_FMADD_D 0x2000043 |
| 425 | #define MASK_FMADD_D 0x600007f |
| 426 | #define MATCH_FMSUB_D 0x2000047 |
| 427 | #define MASK_FMSUB_D 0x600007f |
| 428 | #define MATCH_FNMSUB_D 0x200004b |
| 429 | #define MASK_FNMSUB_D 0x600007f |
| 430 | #define MATCH_FNMADD_D 0x200004f |
| 431 | #define MASK_FNMADD_D 0x600007f |
| 432 | #define MATCH_FMADD_Q 0x6000043 |
| 433 | #define MASK_FMADD_Q 0x600007f |
| 434 | #define MATCH_FMSUB_Q 0x6000047 |
| 435 | #define MASK_FMSUB_Q 0x600007f |
| 436 | #define MATCH_FNMSUB_Q 0x600004b |
| 437 | #define MASK_FNMSUB_Q 0x600007f |
| 438 | #define MATCH_FNMADD_Q 0x600004f |
| 439 | #define MASK_FNMADD_Q 0x600007f |
| 440 | #define MATCH_C_ADDI4SPN 0x0 |
| 441 | #define MASK_C_ADDI4SPN 0xe003 |
| 442 | #define MATCH_C_FLD 0x2000 |
| 443 | #define MASK_C_FLD 0xe003 |
| 444 | #define MATCH_C_LW 0x4000 |
| 445 | #define MASK_C_LW 0xe003 |
| 446 | #define MATCH_C_FLW 0x6000 |
| 447 | #define MASK_C_FLW 0xe003 |
| 448 | #define MATCH_C_FSD 0xa000 |
| 449 | #define MASK_C_FSD 0xe003 |
| 450 | #define MATCH_C_SW 0xc000 |
| 451 | #define MASK_C_SW 0xe003 |
| 452 | #define MATCH_C_FSW 0xe000 |
| 453 | #define MASK_C_FSW 0xe003 |
| 454 | #define MATCH_C_ADDI 0x1 |
| 455 | #define MASK_C_ADDI 0xe003 |
| 456 | #define MATCH_C_JAL 0x2001 |
| 457 | #define MASK_C_JAL 0xe003 |
| 458 | #define MATCH_C_LI 0x4001 |
| 459 | #define MASK_C_LI 0xe003 |
| 460 | #define MATCH_C_LUI 0x6001 |
| 461 | #define MASK_C_LUI 0xe003 |
| 462 | #define MATCH_C_SRLI 0x8001 |
| 463 | #define MASK_C_SRLI 0xec03 |
| 464 | #define MATCH_C_SRLI64 0x8001 |
| 465 | #define MASK_C_SRLI64 0xfc7f |
| 466 | #define MATCH_C_SRAI 0x8401 |
| 467 | #define MASK_C_SRAI 0xec03 |
| 468 | #define MATCH_C_SRAI64 0x8401 |
| 469 | #define MASK_C_SRAI64 0xfc7f |
| 470 | #define MATCH_C_ANDI 0x8801 |
| 471 | #define MASK_C_ANDI 0xec03 |
| 472 | #define MATCH_C_SUB 0x8c01 |
| 473 | #define MASK_C_SUB 0xfc63 |
| 474 | #define MATCH_C_XOR 0x8c21 |
| 475 | #define MASK_C_XOR 0xfc63 |
| 476 | #define MATCH_C_OR 0x8c41 |
| 477 | #define MASK_C_OR 0xfc63 |
| 478 | #define MATCH_C_AND 0x8c61 |
| 479 | #define MASK_C_AND 0xfc63 |
| 480 | #define MATCH_C_SUBW 0x9c01 |
| 481 | #define MASK_C_SUBW 0xfc63 |
| 482 | #define MATCH_C_ADDW 0x9c21 |
| 483 | #define MASK_C_ADDW 0xfc63 |
| 484 | #define MATCH_C_J 0xa001 |
| 485 | #define MASK_C_J 0xe003 |
| 486 | #define MATCH_C_BEQZ 0xc001 |
| 487 | #define MASK_C_BEQZ 0xe003 |
| 488 | #define MATCH_C_BNEZ 0xe001 |
| 489 | #define MASK_C_BNEZ 0xe003 |
| 490 | #define MATCH_C_SLLI 0x2 |
| 491 | #define MASK_C_SLLI 0xe003 |
| 492 | #define MATCH_C_SLLI64 0x2 |
| 493 | #define MASK_C_SLLI64 0xf07f |
| 494 | #define MATCH_C_FLDSP 0x2002 |
| 495 | #define MASK_C_FLDSP 0xe003 |
| 496 | #define MATCH_C_LWSP 0x4002 |
| 497 | #define MASK_C_LWSP 0xe003 |
| 498 | #define MATCH_C_FLWSP 0x6002 |
| 499 | #define MASK_C_FLWSP 0xe003 |
| 500 | #define MATCH_C_MV 0x8002 |
| 501 | #define MASK_C_MV 0xf003 |
| 502 | #define MATCH_C_ADD 0x9002 |
| 503 | #define MASK_C_ADD 0xf003 |
| 504 | #define MATCH_C_FSDSP 0xa002 |
| 505 | #define MASK_C_FSDSP 0xe003 |
| 506 | #define MATCH_C_SWSP 0xc002 |
| 507 | #define MASK_C_SWSP 0xe003 |
| 508 | #define MATCH_C_FSWSP 0xe002 |
| 509 | #define MASK_C_FSWSP 0xe003 |
| 510 | #define MATCH_C_NOP 0x1 |
| 511 | #define MASK_C_NOP 0xffff |
| 512 | #define MATCH_C_ADDI16SP 0x6101 |
| 513 | #define MASK_C_ADDI16SP 0xef83 |
| 514 | #define MATCH_C_JR 0x8002 |
| 515 | #define MASK_C_JR 0xf07f |
| 516 | #define MATCH_C_JALR 0x9002 |
| 517 | #define MASK_C_JALR 0xf07f |
| 518 | #define MATCH_C_EBREAK 0x9002 |
| 519 | #define MASK_C_EBREAK 0xffff |
| 520 | #define MATCH_C_LD 0x6000 |
| 521 | #define MASK_C_LD 0xe003 |
| 522 | #define MATCH_C_SD 0xe000 |
| 523 | #define MASK_C_SD 0xe003 |
| 524 | #define MATCH_C_ADDIW 0x2001 |
| 525 | #define MASK_C_ADDIW 0xe003 |
| 526 | #define MATCH_C_LDSP 0x6002 |
| 527 | #define MASK_C_LDSP 0xe003 |
| 528 | #define MATCH_C_SDSP 0xe002 |
| 529 | #define MASK_C_SDSP 0xe003 |
| 530 | #define MATCH_CUSTOM0 0xb |
| 531 | #define MASK_CUSTOM0 0x707f |
| 532 | #define MATCH_CUSTOM0_RS1 0x200b |
| 533 | #define MASK_CUSTOM0_RS1 0x707f |
| 534 | #define MATCH_CUSTOM0_RS1_RS2 0x300b |
| 535 | #define MASK_CUSTOM0_RS1_RS2 0x707f |
| 536 | #define MATCH_CUSTOM0_RD 0x400b |
| 537 | #define MASK_CUSTOM0_RD 0x707f |
| 538 | #define MATCH_CUSTOM0_RD_RS1 0x600b |
| 539 | #define MASK_CUSTOM0_RD_RS1 0x707f |
| 540 | #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b |
| 541 | #define MASK_CUSTOM0_RD_RS1_RS2 0x707f |
| 542 | #define MATCH_CUSTOM1 0x2b |
| 543 | #define MASK_CUSTOM1 0x707f |
| 544 | #define MATCH_CUSTOM1_RS1 0x202b |
| 545 | #define MASK_CUSTOM1_RS1 0x707f |
| 546 | #define MATCH_CUSTOM1_RS1_RS2 0x302b |
| 547 | #define MASK_CUSTOM1_RS1_RS2 0x707f |
| 548 | #define MATCH_CUSTOM1_RD 0x402b |
| 549 | #define MASK_CUSTOM1_RD 0x707f |
| 550 | #define MATCH_CUSTOM1_RD_RS1 0x602b |
| 551 | #define MASK_CUSTOM1_RD_RS1 0x707f |
| 552 | #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b |
| 553 | #define MASK_CUSTOM1_RD_RS1_RS2 0x707f |
| 554 | #define MATCH_CUSTOM2 0x5b |
| 555 | #define MASK_CUSTOM2 0x707f |
| 556 | #define MATCH_CUSTOM2_RS1 0x205b |
| 557 | #define MASK_CUSTOM2_RS1 0x707f |
| 558 | #define MATCH_CUSTOM2_RS1_RS2 0x305b |
| 559 | #define MASK_CUSTOM2_RS1_RS2 0x707f |
| 560 | #define MATCH_CUSTOM2_RD 0x405b |
| 561 | #define MASK_CUSTOM2_RD 0x707f |
| 562 | #define MATCH_CUSTOM2_RD_RS1 0x605b |
| 563 | #define MASK_CUSTOM2_RD_RS1 0x707f |
| 564 | #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b |
| 565 | #define MASK_CUSTOM2_RD_RS1_RS2 0x707f |
| 566 | #define MATCH_CUSTOM3 0x7b |
| 567 | #define MASK_CUSTOM3 0x707f |
| 568 | #define MATCH_CUSTOM3_RS1 0x207b |
| 569 | #define MASK_CUSTOM3_RS1 0x707f |
| 570 | #define MATCH_CUSTOM3_RS1_RS2 0x307b |
| 571 | #define MASK_CUSTOM3_RS1_RS2 0x707f |
| 572 | #define MATCH_CUSTOM3_RD 0x407b |
| 573 | #define MASK_CUSTOM3_RD 0x707f |
| 574 | #define MATCH_CUSTOM3_RD_RS1 0x607b |
| 575 | #define MASK_CUSTOM3_RD_RS1 0x707f |
| 576 | #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b |
| 577 | #define MASK_CUSTOM3_RD_RS1_RS2 0x707f |
| 578 | /* Support CSR to priv spec 1.11. */ |
| 579 | #define CSR_USTATUS 0x0 |
| 580 | #define CSR_UIE 0x4 |
| 581 | #define CSR_UTVEC 0x5 |
| 582 | #define CSR_USCRATCH 0x40 |
| 583 | #define CSR_UEPC 0x41 |
| 584 | #define CSR_UCAUSE 0x42 |
| 585 | #define CSR_UTVAL 0x43 |
| 586 | #define CSR_UIP 0x44 |
| 587 | #define CSR_FFLAGS 0x1 |
| 588 | #define CSR_FRM 0x2 |
| 589 | #define CSR_FCSR 0x3 |
| 590 | #define CSR_CYCLE 0xc00 |
| 591 | #define CSR_TIME 0xc01 |
| 592 | #define CSR_INSTRET 0xc02 |
| 593 | #define CSR_HPMCOUNTER3 0xc03 |
| 594 | #define CSR_HPMCOUNTER4 0xc04 |
| 595 | #define CSR_HPMCOUNTER5 0xc05 |
| 596 | #define CSR_HPMCOUNTER6 0xc06 |
| 597 | #define CSR_HPMCOUNTER7 0xc07 |
| 598 | #define CSR_HPMCOUNTER8 0xc08 |
| 599 | #define CSR_HPMCOUNTER9 0xc09 |
| 600 | #define CSR_HPMCOUNTER10 0xc0a |
| 601 | #define CSR_HPMCOUNTER11 0xc0b |
| 602 | #define CSR_HPMCOUNTER12 0xc0c |
| 603 | #define CSR_HPMCOUNTER13 0xc0d |
| 604 | #define CSR_HPMCOUNTER14 0xc0e |
| 605 | #define CSR_HPMCOUNTER15 0xc0f |
| 606 | #define CSR_HPMCOUNTER16 0xc10 |
| 607 | #define CSR_HPMCOUNTER17 0xc11 |
| 608 | #define CSR_HPMCOUNTER18 0xc12 |
| 609 | #define CSR_HPMCOUNTER19 0xc13 |
| 610 | #define CSR_HPMCOUNTER20 0xc14 |
| 611 | #define CSR_HPMCOUNTER21 0xc15 |
| 612 | #define CSR_HPMCOUNTER22 0xc16 |
| 613 | #define CSR_HPMCOUNTER23 0xc17 |
| 614 | #define CSR_HPMCOUNTER24 0xc18 |
| 615 | #define CSR_HPMCOUNTER25 0xc19 |
| 616 | #define CSR_HPMCOUNTER26 0xc1a |
| 617 | #define CSR_HPMCOUNTER27 0xc1b |
| 618 | #define CSR_HPMCOUNTER28 0xc1c |
| 619 | #define CSR_HPMCOUNTER29 0xc1d |
| 620 | #define CSR_HPMCOUNTER30 0xc1e |
| 621 | #define CSR_HPMCOUNTER31 0xc1f |
| 622 | #define CSR_CYCLEH 0xc80 |
| 623 | #define CSR_TIMEH 0xc81 |
| 624 | #define CSR_INSTRETH 0xc82 |
| 625 | #define CSR_HPMCOUNTER3H 0xc83 |
| 626 | #define CSR_HPMCOUNTER4H 0xc84 |
| 627 | #define CSR_HPMCOUNTER5H 0xc85 |
| 628 | #define CSR_HPMCOUNTER6H 0xc86 |
| 629 | #define CSR_HPMCOUNTER7H 0xc87 |
| 630 | #define CSR_HPMCOUNTER8H 0xc88 |
| 631 | #define CSR_HPMCOUNTER9H 0xc89 |
| 632 | #define CSR_HPMCOUNTER10H 0xc8a |
| 633 | #define CSR_HPMCOUNTER11H 0xc8b |
| 634 | #define CSR_HPMCOUNTER12H 0xc8c |
| 635 | #define CSR_HPMCOUNTER13H 0xc8d |
| 636 | #define CSR_HPMCOUNTER14H 0xc8e |
| 637 | #define CSR_HPMCOUNTER15H 0xc8f |
| 638 | #define CSR_HPMCOUNTER16H 0xc90 |
| 639 | #define CSR_HPMCOUNTER17H 0xc91 |
| 640 | #define CSR_HPMCOUNTER18H 0xc92 |
| 641 | #define CSR_HPMCOUNTER19H 0xc93 |
| 642 | #define CSR_HPMCOUNTER20H 0xc94 |
| 643 | #define CSR_HPMCOUNTER21H 0xc95 |
| 644 | #define CSR_HPMCOUNTER22H 0xc96 |
| 645 | #define CSR_HPMCOUNTER23H 0xc97 |
| 646 | #define CSR_HPMCOUNTER24H 0xc98 |
| 647 | #define CSR_HPMCOUNTER25H 0xc99 |
| 648 | #define CSR_HPMCOUNTER26H 0xc9a |
| 649 | #define CSR_HPMCOUNTER27H 0xc9b |
| 650 | #define CSR_HPMCOUNTER28H 0xc9c |
| 651 | #define CSR_HPMCOUNTER29H 0xc9d |
| 652 | #define CSR_HPMCOUNTER30H 0xc9e |
| 653 | #define CSR_HPMCOUNTER31H 0xc9f |
| 654 | #define CSR_SSTATUS 0x100 |
| 655 | #define CSR_SEDELEG 0x102 |
| 656 | #define CSR_SIDELEG 0x103 |
| 657 | #define CSR_SIE 0x104 |
| 658 | #define CSR_STVEC 0x105 |
| 659 | #define CSR_SCOUNTEREN 0x106 |
| 660 | #define CSR_SSCRATCH 0x140 |
| 661 | #define CSR_SEPC 0x141 |
| 662 | #define CSR_SCAUSE 0x142 |
| 663 | #define CSR_STVAL 0x143 |
| 664 | #define CSR_SIP 0x144 |
| 665 | #define CSR_SATP 0x180 |
| 666 | #define CSR_MVENDORID 0xf11 |
| 667 | #define CSR_MARCHID 0xf12 |
| 668 | #define CSR_MIMPID 0xf13 |
| 669 | #define CSR_MHARTID 0xf14 |
| 670 | #define CSR_MSTATUS 0x300 |
| 671 | #define CSR_MISA 0x301 |
| 672 | #define CSR_MEDELEG 0x302 |
| 673 | #define CSR_MIDELEG 0x303 |
| 674 | #define CSR_MIE 0x304 |
| 675 | #define CSR_MTVEC 0x305 |
| 676 | #define CSR_MCOUNTEREN 0x306 |
| 677 | #define CSR_MSCRATCH 0x340 |
| 678 | #define CSR_MEPC 0x341 |
| 679 | #define CSR_MCAUSE 0x342 |
| 680 | #define CSR_MTVAL 0x343 |
| 681 | #define CSR_MIP 0x344 |
| 682 | #define CSR_PMPCFG0 0x3a0 |
| 683 | #define CSR_PMPCFG1 0x3a1 |
| 684 | #define CSR_PMPCFG2 0x3a2 |
| 685 | #define CSR_PMPCFG3 0x3a3 |
| 686 | #define CSR_PMPADDR0 0x3b0 |
| 687 | #define CSR_PMPADDR1 0x3b1 |
| 688 | #define CSR_PMPADDR2 0x3b2 |
| 689 | #define CSR_PMPADDR3 0x3b3 |
| 690 | #define CSR_PMPADDR4 0x3b4 |
| 691 | #define CSR_PMPADDR5 0x3b5 |
| 692 | #define CSR_PMPADDR6 0x3b6 |
| 693 | #define CSR_PMPADDR7 0x3b7 |
| 694 | #define CSR_PMPADDR8 0x3b8 |
| 695 | #define CSR_PMPADDR9 0x3b9 |
| 696 | #define CSR_PMPADDR10 0x3ba |
| 697 | #define CSR_PMPADDR11 0x3bb |
| 698 | #define CSR_PMPADDR12 0x3bc |
| 699 | #define CSR_PMPADDR13 0x3bd |
| 700 | #define CSR_PMPADDR14 0x3be |
| 701 | #define CSR_PMPADDR15 0x3bf |
| 702 | #define CSR_MCYCLE 0xb00 |
| 703 | #define CSR_MINSTRET 0xb02 |
| 704 | #define CSR_MHPMCOUNTER3 0xb03 |
| 705 | #define CSR_MHPMCOUNTER4 0xb04 |
| 706 | #define CSR_MHPMCOUNTER5 0xb05 |
| 707 | #define CSR_MHPMCOUNTER6 0xb06 |
| 708 | #define CSR_MHPMCOUNTER7 0xb07 |
| 709 | #define CSR_MHPMCOUNTER8 0xb08 |
| 710 | #define CSR_MHPMCOUNTER9 0xb09 |
| 711 | #define CSR_MHPMCOUNTER10 0xb0a |
| 712 | #define CSR_MHPMCOUNTER11 0xb0b |
| 713 | #define CSR_MHPMCOUNTER12 0xb0c |
| 714 | #define CSR_MHPMCOUNTER13 0xb0d |
| 715 | #define CSR_MHPMCOUNTER14 0xb0e |
| 716 | #define CSR_MHPMCOUNTER15 0xb0f |
| 717 | #define CSR_MHPMCOUNTER16 0xb10 |
| 718 | #define CSR_MHPMCOUNTER17 0xb11 |
| 719 | #define CSR_MHPMCOUNTER18 0xb12 |
| 720 | #define CSR_MHPMCOUNTER19 0xb13 |
| 721 | #define CSR_MHPMCOUNTER20 0xb14 |
| 722 | #define CSR_MHPMCOUNTER21 0xb15 |
| 723 | #define CSR_MHPMCOUNTER22 0xb16 |
| 724 | #define CSR_MHPMCOUNTER23 0xb17 |
| 725 | #define CSR_MHPMCOUNTER24 0xb18 |
| 726 | #define CSR_MHPMCOUNTER25 0xb19 |
| 727 | #define CSR_MHPMCOUNTER26 0xb1a |
| 728 | #define CSR_MHPMCOUNTER27 0xb1b |
| 729 | #define CSR_MHPMCOUNTER28 0xb1c |
| 730 | #define CSR_MHPMCOUNTER29 0xb1d |
| 731 | #define CSR_MHPMCOUNTER30 0xb1e |
| 732 | #define CSR_MHPMCOUNTER31 0xb1f |
| 733 | #define CSR_MCYCLEH 0xb80 |
| 734 | #define CSR_MINSTRETH 0xb82 |
| 735 | #define CSR_MHPMCOUNTER3H 0xb83 |
| 736 | #define CSR_MHPMCOUNTER4H 0xb84 |
| 737 | #define CSR_MHPMCOUNTER5H 0xb85 |
| 738 | #define CSR_MHPMCOUNTER6H 0xb86 |
| 739 | #define CSR_MHPMCOUNTER7H 0xb87 |
| 740 | #define CSR_MHPMCOUNTER8H 0xb88 |
| 741 | #define CSR_MHPMCOUNTER9H 0xb89 |
| 742 | #define CSR_MHPMCOUNTER10H 0xb8a |
| 743 | #define CSR_MHPMCOUNTER11H 0xb8b |
| 744 | #define CSR_MHPMCOUNTER12H 0xb8c |
| 745 | #define CSR_MHPMCOUNTER13H 0xb8d |
| 746 | #define CSR_MHPMCOUNTER14H 0xb8e |
| 747 | #define CSR_MHPMCOUNTER15H 0xb8f |
| 748 | #define CSR_MHPMCOUNTER16H 0xb90 |
| 749 | #define CSR_MHPMCOUNTER17H 0xb91 |
| 750 | #define CSR_MHPMCOUNTER18H 0xb92 |
| 751 | #define CSR_MHPMCOUNTER19H 0xb93 |
| 752 | #define CSR_MHPMCOUNTER20H 0xb94 |
| 753 | #define CSR_MHPMCOUNTER21H 0xb95 |
| 754 | #define CSR_MHPMCOUNTER22H 0xb96 |
| 755 | #define CSR_MHPMCOUNTER23H 0xb97 |
| 756 | #define CSR_MHPMCOUNTER24H 0xb98 |
| 757 | #define CSR_MHPMCOUNTER25H 0xb99 |
| 758 | #define CSR_MHPMCOUNTER26H 0xb9a |
| 759 | #define CSR_MHPMCOUNTER27H 0xb9b |
| 760 | #define CSR_MHPMCOUNTER28H 0xb9c |
| 761 | #define CSR_MHPMCOUNTER29H 0xb9d |
| 762 | #define CSR_MHPMCOUNTER30H 0xb9e |
| 763 | #define CSR_MHPMCOUNTER31H 0xb9f |
| 764 | #define CSR_MCOUNTINHIBIT 0x320 |
| 765 | #define CSR_MHPMEVENT3 0x323 |
| 766 | #define CSR_MHPMEVENT4 0x324 |
| 767 | #define CSR_MHPMEVENT5 0x325 |
| 768 | #define CSR_MHPMEVENT6 0x326 |
| 769 | #define CSR_MHPMEVENT7 0x327 |
| 770 | #define CSR_MHPMEVENT8 0x328 |
| 771 | #define CSR_MHPMEVENT9 0x329 |
| 772 | #define CSR_MHPMEVENT10 0x32a |
| 773 | #define CSR_MHPMEVENT11 0x32b |
| 774 | #define CSR_MHPMEVENT12 0x32c |
| 775 | #define CSR_MHPMEVENT13 0x32d |
| 776 | #define CSR_MHPMEVENT14 0x32e |
| 777 | #define CSR_MHPMEVENT15 0x32f |
| 778 | #define CSR_MHPMEVENT16 0x330 |
| 779 | #define CSR_MHPMEVENT17 0x331 |
| 780 | #define CSR_MHPMEVENT18 0x332 |
| 781 | #define CSR_MHPMEVENT19 0x333 |
| 782 | #define CSR_MHPMEVENT20 0x334 |
| 783 | #define CSR_MHPMEVENT21 0x335 |
| 784 | #define CSR_MHPMEVENT22 0x336 |
| 785 | #define CSR_MHPMEVENT23 0x337 |
| 786 | #define CSR_MHPMEVENT24 0x338 |
| 787 | #define CSR_MHPMEVENT25 0x339 |
| 788 | #define CSR_MHPMEVENT26 0x33a |
| 789 | #define CSR_MHPMEVENT27 0x33b |
| 790 | #define CSR_MHPMEVENT28 0x33c |
| 791 | #define CSR_MHPMEVENT29 0x33d |
| 792 | #define CSR_MHPMEVENT30 0x33e |
| 793 | #define CSR_MHPMEVENT31 0x33f |
| 794 | #define CSR_TSELECT 0x7a0 |
| 795 | #define CSR_TDATA1 0x7a1 |
| 796 | #define CSR_TDATA2 0x7a2 |
| 797 | #define CSR_TDATA3 0x7a3 |
| 798 | #define CSR_DCSR 0x7b0 |
| 799 | #define CSR_DPC 0x7b1 |
| 800 | #define CSR_DSCRATCH0 0x7b2 |
| 801 | #define CSR_DSCRATCH1 0x7b3 |
| 802 | #define CSR_HSTATUS 0x200 |
| 803 | #define CSR_HEDELEG 0x202 |
| 804 | #define CSR_HIDELEG 0x203 |
| 805 | #define CSR_HIE 0x204 |
| 806 | #define CSR_HTVEC 0x205 |
| 807 | #define CSR_HSCRATCH 0x240 |
| 808 | #define CSR_HEPC 0x241 |
| 809 | #define CSR_HCAUSE 0x242 |
| 810 | #define CSR_HBADADDR 0x243 |
| 811 | #define CSR_HIP 0x244 |
| 812 | #define CSR_MBASE 0x380 |
| 813 | #define CSR_MBOUND 0x381 |
| 814 | #define CSR_MIBASE 0x382 |
| 815 | #define CSR_MIBOUND 0x383 |
| 816 | #define CSR_MDBASE 0x384 |
| 817 | #define CSR_MDBOUND 0x385 |
| 818 | #define CSR_MSCOUNTEREN 0x321 |
| 819 | #define CSR_MHCOUNTEREN 0x322 |
| 820 | |
| 821 | #define CAUSE_MISALIGNED_FETCH 0x0 |
| 822 | #define CAUSE_FAULT_FETCH 0x1 |
| 823 | #define CAUSE_ILLEGAL_INSTRUCTION 0x2 |
| 824 | #define CAUSE_BREAKPOINT 0x3 |
| 825 | #define CAUSE_MISALIGNED_LOAD 0x4 |
| 826 | #define CAUSE_FAULT_LOAD 0x5 |
| 827 | #define CAUSE_MISALIGNED_STORE 0x6 |
| 828 | #define CAUSE_FAULT_STORE 0x7 |
| 829 | #define CAUSE_USER_ECALL 0x8 |
| 830 | #define CAUSE_SUPERVISOR_ECALL 0x9 |
| 831 | #define CAUSE_HYPERVISOR_ECALL 0xa |
| 832 | #define CAUSE_MACHINE_ECALL 0xb |
| 833 | #endif |
| 834 | #ifdef DECLARE_INSN |
| 835 | DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) |
| 836 | DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) |
| 837 | DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) |
| 838 | DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS) |
| 839 | DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS) |
| 840 | DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI) |
| 841 | DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM) |
| 842 | DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM) |
| 843 | DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI) |
| 844 | DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR) |
| 845 | DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR) |
| 846 | DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE) |
| 847 | DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME) |
| 848 | DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET) |
| 849 | DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH) |
| 850 | DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH) |
| 851 | DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH) |
| 852 | DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) |
| 853 | DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK) |
| 854 | DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) |
| 855 | DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) |
| 856 | DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) |
| 857 | DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) |
| 858 | DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) |
| 859 | DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) |
| 860 | DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) |
| 861 | DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) |
| 862 | DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) |
| 863 | DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) |
| 864 | DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) |
| 865 | DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) |
| 866 | DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) |
| 867 | DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) |
| 868 | DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) |
| 869 | DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) |
| 870 | DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) |
| 871 | DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) |
| 872 | DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) |
| 873 | DECLARE_INSN(add, MATCH_ADD, MASK_ADD) |
| 874 | DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) |
| 875 | DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) |
| 876 | DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) |
| 877 | DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) |
| 878 | DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) |
| 879 | DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) |
| 880 | DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) |
| 881 | DECLARE_INSN(or, MATCH_OR, MASK_OR) |
| 882 | DECLARE_INSN(and, MATCH_AND, MASK_AND) |
| 883 | DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) |
| 884 | DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) |
| 885 | DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) |
| 886 | DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) |
| 887 | DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) |
| 888 | DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) |
| 889 | DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) |
| 890 | DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) |
| 891 | DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) |
| 892 | DECLARE_INSN(lb, MATCH_LB, MASK_LB) |
| 893 | DECLARE_INSN(lh, MATCH_LH, MASK_LH) |
| 894 | DECLARE_INSN(lw, MATCH_LW, MASK_LW) |
| 895 | DECLARE_INSN(ld, MATCH_LD, MASK_LD) |
| 896 | DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) |
| 897 | DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) |
| 898 | DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) |
| 899 | DECLARE_INSN(sb, MATCH_SB, MASK_SB) |
| 900 | DECLARE_INSN(sh, MATCH_SH, MASK_SH) |
| 901 | DECLARE_INSN(sw, MATCH_SW, MASK_SW) |
| 902 | DECLARE_INSN(sd, MATCH_SD, MASK_SD) |
| 903 | DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) |
| 904 | DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) |
| 905 | DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) |
| 906 | DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) |
| 907 | DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) |
| 908 | DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) |
| 909 | DECLARE_INSN(div, MATCH_DIV, MASK_DIV) |
| 910 | DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) |
| 911 | DECLARE_INSN(rem, MATCH_REM, MASK_REM) |
| 912 | DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) |
| 913 | DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) |
| 914 | DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) |
| 915 | DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) |
| 916 | DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) |
| 917 | DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) |
| 918 | DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) |
| 919 | DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) |
| 920 | DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) |
| 921 | DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) |
| 922 | DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) |
| 923 | DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) |
| 924 | DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) |
| 925 | DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) |
| 926 | DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) |
| 927 | DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) |
| 928 | DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) |
| 929 | DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) |
| 930 | DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) |
| 931 | DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) |
| 932 | DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) |
| 933 | DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) |
| 934 | DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) |
| 935 | DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) |
| 936 | DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) |
| 937 | DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) |
| 938 | DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) |
| 939 | DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) |
| 940 | DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) |
| 941 | DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) |
| 942 | DECLARE_INSN(uret, MATCH_URET, MASK_URET) |
| 943 | DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) |
| 944 | DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) |
| 945 | DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) |
| 946 | DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) |
| 947 | DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) |
| 948 | DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) |
| 949 | DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) |
| 950 | DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) |
| 951 | DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) |
| 952 | DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) |
| 953 | DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) |
| 954 | DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) |
| 955 | DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) |
| 956 | DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) |
| 957 | DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) |
| 958 | DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) |
| 959 | DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) |
| 960 | DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) |
| 961 | DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) |
| 962 | DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) |
| 963 | DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) |
| 964 | DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) |
| 965 | DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) |
| 966 | DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) |
| 967 | DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) |
| 968 | DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) |
| 969 | DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) |
| 970 | DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) |
| 971 | DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) |
| 972 | DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) |
| 973 | DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) |
| 974 | DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) |
| 975 | DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) |
| 976 | DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) |
| 977 | DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) |
| 978 | DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) |
| 979 | DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) |
| 980 | DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) |
| 981 | DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) |
| 982 | DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) |
| 983 | DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) |
| 984 | DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) |
| 985 | DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) |
| 986 | DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) |
| 987 | DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) |
| 988 | DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) |
| 989 | DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) |
| 990 | DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) |
| 991 | DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) |
| 992 | DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) |
| 993 | DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) |
| 994 | DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) |
| 995 | DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) |
| 996 | DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) |
| 997 | DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) |
| 998 | DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) |
| 999 | DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) |
| 1000 | DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) |
| 1001 | DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) |
| 1002 | DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) |
| 1003 | DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) |
| 1004 | DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) |
| 1005 | DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) |
| 1006 | DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) |
| 1007 | DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) |
| 1008 | DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) |
| 1009 | DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) |
| 1010 | DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) |
| 1011 | DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) |
| 1012 | DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) |
| 1013 | DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) |
| 1014 | DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) |
| 1015 | DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) |
| 1016 | DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) |
| 1017 | DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) |
| 1018 | DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) |
| 1019 | DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) |
| 1020 | DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) |
| 1021 | DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) |
| 1022 | DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) |
| 1023 | DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) |
| 1024 | DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) |
| 1025 | DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) |
| 1026 | DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) |
| 1027 | DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) |
| 1028 | DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) |
| 1029 | DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) |
| 1030 | DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) |
| 1031 | DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) |
| 1032 | DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) |
| 1033 | DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) |
| 1034 | DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) |
| 1035 | DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) |
| 1036 | DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) |
| 1037 | DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) |
| 1038 | DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) |
| 1039 | DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) |
| 1040 | DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) |
| 1041 | DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) |
| 1042 | DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) |
| 1043 | DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) |
| 1044 | DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) |
| 1045 | DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) |
| 1046 | DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) |
| 1047 | DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) |
| 1048 | DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) |
| 1049 | DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) |
| 1050 | DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) |
| 1051 | DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) |
| 1052 | DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) |
| 1053 | DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) |
| 1054 | DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) |
| 1055 | DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) |
| 1056 | DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) |
| 1057 | DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) |
| 1058 | DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) |
| 1059 | DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) |
| 1060 | DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) |
| 1061 | DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) |
| 1062 | DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) |
| 1063 | DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) |
| 1064 | DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) |
| 1065 | DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) |
| 1066 | DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) |
| 1067 | DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) |
| 1068 | DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) |
| 1069 | DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) |
| 1070 | DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) |
| 1071 | DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) |
| 1072 | DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) |
| 1073 | DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) |
| 1074 | DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) |
| 1075 | DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) |
| 1076 | DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) |
| 1077 | DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) |
| 1078 | DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) |
| 1079 | DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) |
| 1080 | DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) |
| 1081 | DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) |
| 1082 | DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) |
| 1083 | DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) |
| 1084 | DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) |
| 1085 | DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) |
| 1086 | DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) |
| 1087 | DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) |
| 1088 | DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) |
| 1089 | DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) |
| 1090 | DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) |
| 1091 | DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) |
| 1092 | DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) |
| 1093 | DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) |
| 1094 | DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) |
| 1095 | DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) |
| 1096 | DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) |
| 1097 | DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) |
| 1098 | DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) |
| 1099 | DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) |
| 1100 | DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) |
| 1101 | DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) |
| 1102 | DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) |
| 1103 | DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) |
| 1104 | DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) |
| 1105 | DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) |
| 1106 | DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) |
| 1107 | DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) |
| 1108 | DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) |
| 1109 | DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) |
| 1110 | DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) |
| 1111 | DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) |
| 1112 | DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) |
| 1113 | DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) |
| 1114 | DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) |
| 1115 | DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) |
| 1116 | DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) |
| 1117 | DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) |
| 1118 | #endif |
| 1119 | #ifdef DECLARE_CSR |
| 1120 | DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1121 | DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1122 | DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1123 | DECLARE_CSR(uscratch, CSR_USCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1124 | DECLARE_CSR(uepc, CSR_UEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1125 | DECLARE_CSR(ucause, CSR_UCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1126 | DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1127 | DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1128 | DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1129 | DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1130 | DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1131 | DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1132 | DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1133 | DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1134 | DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1135 | DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1136 | DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1137 | DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1138 | DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1139 | DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1140 | DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1141 | DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1142 | DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1143 | DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1144 | DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1145 | DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1146 | DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1147 | DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1148 | DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1149 | DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1150 | DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1151 | DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1152 | DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1153 | DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1154 | DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1155 | DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1156 | DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1157 | DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1158 | DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1159 | DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1160 | DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1161 | DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1162 | DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1163 | DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1164 | DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1165 | DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1166 | DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1167 | DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1168 | DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1169 | DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1170 | DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1171 | DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1172 | DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1173 | DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1174 | DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1175 | DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1176 | DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1177 | DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1178 | DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1179 | DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1180 | DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1181 | DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1182 | DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1183 | DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1184 | DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1185 | DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1186 | DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1187 | DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1188 | DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1189 | DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1190 | DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1191 | DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1192 | DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1193 | DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1194 | DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1195 | DECLARE_CSR(sstatus, CSR_SSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1196 | DECLARE_CSR(sedeleg, CSR_SEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1197 | DECLARE_CSR(sideleg, CSR_SIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1198 | DECLARE_CSR(sie, CSR_SIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1199 | DECLARE_CSR(stvec, CSR_STVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1200 | DECLARE_CSR(scounteren, CSR_SCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1201 | DECLARE_CSR(sscratch, CSR_SSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1202 | DECLARE_CSR(sepc, CSR_SEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1203 | DECLARE_CSR(scause, CSR_SCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1204 | DECLARE_CSR(stval, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1205 | DECLARE_CSR(sip, CSR_SIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1206 | DECLARE_CSR(satp, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1207 | DECLARE_CSR(mvendorid, CSR_MVENDORID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1208 | DECLARE_CSR(marchid, CSR_MARCHID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1209 | DECLARE_CSR(mimpid, CSR_MIMPID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1210 | DECLARE_CSR(mhartid, CSR_MHARTID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1211 | DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1212 | DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) |
| 1213 | DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1214 | DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1215 | DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1216 | DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1217 | DECLARE_CSR(mcounteren, CSR_MCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1218 | DECLARE_CSR(mscratch, CSR_MSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1219 | DECLARE_CSR(mepc, CSR_MEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1220 | DECLARE_CSR(mcause, CSR_MCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1221 | DECLARE_CSR(mtval, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1222 | DECLARE_CSR(mip, CSR_MIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1223 | DECLARE_CSR(pmpcfg0, CSR_PMPCFG0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1224 | DECLARE_CSR(pmpcfg1, CSR_PMPCFG1, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1225 | DECLARE_CSR(pmpcfg2, CSR_PMPCFG2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1226 | DECLARE_CSR(pmpcfg3, CSR_PMPCFG3, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1227 | DECLARE_CSR(pmpaddr0, CSR_PMPADDR0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1228 | DECLARE_CSR(pmpaddr1, CSR_PMPADDR1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1229 | DECLARE_CSR(pmpaddr2, CSR_PMPADDR2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1230 | DECLARE_CSR(pmpaddr3, CSR_PMPADDR3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1231 | DECLARE_CSR(pmpaddr4, CSR_PMPADDR4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1232 | DECLARE_CSR(pmpaddr5, CSR_PMPADDR5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1233 | DECLARE_CSR(pmpaddr6, CSR_PMPADDR6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1234 | DECLARE_CSR(pmpaddr7, CSR_PMPADDR7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1235 | DECLARE_CSR(pmpaddr8, CSR_PMPADDR8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1236 | DECLARE_CSR(pmpaddr9, CSR_PMPADDR9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1237 | DECLARE_CSR(pmpaddr10, CSR_PMPADDR10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1238 | DECLARE_CSR(pmpaddr11, CSR_PMPADDR11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1239 | DECLARE_CSR(pmpaddr12, CSR_PMPADDR12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1240 | DECLARE_CSR(pmpaddr13, CSR_PMPADDR13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1241 | DECLARE_CSR(pmpaddr14, CSR_PMPADDR14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1242 | DECLARE_CSR(pmpaddr15, CSR_PMPADDR15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) |
| 1243 | DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1244 | DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1245 | DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1246 | DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1247 | DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1248 | DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1249 | DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1250 | DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1251 | DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1252 | DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1253 | DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1254 | DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1255 | DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1256 | DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1257 | DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1258 | DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1259 | DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1260 | DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1261 | DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1262 | DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1263 | DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1264 | DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1265 | DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1266 | DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1267 | DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1268 | DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1269 | DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1270 | DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1271 | DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1272 | DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1273 | DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1274 | DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1275 | DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1276 | DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1277 | DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1278 | DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1279 | DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1280 | DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1281 | DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1282 | DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1283 | DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1284 | DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1285 | DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1286 | DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1287 | DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1288 | DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1289 | DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1290 | DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1291 | DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1292 | DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1293 | DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1294 | DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1295 | DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1296 | DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1297 | DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1298 | DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1299 | DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1300 | DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1301 | DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1302 | DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1303 | DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1304 | DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1305 | DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT) |
| 1306 | DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1307 | DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1308 | DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1309 | DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1310 | DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1311 | DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1312 | DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1313 | DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1314 | DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1315 | DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1316 | DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1317 | DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1318 | DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1319 | DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1320 | DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1321 | DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1322 | DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1323 | DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1324 | DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1325 | DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1326 | DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1327 | DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1328 | DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1329 | DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1330 | DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1331 | DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1332 | DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1333 | DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1334 | DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1335 | DECLARE_CSR(tselect, CSR_TSELECT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1336 | DECLARE_CSR(tdata1, CSR_TDATA1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1337 | DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1338 | DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1339 | DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1340 | DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT) |
| 1341 | DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT) |
| 1342 | DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT) |
| 1343 | DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1344 | DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1345 | DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1346 | DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1347 | DECLARE_CSR(htvec, CSR_HTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1348 | DECLARE_CSR(hscratch, CSR_HSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1349 | DECLARE_CSR(hepc, CSR_HEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1350 | DECLARE_CSR(hcause, CSR_HCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1351 | DECLARE_CSR(hbadaddr, CSR_HBADADDR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1352 | DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1353 | DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1354 | DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1355 | DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1356 | DECLARE_CSR(mibound, CSR_MIBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1357 | DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1358 | DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1359 | DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1360 | DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1361 | #endif |
| 1362 | #ifdef DECLARE_CSR_ALIAS |
| 1363 | DECLARE_CSR_ALIAS(misa, 0xf10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P9P1) |
| 1364 | DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1365 | DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1366 | DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1367 | DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1368 | DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) |
| 1369 | DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P11) |
| 1370 | #endif |
| 1371 | #ifdef DECLARE_CAUSE |
| 1372 | DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) |
| 1373 | DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) |
| 1374 | DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) |
| 1375 | DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) |
| 1376 | DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) |
| 1377 | DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) |
| 1378 | DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) |
| 1379 | DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) |
| 1380 | DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) |
| 1381 | DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) |
| 1382 | DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) |
| 1383 | DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) |
| 1384 | #endif |