| 1 | /* Definitions for opcode table for the sparc. |
| 2 | Copyright 1989, 1991, 1992, 1995 Free Software Foundation, Inc. |
| 3 | |
| 4 | This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and |
| 5 | the GNU Binutils. |
| 6 | |
| 7 | GAS/GDB is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2, or (at your option) |
| 10 | any later version. |
| 11 | |
| 12 | GAS/GDB is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with GAS or GDB; see the file COPYING. If not, write to |
| 19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
| 20 | Boston, MA 02111-1307, USA. */ |
| 21 | |
| 22 | /* The SPARC opcode table (and other related data) is defined in |
| 23 | the opcodes library in sparc-opc.c. If you change anything here, make |
| 24 | sure you fix up that file, and vice versa. */ |
| 25 | |
| 26 | /* FIXME-someday: perhaps the ,a's and such should be embedded in the |
| 27 | instruction's name rather than the args. This would make gas faster, pinsn |
| 28 | slower, but would mess up some macros a bit. xoxorich. */ |
| 29 | |
| 30 | #define sparc_architecture bfd_sparc_architecture |
| 31 | #define architecture_pname bfd_sparc_architecture_pname |
| 32 | #define sparc_opcode bfd_sparc_opcode |
| 33 | #define sparc_opcodes bfd_sparc_opcodes |
| 34 | |
| 35 | /* |
| 36 | * Structure of an opcode table entry. |
| 37 | * This enumerator must parallel the architecture_pname array |
| 38 | * in bfd/opc-sparc.c. |
| 39 | */ |
| 40 | enum sparc_architecture { |
| 41 | v6 = 0, |
| 42 | v7, |
| 43 | v8, |
| 44 | sparclite, |
| 45 | v9 |
| 46 | }; |
| 47 | |
| 48 | extern const char *architecture_pname[]; |
| 49 | |
| 50 | /* Sparclite and v9 are both supersets of v8; we can't bump between them. */ |
| 51 | |
| 52 | #define ARCHITECTURES_CONFLICT_P(ARCH1, ARCH2) ((ARCH1) == sparclite && (ARCH2) == v9) |
| 53 | |
| 54 | struct sparc_opcode { |
| 55 | const char *name; |
| 56 | unsigned long match; /* Bits that must be set. */ |
| 57 | unsigned long lose; /* Bits that must not be set. */ |
| 58 | const char *args; |
| 59 | /* This was called "delayed" in versions before the flags. */ |
| 60 | char flags; |
| 61 | enum sparc_architecture architecture; |
| 62 | }; |
| 63 | |
| 64 | #define F_DELAYED 1 /* Delayed branch */ |
| 65 | #define F_ALIAS 2 /* Alias for a "real" instruction */ |
| 66 | #define F_UNBR 4 /* Unconditional branch */ |
| 67 | #define F_CONDBR 8 /* Conditional branch */ |
| 68 | #define F_JSR 16 /* Subroutine call */ |
| 69 | /* ??? One can argue this shouldn't be here and the architecture |
| 70 | field should be used instead. */ |
| 71 | #define F_NOTV9 32 /* Doesn't exist in v9 */ |
| 72 | /* FIXME: Add F_ANACHRONISTIC flag for v9. */ |
| 73 | |
| 74 | /* |
| 75 | |
| 76 | All sparc opcodes are 32 bits, except for the `set' instruction (really a |
| 77 | macro), which is 64 bits. It is handled as a special case. |
| 78 | |
| 79 | The match component is a mask saying which bits must match a particular |
| 80 | opcode in order for an instruction to be an instance of that opcode. |
| 81 | |
| 82 | The args component is a string containing one character for each operand of the |
| 83 | instruction. |
| 84 | |
| 85 | Kinds of operands: |
| 86 | # Number used by optimizer. It is ignored. |
| 87 | 1 rs1 register. |
| 88 | 2 rs2 register. |
| 89 | d rd register. |
| 90 | e frs1 floating point register. |
| 91 | v frs1 floating point register (double/even). |
| 92 | V frs1 floating point register (quad/multiple of 4). |
| 93 | f frs2 floating point register. |
| 94 | B frs2 floating point register (double/even). |
| 95 | R frs2 floating point register (quad/multiple of 4). |
| 96 | g frsd floating point register. |
| 97 | H frsd floating point register (double/even). |
| 98 | J frsd floating point register (quad/multiple of 4). |
| 99 | b crs1 coprocessor register |
| 100 | c crs2 coprocessor register |
| 101 | D crsd coprocessor register |
| 102 | m alternate space register (asr) in rd |
| 103 | M alternate space register (asr) in rs1 |
| 104 | h 22 high bits. |
| 105 | K MEMBAR mask (7 bits). (v9) |
| 106 | j 10 bit Immediate. (v9) |
| 107 | I 11 bit Immediate. (v9) |
| 108 | i 13 bit Immediate. |
| 109 | n 22 bit immediate. |
| 110 | k 2+14 bit PC relative immediate. (v9) |
| 111 | G 19 bit PC relative immediate. (v9) |
| 112 | l 22 bit PC relative immediate. |
| 113 | L 30 bit PC relative immediate. |
| 114 | a Annul. The annul bit is set. |
| 115 | A Alternate address space. Stored as 8 bits. |
| 116 | C Coprocessor state register. |
| 117 | F floating point state register. |
| 118 | p Processor state register. |
| 119 | N Branch predict clear ",pn" (v9) |
| 120 | T Branch predict set ",pt" (v9) |
| 121 | z %icc. (v9) |
| 122 | Z %xcc. (v9) |
| 123 | q Floating point queue. |
| 124 | r Single register that is both rs1 and rsd. |
| 125 | Q Coprocessor queue. |
| 126 | S Special case. |
| 127 | t Trap base register. |
| 128 | w Window invalid mask register. |
| 129 | y Y register. |
| 130 | E %ccr. (v9) |
| 131 | s %fprs. (v9) |
| 132 | P %pc. (v9) |
| 133 | W %tick. (v9) |
| 134 | o %asi. (v9) |
| 135 | 6 %fcc0. (v9) |
| 136 | 7 %fcc1. (v9) |
| 137 | 8 %fcc2. (v9) |
| 138 | 9 %fcc3. (v9) |
| 139 | ! Privileged Register in rd (v9) |
| 140 | ? Privileged Register in rs1 (v9) |
| 141 | * Prefetch function constant. (v9) |
| 142 | x OPF field (v9 impdep). |
| 143 | |
| 144 | The following chars are unused: (note: ,[] are used as punctuation) |
| 145 | [uOUXY3450] |
| 146 | |
| 147 | */ |
| 148 | |
| 149 | #define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */ |
| 150 | #define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */ |
| 151 | #define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */ |
| 152 | #define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */ |
| 153 | #define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */ |
| 154 | #define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */ |
| 155 | #define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */ |
| 156 | #define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */ |
| 157 | #define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */ |
| 158 | #define F1(x) (OP(x)) |
| 159 | #define DISP30(x) ((x)&0x3fffffff) |
| 160 | #define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */ |
| 161 | #define RS2(x) ((x)&0x1f) /* rs2 field */ |
| 162 | #define SIMM13(x) ((x)&0x1fff) /* simm13 field */ |
| 163 | #define RD(x) (((x)&0x1f) << 25) /* destination register field */ |
| 164 | #define RS1(x) (((x)&0x1f) << 14) /* rs1 field */ |
| 165 | #define ASI_RS2(x) (SIMM13(x)) |
| 166 | |
| 167 | #define ANNUL (1<<29) |
| 168 | #define BPRED (1<<19) /* v9 */ |
| 169 | #define IMMED F3I(1) |
| 170 | #define RD_G0 RD(~0) |
| 171 | #define RS1_G0 RS1(~0) |
| 172 | #define RS2_G0 RS2(~0) |
| 173 | |
| 174 | extern struct sparc_opcode sparc_opcodes[]; |
| 175 | extern const int bfd_sparc_num_opcodes; |
| 176 | |
| 177 | #define NUMOPCODES bfd_sparc_num_opcodes |
| 178 | |
| 179 | int sparc_encode_asi (); |
| 180 | char *sparc_decode_asi (); |
| 181 | |
| 182 | /* |
| 183 | * Local Variables: |
| 184 | * fill-column: 131 |
| 185 | * comment-column: 0 |
| 186 | * End: |
| 187 | */ |
| 188 | |
| 189 | /* end of sparc.h */ |