| | 1 | /* Xtensa configuration settings. |
| | 2 | Copyright (C) 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
| | 3 | Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. |
| | 4 | |
| | 5 | This program is free software; you can redistribute it and/or modify |
| | 6 | it under the terms of the GNU General Public License as published by |
| | 7 | the Free Software Foundation; either version 2, or (at your option) |
| | 8 | any later version. |
| | 9 | |
| | 10 | This program is distributed in the hope that it will be useful, but |
| | 11 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| | 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| | 13 | General Public License for more details. |
| | 14 | |
| | 15 | You should have received a copy of the GNU General Public License |
| | 16 | along with this program; if not, write to the Free Software |
| | 17 | Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
| | 18 | |
| | 19 | #ifndef XTENSA_CONFIG_H |
| | 20 | #define XTENSA_CONFIG_H |
| | 21 | |
| | 22 | /* The macros defined here match those with the same names in the Xtensa |
| | 23 | compile-time HAL (Hardware Abstraction Layer). Please refer to the |
| | 24 | Xtensa System Software Reference Manual for documentation of these |
| | 25 | macros. */ |
| | 26 | |
| | 27 | #undef XCHAL_HAVE_BE |
| | 28 | #define XCHAL_HAVE_BE 1 |
| | 29 | |
| | 30 | #undef XCHAL_HAVE_DENSITY |
| | 31 | #define XCHAL_HAVE_DENSITY 1 |
| | 32 | |
| | 33 | #undef XCHAL_HAVE_CONST16 |
| | 34 | #define XCHAL_HAVE_CONST16 0 |
| | 35 | |
| | 36 | #undef XCHAL_HAVE_ABS |
| | 37 | #define XCHAL_HAVE_ABS 1 |
| | 38 | |
| | 39 | #undef XCHAL_HAVE_ADDX |
| | 40 | #define XCHAL_HAVE_ADDX 1 |
| | 41 | |
| | 42 | #undef XCHAL_HAVE_L32R |
| | 43 | #define XCHAL_HAVE_L32R 1 |
| | 44 | |
| | 45 | #undef XSHAL_USE_ABSOLUTE_LITERALS |
| | 46 | #define XSHAL_USE_ABSOLUTE_LITERALS 0 |
| | 47 | |
| | 48 | #undef XCHAL_HAVE_MAC16 |
| | 49 | #define XCHAL_HAVE_MAC16 0 |
| | 50 | |
| | 51 | #undef XCHAL_HAVE_MUL16 |
| | 52 | #define XCHAL_HAVE_MUL16 0 |
| | 53 | |
| | 54 | #undef XCHAL_HAVE_MUL32 |
| | 55 | #define XCHAL_HAVE_MUL32 0 |
| | 56 | |
| | 57 | #undef XCHAL_HAVE_DIV32 |
| | 58 | #define XCHAL_HAVE_DIV32 0 |
| | 59 | |
| | 60 | #undef XCHAL_HAVE_NSA |
| | 61 | #define XCHAL_HAVE_NSA 1 |
| | 62 | |
| | 63 | #undef XCHAL_HAVE_MINMAX |
| | 64 | #define XCHAL_HAVE_MINMAX 0 |
| | 65 | |
| | 66 | #undef XCHAL_HAVE_SEXT |
| | 67 | #define XCHAL_HAVE_SEXT 0 |
| | 68 | |
| | 69 | #undef XCHAL_HAVE_LOOPS |
| | 70 | #define XCHAL_HAVE_LOOPS 1 |
| | 71 | |
| | 72 | #undef XCHAL_HAVE_BOOLEANS |
| | 73 | #define XCHAL_HAVE_BOOLEANS 0 |
| | 74 | |
| | 75 | #undef XCHAL_HAVE_FP |
| | 76 | #define XCHAL_HAVE_FP 0 |
| | 77 | |
| | 78 | #undef XCHAL_HAVE_FP_DIV |
| | 79 | #define XCHAL_HAVE_FP_DIV 0 |
| | 80 | |
| | 81 | #undef XCHAL_HAVE_FP_RECIP |
| | 82 | #define XCHAL_HAVE_FP_RECIP 0 |
| | 83 | |
| | 84 | #undef XCHAL_HAVE_FP_SQRT |
| | 85 | #define XCHAL_HAVE_FP_SQRT 0 |
| | 86 | |
| | 87 | #undef XCHAL_HAVE_FP_RSQRT |
| | 88 | #define XCHAL_HAVE_FP_RSQRT 0 |
| | 89 | |
| | 90 | #undef XCHAL_HAVE_WINDOWED |
| | 91 | #define XCHAL_HAVE_WINDOWED 1 |
| | 92 | |
| | 93 | #undef XCHAL_HAVE_PREDICTED_BRANCHES |
| | 94 | #define XCHAL_HAVE_PREDICTED_BRANCHES 0 |
| | 95 | |
| | 96 | |
| | 97 | #undef XCHAL_ICACHE_SIZE |
| | 98 | #define XCHAL_ICACHE_SIZE 8192 |
| | 99 | |
| | 100 | #undef XCHAL_DCACHE_SIZE |
| | 101 | #define XCHAL_DCACHE_SIZE 8192 |
| | 102 | |
| | 103 | #undef XCHAL_ICACHE_LINESIZE |
| | 104 | #define XCHAL_ICACHE_LINESIZE 16 |
| | 105 | |
| | 106 | #undef XCHAL_DCACHE_LINESIZE |
| | 107 | #define XCHAL_DCACHE_LINESIZE 16 |
| | 108 | |
| | 109 | #undef XCHAL_ICACHE_LINEWIDTH |
| | 110 | #define XCHAL_ICACHE_LINEWIDTH 4 |
| | 111 | |
| | 112 | #undef XCHAL_DCACHE_LINEWIDTH |
| | 113 | #define XCHAL_DCACHE_LINEWIDTH 4 |
| | 114 | |
| | 115 | #undef XCHAL_DCACHE_IS_WRITEBACK |
| | 116 | #define XCHAL_DCACHE_IS_WRITEBACK 0 |
| | 117 | |
| | 118 | |
| | 119 | #undef XCHAL_HAVE_MMU |
| | 120 | #define XCHAL_HAVE_MMU 1 |
| | 121 | |
| | 122 | #undef XCHAL_MMU_MIN_PTE_PAGE_SIZE |
| | 123 | #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 |
| | 124 | |
| | 125 | |
| | 126 | #undef XCHAL_HAVE_DEBUG |
| | 127 | #define XCHAL_HAVE_DEBUG 1 |
| | 128 | |
| | 129 | #undef XCHAL_NUM_IBREAK |
| | 130 | #define XCHAL_NUM_IBREAK 2 |
| | 131 | |
| | 132 | #undef XCHAL_NUM_DBREAK |
| | 133 | #define XCHAL_NUM_DBREAK 2 |
| | 134 | |
| | 135 | #undef XCHAL_DEBUGLEVEL |
| | 136 | #define XCHAL_DEBUGLEVEL 4 |
| | 137 | |
| | 138 | |
| | 139 | #undef XCHAL_INST_FETCH_WIDTH |
| | 140 | #define XCHAL_INST_FETCH_WIDTH 4 |
| | 141 | |
| | 142 | #endif /* !XTENSA_CONFIG_H */ |
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