| 1 | 2011-07-01 Nick Clifton <nickc@redhat.com> |
| 2 | |
| 3 | PR binutils/12329 |
| 4 | * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM |
| 5 | insns using post-increment addressing. |
| 6 | |
| 7 | 2011-06-30 H.J. Lu <hongjiu.lu@intel.com> |
| 8 | |
| 9 | * i386-dis.c (vex_len_table): Update rorxS. |
| 10 | |
| 11 | 2011-06-30 H.J. Lu <hongjiu.lu@intel.com> |
| 12 | |
| 13 | AVX Programming Reference (June, 2011) |
| 14 | * i386-dis.c (vex_len_table): Correct rorxS. |
| 15 | |
| 16 | * i386-opc.tbl: Correct rorx. |
| 17 | * i386-tbl.h: Regenerated. |
| 18 | |
| 19 | 2011-06-29 H.J. Lu <hongjiu.lu@intel.com> |
| 20 | |
| 21 | * tilegx-opc.c (find_opcode): Replace "index" with "i". |
| 22 | * tilepro-opc.c (find_opcode): Likewise. |
| 23 | |
| 24 | 2011-06-29 Richard Sandiford <rdsandiford@googlemail.com> |
| 25 | |
| 26 | * mips16-opc.c (jalrc, jrc): Move earlier in file. |
| 27 | |
| 28 | 2011-06-21 H.J. Lu <hongjiu.lu@intel.com> |
| 29 | |
| 30 | * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and |
| 31 | PREFIX_VEX_0F388E. |
| 32 | |
| 33 | 2011-06-17 Andreas Schwab <schwab@redhat.com> |
| 34 | |
| 35 | * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ... |
| 36 | (MOSTLYCLEANFILES): ... here. |
| 37 | * Makefile.in: Regenerate. |
| 38 | |
| 39 | 2011-06-14 Alan Modra <amodra@gmail.com> |
| 40 | |
| 41 | * Makefile.in: Regenerate. |
| 42 | |
| 43 | 2011-06-13 Walter Lee <walt@tilera.com> |
| 44 | |
| 45 | * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c, |
| 46 | tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c. |
| 47 | * Makefile.in: Regenerate. |
| 48 | * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch. |
| 49 | * configure: Regenerate. |
| 50 | * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro. |
| 51 | * po/POTFILES.in: Regenerate. |
| 52 | * tilegx-dis.c: New file. |
| 53 | * tilegx-opc.c: New file. |
| 54 | * tilepro-dis.c: New file. |
| 55 | * tilepro-opc.c: New file. |
| 56 | |
| 57 | 2011-06-10 H.J. Lu <hongjiu.lu@intel.com> |
| 58 | |
| 59 | AVX Programming Reference (June, 2011) |
| 60 | * i386-dis.c (XMGatherQ): New. |
| 61 | * i386-dis.c (EXxmm_mb): New. |
| 62 | (EXxmm_mb): Likewise. |
| 63 | (EXxmm_mw): Likewise. |
| 64 | (EXxmm_md): Likewise. |
| 65 | (EXxmm_mq): Likewise. |
| 66 | (EXxmmdw): Likewise. |
| 67 | (EXxmmqd): Likewise. |
| 68 | (VexGatherQ): Likewise. |
| 69 | (MVexVSIBDWpX): Likewise. |
| 70 | (MVexVSIBQWpX): Likewise. |
| 71 | (xmm_mb_mode): Likewise. |
| 72 | (xmm_mw_mode): Likewise. |
| 73 | (xmm_md_mode): Likewise. |
| 74 | (xmm_mq_mode): Likewise. |
| 75 | (xmmdw_mode): Likewise. |
| 76 | (xmmqd_mode): Likewise. |
| 77 | (ymmxmm_mode): Likewise. |
| 78 | (vex_vsib_d_w_dq_mode): Likewise. |
| 79 | (vex_vsib_q_w_dq_mode): Likewise. |
| 80 | (MOD_VEX_0F385A_PREFIX_2): Likewise. |
| 81 | (MOD_VEX_0F388C_PREFIX_2): Likewise. |
| 82 | (MOD_VEX_0F388E_PREFIX_2): Likewise. |
| 83 | (PREFIX_0F3882): Likewise. |
| 84 | (PREFIX_VEX_0F3816): Likewise. |
| 85 | (PREFIX_VEX_0F3836): Likewise. |
| 86 | (PREFIX_VEX_0F3845): Likewise. |
| 87 | (PREFIX_VEX_0F3846): Likewise. |
| 88 | (PREFIX_VEX_0F3847): Likewise. |
| 89 | (PREFIX_VEX_0F3858): Likewise. |
| 90 | (PREFIX_VEX_0F3859): Likewise. |
| 91 | (PREFIX_VEX_0F385A): Likewise. |
| 92 | (PREFIX_VEX_0F3878): Likewise. |
| 93 | (PREFIX_VEX_0F3879): Likewise. |
| 94 | (PREFIX_VEX_0F388C): Likewise. |
| 95 | (PREFIX_VEX_0F388E): Likewise. |
| 96 | (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise. |
| 97 | (PREFIX_VEX_0F38F5): Likewise. |
| 98 | (PREFIX_VEX_0F38F6): Likewise. |
| 99 | (PREFIX_VEX_0F3A00): Likewise. |
| 100 | (PREFIX_VEX_0F3A01): Likewise. |
| 101 | (PREFIX_VEX_0F3A02): Likewise. |
| 102 | (PREFIX_VEX_0F3A38): Likewise. |
| 103 | (PREFIX_VEX_0F3A39): Likewise. |
| 104 | (PREFIX_VEX_0F3A46): Likewise. |
| 105 | (PREFIX_VEX_0F3AF0): Likewise. |
| 106 | (VEX_LEN_0F3816_P_2): Likewise. |
| 107 | (VEX_LEN_0F3819_P_2): Likewise. |
| 108 | (VEX_LEN_0F3836_P_2): Likewise. |
| 109 | (VEX_LEN_0F385A_P_2_M_0): Likewise. |
| 110 | (VEX_LEN_0F38F5_P_0): Likewise. |
| 111 | (VEX_LEN_0F38F5_P_1): Likewise. |
| 112 | (VEX_LEN_0F38F5_P_3): Likewise. |
| 113 | (VEX_LEN_0F38F6_P_3): Likewise. |
| 114 | (VEX_LEN_0F38F7_P_1): Likewise. |
| 115 | (VEX_LEN_0F38F7_P_2): Likewise. |
| 116 | (VEX_LEN_0F38F7_P_3): Likewise. |
| 117 | (VEX_LEN_0F3A00_P_2): Likewise. |
| 118 | (VEX_LEN_0F3A01_P_2): Likewise. |
| 119 | (VEX_LEN_0F3A38_P_2): Likewise. |
| 120 | (VEX_LEN_0F3A39_P_2): Likewise. |
| 121 | (VEX_LEN_0F3A46_P_2): Likewise. |
| 122 | (VEX_LEN_0F3AF0_P_3): Likewise. |
| 123 | (VEX_W_0F3816_P_2): Likewise. |
| 124 | (VEX_W_0F3818_P_2): Likewise. |
| 125 | (VEX_W_0F3819_P_2): Likewise. |
| 126 | (VEX_W_0F3836_P_2): Likewise. |
| 127 | (VEX_W_0F3846_P_2): Likewise. |
| 128 | (VEX_W_0F3858_P_2): Likewise. |
| 129 | (VEX_W_0F3859_P_2): Likewise. |
| 130 | (VEX_W_0F385A_P_2_M_0): Likewise. |
| 131 | (VEX_W_0F3878_P_2): Likewise. |
| 132 | (VEX_W_0F3879_P_2): Likewise. |
| 133 | (VEX_W_0F3A00_P_2): Likewise. |
| 134 | (VEX_W_0F3A01_P_2): Likewise. |
| 135 | (VEX_W_0F3A02_P_2): Likewise. |
| 136 | (VEX_W_0F3A38_P_2): Likewise. |
| 137 | (VEX_W_0F3A39_P_2): Likewise. |
| 138 | (VEX_W_0F3A46_P_2): Likewise. |
| 139 | (MOD_VEX_0F3818_PREFIX_2): Removed. |
| 140 | (MOD_VEX_0F3819_PREFIX_2): Likewise. |
| 141 | (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise. |
| 142 | (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise. |
| 143 | (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise. |
| 144 | (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise. |
| 145 | (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise. |
| 146 | (VEX_LEN_0F3A0E_P_2): Likewise. |
| 147 | (VEX_LEN_0F3A0F_P_2): Likewise. |
| 148 | (VEX_LEN_0F3A42_P_2): Likewise. |
| 149 | (VEX_LEN_0F3A4C_P_2): Likewise. |
| 150 | (VEX_W_0F3818_P_2_M_0): Likewise. |
| 151 | (VEX_W_0F3819_P_2_M_0): Likewise. |
| 152 | (prefix_table): Updated. |
| 153 | (three_byte_table): Likewise. |
| 154 | (vex_table): Likewise. |
| 155 | (vex_len_table): Likewise. |
| 156 | (vex_w_table): Likewise. |
| 157 | (mod_table): Likewise. |
| 158 | (putop): Handle "LW". |
| 159 | (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode, |
| 160 | xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode, |
| 161 | vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode. |
| 162 | (OP_EX): Likewise. |
| 163 | (OP_E_memory): Handle vex_vsib_d_w_dq_mode and |
| 164 | vex_vsib_q_w_dq_mode. |
| 165 | (OP_XMM): Handle vex_vsib_q_w_dq_mode. |
| 166 | (OP_VEX): Likewise. |
| 167 | |
| 168 | * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS |
| 169 | and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS, |
| 170 | CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS. |
| 171 | (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID. |
| 172 | (opcode_modifiers): Add VecSIB. |
| 173 | |
| 174 | * i386-opc.h (CpuAVX2): New. |
| 175 | (CpuBMI2): Likewise. |
| 176 | (CpuLZCNT): Likewise. |
| 177 | (CpuINVPCID): Likewise. |
| 178 | (VecSIB128): Likewise. |
| 179 | (VecSIB256): Likewise. |
| 180 | (VecSIB): Likewise. |
| 181 | (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid. |
| 182 | (i386_opcode_modifier): Add vecsib. |
| 183 | |
| 184 | * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions. |
| 185 | * i386-init.h: Regenerated. |
| 186 | * i386-tbl.h: Likewise. |
| 187 | |
| 188 | 2011-06-03 Quentin Neill <quentin.neill@amd.com> |
| 189 | |
| 190 | * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS. |
| 191 | * i386-init.h: Regenerated. |
| 192 | |
| 193 | 2011-06-03 Nick Clifton <nickc@redhat.com> |
| 194 | |
| 195 | PR binutils/12752 |
| 196 | * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for |
| 197 | computing address offsets. |
| 198 | (print_arm_address): Likewise. |
| 199 | (print_insn_arm): Likewise. |
| 200 | (print_insn_thumb16): Likewise. |
| 201 | (print_insn_thumb32): Likewise. |
| 202 | |
| 203 | 2011-06-02 Jie Zhang <jie@codesourcery.com> |
| 204 | Nathan Sidwell <nathan@codesourcery.com> |
| 205 | Maciej Rozycki <macro@codesourcery.com> |
| 206 | |
| 207 | * arm-dis.c (print_insn_coprocessor): Explicitly print #-0 |
| 208 | as address offset. |
| 209 | (print_arm_address): Likewise. Elide positive #0 appropriately. |
| 210 | (print_insn_arm): Likewise. |
| 211 | |
| 212 | 2011-06-02 Nick Clifton <nickc@redhat.com> |
| 213 | |
| 214 | PR gas/12752 |
| 215 | * arm-dis.c (print_insn_thumb32): Do not sign extend addresses |
| 216 | passed to print_address_func. |
| 217 | |
| 218 | 2011-06-02 Nick Clifton <nickc@redhat.com> |
| 219 | |
| 220 | * arm-dis.c: Fix spelling mistakes. |
| 221 | * op/opcodes.pot: Regenerate. |
| 222 | |
| 223 | 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> |
| 224 | |
| 225 | * s390-opc.c: Replace S390_OPERAND_REG_EVEN with |
| 226 | S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type. |
| 227 | * s390-opc.txt: Fix cxr instruction type. |
| 228 | |
| 229 | 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> |
| 230 | |
| 231 | * s390-opc.c: Add new instruction types marking register pair |
| 232 | operands. |
| 233 | * s390-opc.txt: Match instructions having register pair operands |
| 234 | to the new instruction types. |
| 235 | |
| 236 | 2011-05-19 Nick Clifton <nickc@redhat.com> |
| 237 | |
| 238 | * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2 |
| 239 | operands. |
| 240 | |
| 241 | 2011-05-10 Quentin Neill <quentin.neill@amd.com> |
| 242 | |
| 243 | * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS. |
| 244 | * i386-init.h: Regenerated. |
| 245 | |
| 246 | 2011-04-27 Nick Clifton <nickc@redhat.com> |
| 247 | |
| 248 | * po/da.po: Updated Danish translation. |
| 249 | |
| 250 | 2011-04-26 Anton Blanchard <anton@samba.org> |
| 251 | |
| 252 | * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7. |
| 253 | |
| 254 | 2011-04-21 DJ Delorie <dj@redhat.com> |
| 255 | |
| 256 | * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs. |
| 257 | * rx-decode.c: Regenerate. |
| 258 | |
| 259 | 2011-04-20 H.J. Lu <hongjiu.lu@intel.com> |
| 260 | |
| 261 | * i386-init.h: Regenerated. |
| 262 | |
| 263 | 2011-04-19 Quentin Neill <quentin.neill@amd.com> |
| 264 | |
| 265 | * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits |
| 266 | from bdver1 flags. |
| 267 | |
| 268 | 2011-04-13 Nick Clifton <nickc@redhat.com> |
| 269 | |
| 270 | * v850-dis.c (disassemble): Always print a closing square brace if |
| 271 | an opening square brace was printed. |
| 272 | |
| 273 | 2011-04-12 Nick Clifton <nickc@redhat.com> |
| 274 | |
| 275 | PR binutils/12534 |
| 276 | * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn |
| 277 | patterns. |
| 278 | (print_insn_thumb32): Handle %L. |
| 279 | |
| 280 | 2011-04-11 Julian Brown <julian@codesourcery.com> |
| 281 | |
| 282 | * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX. |
| 283 | (print_insn_thumb32): Add APSR bitmask support. |
| 284 | |
| 285 | 2011-04-07 Paul Carroll<pcarroll@codesourcery.com> |
| 286 | |
| 287 | * arm-dis.c (print_insn): init vars moved into private_data structure. |
| 288 | |
| 289 | 2011-03-24 Mike Frysinger <vapier@gentoo.org> |
| 290 | |
| 291 | * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic. |
| 292 | |
| 293 | 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> |
| 294 | |
| 295 | * avr-dis.c (avr_operand): Add opcode_str parameter. Check for |
| 296 | post-increment to support LPM Z+ instruction. Add support for 'E' |
| 297 | constraint for DES instruction. |
| 298 | (print_insn_avr): Adjust calls to avr_operand. Rename variable. |
| 299 | |
| 300 | 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org> |
| 301 | |
| 302 | * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code. |
| 303 | |
| 304 | 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org> |
| 305 | |
| 306 | * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC. |
| 307 | Use branch types instead. |
| 308 | (print_insn): Likewise. |
| 309 | |
| 310 | 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com> |
| 311 | |
| 312 | * mips-opc.c (mips_builtin_opcodes): Correct register use |
| 313 | annotation of "alnv.ps". |
| 314 | |
| 315 | 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com> |
| 316 | |
| 317 | * mips-opc.c (mips_builtin_opcodes): Add "pref" macro. |
| 318 | |
| 319 | 2011-02-22 Mike Frysinger <vapier@gentoo.org> |
| 320 | |
| 321 | * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check. |
| 322 | |
| 323 | 2011-02-22 Mike Frysinger <vapier@gentoo.org> |
| 324 | |
| 325 | * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS. |
| 326 | |
| 327 | 2011-02-19 Mike Frysinger <vapier@gentoo.org> |
| 328 | |
| 329 | * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and |
| 330 | a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1, |
| 331 | av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts, |
| 332 | exception, end_of_registers, msize, memory, bfd_mach. |
| 333 | (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG, |
| 334 | LB0REG, LC1REG, LT1REG, LB1REG): Delete |
| 335 | (AXREG, AWREG, LCREG, LTREG, LBREG): Define. |
| 336 | (get_allreg): Change to new defines. Fallback to abort(). |
| 337 | |
| 338 | 2011-02-14 Mike Frysinger <vapier@gentoo.org> |
| 339 | |
| 340 | * bfin-dis.c: Add whitespace/parenthesis where needed. |
| 341 | |
| 342 | 2011-02-14 Mike Frysinger <vapier@gentoo.org> |
| 343 | |
| 344 | * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater |
| 345 | than 7. |
| 346 | |
| 347 | 2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> |
| 348 | |
| 349 | * configure: Regenerate. |
| 350 | |
| 351 | 2011-02-13 Mike Frysinger <vapier@gentoo.org> |
| 352 | |
| 353 | * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg. |
| 354 | |
| 355 | 2011-02-13 Mike Frysinger <vapier@gentoo.org> |
| 356 | |
| 357 | * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output |
| 358 | dregs only when P is set, and dregs_lo otherwise. |
| 359 | |
| 360 | 2011-02-13 Mike Frysinger <vapier@gentoo.org> |
| 361 | |
| 362 | * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code. |
| 363 | |
| 364 | 2011-02-12 Mike Frysinger <vapier@gentoo.org> |
| 365 | |
| 366 | * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT. |
| 367 | |
| 368 | 2011-02-12 Mike Frysinger <vapier@gentoo.org> |
| 369 | |
| 370 | * bfin-dis.c (machine_registers): Delete REG_GP. |
| 371 | (reg_names): Delete "GP". |
| 372 | (decode_allregs): Change REG_GP to REG_LASTREG. |
| 373 | |
| 374 | 2011-02-12 Mike Frysinger <vapier@gentoo.org> |
| 375 | |
| 376 | * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, |
| 377 | M_IH, M_IU): Delete. |
| 378 | |
| 379 | 2011-02-11 Mike Frysinger <vapier@gentoo.org> |
| 380 | |
| 381 | * bfin-dis.c (reg_names): Add const. |
| 382 | (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte, |
| 383 | decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs, |
| 384 | decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits, |
| 385 | decode_counters, decode_allregs): Likewise. |
| 386 | |
| 387 | 2011-02-09 Michael Snyder <msnyder@vmware.com> |
| 388 | |
| 389 | * i386-dis.c (OP_J): Parenthesize expression to prevent |
| 390 | truncated addresses. |
| 391 | (print_insn): Fix indentation off-by-one. |
| 392 | |
| 393 | 2011-02-01 Nick Clifton <nickc@redhat.com> |
| 394 | |
| 395 | * po/da.po: Updated Danish translation. |
| 396 | |
| 397 | 2011-01-21 Dave Murphy <davem@devkitpro.org> |
| 398 | |
| 399 | * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS. |
| 400 | |
| 401 | 2011-01-18 H.J. Lu <hongjiu.lu@intel.com> |
| 402 | |
| 403 | * i386-dis.c (sIbT): New. |
| 404 | (b_T_mode): Likewise. |
| 405 | (dis386): Replace sIb with sIbT on "pushT". |
| 406 | (x86_64_table): Replace sIb with Ib on "aam" and "aad". |
| 407 | (OP_sI): Handle b_T_mode. Properly sign-extend byte. |
| 408 | |
| 409 | 2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com> |
| 410 | |
| 411 | * i386-init.h: Regenerated. |
| 412 | * i386-tbl.h: Regenerated |
| 413 | |
| 414 | 2011-01-17 Quentin Neill <quentin.neill@amd.com> |
| 415 | |
| 416 | * i386-dis.c (REG_XOP_TBM_01): New. |
| 417 | (REG_XOP_TBM_02): New. |
| 418 | (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables. |
| 419 | (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02 |
| 420 | entries, and add bextr instruction. |
| 421 | |
| 422 | * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM. |
| 423 | (cpu_flags): Add CpuTBM. |
| 424 | |
| 425 | * i386-opc.h (CpuTBM) New. |
| 426 | (i386_cpu_flags): Add bit cputbm. |
| 427 | |
| 428 | * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk, |
| 429 | blcs, blsfill, blsic, t1mskc, and tzmsk. |
| 430 | |
| 431 | 2011-01-12 DJ Delorie <dj@redhat.com> |
| 432 | |
| 433 | * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg. |
| 434 | |
| 435 | 2011-01-11 Mingjie Xing <mingjie.xing@gmail.com> |
| 436 | |
| 437 | * mips-dis.c (print_insn_args): Adjust the value to print the real |
| 438 | offset for "+c" argument. |
| 439 | |
| 440 | 2011-01-10 Nick Clifton <nickc@redhat.com> |
| 441 | |
| 442 | * po/da.po: Updated Danish translation. |
| 443 | |
| 444 | 2011-01-05 Nathan Sidwell <nathan@codesourcery.com> |
| 445 | |
| 446 | * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear. |
| 447 | |
| 448 | 2011-01-04 H.J. Lu <hongjiu.lu@intel.com> |
| 449 | |
| 450 | * i386-dis.c (REG_VEX_38F3): New. |
| 451 | (PREFIX_0FBC): Likewise. |
| 452 | (PREFIX_VEX_38F2): Likewise. |
| 453 | (PREFIX_VEX_38F3_REG_1): Likewise. |
| 454 | (PREFIX_VEX_38F3_REG_2): Likewise. |
| 455 | (PREFIX_VEX_38F3_REG_3): Likewise. |
| 456 | (PREFIX_VEX_38F7): Likewise. |
| 457 | (VEX_LEN_38F2_P_0): Likewise. |
| 458 | (VEX_LEN_38F3_R_1_P_0): Likewise. |
| 459 | (VEX_LEN_38F3_R_2_P_0): Likewise. |
| 460 | (VEX_LEN_38F3_R_3_P_0): Likewise. |
| 461 | (VEX_LEN_38F7_P_0): Likewise. |
| 462 | (dis386_twobyte): Use PREFIX_0FBC. |
| 463 | (reg_table): Add REG_VEX_38F3. |
| 464 | (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2, |
| 465 | PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2, |
| 466 | PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7. |
| 467 | (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and |
| 468 | PREFIX_VEX_38F7. |
| 469 | (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0, |
| 470 | VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and |
| 471 | VEX_LEN_38F7_P_0. |
| 472 | |
| 473 | * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS. |
| 474 | (cpu_flags): Add CpuBMI. |
| 475 | |
| 476 | * i386-opc.h (CpuBMI): New. |
| 477 | (i386_cpu_flags): Add cpubmi. |
| 478 | |
| 479 | * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt. |
| 480 | * i386-init.h: Regenerated. |
| 481 | * i386-tbl.h: Likewise. |
| 482 | |
| 483 | 2011-01-04 H.J. Lu <hongjiu.lu@intel.com> |
| 484 | |
| 485 | * i386-dis.c (VexGdq): New. |
| 486 | (OP_VEX): Handle dq_mode. |
| 487 | |
| 488 | 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> |
| 489 | |
| 490 | * i386-gen.c (process_copyright): Update copyright to 2011. |
| 491 | |
| 492 | For older changes see ChangeLog-2010 |
| 493 | \f |
| 494 | Local Variables: |
| 495 | mode: change-log |
| 496 | left-margin: 8 |
| 497 | fill-column: 74 |
| 498 | version-control: never |
| 499 | End: |