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Remove tahoe support
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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12018-04-16 Alan Modra <amodra@gmail.com>
2
3 * configure.ac: Remove tahoe support.
4 * configure: Regenerate.
5
62018-04-15 H.J. Lu <hongjiu.lu@intel.com>
7
8 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
9 umwait.
10 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
11 64-bit mode.
12 * i386-tbl.h: Regenerated.
13
142018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
15
16 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
17 PREFIX_MOD_1_0FAE_REG_6.
18 (va_mode): New.
19 (OP_E_register): Use va_mode.
20 * i386-dis-evex.h (prefix_table):
21 New instructions (see prefixes above).
22 * i386-gen.c (cpu_flag_init): Add WAITPKG.
23 (cpu_flags): Likewise.
24 * i386-opc.h (enum): Likewise.
25 (i386_cpu_flags): Likewise.
26 * i386-opc.tbl: Add umonitor, umwait, tpause.
27 * i386-init.h: Regenerate.
28 * i386-tbl.h: Likewise.
29
302018-04-11 Alan Modra <amodra@gmail.com>
31
32 * opcodes/i860-dis.c: Delete.
33 * opcodes/i960-dis.c: Delete.
34 * Makefile.am: Remove i860 and i960 support.
35 * configure.ac: Likewise.
36 * disassemble.c: Likewise.
37 * disassemble.h: Likewise.
38 * Makefile.in: Regenerate.
39 * configure: Regenerate.
40 * po/POTFILES.in: Regenerate.
41
422018-04-04 H.J. Lu <hongjiu.lu@intel.com>
43
44 PR binutils/23025
45 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
46 to 0.
47 (print_insn): Clear vex instead of vex.evex.
48
492018-04-04 Nick Clifton <nickc@redhat.com>
50
51 * po/es.po: Updated Spanish translation.
52
532018-03-28 Jan Beulich <jbeulich@suse.com>
54
55 * i386-gen.c (opcode_modifiers): Delete VecESize.
56 * i386-opc.h (VecESize): Delete.
57 (struct i386_opcode_modifier): Delete vecesize.
58 * i386-opc.tbl: Drop VecESize.
59 * i386-tlb.h: Re-generate.
60
612018-03-28 Jan Beulich <jbeulich@suse.com>
62
63 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
64 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
65 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
66 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
67 * i386-tlb.h: Re-generate.
68
692018-03-28 Jan Beulich <jbeulich@suse.com>
70
71 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
72 Fold AVX512 forms
73 * i386-tlb.h: Re-generate.
74
752018-03-28 Jan Beulich <jbeulich@suse.com>
76
77 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
78 (vex_len_table): Drop Y for vcvt*2si.
79 (putop): Replace plain 'Y' handling by abort().
80
812018-03-28 Nick Clifton <nickc@redhat.com>
82
83 PR 22988
84 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
85 instructions with only a base address register.
86 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
87 handle AARHC64_OPND_SVE_ADDR_R.
88 (aarch64_print_operand): Likewise.
89 * aarch64-asm-2.c: Regenerate.
90 * aarch64_dis-2.c: Regenerate.
91 * aarch64-opc-2.c: Regenerate.
92
932018-03-22 Jan Beulich <jbeulich@suse.com>
94
95 * i386-opc.tbl: Drop VecESize from register only insn forms and
96 memory forms not allowing broadcast.
97 * i386-tlb.h: Re-generate.
98
992018-03-22 Jan Beulich <jbeulich@suse.com>
100
101 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
102 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
103 sha256*): Drop Disp<N>.
104
1052018-03-22 Jan Beulich <jbeulich@suse.com>
106
107 * i386-dis.c (EbndS, bnd_swap_mode): New.
108 (prefix_table): Use EbndS.
109 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
110 * i386-opc.tbl (bndmov): Move misplaced Load.
111 * i386-tlb.h: Re-generate.
112
1132018-03-22 Jan Beulich <jbeulich@suse.com>
114
115 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
116 templates allowing memory operands and folded ones for register
117 only flavors.
118 * i386-tlb.h: Re-generate.
119
1202018-03-22 Jan Beulich <jbeulich@suse.com>
121
122 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
123 256-bit templates. Drop redundant leftover Disp<N>.
124 * i386-tlb.h: Re-generate.
125
1262018-03-14 Kito Cheng <kito.cheng@gmail.com>
127
128 * riscv-opc.c (riscv_insn_types): New.
129
1302018-03-13 Nick Clifton <nickc@redhat.com>
131
132 * po/pt_BR.po: Updated Brazilian Portuguese translation.
133
1342018-03-08 H.J. Lu <hongjiu.lu@intel.com>
135
136 * i386-opc.tbl: Add Optimize to clr.
137 * i386-tbl.h: Regenerated.
138
1392018-03-08 H.J. Lu <hongjiu.lu@intel.com>
140
141 * i386-gen.c (opcode_modifiers): Remove OldGcc.
142 * i386-opc.h (OldGcc): Removed.
143 (i386_opcode_modifier): Remove oldgcc.
144 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
145 instructions for old (<= 2.8.1) versions of gcc.
146 * i386-tbl.h: Regenerated.
147
1482018-03-08 Jan Beulich <jbeulich@suse.com>
149
150 * i386-opc.h (EVEXDYN): New.
151 * i386-opc.tbl: Fold various AVX512VL templates.
152 * i386-tlb.h: Re-generate.
153
1542018-03-08 Jan Beulich <jbeulich@suse.com>
155
156 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
157 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
158 vpexpandd, vpexpandq): Fold AFX512VF templates.
159 * i386-tlb.h: Re-generate.
160
1612018-03-08 Jan Beulich <jbeulich@suse.com>
162
163 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
164 Fold 128- and 256-bit VEX-encoded templates.
165 * i386-tlb.h: Re-generate.
166
1672018-03-08 Jan Beulich <jbeulich@suse.com>
168
169 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
170 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
171 vpexpandd, vpexpandq): Fold AVX512F templates.
172 * i386-tlb.h: Re-generate.
173
1742018-03-08 Jan Beulich <jbeulich@suse.com>
175
176 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
177 64-bit templates. Drop Disp<N>.
178 * i386-tlb.h: Re-generate.
179
1802018-03-08 Jan Beulich <jbeulich@suse.com>
181
182 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
183 and 256-bit templates.
184 * i386-tlb.h: Re-generate.
185
1862018-03-08 Jan Beulich <jbeulich@suse.com>
187
188 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
189 * i386-tlb.h: Re-generate.
190
1912018-03-08 Jan Beulich <jbeulich@suse.com>
192
193 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
194 Drop NoAVX.
195 * i386-tlb.h: Re-generate.
196
1972018-03-08 Jan Beulich <jbeulich@suse.com>
198
199 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
200 * i386-tlb.h: Re-generate.
201
2022018-03-08 Jan Beulich <jbeulich@suse.com>
203
204 * i386-gen.c (opcode_modifiers): Delete FloatD.
205 * i386-opc.h (FloatD): Delete.
206 (struct i386_opcode_modifier): Delete floatd.
207 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
208 FloatD by D.
209 * i386-tlb.h: Re-generate.
210
2112018-03-08 Jan Beulich <jbeulich@suse.com>
212
213 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
214
2152018-03-08 Jan Beulich <jbeulich@suse.com>
216
217 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
218 * i386-tlb.h: Re-generate.
219
2202018-03-08 Jan Beulich <jbeulich@suse.com>
221
222 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
223 forms.
224 * i386-tlb.h: Re-generate.
225
2262018-03-07 Alan Modra <amodra@gmail.com>
227
228 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
229 bfd_arch_rs6000.
230 * disassemble.h (print_insn_rs6000): Delete.
231 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
232 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
233 (print_insn_rs6000): Delete.
234
2352018-03-03 Alan Modra <amodra@gmail.com>
236
237 * sysdep.h (opcodes_error_handler): Define.
238 (_bfd_error_handler): Declare.
239 * Makefile.am: Remove stray #.
240 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
241 EDIT" comment.
242 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
243 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
244 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
245 opcodes_error_handler to print errors. Standardize error messages.
246 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
247 and include opintl.h.
248 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
249 * i386-gen.c: Standardize error messages.
250 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
251 * Makefile.in: Regenerate.
252 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
253 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
254 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
255 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
256 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
257 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
258 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
259 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
260 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
261 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
262 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
263 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
264 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
265
2662018-03-01 H.J. Lu <hongjiu.lu@intel.com>
267
268 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
269 vpsub[bwdq] instructions.
270 * i386-tbl.h: Regenerated.
271
2722018-03-01 Alan Modra <amodra@gmail.com>
273
274 * configure.ac (ALL_LINGUAS): Sort.
275 * configure: Regenerate.
276
2772018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
278
279 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
280 macro by assignements.
281
2822018-02-27 H.J. Lu <hongjiu.lu@intel.com>
283
284 PR gas/22871
285 * i386-gen.c (opcode_modifiers): Add Optimize.
286 * i386-opc.h (Optimize): New enum.
287 (i386_opcode_modifier): Add optimize.
288 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
289 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
290 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
291 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
292 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
293 vpxord and vpxorq.
294 * i386-tbl.h: Regenerated.
295
2962018-02-26 Alan Modra <amodra@gmail.com>
297
298 * crx-dis.c (getregliststring): Allocate a large enough buffer
299 to silence false positive gcc8 warning.
300
3012018-02-22 Shea Levy <shea@shealevy.com>
302
303 * disassemble.c (ARCH_riscv): Define if ARCH_all.
304
3052018-02-22 H.J. Lu <hongjiu.lu@intel.com>
306
307 * i386-opc.tbl: Add {rex},
308 * i386-tbl.h: Regenerated.
309
3102018-02-20 Maciej W. Rozycki <macro@mips.com>
311
312 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
313 (mips16_opcodes): Replace `M' with `m' for "restore".
314
3152018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
316
317 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
318
3192018-02-13 Maciej W. Rozycki <macro@mips.com>
320
321 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
322 variable to `function_index'.
323
3242018-02-13 Nick Clifton <nickc@redhat.com>
325
326 PR 22823
327 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
328 about truncation of printing.
329
3302018-02-12 Henry Wong <henry@stuffedcow.net>
331
332 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
333
3342018-02-05 Nick Clifton <nickc@redhat.com>
335
336 * po/pt_BR.po: Updated Brazilian Portuguese translation.
337
3382018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
339
340 * i386-dis.c (enum): Add pconfig.
341 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
342 (cpu_flags): Add CpuPCONFIG.
343 * i386-opc.h (enum): Add CpuPCONFIG.
344 (i386_cpu_flags): Add cpupconfig.
345 * i386-opc.tbl: Add PCONFIG instruction.
346 * i386-init.h: Regenerate.
347 * i386-tbl.h: Likewise.
348
3492018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
350
351 * i386-dis.c (enum): Add PREFIX_0F09.
352 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
353 (cpu_flags): Add CpuWBNOINVD.
354 * i386-opc.h (enum): Add CpuWBNOINVD.
355 (i386_cpu_flags): Add cpuwbnoinvd.
356 * i386-opc.tbl: Add WBNOINVD instruction.
357 * i386-init.h: Regenerate.
358 * i386-tbl.h: Likewise.
359
3602018-01-17 Jim Wilson <jimw@sifive.com>
361
362 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
363
3642018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
365
366 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
367 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
368 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
369 (cpu_flags): Add CpuIBT, CpuSHSTK.
370 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
371 (i386_cpu_flags): Add cpuibt, cpushstk.
372 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
373 * i386-init.h: Regenerate.
374 * i386-tbl.h: Likewise.
375
3762018-01-16 Nick Clifton <nickc@redhat.com>
377
378 * po/pt_BR.po: Updated Brazilian Portugese translation.
379 * po/de.po: Updated German translation.
380
3812018-01-15 Jim Wilson <jimw@sifive.com>
382
383 * riscv-opc.c (match_c_nop): New.
384 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
385
3862018-01-15 Nick Clifton <nickc@redhat.com>
387
388 * po/uk.po: Updated Ukranian translation.
389
3902018-01-13 Nick Clifton <nickc@redhat.com>
391
392 * po/opcodes.pot: Regenerated.
393
3942018-01-13 Nick Clifton <nickc@redhat.com>
395
396 * configure: Regenerate.
397
3982018-01-13 Nick Clifton <nickc@redhat.com>
399
400 2.30 branch created.
401
4022018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
403
404 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
405 * i386-tbl.h: Regenerate.
406
4072018-01-10 Jan Beulich <jbeulich@suse.com>
408
409 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
410 * i386-tbl.h: Re-generate.
411
4122018-01-10 Jan Beulich <jbeulich@suse.com>
413
414 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
415 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
416 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
417 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
418 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
419 Disp8MemShift of AVX512VL forms.
420 * i386-tbl.h: Re-generate.
421
4222018-01-09 Jim Wilson <jimw@sifive.com>
423
424 * riscv-dis.c (maybe_print_address): If base_reg is zero,
425 then the hi_addr value is zero.
426
4272018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
428
429 * arm-dis.c (arm_opcodes): Add csdb.
430 (thumb32_opcodes): Add csdb.
431
4322018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
433
434 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
435 * aarch64-asm-2.c: Regenerate.
436 * aarch64-dis-2.c: Regenerate.
437 * aarch64-opc-2.c: Regenerate.
438
4392018-01-08 H.J. Lu <hongjiu.lu@intel.com>
440
441 PR gas/22681
442 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
443 Remove AVX512 vmovd with 64-bit operands.
444 * i386-tbl.h: Regenerated.
445
4462018-01-05 Jim Wilson <jimw@sifive.com>
447
448 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
449 jalr.
450
4512018-01-03 Alan Modra <amodra@gmail.com>
452
453 Update year range in copyright notice of all files.
454
4552018-01-02 Jan Beulich <jbeulich@suse.com>
456
457 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
458 and OPERAND_TYPE_REGZMM entries.
459
460For older changes see ChangeLog-2017
461\f
462Copyright (C) 2018 Free Software Foundation, Inc.
463
464Copying and distribution of this file, with or without modification,
465are permitted in any medium without royalty provided the copyright
466notice and this notice are preserved.
467
468Local Variables:
469mode: change-log
470left-margin: 8
471fill-column: 74
472version-control: never
473End:
GDB Binutils - Deliverables
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