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2005-01-21 Fred Fish <fnf@specifixinc.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
... / ...
CommitLineData
12005-01-20 Alan Modra <amodra@bigpond.net.au>
2
3 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
4
52005-01-19 Fred Fish <fnf@specifixinc.com>
6
7 * mips-dis.c (no_aliases): New disassembly option flag.
8 (set_default_mips_dis_options): Init no_aliases to zero.
9 (parse_mips_dis_option): Handle no-aliases option.
10 (print_insn_mips): Ignore table entries that are aliases
11 if no_aliases is set.
12 (print_insn_mips16): Ditto.
13 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
14 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
15 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
16 * mips16-opc.c (mips16_opcodes): Ditto.
17
182005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
19
20 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
21 (inheritance diagram): Add missing edge.
22 (arch_sh1_up): Rename arch_sh_up to match external name to make life
23 easier for the testsuite.
24 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
25 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
26 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
27 arch_sh2a_or_sh4_up child.
28 (sh_table): Do renaming as above.
29 Correct comment for ldc.l for gas testsuite to read.
30 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
31 Correct comments for movy.w and movy.l for gas testsuite to read.
32 Correct comments for fmov.d and fmov.s for gas testsuite to read.
33
342005-01-12 H.J. Lu <hongjiu.lu@intel.com>
35
36 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
37
382005-01-12 H.J. Lu <hongjiu.lu@intel.com>
39
40 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
41
422005-01-10 Andreas Schwab <schwab@suse.de>
43
44 * disassemble.c (disassemble_init_for_target) <case
45 bfd_arch_ia64>: Set skip_zeroes to 16.
46 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
47
482004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
49
50 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
51
522004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
53
54 * avr-dis.c: Prettyprint. Added printing of symbol names in all
55 memory references. Convert avr_operand() to C90 formatting.
56
572004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
58
59 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
60
612004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
62
63 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
64 (no_op_insn): Initialize array with instructions that have no
65 operands.
66 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
67
682004-11-29 Richard Earnshaw <rearnsha@arm.com>
69
70 * arm-dis.c: Correct top-level comment.
71
722004-11-27 Richard Earnshaw <rearnsha@arm.com>
73
74 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
75 architecuture defining the insn.
76 (arm_opcodes, thumb_opcodes): Delete. Move to ...
77 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
78 field.
79 Also include opcode/arm.h.
80 * Makefile.am (arm-dis.lo): Update dependency list.
81 * Makefile.in: Regenerate.
82
832004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
84
85 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
86 reflect the change to the short immediate syntax.
87
882004-11-19 Alan Modra <amodra@bigpond.net.au>
89
90 * or32-opc.c (debug): Warning fix.
91 * po/POTFILES.in: Regenerate.
92
93 * maxq-dis.c: Formatting.
94 (print_insn): Warning fix.
95
962004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
97
98 * arm-dis.c (WORD_ADDRESS): Define.
99 (print_insn): Use it. Correct big-endian end-of-section handling.
100
1012004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
102 Vineet Sharma <vineets@noida.hcltech.com>
103
104 * maxq-dis.c: New file.
105 * disassemble.c (ARCH_maxq): Define.
106 (disassembler): Add 'print_insn_maxq_little' for handling maxq
107 instructions..
108 * configure.in: Add case for bfd_maxq_arch.
109 * configure: Regenerate.
110 * Makefile.am: Add support for maxq-dis.c
111 * Makefile.in: Regenerate.
112 * aclocal.m4: Regenerate.
113
1142004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
115
116 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
117 mode.
118 * crx-dis.c: Likewise.
119
1202004-11-04 Hans-Peter Nilsson <hp@axis.com>
121
122 Generally, handle CRISv32.
123 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
124 (struct cris_disasm_data): New type.
125 (format_reg, format_hex, cris_constraint, print_flags)
126 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
127 callers changed.
128 (format_sup_reg, print_insn_crisv32_with_register_prefix)
129 (print_insn_crisv32_without_register_prefix)
130 (print_insn_crisv10_v32_with_register_prefix)
131 (print_insn_crisv10_v32_without_register_prefix)
132 (cris_parse_disassembler_options): New functions.
133 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
134 parameter. All callers changed.
135 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
136 failure.
137 (cris_constraint) <case 'Y', 'U'>: New cases.
138 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
139 for constraint 'n'.
140 (print_with_operands) <case 'Y'>: New case.
141 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
142 <case 'N', 'Y', 'Q'>: New cases.
143 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
144 (print_insn_cris_with_register_prefix)
145 (print_insn_cris_without_register_prefix): Call
146 cris_parse_disassembler_options.
147 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
148 for CRISv32 and the size of immediate operands. New v32-only
149 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
150 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
151 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
152 Change brp to be v3..v10.
153 (cris_support_regs): New vector.
154 (cris_opcodes): Update head comment. New format characters '[',
155 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
156 Add new opcodes for v32 and adjust existing opcodes to accommodate
157 differences to earlier variants.
158 (cris_cond15s): New vector.
159
1602004-11-04 Jan Beulich <jbeulich@novell.com>
161
162 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
163 (indirEb): Remove.
164 (Mp): Use f_mode rather than none at all.
165 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
166 replaces what previously was x_mode; x_mode now means 128-bit SSE
167 operands.
168 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
169 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
170 pinsrw's second operand is Edqw.
171 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
172 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
173 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
174 mode when an operand size override is present or always suffixing.
175 More instructions will need to be added to this group.
176 (putop): Handle new macro chars 'C' (short/long suffix selector),
177 'I' (Intel mode override for following macro char), and 'J' (for
178 adding the 'l' prefix to far branches in AT&T mode). When an
179 alternative was specified in the template, honor macro character when
180 specified for Intel mode.
181 (OP_E): Handle new *_mode values. Correct pointer specifications for
182 memory operands. Consolidate output of index register.
183 (OP_G): Handle new *_mode values.
184 (OP_I): Handle const_1_mode.
185 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
186 respective opcode prefix bits have been consumed.
187 (OP_EM, OP_EX): Provide some default handling for generating pointer
188 specifications.
189
1902004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
191
192 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
193 COP_INST macro.
194
1952004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
196
197 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
198 (getregliststring): Support HI/LO and user registers.
199 * crx-opc.c (crx_instruction): Update data structure according to the
200 rearrangement done in CRX opcode header file.
201 (crx_regtab): Likewise.
202 (crx_optab): Likewise.
203 (crx_instruction): Reorder load/stor instructions, remove unsupported
204 formats.
205 support new Co-Processor instruction 'cpi'.
206
2072004-10-27 Nick Clifton <nickc@redhat.com>
208
209 * opcodes/iq2000-asm.c: Regenerate.
210 * opcodes/iq2000-desc.c: Regenerate.
211 * opcodes/iq2000-desc.h: Regenerate.
212 * opcodes/iq2000-dis.c: Regenerate.
213 * opcodes/iq2000-ibld.c: Regenerate.
214 * opcodes/iq2000-opc.c: Regenerate.
215 * opcodes/iq2000-opc.h: Regenerate.
216
2172004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
218
219 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
220 us4, us5 (respectively).
221 Remove unsupported 'popa' instruction.
222 Reverse operands order in store co-processor instructions.
223
2242004-10-15 Alan Modra <amodra@bigpond.net.au>
225
226 * Makefile.am: Run "make dep-am"
227 * Makefile.in: Regenerate.
228
2292004-10-12 Bob Wilson <bob.wilson@acm.org>
230
231 * xtensa-dis.c: Use ISO C90 formatting.
232
2332004-10-09 Alan Modra <amodra@bigpond.net.au>
234
235 * ppc-opc.c: Revert 2004-09-09 change.
236
2372004-10-07 Bob Wilson <bob.wilson@acm.org>
238
239 * xtensa-dis.c (state_names): Delete.
240 (fetch_data): Use xtensa_isa_maxlength.
241 (print_xtensa_operand): Replace operand parameter with opcode/operand
242 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
243 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
244 instruction bundles. Use xmalloc instead of malloc.
245
2462004-10-07 David Gibson <david@gibson.dropbear.id.au>
247
248 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
249 initializers.
250
2512004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
252
253 * crx-opc.c (crx_instruction): Support Co-processor insns.
254 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
255 (getregliststring): Change function to use the above enum.
256 (print_arg): Handle CO-Processor insns.
257 (crx_cinvs): Add 'b' option to invalidate the branch-target
258 cache.
259
2602004-10-06 Aldy Hernandez <aldyh@redhat.com>
261
262 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
263 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
264 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
265 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
266 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
267
2682004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
269
270 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
271 rather than add it.
272
2732004-09-30 Paul Brook <paul@codesourcery.com>
274
275 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
276 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
277
2782004-09-17 H.J. Lu <hongjiu.lu@intel.com>
279
280 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
281 (CONFIG_STATUS_DEPENDENCIES): New.
282 (Makefile): Removed.
283 (config.status): Likewise.
284 * Makefile.in: Regenerated.
285
2862004-09-17 Alan Modra <amodra@bigpond.net.au>
287
288 * Makefile.am: Run "make dep-am".
289 * Makefile.in: Regenerate.
290 * aclocal.m4: Regenerate.
291 * configure: Regenerate.
292 * po/POTFILES.in: Regenerate.
293 * po/opcodes.pot: Regenerate.
294
2952004-09-11 Andreas Schwab <schwab@suse.de>
296
297 * configure: Rebuild.
298
2992004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
300
301 * ppc-opc.c (L): Make this field not optional.
302
3032004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
304
305 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
306 Fix parameter to 'm[t|f]csr' insns.
307
3082004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
309
310 * configure.in: Autoupdate to autoconf 2.59.
311 * aclocal.m4: Rebuild with aclocal 1.4p6.
312 * configure: Rebuild with autoconf 2.59.
313 * Makefile.in: Rebuild with automake 1.4p6 (picking up
314 bfd changes for autoconf 2.59 on the way).
315 * config.in: Rebuild with autoheader 2.59.
316
3172004-08-27 Richard Sandiford <rsandifo@redhat.com>
318
319 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
320
3212004-07-30 Michal Ludvig <mludvig@suse.cz>
322
323 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
324 (GRPPADLCK2): New define.
325 (twobyte_has_modrm): True for 0xA6.
326 (grps): GRPPADLCK2 for opcode 0xA6.
327
3282004-07-29 Alexandre Oliva <aoliva@redhat.com>
329
330 Introduce SH2a support.
331 * sh-opc.h (arch_sh2a_base): Renumber.
332 (arch_sh2a_nofpu_base): Remove.
333 (arch_sh_base_mask): Adjust.
334 (arch_opann_mask): New.
335 (arch_sh2a, arch_sh2a_nofpu): Adjust.
336 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
337 (sh_table): Adjust whitespace.
338 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
339 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
340 instruction list throughout.
341 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
342 of arch_sh2a in instruction list throughout.
343 (arch_sh2e_up): Accomodate above changes.
344 (arch_sh2_up): Ditto.
345 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
346 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
347 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
348 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
349 * sh-opc.h (arch_sh2a_nofpu): New.
350 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
351 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
352 instruction.
353 2004-01-20 DJ Delorie <dj@redhat.com>
354 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
355 2003-12-29 DJ Delorie <dj@redhat.com>
356 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
357 sh_opcode_info, sh_table): Add sh2a support.
358 (arch_op32): New, to tag 32-bit opcodes.
359 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
360 2003-12-02 Michael Snyder <msnyder@redhat.com>
361 * sh-opc.h (arch_sh2a): Add.
362 * sh-dis.c (arch_sh2a): Handle.
363 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
364
3652004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
366
367 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
368
3692004-07-22 Nick Clifton <nickc@redhat.com>
370
371 PR/280
372 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
373 insns - this is done by objdump itself.
374 * h8500-dis.c (print_insn_h8500): Likewise.
375
3762004-07-21 Jan Beulich <jbeulich@novell.com>
377
378 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
379 regardless of address size prefix in effect.
380 (ptr_reg): Size or address registers does not depend on rex64, but
381 on the presence of an address size override.
382 (OP_MMX): Use rex.x only for xmm registers.
383 (OP_EM): Use rex.z only for xmm registers.
384
3852004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
386
387 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
388 move/branch operations to the bottom so that VR5400 multimedia
389 instructions take precedence in disassembly.
390
3912004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
392
393 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
394 ISA-specific "break" encoding.
395
3962004-07-13 Elvis Chiang <elvisfb@gmail.com>
397
398 * arm-opc.h: Fix typo in comment.
399
4002004-07-11 Andreas Schwab <schwab@suse.de>
401
402 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
403
4042004-07-09 Andreas Schwab <schwab@suse.de>
405
406 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
407
4082004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
409
410 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
411 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
412 (crx-dis.lo): New target.
413 (crx-opc.lo): Likewise.
414 * Makefile.in: Regenerate.
415 * configure.in: Handle bfd_crx_arch.
416 * configure: Regenerate.
417 * crx-dis.c: New file.
418 * crx-opc.c: New file.
419 * disassemble.c (ARCH_crx): Define.
420 (disassembler): Handle ARCH_crx.
421
4222004-06-29 James E Wilson <wilson@specifixinc.com>
423
424 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
425 * ia64-asmtab.c: Regnerate.
426
4272004-06-28 Alan Modra <amodra@bigpond.net.au>
428
429 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
430 (extract_fxm): Don't test dialect.
431 (XFXFXM_MASK): Include the power4 bit.
432 (XFXM): Add p4 param.
433 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
434
4352004-06-27 Alexandre Oliva <aoliva@redhat.com>
436
437 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
438 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
439
4402004-06-26 Alan Modra <amodra@bigpond.net.au>
441
442 * ppc-opc.c (BH, XLBH_MASK): Define.
443 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
444
4452004-06-24 Alan Modra <amodra@bigpond.net.au>
446
447 * i386-dis.c (x_mode): Comment.
448 (two_source_ops): File scope.
449 (float_mem): Correct fisttpll and fistpll.
450 (float_mem_mode): New table.
451 (dofloat): Use it.
452 (OP_E): Correct intel mode PTR output.
453 (ptr_reg): Use open_char and close_char.
454 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
455 operands. Set two_source_ops.
456
4572004-06-15 Alan Modra <amodra@bigpond.net.au>
458
459 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
460 instead of _raw_size.
461
4622004-06-08 Jakub Jelinek <jakub@redhat.com>
463
464 * ia64-gen.c (in_iclass): Handle more postinc st
465 and ld variants.
466 * ia64-asmtab.c: Rebuilt.
467
4682004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
469
470 * s390-opc.txt: Correct architecture mask for some opcodes.
471 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
472 in the esa mode as well.
473
4742004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
475
476 * sh-dis.c (target_arch): Make unsigned.
477 (print_insn_sh): Replace (most of) switch with a call to
478 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
479 * sh-opc.h: Redefine architecture flags values.
480 Add sh3-nommu architecture.
481 Reorganise <arch>_up macros so they make more visual sense.
482 (SH_MERGE_ARCH_SET): Define new macro.
483 (SH_VALID_BASE_ARCH_SET): Likewise.
484 (SH_VALID_MMU_ARCH_SET): Likewise.
485 (SH_VALID_CO_ARCH_SET): Likewise.
486 (SH_VALID_ARCH_SET): Likewise.
487 (SH_MERGE_ARCH_SET_VALID): Likewise.
488 (SH_ARCH_SET_HAS_FPU): Likewise.
489 (SH_ARCH_SET_HAS_DSP): Likewise.
490 (SH_ARCH_UNKNOWN_ARCH): Likewise.
491 (sh_get_arch_from_bfd_mach): Add prototype.
492 (sh_get_arch_up_from_bfd_mach): Likewise.
493 (sh_get_bfd_mach_from_arch_set): Likewise.
494 (sh_merge_bfd_arc): Likewise.
495
4962004-05-24 Peter Barada <peter@the-baradas.com>
497
498 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
499 into new match_insn_m68k function. Loop over canidate
500 matches and select first that completely matches.
501 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
502 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
503 to verify addressing for MAC/EMAC.
504 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
505 reigster halves since 'fpu' and 'spl' look misleading.
506 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
507 * m68k-opc.c: Rearragne mac/emac cases to use longest for
508 first, tighten up match masks.
509 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
510 'size' from special case code in print_insn_m68k to
511 determine decode size of insns.
512
5132004-05-19 Alan Modra <amodra@bigpond.net.au>
514
515 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
516 well as when -mpower4.
517
5182004-05-13 Nick Clifton <nickc@redhat.com>
519
520 * po/fr.po: Updated French translation.
521
5222004-05-05 Peter Barada <peter@the-baradas.com>
523
524 * m68k-dis.c(print_insn_m68k): Add new chips, use core
525 variants in arch_mask. Only set m68881/68851 for 68k chips.
526 * m68k-op.c: Switch from ColdFire chips to core variants.
527
5282004-05-05 Alan Modra <amodra@bigpond.net.au>
529
530 PR 147.
531 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
532
5332004-04-29 Ben Elliston <bje@au.ibm.com>
534
535 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
536 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
537
5382004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
539
540 * sh-dis.c (print_insn_sh): Print the value in constant pool
541 as a symbol if it looks like a symbol.
542
5432004-04-22 Peter Barada <peter@the-baradas.com>
544
545 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
546 appropriate ColdFire architectures.
547 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
548 mask addressing.
549 Add EMAC instructions, fix MAC instructions. Remove
550 macmw/macml/msacmw/msacml instructions since mask addressing now
551 supported.
552
5532004-04-20 Jakub Jelinek <jakub@redhat.com>
554
555 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
556 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
557 suffix. Use fmov*x macros, create all 3 fpsize variants in one
558 macro. Adjust all users.
559
5602004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
561
562 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
563 separately.
564
5652004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
566
567 * m32r-asm.c: Regenerate.
568
5692004-03-29 Stan Shebs <shebs@apple.com>
570
571 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
572 used.
573
5742004-03-19 Alan Modra <amodra@bigpond.net.au>
575
576 * aclocal.m4: Regenerate.
577 * config.in: Regenerate.
578 * configure: Regenerate.
579 * po/POTFILES.in: Regenerate.
580 * po/opcodes.pot: Regenerate.
581
5822004-03-16 Alan Modra <amodra@bigpond.net.au>
583
584 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
585 PPC_OPERANDS_GPR_0.
586 * ppc-opc.c (RA0): Define.
587 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
588 (RAOPT): Rename from RAO. Update all uses.
589 (powerpc_opcodes): Use RA0 as appropriate.
590
5912004-03-15 Aldy Hernandez <aldyh@redhat.com>
592
593 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
594
5952004-03-15 Alan Modra <amodra@bigpond.net.au>
596
597 * sparc-dis.c (print_insn_sparc): Update getword prototype.
598
5992004-03-12 Michal Ludvig <mludvig@suse.cz>
600
601 * i386-dis.c (GRPPLOCK): Delete.
602 (grps): Delete GRPPLOCK entry.
603
6042004-03-12 Alan Modra <amodra@bigpond.net.au>
605
606 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
607 (M, Mp): Use OP_M.
608 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
609 (GRPPADLCK): Define.
610 (dis386): Use NOP_Fixup on "nop".
611 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
612 (twobyte_has_modrm): Set for 0xa7.
613 (padlock_table): Delete. Move to..
614 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
615 and clflush.
616 (print_insn): Revert PADLOCK_SPECIAL code.
617 (OP_E): Delete sfence, lfence, mfence checks.
618
6192004-03-12 Jakub Jelinek <jakub@redhat.com>
620
621 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
622 (INVLPG_Fixup): New function.
623 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
624
6252004-03-12 Michal Ludvig <mludvig@suse.cz>
626
627 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
628 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
629 (padlock_table): New struct with PadLock instructions.
630 (print_insn): Handle PADLOCK_SPECIAL.
631
6322004-03-12 Alan Modra <amodra@bigpond.net.au>
633
634 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
635 (OP_E): Twiddle clflush to sfence here.
636
6372004-03-08 Nick Clifton <nickc@redhat.com>
638
639 * po/de.po: Updated German translation.
640
6412003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
642
643 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
644 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
645 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
646 accordingly.
647
6482004-03-01 Richard Sandiford <rsandifo@redhat.com>
649
650 * frv-asm.c: Regenerate.
651 * frv-desc.c: Regenerate.
652 * frv-desc.h: Regenerate.
653 * frv-dis.c: Regenerate.
654 * frv-ibld.c: Regenerate.
655 * frv-opc.c: Regenerate.
656 * frv-opc.h: Regenerate.
657
6582004-03-01 Richard Sandiford <rsandifo@redhat.com>
659
660 * frv-desc.c, frv-opc.c: Regenerate.
661
6622004-03-01 Richard Sandiford <rsandifo@redhat.com>
663
664 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
665
6662004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
667
668 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
669 Also correct mistake in the comment.
670
6712004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
672
673 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
674 ensure that double registers have even numbers.
675 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
676 that reserved instruction 0xfffd does not decode the same
677 as 0xfdfd (ftrv).
678 * sh-opc.h: Add REG_N_D nibble type and use it whereever
679 REG_N refers to a double register.
680 Add REG_N_B01 nibble type and use it instead of REG_NM
681 in ftrv.
682 Adjust the bit patterns in a few comments.
683
6842004-02-25 Aldy Hernandez <aldyh@redhat.com>
685
686 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
687
6882004-02-20 Aldy Hernandez <aldyh@redhat.com>
689
690 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
691
6922004-02-20 Aldy Hernandez <aldyh@redhat.com>
693
694 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
695
6962004-02-20 Aldy Hernandez <aldyh@redhat.com>
697
698 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
699 mtivor32, mtivor33, mtivor34.
700
7012004-02-19 Aldy Hernandez <aldyh@redhat.com>
702
703 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
704
7052004-02-10 Petko Manolov <petkan@nucleusys.com>
706
707 * arm-opc.h Maverick accumulator register opcode fixes.
708
7092004-02-13 Ben Elliston <bje@wasabisystems.com>
710
711 * m32r-dis.c: Regenerate.
712
7132004-01-27 Michael Snyder <msnyder@redhat.com>
714
715 * sh-opc.h (sh_table): "fsrra", not "fssra".
716
7172004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
718
719 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
720 contraints.
721
7222004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
723
724 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
725
7262004-01-19 Alan Modra <amodra@bigpond.net.au>
727
728 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
729 1. Don't print scale factor on AT&T mode when index missing.
730
7312004-01-16 Alexandre Oliva <aoliva@redhat.com>
732
733 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
734 when loaded into XR registers.
735
7362004-01-14 Richard Sandiford <rsandifo@redhat.com>
737
738 * frv-desc.h: Regenerate.
739 * frv-desc.c: Regenerate.
740 * frv-opc.c: Regenerate.
741
7422004-01-13 Michael Snyder <msnyder@redhat.com>
743
744 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
745
7462004-01-09 Paul Brook <paul@codesourcery.com>
747
748 * arm-opc.h (arm_opcodes): Move generic mcrr after known
749 specific opcodes.
750
7512004-01-07 Daniel Jacobowitz <drow@mvista.com>
752
753 * Makefile.am (libopcodes_la_DEPENDENCIES)
754 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
755 comment about the problem.
756 * Makefile.in: Regenerate.
757
7582004-01-06 Alexandre Oliva <aoliva@redhat.com>
759
760 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
761 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
762 cut&paste errors in shifting/truncating numerical operands.
763 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
764 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
765 (parse_uslo16): Likewise.
766 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
767 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
768 (parse_s12): Likewise.
769 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
770 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
771 (parse_uslo16): Likewise.
772 (parse_uhi16): Parse gothi and gotfuncdeschi.
773 (parse_d12): Parse got12 and gotfuncdesc12.
774 (parse_s12): Likewise.
775
7762004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
777
778 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
779 instruction which looks similar to an 'rla' instruction.
780
781For older changes see ChangeLog-0203
782\f
783Local Variables:
784mode: change-log
785left-margin: 8
786fill-column: 74
787version-control: never
788End:
GDB Binutils - Deliverables
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