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PR26011, excessive memory allocation with fuzzed reloc sections
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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12020-05-19 Stafford Horne <shorne@gmail.com>
2
3 PR 25184
4 * or1k-asm.c: Regenerate.
5 * or1k-desc.c: Regenerate.
6 * or1k-desc.h: Regenerate.
7 * or1k-dis.c: Regenerate.
8 * or1k-ibld.c: Regenerate.
9 * or1k-opc.c: Regenerate.
10 * or1k-opc.h: Regenerate.
11 * or1k-opinst.c: Regenerate.
12
132020-05-11 Alan Modra <amodra@gmail.com>
14
15 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
16 xsmaxcqp, xsmincqp.
17
182020-05-11 Alan Modra <amodra@gmail.com>
19
20 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
21 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
22
232020-05-11 Alan Modra <amodra@gmail.com>
24
25 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
26
272020-05-11 Alan Modra <amodra@gmail.com>
28
29 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
30 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
31
322020-05-11 Peter Bergner <bergner@linux.ibm.com>
33
34 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
35 mnemonics.
36
372020-05-11 Alan Modra <amodra@gmail.com>
38
39 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
40 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
41 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
42 (prefix_opcodes): Add xxeval.
43
442020-05-11 Alan Modra <amodra@gmail.com>
45
46 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
47 xxgenpcvwm, xxgenpcvdm.
48
492020-05-11 Alan Modra <amodra@gmail.com>
50
51 * ppc-opc.c (MP, VXVAM_MASK): Define.
52 (VXVAPS_MASK): Use VXVA_MASK.
53 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
54 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
55 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
56 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
57
582020-05-11 Alan Modra <amodra@gmail.com>
59 Peter Bergner <bergner@linux.ibm.com>
60
61 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
62 New functions.
63 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
64 YMSK2, XA6a, XA6ap, XB6a entries.
65 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
66 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
67 (PPCVSX4): Define.
68 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
69 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
70 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
71 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
72 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
73 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
74 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
75 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
76 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
77 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
78 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
79 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
80 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
81 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
82
832020-05-11 Alan Modra <amodra@gmail.com>
84
85 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
86 (insert_xts, extract_xts): New functions.
87 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
88 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
89 (VXRC_MASK, VXSH_MASK): Define.
90 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
91 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
92 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
93 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
94 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
95 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
96 xxblendvh, xxblendvw, xxblendvd, xxpermx.
97
982020-05-11 Alan Modra <amodra@gmail.com>
99
100 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
101 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
102 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
103 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
104 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
105
1062020-05-11 Alan Modra <amodra@gmail.com>
107
108 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
109 (XTP, DQXP, DQXP_MASK): Define.
110 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
111 (prefix_opcodes): Add plxvp and pstxvp.
112
1132020-05-11 Alan Modra <amodra@gmail.com>
114
115 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
116 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
117 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
118
1192020-05-11 Peter Bergner <bergner@linux.ibm.com>
120
121 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
122
1232020-05-11 Peter Bergner <bergner@linux.ibm.com>
124
125 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
126 (L1OPT): Define.
127 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
128
1292020-05-11 Peter Bergner <bergner@linux.ibm.com>
130
131 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
132
1332020-05-11 Alan Modra <amodra@gmail.com>
134
135 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
136
1372020-05-11 Alan Modra <amodra@gmail.com>
138
139 * ppc-dis.c (ppc_opts): Add "power10" entry.
140 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
141 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
142
1432020-05-11 Nick Clifton <nickc@redhat.com>
144
145 * po/fr.po: Updated French translation.
146
1472020-04-30 Alex Coplan <alex.coplan@arm.com>
148
149 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
150 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
151 (operand_general_constraint_met_p): validate
152 AARCH64_OPND_UNDEFINED.
153 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
154 for FLD_imm16_2.
155 * aarch64-asm-2.c: Regenerated.
156 * aarch64-dis-2.c: Regenerated.
157 * aarch64-opc-2.c: Regenerated.
158
1592020-04-29 Nick Clifton <nickc@redhat.com>
160
161 PR 22699
162 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
163 and SETRC insns.
164
1652020-04-29 Nick Clifton <nickc@redhat.com>
166
167 * po/sv.po: Updated Swedish translation.
168
1692020-04-29 Nick Clifton <nickc@redhat.com>
170
171 PR 22699
172 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
173 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
174 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
175 IMM0_8U case.
176
1772020-04-21 Andreas Schwab <schwab@linux-m68k.org>
178
179 PR 25848
180 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
181 cmpi only on m68020up and cpu32.
182
1832020-04-20 Sudakshina Das <sudi.das@arm.com>
184
185 * aarch64-asm.c (aarch64_ins_none): New.
186 * aarch64-asm.h (ins_none): New declaration.
187 * aarch64-dis.c (aarch64_ext_none): New.
188 * aarch64-dis.h (ext_none): New declaration.
189 * aarch64-opc.c (aarch64_print_operand): Update case for
190 AARCH64_OPND_BARRIER_PSB.
191 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
192 (AARCH64_OPERANDS): Update inserter/extracter for
193 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
194 * aarch64-asm-2.c: Regenerated.
195 * aarch64-dis-2.c: Regenerated.
196 * aarch64-opc-2.c: Regenerated.
197
1982020-04-20 Sudakshina Das <sudi.das@arm.com>
199
200 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
201 (aarch64_feature_ras, RAS): Likewise.
202 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
203 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
204 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
205 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
206 * aarch64-asm-2.c: Regenerated.
207 * aarch64-dis-2.c: Regenerated.
208 * aarch64-opc-2.c: Regenerated.
209
2102020-04-17 Fredrik Strupe <fredrik@strupe.net>
211
212 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
213 (print_insn_neon): Support disassembly of conditional
214 instructions.
215
2162020-02-16 David Faust <david.faust@oracle.com>
217
218 * bpf-desc.c: Regenerate.
219 * bpf-desc.h: Likewise.
220 * bpf-opc.c: Regenerate.
221 * bpf-opc.h: Likewise.
222
2232020-04-07 Lili Cui <lili.cui@intel.com>
224
225 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
226 (prefix_table): New instructions (see prefixes above).
227 (rm_table): Likewise
228 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
229 CPU_ANY_TSXLDTRK_FLAGS.
230 (cpu_flags): Add CpuTSXLDTRK.
231 * i386-opc.h (enum): Add CpuTSXLDTRK.
232 (i386_cpu_flags): Add cputsxldtrk.
233 * i386-opc.tbl: Add XSUSPLDTRK insns.
234 * i386-init.h: Regenerate.
235 * i386-tbl.h: Likewise.
236
2372020-04-02 Lili Cui <lili.cui@intel.com>
238
239 * i386-dis.c (prefix_table): New instructions serialize.
240 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
241 CPU_ANY_SERIALIZE_FLAGS.
242 (cpu_flags): Add CpuSERIALIZE.
243 * i386-opc.h (enum): Add CpuSERIALIZE.
244 (i386_cpu_flags): Add cpuserialize.
245 * i386-opc.tbl: Add SERIALIZE insns.
246 * i386-init.h: Regenerate.
247 * i386-tbl.h: Likewise.
248
2492020-03-26 Alan Modra <amodra@gmail.com>
250
251 * disassemble.h (opcodes_assert): Declare.
252 (OPCODES_ASSERT): Define.
253 * disassemble.c: Don't include assert.h. Include opintl.h.
254 (opcodes_assert): New function.
255 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
256 (bfd_h8_disassemble): Reduce size of data array. Correctly
257 calculate maxlen. Omit insn decoding when insn length exceeds
258 maxlen. Exit from nibble loop when looking for E, before
259 accessing next data byte. Move processing of E outside loop.
260 Replace tests of maxlen in loop with assertions.
261
2622020-03-26 Alan Modra <amodra@gmail.com>
263
264 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
265
2662020-03-25 Alan Modra <amodra@gmail.com>
267
268 * z80-dis.c (suffix): Init mybuf.
269
2702020-03-22 Alan Modra <amodra@gmail.com>
271
272 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
273 successflly read from section.
274
2752020-03-22 Alan Modra <amodra@gmail.com>
276
277 * arc-dis.c (find_format): Use ISO C string concatenation rather
278 than line continuation within a string. Don't access needs_limm
279 before testing opcode != NULL.
280
2812020-03-22 Alan Modra <amodra@gmail.com>
282
283 * ns32k-dis.c (print_insn_arg): Update comment.
284 (print_insn_ns32k): Reduce size of index_offset array, and
285 initialize, passing -1 to print_insn_arg for args that are not
286 an index. Don't exit arg loop early. Abort on bad arg number.
287
2882020-03-22 Alan Modra <amodra@gmail.com>
289
290 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
291 * s12z-opc.c: Formatting.
292 (operands_f): Return an int.
293 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
294 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
295 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
296 (exg_sex_discrim): Likewise.
297 (create_immediate_operand, create_bitfield_operand),
298 (create_register_operand_with_size, create_register_all_operand),
299 (create_register_all16_operand, create_simple_memory_operand),
300 (create_memory_operand, create_memory_auto_operand): Don't
301 segfault on malloc failure.
302 (z_ext24_decode): Return an int status, negative on fail, zero
303 on success.
304 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
305 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
306 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
307 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
308 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
309 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
310 (loop_primitive_decode, shift_decode, psh_pul_decode),
311 (bit_field_decode): Similarly.
312 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
313 to return value, update callers.
314 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
315 Don't segfault on NULL operand.
316 (decode_operation): Return OP_INVALID on first fail.
317 (decode_s12z): Check all reads, returning -1 on fail.
318
3192020-03-20 Alan Modra <amodra@gmail.com>
320
321 * metag-dis.c (print_insn_metag): Don't ignore status from
322 read_memory_func.
323
3242020-03-20 Alan Modra <amodra@gmail.com>
325
326 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
327 Initialize parts of buffer not written when handling a possible
328 2-byte insn at end of section. Don't attempt decoding of such
329 an insn by the 4-byte machinery.
330
3312020-03-20 Alan Modra <amodra@gmail.com>
332
333 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
334 partially filled buffer. Prevent lookup of 4-byte insns when
335 only VLE 2-byte insns are possible due to section size. Print
336 ".word" rather than ".long" for 2-byte leftovers.
337
3382020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
339
340 PR 25641
341 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
342
3432020-03-13 Jan Beulich <jbeulich@suse.com>
344
345 * i386-dis.c (X86_64_0D): Rename to ...
346 (X86_64_0E): ... this.
347
3482020-03-09 H.J. Lu <hongjiu.lu@intel.com>
349
350 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
351 * Makefile.in: Regenerated.
352
3532020-03-09 Jan Beulich <jbeulich@suse.com>
354
355 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
356 3-operand pseudos.
357 * i386-tbl.h: Re-generate.
358
3592020-03-09 Jan Beulich <jbeulich@suse.com>
360
361 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
362 vprot*, vpsha*, and vpshl*.
363 * i386-tbl.h: Re-generate.
364
3652020-03-09 Jan Beulich <jbeulich@suse.com>
366
367 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
368 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
369 * i386-tbl.h: Re-generate.
370
3712020-03-09 Jan Beulich <jbeulich@suse.com>
372
373 * i386-gen.c (set_bitfield): Ignore zero-length field names.
374 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
375 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
376 * i386-tbl.h: Re-generate.
377
3782020-03-09 Jan Beulich <jbeulich@suse.com>
379
380 * i386-gen.c (struct template_arg, struct template_instance,
381 struct template_param, struct template, templates,
382 parse_template, expand_templates): New.
383 (process_i386_opcodes): Various local variables moved to
384 expand_templates. Call parse_template and expand_templates.
385 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
386 * i386-tbl.h: Re-generate.
387
3882020-03-06 Jan Beulich <jbeulich@suse.com>
389
390 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
391 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
392 register and memory source templates. Replace VexW= by VexW*
393 where applicable.
394 * i386-tbl.h: Re-generate.
395
3962020-03-06 Jan Beulich <jbeulich@suse.com>
397
398 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
399 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
400 * i386-tbl.h: Re-generate.
401
4022020-03-06 Jan Beulich <jbeulich@suse.com>
403
404 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
405 * i386-tbl.h: Re-generate.
406
4072020-03-06 Jan Beulich <jbeulich@suse.com>
408
409 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
410 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
411 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
412 VexW0 on SSE2AVX variants.
413 (vmovq): Drop NoRex64 from XMM/XMM variants.
414 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
415 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
416 applicable use VexW0.
417 * i386-tbl.h: Re-generate.
418
4192020-03-06 Jan Beulich <jbeulich@suse.com>
420
421 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
422 * i386-opc.h (Rex64): Delete.
423 (struct i386_opcode_modifier): Remove rex64 field.
424 * i386-opc.tbl (crc32): Drop Rex64.
425 Replace Rex64 with Size64 everywhere else.
426 * i386-tbl.h: Re-generate.
427
4282020-03-06 Jan Beulich <jbeulich@suse.com>
429
430 * i386-dis.c (OP_E_memory): Exclude recording of used address
431 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
432 addressed memory operands for MPX insns.
433
4342020-03-06 Jan Beulich <jbeulich@suse.com>
435
436 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
437 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
438 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
439 (ptwrite): Split into non-64-bit and 64-bit forms.
440 * i386-tbl.h: Re-generate.
441
4422020-03-06 Jan Beulich <jbeulich@suse.com>
443
444 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
445 template.
446 * i386-tbl.h: Re-generate.
447
4482020-03-04 Jan Beulich <jbeulich@suse.com>
449
450 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
451 (prefix_table): Move vmmcall here. Add vmgexit.
452 (rm_table): Replace vmmcall entry by prefix_table[] escape.
453 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
454 (cpu_flags): Add CpuSEV_ES entry.
455 * i386-opc.h (CpuSEV_ES): New.
456 (union i386_cpu_flags): Add cpusev_es field.
457 * i386-opc.tbl (vmgexit): New.
458 * i386-init.h, i386-tbl.h: Re-generate.
459
4602020-03-03 H.J. Lu <hongjiu.lu@intel.com>
461
462 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
463 with MnemonicSize.
464 * i386-opc.h (IGNORESIZE): New.
465 (DEFAULTSIZE): Likewise.
466 (IgnoreSize): Removed.
467 (DefaultSize): Likewise.
468 (MnemonicSize): New.
469 (i386_opcode_modifier): Replace ignoresize/defaultsize with
470 mnemonicsize.
471 * i386-opc.tbl (IgnoreSize): New.
472 (DefaultSize): Likewise.
473 * i386-tbl.h: Regenerated.
474
4752020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
476
477 PR 25627
478 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
479 instructions.
480
4812020-03-03 H.J. Lu <hongjiu.lu@intel.com>
482
483 PR gas/25622
484 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
485 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
486 * i386-tbl.h: Regenerated.
487
4882020-02-26 Alan Modra <amodra@gmail.com>
489
490 * aarch64-asm.c: Indent labels correctly.
491 * aarch64-dis.c: Likewise.
492 * aarch64-gen.c: Likewise.
493 * aarch64-opc.c: Likewise.
494 * alpha-dis.c: Likewise.
495 * i386-dis.c: Likewise.
496 * nds32-asm.c: Likewise.
497 * nfp-dis.c: Likewise.
498 * visium-dis.c: Likewise.
499
5002020-02-25 Claudiu Zissulescu <claziss@gmail.com>
501
502 * arc-regs.h (int_vector_base): Make it available for all ARC
503 CPUs.
504
5052020-02-20 Nelson Chu <nelson.chu@sifive.com>
506
507 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
508 changed.
509
5102020-02-19 Nelson Chu <nelson.chu@sifive.com>
511
512 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
513 c.mv/c.li if rs1 is zero.
514
5152020-02-17 H.J. Lu <hongjiu.lu@intel.com>
516
517 * i386-gen.c (cpu_flag_init): Replace CpuABM with
518 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
519 CPU_POPCNT_FLAGS.
520 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
521 * i386-opc.h (CpuABM): Removed.
522 (CpuPOPCNT): New.
523 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
524 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
525 popcnt. Remove CpuABM from lzcnt.
526 * i386-init.h: Regenerated.
527 * i386-tbl.h: Likewise.
528
5292020-02-17 Jan Beulich <jbeulich@suse.com>
530
531 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
532 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
533 VexW1 instead of open-coding them.
534 * i386-tbl.h: Re-generate.
535
5362020-02-17 Jan Beulich <jbeulich@suse.com>
537
538 * i386-opc.tbl (AddrPrefixOpReg): Define.
539 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
540 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
541 templates. Drop NoRex64.
542 * i386-tbl.h: Re-generate.
543
5442020-02-17 Jan Beulich <jbeulich@suse.com>
545
546 PR gas/6518
547 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
548 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
549 into Intel syntax instance (with Unpsecified) and AT&T one
550 (without).
551 (vcvtneps2bf16): Likewise, along with folding the two so far
552 separate ones.
553 * i386-tbl.h: Re-generate.
554
5552020-02-16 H.J. Lu <hongjiu.lu@intel.com>
556
557 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
558 CPU_ANY_SSE4A_FLAGS.
559
5602020-02-17 Alan Modra <amodra@gmail.com>
561
562 * i386-gen.c (cpu_flag_init): Correct last change.
563
5642020-02-16 H.J. Lu <hongjiu.lu@intel.com>
565
566 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
567 CPU_ANY_SSE4_FLAGS.
568
5692020-02-14 H.J. Lu <hongjiu.lu@intel.com>
570
571 * i386-opc.tbl (movsx): Remove Intel syntax comments.
572 (movzx): Likewise.
573
5742020-02-14 Jan Beulich <jbeulich@suse.com>
575
576 PR gas/25438
577 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
578 destination for Cpu64-only variant.
579 (movzx): Fold patterns.
580 * i386-tbl.h: Re-generate.
581
5822020-02-13 Jan Beulich <jbeulich@suse.com>
583
584 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
585 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
586 CPU_ANY_SSE4_FLAGS entry.
587 * i386-init.h: Re-generate.
588
5892020-02-12 Jan Beulich <jbeulich@suse.com>
590
591 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
592 with Unspecified, making the present one AT&T syntax only.
593 * i386-tbl.h: Re-generate.
594
5952020-02-12 Jan Beulich <jbeulich@suse.com>
596
597 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
598 * i386-tbl.h: Re-generate.
599
6002020-02-12 Jan Beulich <jbeulich@suse.com>
601
602 PR gas/24546
603 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
604 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
605 Amd64 and Intel64 templates.
606 (call, jmp): Likewise for far indirect variants. Dro
607 Unspecified.
608 * i386-tbl.h: Re-generate.
609
6102020-02-11 Jan Beulich <jbeulich@suse.com>
611
612 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
613 * i386-opc.h (ShortForm): Delete.
614 (struct i386_opcode_modifier): Remove shortform field.
615 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
616 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
617 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
618 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
619 Drop ShortForm.
620 * i386-tbl.h: Re-generate.
621
6222020-02-11 Jan Beulich <jbeulich@suse.com>
623
624 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
625 fucompi): Drop ShortForm from operand-less templates.
626 * i386-tbl.h: Re-generate.
627
6282020-02-11 Alan Modra <amodra@gmail.com>
629
630 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
631 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
632 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
633 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
634 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
635
6362020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
637
638 * arm-dis.c (print_insn_cde): Define 'V' parse character.
639 (cde_opcodes): Add VCX* instructions.
640
6412020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
642 Matthew Malcomson <matthew.malcomson@arm.com>
643
644 * arm-dis.c (struct cdeopcode32): New.
645 (CDE_OPCODE): New macro.
646 (cde_opcodes): New disassembly table.
647 (regnames): New option to table.
648 (cde_coprocs): New global variable.
649 (print_insn_cde): New
650 (print_insn_thumb32): Use print_insn_cde.
651 (parse_arm_disassembler_options): Parse coprocN args.
652
6532020-02-10 H.J. Lu <hongjiu.lu@intel.com>
654
655 PR gas/25516
656 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
657 with ISA64.
658 * i386-opc.h (AMD64): Removed.
659 (Intel64): Likewose.
660 (AMD64): New.
661 (INTEL64): Likewise.
662 (INTEL64ONLY): Likewise.
663 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
664 * i386-opc.tbl (Amd64): New.
665 (Intel64): Likewise.
666 (Intel64Only): Likewise.
667 Replace AMD64 with Amd64. Update sysenter/sysenter with
668 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
669 * i386-tbl.h: Regenerated.
670
6712020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
672
673 PR 25469
674 * z80-dis.c: Add support for GBZ80 opcodes.
675
6762020-02-04 Alan Modra <amodra@gmail.com>
677
678 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
679
6802020-02-03 Alan Modra <amodra@gmail.com>
681
682 * m32c-ibld.c: Regenerate.
683
6842020-02-01 Alan Modra <amodra@gmail.com>
685
686 * frv-ibld.c: Regenerate.
687
6882020-01-31 Jan Beulich <jbeulich@suse.com>
689
690 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
691 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
692 (OP_E_memory): Replace xmm_mdq_mode case label by
693 vex_scalar_w_dq_mode one.
694 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
695
6962020-01-31 Jan Beulich <jbeulich@suse.com>
697
698 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
699 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
700 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
701 (intel_operand_size): Drop vex_w_dq_mode case label.
702
7032020-01-31 Richard Sandiford <richard.sandiford@arm.com>
704
705 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
706 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
707
7082020-01-30 Alan Modra <amodra@gmail.com>
709
710 * m32c-ibld.c: Regenerate.
711
7122020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
713
714 * bpf-opc.c: Regenerate.
715
7162020-01-30 Jan Beulich <jbeulich@suse.com>
717
718 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
719 (dis386): Use them to replace C2/C3 table entries.
720 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
721 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
722 ones. Use Size64 instead of DefaultSize on Intel64 ones.
723 * i386-tbl.h: Re-generate.
724
7252020-01-30 Jan Beulich <jbeulich@suse.com>
726
727 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
728 forms.
729 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
730 DefaultSize.
731 * i386-tbl.h: Re-generate.
732
7332020-01-30 Alan Modra <amodra@gmail.com>
734
735 * tic4x-dis.c (tic4x_dp): Make unsigned.
736
7372020-01-27 H.J. Lu <hongjiu.lu@intel.com>
738 Jan Beulich <jbeulich@suse.com>
739
740 PR binutils/25445
741 * i386-dis.c (MOVSXD_Fixup): New function.
742 (movsxd_mode): New enum.
743 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
744 (intel_operand_size): Handle movsxd_mode.
745 (OP_E_register): Likewise.
746 (OP_G): Likewise.
747 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
748 register on movsxd. Add movsxd with 16-bit destination register
749 for AMD64 and Intel64 ISAs.
750 * i386-tbl.h: Regenerated.
751
7522020-01-27 Tamar Christina <tamar.christina@arm.com>
753
754 PR 25403
755 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
756 * aarch64-asm-2.c: Regenerate
757 * aarch64-dis-2.c: Likewise.
758 * aarch64-opc-2.c: Likewise.
759
7602020-01-21 Jan Beulich <jbeulich@suse.com>
761
762 * i386-opc.tbl (sysret): Drop DefaultSize.
763 * i386-tbl.h: Re-generate.
764
7652020-01-21 Jan Beulich <jbeulich@suse.com>
766
767 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
768 Dword.
769 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
770 * i386-tbl.h: Re-generate.
771
7722020-01-20 Nick Clifton <nickc@redhat.com>
773
774 * po/de.po: Updated German translation.
775 * po/pt_BR.po: Updated Brazilian Portuguese translation.
776 * po/uk.po: Updated Ukranian translation.
777
7782020-01-20 Alan Modra <amodra@gmail.com>
779
780 * hppa-dis.c (fput_const): Remove useless cast.
781
7822020-01-20 Alan Modra <amodra@gmail.com>
783
784 * arm-dis.c (print_insn_arm): Wrap 'T' value.
785
7862020-01-18 Nick Clifton <nickc@redhat.com>
787
788 * configure: Regenerate.
789 * po/opcodes.pot: Regenerate.
790
7912020-01-18 Nick Clifton <nickc@redhat.com>
792
793 Binutils 2.34 branch created.
794
7952020-01-17 Christian Biesinger <cbiesinger@google.com>
796
797 * opintl.h: Fix spelling error (seperate).
798
7992020-01-17 H.J. Lu <hongjiu.lu@intel.com>
800
801 * i386-opc.tbl: Add {vex} pseudo prefix.
802 * i386-tbl.h: Regenerated.
803
8042020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
805
806 PR 25376
807 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
808 (neon_opcodes): Likewise.
809 (select_arm_features): Make sure we enable MVE bits when selecting
810 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
811 any architecture.
812
8132020-01-16 Jan Beulich <jbeulich@suse.com>
814
815 * i386-opc.tbl: Drop stale comment from XOP section.
816
8172020-01-16 Jan Beulich <jbeulich@suse.com>
818
819 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
820 (extractps): Add VexWIG to SSE2AVX forms.
821 * i386-tbl.h: Re-generate.
822
8232020-01-16 Jan Beulich <jbeulich@suse.com>
824
825 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
826 Size64 from and use VexW1 on SSE2AVX forms.
827 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
828 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
829 * i386-tbl.h: Re-generate.
830
8312020-01-15 Alan Modra <amodra@gmail.com>
832
833 * tic4x-dis.c (tic4x_version): Make unsigned long.
834 (optab, optab_special, registernames): New file scope vars.
835 (tic4x_print_register): Set up registernames rather than
836 malloc'd registertable.
837 (tic4x_disassemble): Delete optable and optable_special. Use
838 optab and optab_special instead. Throw away old optab,
839 optab_special and registernames when info->mach changes.
840
8412020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
842
843 PR 25377
844 * z80-dis.c (suffix): Use .db instruction to generate double
845 prefix.
846
8472020-01-14 Alan Modra <amodra@gmail.com>
848
849 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
850 values to unsigned before shifting.
851
8522020-01-13 Thomas Troeger <tstroege@gmx.de>
853
854 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
855 flow instructions.
856 (print_insn_thumb16, print_insn_thumb32): Likewise.
857 (print_insn): Initialize the insn info.
858 * i386-dis.c (print_insn): Initialize the insn info fields, and
859 detect jumps.
860
8612012-01-13 Claudiu Zissulescu <claziss@gmail.com>
862
863 * arc-opc.c (C_NE): Make it required.
864
8652012-01-13 Claudiu Zissulescu <claziss@gmail.com>
866
867 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
868 reserved register name.
869
8702020-01-13 Alan Modra <amodra@gmail.com>
871
872 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
873 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
874
8752020-01-13 Alan Modra <amodra@gmail.com>
876
877 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
878 result of wasm_read_leb128 in a uint64_t and check that bits
879 are not lost when copying to other locals. Use uint32_t for
880 most locals. Use PRId64 when printing int64_t.
881
8822020-01-13 Alan Modra <amodra@gmail.com>
883
884 * score-dis.c: Formatting.
885 * score7-dis.c: Formatting.
886
8872020-01-13 Alan Modra <amodra@gmail.com>
888
889 * score-dis.c (print_insn_score48): Use unsigned variables for
890 unsigned values. Don't left shift negative values.
891 (print_insn_score32): Likewise.
892 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
893
8942020-01-13 Alan Modra <amodra@gmail.com>
895
896 * tic4x-dis.c (tic4x_print_register): Remove dead code.
897
8982020-01-13 Alan Modra <amodra@gmail.com>
899
900 * fr30-ibld.c: Regenerate.
901
9022020-01-13 Alan Modra <amodra@gmail.com>
903
904 * xgate-dis.c (print_insn): Don't left shift signed value.
905 (ripBits): Formatting, use 1u.
906
9072020-01-10 Alan Modra <amodra@gmail.com>
908
909 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
910 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
911
9122020-01-10 Alan Modra <amodra@gmail.com>
913
914 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
915 and XRREG value earlier to avoid a shift with negative exponent.
916 * m10200-dis.c (disassemble): Similarly.
917
9182020-01-09 Nick Clifton <nickc@redhat.com>
919
920 PR 25224
921 * z80-dis.c (ld_ii_ii): Use correct cast.
922
9232020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
924
925 PR 25224
926 * z80-dis.c (ld_ii_ii): Use character constant when checking
927 opcode byte value.
928
9292020-01-09 Jan Beulich <jbeulich@suse.com>
930
931 * i386-dis.c (SEP_Fixup): New.
932 (SEP): Define.
933 (dis386_twobyte): Use it for sysenter/sysexit.
934 (enum x86_64_isa): Change amd64 enumerator to value 1.
935 (OP_J): Compare isa64 against intel64 instead of amd64.
936 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
937 forms.
938 * i386-tbl.h: Re-generate.
939
9402020-01-08 Alan Modra <amodra@gmail.com>
941
942 * z8k-dis.c: Include libiberty.h
943 (instr_data_s): Make max_fetched unsigned.
944 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
945 Don't exceed byte_info bounds.
946 (output_instr): Make num_bytes unsigned.
947 (unpack_instr): Likewise for nibl_count and loop.
948 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
949 idx unsigned.
950 * z8k-opc.h: Regenerate.
951
9522020-01-07 Shahab Vahedi <shahab@synopsys.com>
953
954 * arc-tbl.h (llock): Use 'LLOCK' as class.
955 (llockd): Likewise.
956 (scond): Use 'SCOND' as class.
957 (scondd): Likewise.
958 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
959 (scondd): Likewise.
960
9612020-01-06 Alan Modra <amodra@gmail.com>
962
963 * m32c-ibld.c: Regenerate.
964
9652020-01-06 Alan Modra <amodra@gmail.com>
966
967 PR 25344
968 * z80-dis.c (suffix): Don't use a local struct buffer copy.
969 Peek at next byte to prevent recursion on repeated prefix bytes.
970 Ensure uninitialised "mybuf" is not accessed.
971 (print_insn_z80): Don't zero n_fetch and n_used here,..
972 (print_insn_z80_buf): ..do it here instead.
973
9742020-01-04 Alan Modra <amodra@gmail.com>
975
976 * m32r-ibld.c: Regenerate.
977
9782020-01-04 Alan Modra <amodra@gmail.com>
979
980 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
981
9822020-01-04 Alan Modra <amodra@gmail.com>
983
984 * crx-dis.c (match_opcode): Avoid shift left of signed value.
985
9862020-01-04 Alan Modra <amodra@gmail.com>
987
988 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
989
9902020-01-03 Jan Beulich <jbeulich@suse.com>
991
992 * aarch64-tbl.h (aarch64_opcode_table): Use
993 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
994
9952020-01-03 Jan Beulich <jbeulich@suse.com>
996
997 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
998 forms of SUDOT and USDOT.
999
10002020-01-03 Jan Beulich <jbeulich@suse.com>
1001
1002 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1003 uzip{1,2}.
1004 * opcodes/aarch64-dis-2.c: Re-generate.
1005
10062020-01-03 Jan Beulich <jbeulich@suse.com>
1007
1008 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1009 FMMLA encoding.
1010 * opcodes/aarch64-dis-2.c: Re-generate.
1011
10122020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1013
1014 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1015
10162020-01-01 Alan Modra <amodra@gmail.com>
1017
1018 Update year range in copyright notice of all files.
1019
1020For older changes see ChangeLog-2019
1021\f
1022Copyright (C) 2020 Free Software Foundation, Inc.
1023
1024Copying and distribution of this file, with or without modification,
1025are permitted in any medium without royalty provided the copyright
1026notice and this notice are preserved.
1027
1028Local Variables:
1029mode: change-log
1030left-margin: 8
1031fill-column: 74
1032version-control: never
1033End:
GDB Binutils - Deliverables
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