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[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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12015-12-14 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64-asm-2.c: Regenerate.
4 * aarch64-dis-2.c: Regenerate.
5 * aarch64-opc-2.c: Regenerate.
6 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
7 fmls, fmul and fmulx to the scalar indexed element group.
8
92015-12-14 Matthew Wahab <matthew.wahab@arm.com>
10
11 * aarch64-asm-2.c: Regenerate.
12 * aarch64-dis-2.c: Regenerate.
13 * aarch64-opc-2.c: Regenerate.
14 * aarch64-tbl.h (QL_ELEMENT_FP_H): New.
15 (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
16 fmulx to the vector indexed element group.
17
182015-12-14 Matthew Wahab <matthew.wahab@arm.com>
19
20 * aarch64-asm-2.c: Regenerate.
21 * aarch64-dis-2.c: Regenerate.
22 * aarch64-opc-2.c: Regenerate.
23 * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
24 (QL_S_2SAMEH): New.
25 (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
26 fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
27 frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
28 fcvtzu and frsqrte to the scalar two register misc. group.
29
302015-12-14 Matthew Wahab <matthew.wahab@arm.com>
31
32 * aarch64-asm-2.c: Regenerate.
33 * aarch64-dis-2.c: Regenerate.
34 * aarch64-opc-2.c: Regenerate.
35 * aarch64-tbl.h (QL_V2SAMEH): New.
36 (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
37 fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
38 frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
39 fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
40 and fsqrt to the vector register misc. group.
41
422015-12-14 Matthew Wahab <matthew.wahab@arm.com>
43
44 * aarch64-asm-2.c: Regenerate.
45 * aarch64-dis-2.c: Regenerate.
46 * aarch64-opc-2.c: Regenerate.
47 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
48 fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
49 to the scalar three same group.
50
512015-12-14 Matthew Wahab <matthew.wahab@arm.com>
52
53 * aarch64-asm-2.c: Regenerate.
54 * aarch64-dis-2.c: Regenerate.
55 * aarch64-opc-2.c: Regenerate.
56 * aarch64-tbl.h (QL_V3SAMEH): New.
57 (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
58 fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
59 fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
60 fcmgt, facgt and fminp to the vector three same group.
61
622015-12-14 Matthew Wahab <matthew.wahab@arm.com>
63
64 * aarch64-tbl.h (aarch64_feature_simd_f16): New.
65 (SIMD_F16): New.
66
672015-12-14 Matthew Wahab <matthew.wahab@arm.com>
68
69 * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
70 removed statement.
71 (aarch64_pstatefield_supported_p): Move feature checks for AT
72 registers ..
73 (aarch64_sys_ins_reg_supported_p): .. to here.
74
752015-12-12 Alan Modra <amodra@gmail.com>
76
77 PR 19359
78 * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
79 (powerpc_opcodes): Remove single-operand mfcr.
80
812015-12-11 Matthew Wahab <matthew.wahab@arm.com>
82
83 * aarch64-asm.c (aarch64_ins_hint): New.
84 * aarch64-asm.h (aarch64_ins_hint): Declare.
85 * aarch64-dis.c (aarch64_ext_hint): New.
86 * aarch64-dis.h (aarch64_ext_hint): Declare.
87 * aarch64-opc-2.c: Regenerate.
88 * aarch64-opc.c (aarch64_hint_options): New.
89 * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
90
912015-12-11 Matthew Wahab <matthew.wahab@arm.com>
92
93 * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
94
952015-12-11 Matthew Wahab <matthew.wahab@arm.com>
96
97 * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
98 pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
99 pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
100 pmscr_el2.
101 (aarch64_sys_reg_supported_p): Add architecture feature tests for
102 the new registers.
103
1042015-12-10 Matthew Wahab <matthew.wahab@arm.com>
105
106 * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
107 (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
108 feature test for "s1e1rp" and "s1e1wp".
109
1102015-12-10 Matthew Wahab <matthew.wahab@arm.com>
111
112 * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
113 (aarch64_sys_ins_reg_supported_p): New.
114
1152015-12-10 Matthew Wahab <matthew.wahab@arm.com>
116
117 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
118 with aarch64_sys_ins_reg_has_xt.
119 (aarch64_ext_sysins_op): Likewise.
120 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
121 (F_HASXT): New.
122 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
123 (aarch64_sys_regs_dc): Likewise.
124 (aarch64_sys_regs_at): Likewise.
125 (aarch64_sys_regs_tlbi): Likewise.
126 (aarch64_sys_ins_reg_has_xt): New.
127
1282015-12-10 Matthew Wahab <matthew.wahab@arm.com>
129
130 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
131 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
132 (aarch64_pstatefields): Add "uao".
133 (aarch64_pstatefield_supported_p): Add checks for "uao".
134
1352015-12-10 Matthew Wahab <matthew.wahab@arm.com>
136
137 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
138 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
139 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
140 (aarch64_sys_reg_supported_p): Add architecture feature tests for
141 new registers.
142
1432015-12-10 Matthew Wahab <matthew.wahab@arm.com>
144
145 * aarch64-asm-2.c: Regenerate.
146 * aarch64-dis-2.c: Regenerate.
147 * aarch64-tbl.h (aarch64_feature_ras): New.
148 (RAS): New.
149 (aarch64_opcode_table): Add "esb".
150
1512015-12-09 H.J. Lu <hongjiu.lu@intel.com>
152
153 * i386-dis.c (MOD_0F01_REG_5): New.
154 (RM_0F01_REG_5): Likewise.
155 (reg_table): Use MOD_0F01_REG_5.
156 (mod_table): Add MOD_0F01_REG_5.
157 (rm_table): Add RM_0F01_REG_5.
158 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
159 (cpu_flags): Add CpuOSPKE.
160 * i386-opc.h (CpuOSPKE): New.
161 (i386_cpu_flags): Add cpuospke.
162 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
163 * i386-init.h: Regenerated.
164 * i386-tbl.h: Likewise.
165
1662015-12-07 DJ Delorie <dj@redhat.com>
167
168 * rl78-decode.opc: Enable MULU for all ISAs.
169 * rl78-decode.c: Regenerate.
170
1712015-12-07 Alan Modra <amodra@gmail.com>
172
173 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
174 major opcode/xop.
175
1762015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
177
178 * arc-dis.c (special_flag_p): Match full mnemonic.
179 * arc-opc.c (print_insn_arc): Check section size to read
180 appropriate number of bytes. Fix printing.
181 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
182 arguments.
183
1842015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
185
186 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
187 <ldah>: ... to this.
188
1892015-11-27 Matthew Wahab <matthew.wahab@arm.com>
190
191 * aarch64-asm-2.c: Regenerate.
192 * aarch64-dis-2.c: Regenerate.
193 * aarch64-opc-2.c: Regenerate.
194 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
195 (QL_INT2FP_H, QL_FP2INT_H): New.
196 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
197 (QL_DST_H): New.
198 (QL_FCCMP_H): New.
199 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
200 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
201 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
202 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
203 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
204 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
205 fcsel.
206
2072015-11-27 Matthew Wahab <matthew.wahab@arm.com>
208
209 * aarch64-opc.c (half_conv_t): New.
210 (expand_fp_imm): Replace is_dp flag with the parameter size to
211 specify the number of bytes for the required expansion. Treat
212 a 16-bit expansion like a 32-bit expansion. Add check for an
213 unsupported size request. Update comment.
214 (aarch64_print_operand): Update to support 16-bit floating point
215 values. Update for changes to expand_fp_imm.
216
2172015-11-27 Matthew Wahab <matthew.wahab@arm.com>
218
219 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
220 (FP_F16): New.
221
2222015-11-27 Matthew Wahab <matthew.wahab@arm.com>
223
224 * aarch64-asm-2.c: Regenerate.
225 * aarch64-dis-2.c: Regenerate.
226 * aarch64-opc-2.c: Regenerate.
227 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
228 "rev64".
229
2302015-11-27 Matthew Wahab <matthew.wahab@arm.com>
231
232 * aarch64-asm-2.c: Regenerate.
233 * aarch64-asm.c (convert_bfc_to_bfm): New.
234 (convert_to_real): Add case for OP_BFC.
235 * aarch64-dis-2.c: Regenerate.
236 * aarch64-dis.c: (convert_bfm_to_bfc): New.
237 (convert_to_alias): Add case for OP_BFC.
238 * aarch64-opc-2.c: Regenerate.
239 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
240 to allow width operand in three-operand instructions.
241 * aarch64-tbl.h (QL_BF1): New.
242 (aarch64_feature_v8_2): New.
243 (ARMV8_2): New.
244 (aarch64_opcode_table): Add "bfc".
245
2462015-11-27 Matthew Wahab <matthew.wahab@arm.com>
247
248 * aarch64-asm-2.c: Regenerate.
249 * aarch64-dis-2.c: Regenerate.
250 * aarch64-dis.c: Weaken assert.
251 * aarch64-gen.c: Include the instruction in the list of its
252 possible aliases.
253
2542015-11-27 Matthew Wahab <matthew.wahab@arm.com>
255
256 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
257 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
258 feature test.
259
2602015-11-23 Tristan Gingold <gingold@adacore.com>
261
262 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
263
2642015-11-20 Matthew Wahab <matthew.wahab@arm.com>
265
266 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
267 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
268 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
269 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
270 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
271 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
272 cnthv_ctl_el2, cnthv_cval_el2.
273 (aarch64_sys_reg_supported_p): Update for the new system
274 registers.
275
2762015-11-20 Nick Clifton <nickc@redhat.com>
277
278 PR binutils/19224
279 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
280
2812015-11-20 Nick Clifton <nickc@redhat.com>
282
283 * po/zh_CN.po: Updated simplified Chinese translation.
284
2852015-11-19 Matthew Wahab <matthew.wahab@arm.com>
286
287 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
288 of MSR PAN immediate operand.
289
2902015-11-16 Nick Clifton <nickc@redhat.com>
291
292 * rx-dis.c (condition_names): Replace always and never with
293 invalid, since the always/never conditions can never be legal.
294
2952015-11-13 Tristan Gingold <gingold@adacore.com>
296
297 * configure: Regenerate.
298
2992015-11-11 Alan Modra <amodra@gmail.com>
300 Peter Bergner <bergner@vnet.ibm.com>
301
302 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
303 Add PPC_OPCODE_VSX3 to the vsx entry.
304 (powerpc_init_dialect): Set default dialect to power9.
305 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
306 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
307 extract_l1 insert_xtq6, extract_xtq6): New static functions.
308 (insert_esync): Test for illegal L operand value.
309 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
310 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
311 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
312 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
313 PPCVSX3): New defines.
314 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
315 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
316 <mcrxr>: Use XBFRARB_MASK.
317 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
318 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
319 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
320 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
321 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
322 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
323 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
324 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
325 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
326 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
327 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
328 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
329 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
330 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
331 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
332 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
333 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
334 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
335 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
336 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
337 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
338 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
339 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
340 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
341 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
342 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
343 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
344 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
345 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
346 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
347 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
348 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
349
3502015-11-02 Nick Clifton <nickc@redhat.com>
351
352 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
353 instructions.
354 * rx-decode.c: Regenerate.
355
3562015-11-02 Nick Clifton <nickc@redhat.com>
357
358 * rx-decode.opc (rx_disp): If the displacement is zero, set the
359 type to RX_Operand_Zero_Indirect.
360 * rx-decode.c: Regenerate.
361 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
362
3632015-10-28 Yao Qi <yao.qi@linaro.org>
364
365 * aarch64-dis.c (aarch64_decode_insn): Add one argument
366 noaliases_p. Update comments. Pass noaliases_p rather than
367 no_aliases to aarch64_opcode_decode.
368 (print_insn_aarch64_word): Pass no_aliases to
369 aarch64_decode_insn.
370
3712015-10-27 Vinay <Vinay.G@kpit.com>
372
373 PR binutils/19159
374 * rl78-decode.opc (MOV): Added offset to DE register in index
375 addressing mode.
376 * rl78-decode.c: Regenerate.
377
3782015-10-27 Vinay Kumar <vinay.g@kpit.com>
379
380 PR binutils/19158
381 * rl78-decode.opc: Add 's' print operator to instructions that
382 access system registers.
383 * rl78-decode.c: Regenerate.
384 * rl78-dis.c (print_insn_rl78_common): Decode all system
385 registers.
386
3872015-10-27 Vinay Kumar <vinay.g@kpit.com>
388
389 PR binutils/19157
390 * rl78-decode.opc: Add 'a' print operator to mov instructions
391 using stack pointer plus index addressing.
392 * rl78-decode.c: Regenerate.
393
3942015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
395
396 * s390-opc.c: Fix comment.
397 * s390-opc.txt: Change instruction type for troo, trot, trto, and
398 trtt to RRF_U0RER since the second parameter does not need to be a
399 register pair.
400
4012015-10-08 Nick Clifton <nickc@redhat.com>
402
403 * arc-dis.c (print_insn_arc): Initiallise insn array.
404
4052015-10-07 Yao Qi <yao.qi@linaro.org>
406
407 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
408 'name' rather than 'template'.
409 * aarch64-opc.c (aarch64_print_operand): Likewise.
410
4112015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
412
413 * arc-dis.c: Revamped file for ARC support
414 * arc-dis.h: Likewise.
415 * arc-ext.c: Likewise.
416 * arc-ext.h: Likewise.
417 * arc-opc.c: Likewise.
418 * arc-fxi.h: New file.
419 * arc-regs.h: Likewise.
420 * arc-tbl.h: Likewise.
421
4222015-10-02 Yao Qi <yao.qi@linaro.org>
423
424 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
425 argument insn type to aarch64_insn. Rename to ...
426 (aarch64_decode_insn): ... it.
427 (print_insn_aarch64_word): Caller updated.
428
4292015-10-02 Yao Qi <yao.qi@linaro.org>
430
431 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
432 (print_insn_aarch64_word): Caller updated.
433
4342015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
435
436 * s390-mkopc.c (main): Parse htm and vx flag.
437 * s390-opc.txt: Mark instructions from the hardware transactional
438 memory and vector facilities with the "htm"/"vx" flag.
439
4402015-09-28 Nick Clifton <nickc@redhat.com>
441
442 * po/de.po: Updated German translation.
443
4442015-09-28 Tom Rix <tom@bumblecow.com>
445
446 * ppc-opc.c (PPC500): Mark some opcodes as invalid
447
4482015-09-23 Nick Clifton <nickc@redhat.com>
449
450 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
451 function.
452 * tic30-dis.c (print_branch): Likewise.
453 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
454 value before left shifting.
455 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
456 * hppa-dis.c (print_insn_hppa): Likewise.
457 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
458 array.
459 * msp430-dis.c (msp430_singleoperand): Likewise.
460 (msp430_doubleoperand): Likewise.
461 (print_insn_msp430): Likewise.
462 * nds32-asm.c (parse_operand): Likewise.
463 * sh-opc.h (MASK): Likewise.
464 * v850-dis.c (get_operand_value): Likewise.
465
4662015-09-22 Nick Clifton <nickc@redhat.com>
467
468 * rx-decode.opc (bwl): Use RX_Bad_Size.
469 (sbwl): Likewise.
470 (ubwl): Likewise. Rename to ubw.
471 (uBWL): Rename to uBW.
472 Replace all references to uBWL with uBW.
473 * rx-decode.c: Regenerate.
474 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
475 (opsize_names): Likewise.
476 (print_insn_rx): Detect and report RX_Bad_Size.
477
4782015-09-22 Anton Blanchard <anton@samba.org>
479
480 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
481
4822015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
483
484 * sparc-dis.c (print_insn_sparc): Handle the privileged register
485 %pmcdper.
486
4872015-08-24 Jan Stancek <jstancek@redhat.com>
488
489 * i386-dis.c (print_insn): Fix decoding of three byte operands.
490
4912015-08-21 Alexander Fomin <alexander.fomin@intel.com>
492
493 PR binutils/18257
494 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
495 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
496 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
497 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
498 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
499 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
500 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
501 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
502 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
503 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
504 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
505 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
506 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
507 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
508 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
509 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
510 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
511 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
512 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
513 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
514 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
515 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
516 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
517 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
518 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
519 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
520 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
521 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
522 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
523 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
524 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
525 (vex_w_table): Replace terminals with MOD_TABLE entries for
526 most of mask instructions.
527
5282015-08-17 Alan Modra <amodra@gmail.com>
529
530 * cgen.sh: Trim trailing space from cgen output.
531 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
532 (print_dis_table): Likewise.
533 * opc2c.c (dump_lines): Likewise.
534 (orig_filename): Warning fix.
535 * ia64-asmtab.c: Regenerate.
536
5372015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
538
539 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
540 and higher with ARM instruction set will now mark the 26-bit
541 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
542 (arm_opcodes): Fix for unpredictable nop being recognized as a
543 teq.
544
5452015-08-12 Simon Dardis <simon.dardis@imgtec.com>
546
547 * micromips-opc.c (micromips_opcodes): Re-order table so that move
548 based on 'or' is first.
549 * mips-opc.c (mips_builtin_opcodes): Ditto.
550
5512015-08-11 Nick Clifton <nickc@redhat.com>
552
553 PR 18800
554 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
555 instruction.
556
5572015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
558
559 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
560
5612015-08-07 Amit Pawar <Amit.Pawar@amd.com>
562
563 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
564 * i386-init.h: Regenerated.
565
5662015-07-30 H.J. Lu <hongjiu.lu@intel.com>
567
568 PR binutils/13571
569 * i386-dis.c (MOD_0FC3): New.
570 (PREFIX_0FC3): Renamed to ...
571 (PREFIX_MOD_0_0FC3): This.
572 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
573 (prefix_table): Replace Ma with Ev on movntiS.
574 (mod_table): Add MOD_0FC3.
575
5762015-07-27 H.J. Lu <hongjiu.lu@intel.com>
577
578 * configure: Regenerated.
579
5802015-07-23 Alan Modra <amodra@gmail.com>
581
582 PR 18708
583 * i386-dis.c (get64): Avoid signed integer overflow.
584
5852015-07-22 Alexander Fomin <alexander.fomin@intel.com>
586
587 PR binutils/18631
588 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
589 "EXEvexHalfBcstXmmq" for the second operand.
590 (EVEX_W_0F79_P_2): Likewise.
591 (EVEX_W_0F7A_P_2): Likewise.
592 (EVEX_W_0F7B_P_2): Likewise.
593
5942015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
595
596 * arm-dis.c (print_insn_coprocessor): Added support for quarter
597 float bitfield format.
598 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
599 quarter float bitfield format.
600
6012015-07-14 H.J. Lu <hongjiu.lu@intel.com>
602
603 * configure: Regenerated.
604
6052015-07-03 Alan Modra <amodra@gmail.com>
606
607 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
608 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
609 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
610
6112015-07-01 Sandra Loosemore <sandra@codesourcery.com>
612 Cesar Philippidis <cesar@codesourcery.com>
613
614 * nios2-dis.c (nios2_extract_opcode): New.
615 (nios2_disassembler_state): New.
616 (nios2_find_opcode_hash): Use mach parameter to select correct
617 disassembler state.
618 (nios2_print_insn_arg): Extend to support new R2 argument letters
619 and formats.
620 (print_insn_nios2): Check for 16-bit instruction at end of memory.
621 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
622 (NIOS2_NUM_OPCODES): Rename to...
623 (NIOS2_NUM_R1_OPCODES): This.
624 (nios2_r2_opcodes): New.
625 (NIOS2_NUM_R2_OPCODES): New.
626 (nios2_num_r2_opcodes): New.
627 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
628 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
629 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
630 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
631 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
632
6332015-06-30 Amit Pawar <Amit.Pawar@amd.com>
634
635 * i386-dis.c (OP_Mwaitx): New.
636 (rm_table): Add monitorx/mwaitx.
637 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
638 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
639 (operand_type_init): Add CpuMWAITX.
640 * i386-opc.h (CpuMWAITX): New.
641 (i386_cpu_flags): Add cpumwaitx.
642 * i386-opc.tbl: Add monitorx and mwaitx.
643 * i386-init.h: Regenerated.
644 * i386-tbl.h: Likewise.
645
6462015-06-22 Peter Bergner <bergner@vnet.ibm.com>
647
648 * ppc-opc.c (insert_ls): Test for invalid LS operands.
649 (insert_esync): New function.
650 (LS, WC): Use insert_ls.
651 (ESYNC): Use insert_esync.
652
6532015-06-22 Nick Clifton <nickc@redhat.com>
654
655 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
656 requested region lies beyond it.
657 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
658 looking for 32-bit insns.
659 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
660 data.
661 * sh-dis.c (print_insn_sh): Likewise.
662 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
663 blocks of instructions.
664 * vax-dis.c (print_insn_vax): Check that the requested address
665 does not clash with the stop_vma.
666
6672015-06-19 Peter Bergner <bergner@vnet.ibm.com>
668
669 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
670 * ppc-opc.c (FXM4): Add non-zero optional value.
671 (TBR): Likewise.
672 (SXL): Likewise.
673 (insert_fxm): Handle new default operand value.
674 (extract_fxm): Likewise.
675 (insert_tbr): Likewise.
676 (extract_tbr): Likewise.
677
6782015-06-16 Matthew Wahab <matthew.wahab@arm.com>
679
680 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
681
6822015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
683
684 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
685
6862015-06-12 Peter Bergner <bergner@vnet.ibm.com>
687
688 * ppc-opc.c: Add comment accidentally removed by old commit.
689 (MTMSRD_L): Delete.
690
6912015-06-04 Peter Bergner <bergner@vnet.ibm.com>
692
693 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
694
6952015-06-04 Nick Clifton <nickc@redhat.com>
696
697 PR 18474
698 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
699
7002015-06-02 Matthew Wahab <matthew.wahab@arm.com>
701
702 * arm-dis.c (arm_opcodes): Add "setpan".
703 (thumb_opcodes): Add "setpan".
704
7052015-06-02 Matthew Wahab <matthew.wahab@arm.com>
706
707 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
708 macros.
709
7102015-06-02 Matthew Wahab <matthew.wahab@arm.com>
711
712 * aarch64-tbl.h (aarch64_feature_rdma): New.
713 (RDMA): New.
714 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
715 * aarch64-asm-2.c: Regenerate.
716 * aarch64-dis-2.c: Regenerate.
717 * aarch64-opc-2.c: Regenerate.
718
7192015-06-02 Matthew Wahab <matthew.wahab@arm.com>
720
721 * aarch64-tbl.h (aarch64_feature_lor): New.
722 (LOR): New.
723 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
724 "stllrb", "stllrh".
725 * aarch64-asm-2.c: Regenerate.
726 * aarch64-dis-2.c: Regenerate.
727 * aarch64-opc-2.c: Regenerate.
728
7292015-06-01 Matthew Wahab <matthew.wahab@arm.com>
730
731 * aarch64-opc.c (F_ARCHEXT): New.
732 (aarch64_sys_regs): Add "pan".
733 (aarch64_sys_reg_supported_p): New.
734 (aarch64_pstatefields): Add "pan".
735 (aarch64_pstatefield_supported_p): New.
736
7372015-06-01 Jan Beulich <jbeulich@suse.com>
738
739 * i386-tbl.h: Regenerate.
740
7412015-06-01 Jan Beulich <jbeulich@suse.com>
742
743 * i386-dis.c (print_insn): Swap rounding mode specifier and
744 general purpose register in Intel mode.
745
7462015-06-01 Jan Beulich <jbeulich@suse.com>
747
748 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
749 * i386-tbl.h: Regenerate.
750
7512015-05-18 H.J. Lu <hongjiu.lu@intel.com>
752
753 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
754 * i386-init.h: Regenerated.
755
7562015-05-15 H.J. Lu <hongjiu.lu@intel.com>
757
758 PR binutis/18386
759 * i386-dis.c: Add comments for '@'.
760 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
761 (enum x86_64_isa): New.
762 (isa64): Likewise.
763 (print_i386_disassembler_options): Add amd64 and intel64.
764 (print_insn): Handle amd64 and intel64.
765 (putop): Handle '@'.
766 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
767 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
768 * i386-opc.h (AMD64): New.
769 (CpuIntel64): Likewise.
770 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
771 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
772 Mark direct call/jmp without Disp16|Disp32 as Intel64.
773 * i386-init.h: Regenerated.
774 * i386-tbl.h: Likewise.
775
7762015-05-14 Peter Bergner <bergner@vnet.ibm.com>
777
778 * ppc-opc.c (IH) New define.
779 (powerpc_opcodes) <wait>: Do not enable for POWER7.
780 <tlbie>: Add RS operand for POWER7.
781 <slbia>: Add IH operand for POWER6.
782
7832015-05-11 H.J. Lu <hongjiu.lu@intel.com>
784
785 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
786 direct branch.
787 (jmp): Likewise.
788 * i386-tbl.h: Regenerated.
789
7902015-05-11 H.J. Lu <hongjiu.lu@intel.com>
791
792 * configure.ac: Support bfd_iamcu_arch.
793 * disassemble.c (disassembler): Support bfd_iamcu_arch.
794 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
795 CPU_IAMCU_COMPAT_FLAGS.
796 (cpu_flags): Add CpuIAMCU.
797 * i386-opc.h (CpuIAMCU): New.
798 (i386_cpu_flags): Add cpuiamcu.
799 * configure: Regenerated.
800 * i386-init.h: Likewise.
801 * i386-tbl.h: Likewise.
802
8032015-05-08 H.J. Lu <hongjiu.lu@intel.com>
804
805 PR binutis/18386
806 * i386-dis.c (X86_64_E8): New.
807 (X86_64_E9): Likewise.
808 Update comments on 'T', 'U', 'V'. Add comments for '^'.
809 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
810 (x86_64_table): Add X86_64_E8 and X86_64_E9.
811 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
812 (putop): Handle '^'.
813 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
814 REX_W.
815
8162015-04-30 DJ Delorie <dj@redhat.com>
817
818 * disassemble.c (disassembler): Choose suitable disassembler based
819 on E_ABI.
820 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
821 it to decode mul/div insns.
822 * rl78-decode.c: Regenerate.
823 * rl78-dis.c (print_insn_rl78): Rename to...
824 (print_insn_rl78_common): ...this, take ISA parameter.
825 (print_insn_rl78): New.
826 (print_insn_rl78_g10): New.
827 (print_insn_rl78_g13): New.
828 (print_insn_rl78_g14): New.
829 (rl78_get_disassembler): New.
830
8312015-04-29 Nick Clifton <nickc@redhat.com>
832
833 * po/fr.po: Updated French translation.
834
8352015-04-27 Peter Bergner <bergner@vnet.ibm.com>
836
837 * ppc-opc.c (DCBT_EO): New define.
838 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
839 <lharx>: Likewise.
840 <stbcx.>: Likewise.
841 <sthcx.>: Likewise.
842 <waitrsv>: Do not enable for POWER7 and later.
843 <waitimpl>: Likewise.
844 <dcbt>: Default to the two operand form of the instruction for all
845 "old" cpus. For "new" cpus, use the operand ordering that matches
846 whether the cpu is server or embedded.
847 <dcbtst>: Likewise.
848
8492015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
850
851 * s390-opc.c: New instruction type VV0UU2.
852 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
853 and WFC.
854
8552015-04-23 Jan Beulich <jbeulich@suse.com>
856
857 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
858 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
859 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
860 (vfpclasspd, vfpclassps): Add %XZ.
861
8622015-04-15 H.J. Lu <hongjiu.lu@intel.com>
863
864 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
865 (PREFIX_UD_REPZ): Likewise.
866 (PREFIX_UD_REPNZ): Likewise.
867 (PREFIX_UD_DATA): Likewise.
868 (PREFIX_UD_ADDR): Likewise.
869 (PREFIX_UD_LOCK): Likewise.
870
8712015-04-15 H.J. Lu <hongjiu.lu@intel.com>
872
873 * i386-dis.c (prefix_requirement): Removed.
874 (print_insn): Don't set prefix_requirement. Check
875 dp->prefix_requirement instead of prefix_requirement.
876
8772015-04-15 H.J. Lu <hongjiu.lu@intel.com>
878
879 PR binutils/17898
880 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
881 (PREFIX_MOD_0_0FC7_REG_6): This.
882 (PREFIX_MOD_3_0FC7_REG_6): New.
883 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
884 (prefix_table): Replace PREFIX_0FC7_REG_6 with
885 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
886 PREFIX_MOD_3_0FC7_REG_7.
887 (mod_table): Replace PREFIX_0FC7_REG_6 with
888 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
889 PREFIX_MOD_3_0FC7_REG_7.
890
8912015-04-15 H.J. Lu <hongjiu.lu@intel.com>
892
893 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
894 (PREFIX_MANDATORY_REPNZ): Likewise.
895 (PREFIX_MANDATORY_DATA): Likewise.
896 (PREFIX_MANDATORY_ADDR): Likewise.
897 (PREFIX_MANDATORY_LOCK): Likewise.
898 (PREFIX_MANDATORY): Likewise.
899 (PREFIX_UD_SHIFT): Set to 8
900 (PREFIX_UD_REPZ): Updated.
901 (PREFIX_UD_REPNZ): Likewise.
902 (PREFIX_UD_DATA): Likewise.
903 (PREFIX_UD_ADDR): Likewise.
904 (PREFIX_UD_LOCK): Likewise.
905 (PREFIX_IGNORED_SHIFT): New.
906 (PREFIX_IGNORED_REPZ): Likewise.
907 (PREFIX_IGNORED_REPNZ): Likewise.
908 (PREFIX_IGNORED_DATA): Likewise.
909 (PREFIX_IGNORED_ADDR): Likewise.
910 (PREFIX_IGNORED_LOCK): Likewise.
911 (PREFIX_OPCODE): Likewise.
912 (PREFIX_IGNORED): Likewise.
913 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
914 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
915 (three_byte_table): Likewise.
916 (mod_table): Likewise.
917 (mandatory_prefix): Renamed to ...
918 (prefix_requirement): This.
919 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
920 Update PREFIX_90 entry.
921 (get_valid_dis386): Check prefix_requirement to see if a prefix
922 should be ignored.
923 (print_insn): Replace mandatory_prefix with prefix_requirement.
924
9252015-04-15 Renlin Li <renlin.li@arm.com>
926
927 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
928 use it for ssat and ssat16.
929 (print_insn_thumb32): Add handle case for 'D' control code.
930
9312015-04-06 Ilya Tocar <ilya.tocar@intel.com>
932 H.J. Lu <hongjiu.lu@intel.com>
933
934 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
935 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
936 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
937 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
938 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
939 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
940 Fill prefix_requirement field.
941 (struct dis386): Add prefix_requirement field.
942 (dis386): Fill prefix_requirement field.
943 (dis386_twobyte): Ditto.
944 (twobyte_has_mandatory_prefix_: Remove.
945 (reg_table): Fill prefix_requirement field.
946 (prefix_table): Ditto.
947 (x86_64_table): Ditto.
948 (three_byte_table): Ditto.
949 (xop_table): Ditto.
950 (vex_table): Ditto.
951 (vex_len_table): Ditto.
952 (vex_w_table): Ditto.
953 (mod_table): Ditto.
954 (bad_opcode): Ditto.
955 (print_insn): Use prefix_requirement.
956 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
957 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
958 (float_reg): Ditto.
959
9602015-03-30 Mike Frysinger <vapier@gentoo.org>
961
962 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
963
9642015-03-29 H.J. Lu <hongjiu.lu@intel.com>
965
966 * Makefile.in: Regenerated.
967
9682015-03-25 Anton Blanchard <anton@samba.org>
969
970 * ppc-dis.c (disassemble_init_powerpc): Only initialise
971 powerpc_opcd_indices and vle_opcd_indices once.
972
9732015-03-25 Anton Blanchard <anton@samba.org>
974
975 * ppc-opc.c (powerpc_opcodes): Add slbfee.
976
9772015-03-24 Terry Guo <terry.guo@arm.com>
978
979 * arm-dis.c (opcode32): Updated to use new arm feature struct.
980 (opcode16): Likewise.
981 (coprocessor_opcodes): Replace bit with feature struct.
982 (neon_opcodes): Likewise.
983 (arm_opcodes): Likewise.
984 (thumb_opcodes): Likewise.
985 (thumb32_opcodes): Likewise.
986 (print_insn_coprocessor): Likewise.
987 (print_insn_arm): Likewise.
988 (select_arm_features): Follow new feature struct.
989
9902015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
991
992 * i386-dis.c (rm_table): Add clzero.
993 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
994 Add CPU_CLZERO_FLAGS.
995 (cpu_flags): Add CpuCLZERO.
996 * i386-opc.h: Add CpuCLZERO.
997 * i386-opc.tbl: Add clzero.
998 * i386-init.h: Re-generated.
999 * i386-tbl.h: Re-generated.
1000
10012015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
1002
1003 * mips-opc.c (decode_mips_operand): Fix constraint issues
1004 with u and y operands.
1005
10062015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
1007
1008 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
1009
10102015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1011
1012 * s390-opc.c: Add new IBM z13 instructions.
1013 * s390-opc.txt: Likewise.
1014
10152015-03-10 Renlin Li <renlin.li@arm.com>
1016
1017 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
1018 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
1019 related alias.
1020 * aarch64-asm-2.c: Regenerate.
1021 * aarch64-dis-2.c: Likewise.
1022 * aarch64-opc-2.c: Likewise.
1023
10242015-03-03 Jiong Wang <jiong.wang@arm.com>
1025
1026 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
1027
10282015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
1029
1030 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
1031 arch_sh_up.
1032 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
1033 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
1034
10352015-02-23 Vinay <Vinay.G@kpit.com>
1036
1037 * rl78-decode.opc (MOV): Added space between two operands for
1038 'mov' instruction in index addressing mode.
1039 * rl78-decode.c: Regenerate.
1040
10412015-02-19 Pedro Alves <palves@redhat.com>
1042
1043 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
1044
10452015-02-10 Pedro Alves <palves@redhat.com>
1046 Tom Tromey <tromey@redhat.com>
1047
1048 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
1049 microblaze_and, microblaze_xor.
1050 * microblaze-opc.h (opcodes): Adjust.
1051
10522015-01-28 James Bowman <james.bowman@ftdichip.com>
1053
1054 * Makefile.am: Add FT32 files.
1055 * configure.ac: Handle FT32.
1056 * disassemble.c (disassembler): Call print_insn_ft32.
1057 * ft32-dis.c: New file.
1058 * ft32-opc.c: New file.
1059 * Makefile.in: Regenerate.
1060 * configure: Regenerate.
1061 * po/POTFILES.in: Regenerate.
1062
10632015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1064
1065 * nds32-asm.c (keyword_sr): Add new system registers.
1066
10672015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1068
1069 * s390-dis.c (s390_extract_operand): Support vector register
1070 operands.
1071 (s390_print_insn_with_opcode): Support new operands types and add
1072 new handling of optional operands.
1073 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1074 and include opcode/s390.h instead.
1075 (struct op_struct): New field `flags'.
1076 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1077 (dumpTable): Dump flags.
1078 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
1079 string.
1080 * s390-opc.c: Add new operands types, instruction formats, and
1081 instruction masks.
1082 (s390_opformats): Add new formats for .insn.
1083 * s390-opc.txt: Add new instructions.
1084
10852015-01-01 Alan Modra <amodra@gmail.com>
1086
1087 Update year range in copyright notice of all files.
1088
1089For older changes see ChangeLog-2014
1090\f
1091Copyright (C) 2015 Free Software Foundation, Inc.
1092
1093Copying and distribution of this file, with or without modification,
1094are permitted in any medium without royalty provided the copyright
1095notice and this notice are preserved.
1096
1097Local Variables:
1098mode: change-log
1099left-margin: 8
1100fill-column: 74
1101version-control: never
1102End:
GDB Binutils - Deliverables
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