| 1 | 2020-05-11 Alan Modra <amodra@gmail.com> |
| 2 | |
| 3 | * ppc-opc.c (insert_imm32, extract_imm32): New functions. |
| 4 | (insert_xts, extract_xts): New functions. |
| 5 | (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define. |
| 6 | (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define. |
| 7 | (VXRC_MASK, VXSH_MASK): Define. |
| 8 | (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx, |
| 9 | vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx, |
| 10 | vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx, |
| 11 | vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx, |
| 12 | vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq. |
| 13 | (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb, |
| 14 | xxblendvh, xxblendvw, xxblendvd, xxpermx. |
| 15 | |
| 16 | 2020-05-11 Alan Modra <amodra@gmail.com> |
| 17 | |
| 18 | * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi, |
| 19 | vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd, |
| 20 | vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd, |
| 21 | vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz, |
| 22 | xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq. |
| 23 | |
| 24 | 2020-05-11 Alan Modra <amodra@gmail.com> |
| 25 | |
| 26 | * ppc-opc.c (insert_xtp, extract_xtp): New functions. |
| 27 | (XTP, DQXP, DQXP_MASK): Define. |
| 28 | (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx. |
| 29 | (prefix_opcodes): Add plxvp and pstxvp. |
| 30 | |
| 31 | 2020-05-11 Alan Modra <amodra@gmail.com> |
| 32 | |
| 33 | * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld, |
| 34 | vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw, |
| 35 | vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd. |
| 36 | |
| 37 | 2020-05-11 Peter Bergner <bergner@linux.ibm.com> |
| 38 | |
| 39 | * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics. |
| 40 | |
| 41 | 2020-05-11 Peter Bergner <bergner@linux.ibm.com> |
| 42 | |
| 43 | * ppc-opc.c (insert_l1opt, extract_l1opt): New functions. |
| 44 | (L1OPT): Define. |
| 45 | (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10. |
| 46 | |
| 47 | 2020-05-11 Peter Bergner <bergner@linux.ibm.com> |
| 48 | |
| 49 | * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand. |
| 50 | |
| 51 | 2020-05-11 Alan Modra <amodra@gmail.com> |
| 52 | |
| 53 | * ppc-dis.c (powerpc_init_dialect): Default to "power10". |
| 54 | |
| 55 | 2020-05-11 Alan Modra <amodra@gmail.com> |
| 56 | |
| 57 | * ppc-dis.c (ppc_opts): Add "power10" entry. |
| 58 | (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming. |
| 59 | * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses. |
| 60 | |
| 61 | 2020-05-11 Nick Clifton <nickc@redhat.com> |
| 62 | |
| 63 | * po/fr.po: Updated French translation. |
| 64 | |
| 65 | 2020-04-30 Alex Coplan <alex.coplan@arm.com> |
| 66 | |
| 67 | * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2. |
| 68 | * aarch64-opc.c (fields): Add entry for FLD_imm16_2. |
| 69 | (operand_general_constraint_met_p): validate |
| 70 | AARCH64_OPND_UNDEFINED. |
| 71 | * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry |
| 72 | for FLD_imm16_2. |
| 73 | * aarch64-asm-2.c: Regenerated. |
| 74 | * aarch64-dis-2.c: Regenerated. |
| 75 | * aarch64-opc-2.c: Regenerated. |
| 76 | |
| 77 | 2020-04-29 Nick Clifton <nickc@redhat.com> |
| 78 | |
| 79 | PR 22699 |
| 80 | * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC |
| 81 | and SETRC insns. |
| 82 | |
| 83 | 2020-04-29 Nick Clifton <nickc@redhat.com> |
| 84 | |
| 85 | * po/sv.po: Updated Swedish translation. |
| 86 | |
| 87 | 2020-04-29 Nick Clifton <nickc@redhat.com> |
| 88 | |
| 89 | PR 22699 |
| 90 | * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use |
| 91 | IMM0_8S for arithmetic insns and IMM0_8U for logical insns. |
| 92 | * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add |
| 93 | IMM0_8U case. |
| 94 | |
| 95 | 2020-04-21 Andreas Schwab <schwab@linux-m68k.org> |
| 96 | |
| 97 | PR 25848 |
| 98 | * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of |
| 99 | cmpi only on m68020up and cpu32. |
| 100 | |
| 101 | 2020-04-20 Sudakshina Das <sudi.das@arm.com> |
| 102 | |
| 103 | * aarch64-asm.c (aarch64_ins_none): New. |
| 104 | * aarch64-asm.h (ins_none): New declaration. |
| 105 | * aarch64-dis.c (aarch64_ext_none): New. |
| 106 | * aarch64-dis.h (ext_none): New declaration. |
| 107 | * aarch64-opc.c (aarch64_print_operand): Update case for |
| 108 | AARCH64_OPND_BARRIER_PSB. |
| 109 | * aarch64-tbl.h (aarch64_opcode_table): Add tsb. |
| 110 | (AARCH64_OPERANDS): Update inserter/extracter for |
| 111 | AARCH64_OPND_BARRIER_PSB to use new dummy functions. |
| 112 | * aarch64-asm-2.c: Regenerated. |
| 113 | * aarch64-dis-2.c: Regenerated. |
| 114 | * aarch64-opc-2.c: Regenerated. |
| 115 | |
| 116 | 2020-04-20 Sudakshina Das <sudi.das@arm.com> |
| 117 | |
| 118 | * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove. |
| 119 | (aarch64_feature_ras, RAS): Likewise. |
| 120 | (aarch64_feature_stat_profile, STAT_PROFILE): Likewise. |
| 121 | (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716, |
| 122 | autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp, |
| 123 | autiaz, autiasp, autibz, autibsp to be CORE_INSN. |
| 124 | * aarch64-asm-2.c: Regenerated. |
| 125 | * aarch64-dis-2.c: Regenerated. |
| 126 | * aarch64-opc-2.c: Regenerated. |
| 127 | |
| 128 | 2020-04-17 Fredrik Strupe <fredrik@strupe.net> |
| 129 | |
| 130 | * arm-dis.c (neon_opcodes): Fix VDUP instruction masks. |
| 131 | (print_insn_neon): Support disassembly of conditional |
| 132 | instructions. |
| 133 | |
| 134 | 2020-02-16 David Faust <david.faust@oracle.com> |
| 135 | |
| 136 | * bpf-desc.c: Regenerate. |
| 137 | * bpf-desc.h: Likewise. |
| 138 | * bpf-opc.c: Regenerate. |
| 139 | * bpf-opc.h: Likewise. |
| 140 | |
| 141 | 2020-04-07 Lili Cui <lili.cui@intel.com> |
| 142 | |
| 143 | * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1, |
| 144 | (prefix_table): New instructions (see prefixes above). |
| 145 | (rm_table): Likewise |
| 146 | * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS, |
| 147 | CPU_ANY_TSXLDTRK_FLAGS. |
| 148 | (cpu_flags): Add CpuTSXLDTRK. |
| 149 | * i386-opc.h (enum): Add CpuTSXLDTRK. |
| 150 | (i386_cpu_flags): Add cputsxldtrk. |
| 151 | * i386-opc.tbl: Add XSUSPLDTRK insns. |
| 152 | * i386-init.h: Regenerate. |
| 153 | * i386-tbl.h: Likewise. |
| 154 | |
| 155 | 2020-04-02 Lili Cui <lili.cui@intel.com> |
| 156 | |
| 157 | * i386-dis.c (prefix_table): New instructions serialize. |
| 158 | * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS, |
| 159 | CPU_ANY_SERIALIZE_FLAGS. |
| 160 | (cpu_flags): Add CpuSERIALIZE. |
| 161 | * i386-opc.h (enum): Add CpuSERIALIZE. |
| 162 | (i386_cpu_flags): Add cpuserialize. |
| 163 | * i386-opc.tbl: Add SERIALIZE insns. |
| 164 | * i386-init.h: Regenerate. |
| 165 | * i386-tbl.h: Likewise. |
| 166 | |
| 167 | 2020-03-26 Alan Modra <amodra@gmail.com> |
| 168 | |
| 169 | * disassemble.h (opcodes_assert): Declare. |
| 170 | (OPCODES_ASSERT): Define. |
| 171 | * disassemble.c: Don't include assert.h. Include opintl.h. |
| 172 | (opcodes_assert): New function. |
| 173 | * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT. |
| 174 | (bfd_h8_disassemble): Reduce size of data array. Correctly |
| 175 | calculate maxlen. Omit insn decoding when insn length exceeds |
| 176 | maxlen. Exit from nibble loop when looking for E, before |
| 177 | accessing next data byte. Move processing of E outside loop. |
| 178 | Replace tests of maxlen in loop with assertions. |
| 179 | |
| 180 | 2020-03-26 Alan Modra <amodra@gmail.com> |
| 181 | |
| 182 | * arc-dis.c (find_format): Init needs_limm. Simplify use of limm. |
| 183 | |
| 184 | 2020-03-25 Alan Modra <amodra@gmail.com> |
| 185 | |
| 186 | * z80-dis.c (suffix): Init mybuf. |
| 187 | |
| 188 | 2020-03-22 Alan Modra <amodra@gmail.com> |
| 189 | |
| 190 | * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that |
| 191 | successflly read from section. |
| 192 | |
| 193 | 2020-03-22 Alan Modra <amodra@gmail.com> |
| 194 | |
| 195 | * arc-dis.c (find_format): Use ISO C string concatenation rather |
| 196 | than line continuation within a string. Don't access needs_limm |
| 197 | before testing opcode != NULL. |
| 198 | |
| 199 | 2020-03-22 Alan Modra <amodra@gmail.com> |
| 200 | |
| 201 | * ns32k-dis.c (print_insn_arg): Update comment. |
| 202 | (print_insn_ns32k): Reduce size of index_offset array, and |
| 203 | initialize, passing -1 to print_insn_arg for args that are not |
| 204 | an index. Don't exit arg loop early. Abort on bad arg number. |
| 205 | |
| 206 | 2020-03-22 Alan Modra <amodra@gmail.com> |
| 207 | |
| 208 | * s12z-dis.c (abstract_read_memory): Don't print error on EOI. |
| 209 | * s12z-opc.c: Formatting. |
| 210 | (operands_f): Return an int. |
| 211 | (opr_n_bytes_p1): Return -1 on reaching buffer memory limit. |
| 212 | (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes), |
| 213 | (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes), |
| 214 | (exg_sex_discrim): Likewise. |
| 215 | (create_immediate_operand, create_bitfield_operand), |
| 216 | (create_register_operand_with_size, create_register_all_operand), |
| 217 | (create_register_all16_operand, create_simple_memory_operand), |
| 218 | (create_memory_operand, create_memory_auto_operand): Don't |
| 219 | segfault on malloc failure. |
| 220 | (z_ext24_decode): Return an int status, negative on fail, zero |
| 221 | on success. |
| 222 | (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2), |
| 223 | (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base), |
| 224 | (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7), |
| 225 | (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x), |
| 226 | (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode), |
| 227 | (mov_imm_opr, ld_18bit_decode, exg_sex_decode), |
| 228 | (loop_primitive_decode, shift_decode, psh_pul_decode), |
| 229 | (bit_field_decode): Similarly. |
| 230 | (z_decode_signed_value, decode_signed_value): Similarly. Add arg |
| 231 | to return value, update callers. |
| 232 | (x_opr_decode_with_size): Check all reads, returning NULL on fail. |
| 233 | Don't segfault on NULL operand. |
| 234 | (decode_operation): Return OP_INVALID on first fail. |
| 235 | (decode_s12z): Check all reads, returning -1 on fail. |
| 236 | |
| 237 | 2020-03-20 Alan Modra <amodra@gmail.com> |
| 238 | |
| 239 | * metag-dis.c (print_insn_metag): Don't ignore status from |
| 240 | read_memory_func. |
| 241 | |
| 242 | 2020-03-20 Alan Modra <amodra@gmail.com> |
| 243 | |
| 244 | * nds32-dis.c (print_insn_nds32): Remove unnecessary casts. |
| 245 | Initialize parts of buffer not written when handling a possible |
| 246 | 2-byte insn at end of section. Don't attempt decoding of such |
| 247 | an insn by the 4-byte machinery. |
| 248 | |
| 249 | 2020-03-20 Alan Modra <amodra@gmail.com> |
| 250 | |
| 251 | * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of |
| 252 | partially filled buffer. Prevent lookup of 4-byte insns when |
| 253 | only VLE 2-byte insns are possible due to section size. Print |
| 254 | ".word" rather than ".long" for 2-byte leftovers. |
| 255 | |
| 256 | 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com> |
| 257 | |
| 258 | PR 25641 |
| 259 | * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes. |
| 260 | |
| 261 | 2020-03-13 Jan Beulich <jbeulich@suse.com> |
| 262 | |
| 263 | * i386-dis.c (X86_64_0D): Rename to ... |
| 264 | (X86_64_0E): ... this. |
| 265 | |
| 266 | 2020-03-09 H.J. Lu <hongjiu.lu@intel.com> |
| 267 | |
| 268 | * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP). |
| 269 | * Makefile.in: Regenerated. |
| 270 | |
| 271 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
| 272 | |
| 273 | * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp* |
| 274 | 3-operand pseudos. |
| 275 | * i386-tbl.h: Re-generate. |
| 276 | |
| 277 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
| 278 | |
| 279 | * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*, |
| 280 | vprot*, vpsha*, and vpshl*. |
| 281 | * i386-tbl.h: Re-generate. |
| 282 | |
| 283 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
| 284 | |
| 285 | * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps, |
| 286 | vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops. |
| 287 | * i386-tbl.h: Re-generate. |
| 288 | |
| 289 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
| 290 | |
| 291 | * i386-gen.c (set_bitfield): Ignore zero-length field names. |
| 292 | * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps, |
| 293 | cmpss, cmppd, and cmpsd 2-operand pseudo-ops. |
| 294 | * i386-tbl.h: Re-generate. |
| 295 | |
| 296 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
| 297 | |
| 298 | * i386-gen.c (struct template_arg, struct template_instance, |
| 299 | struct template_param, struct template, templates, |
| 300 | parse_template, expand_templates): New. |
| 301 | (process_i386_opcodes): Various local variables moved to |
| 302 | expand_templates. Call parse_template and expand_templates. |
| 303 | * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc. |
| 304 | * i386-tbl.h: Re-generate. |
| 305 | |
| 306 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
| 307 | |
| 308 | * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph, |
| 309 | vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate |
| 310 | register and memory source templates. Replace VexW= by VexW* |
| 311 | where applicable. |
| 312 | * i386-tbl.h: Re-generate. |
| 313 | |
| 314 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
| 315 | |
| 316 | * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace |
| 317 | VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable. |
| 318 | * i386-tbl.h: Re-generate. |
| 319 | |
| 320 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
| 321 | |
| 322 | * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax. |
| 323 | * i386-tbl.h: Re-generate. |
| 324 | |
| 325 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
| 326 | |
| 327 | * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants. |
| 328 | (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps, |
| 329 | pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use |
| 330 | VexW0 on SSE2AVX variants. |
| 331 | (vmovq): Drop NoRex64 from XMM/XMM variants. |
| 332 | (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb, |
| 333 | vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where |
| 334 | applicable use VexW0. |
| 335 | * i386-tbl.h: Re-generate. |
| 336 | |
| 337 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
| 338 | |
| 339 | * i386-gen.c (opcode_modifiers): Remove Rex64 field. |
| 340 | * i386-opc.h (Rex64): Delete. |
| 341 | (struct i386_opcode_modifier): Remove rex64 field. |
| 342 | * i386-opc.tbl (crc32): Drop Rex64. |
| 343 | Replace Rex64 with Size64 everywhere else. |
| 344 | * i386-tbl.h: Re-generate. |
| 345 | |
| 346 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
| 347 | |
| 348 | * i386-dis.c (OP_E_memory): Exclude recording of used address |
| 349 | prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit |
| 350 | addressed memory operands for MPX insns. |
| 351 | |
| 352 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
| 353 | |
| 354 | * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept, |
| 355 | invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx, |
| 356 | adox, mwaitx, rdpid, movdiri): Add IgnoreSize. |
| 357 | (ptwrite): Split into non-64-bit and 64-bit forms. |
| 358 | * i386-tbl.h: Re-generate. |
| 359 | |
| 360 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
| 361 | |
| 362 | * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand |
| 363 | template. |
| 364 | * i386-tbl.h: Re-generate. |
| 365 | |
| 366 | 2020-03-04 Jan Beulich <jbeulich@suse.com> |
| 367 | |
| 368 | * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New. |
| 369 | (prefix_table): Move vmmcall here. Add vmgexit. |
| 370 | (rm_table): Replace vmmcall entry by prefix_table[] escape. |
| 371 | * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry. |
| 372 | (cpu_flags): Add CpuSEV_ES entry. |
| 373 | * i386-opc.h (CpuSEV_ES): New. |
| 374 | (union i386_cpu_flags): Add cpusev_es field. |
| 375 | * i386-opc.tbl (vmgexit): New. |
| 376 | * i386-init.h, i386-tbl.h: Re-generate. |
| 377 | |
| 378 | 2020-03-03 H.J. Lu <hongjiu.lu@intel.com> |
| 379 | |
| 380 | * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize |
| 381 | with MnemonicSize. |
| 382 | * i386-opc.h (IGNORESIZE): New. |
| 383 | (DEFAULTSIZE): Likewise. |
| 384 | (IgnoreSize): Removed. |
| 385 | (DefaultSize): Likewise. |
| 386 | (MnemonicSize): New. |
| 387 | (i386_opcode_modifier): Replace ignoresize/defaultsize with |
| 388 | mnemonicsize. |
| 389 | * i386-opc.tbl (IgnoreSize): New. |
| 390 | (DefaultSize): Likewise. |
| 391 | * i386-tbl.h: Regenerated. |
| 392 | |
| 393 | 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com> |
| 394 | |
| 395 | PR 25627 |
| 396 | * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX |
| 397 | instructions. |
| 398 | |
| 399 | 2020-03-03 H.J. Lu <hongjiu.lu@intel.com> |
| 400 | |
| 401 | PR gas/25622 |
| 402 | * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd, |
| 403 | vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax. |
| 404 | * i386-tbl.h: Regenerated. |
| 405 | |
| 406 | 2020-02-26 Alan Modra <amodra@gmail.com> |
| 407 | |
| 408 | * aarch64-asm.c: Indent labels correctly. |
| 409 | * aarch64-dis.c: Likewise. |
| 410 | * aarch64-gen.c: Likewise. |
| 411 | * aarch64-opc.c: Likewise. |
| 412 | * alpha-dis.c: Likewise. |
| 413 | * i386-dis.c: Likewise. |
| 414 | * nds32-asm.c: Likewise. |
| 415 | * nfp-dis.c: Likewise. |
| 416 | * visium-dis.c: Likewise. |
| 417 | |
| 418 | 2020-02-25 Claudiu Zissulescu <claziss@gmail.com> |
| 419 | |
| 420 | * arc-regs.h (int_vector_base): Make it available for all ARC |
| 421 | CPUs. |
| 422 | |
| 423 | 2020-02-20 Nelson Chu <nelson.chu@sifive.com> |
| 424 | |
| 425 | * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is |
| 426 | changed. |
| 427 | |
| 428 | 2020-02-19 Nelson Chu <nelson.chu@sifive.com> |
| 429 | |
| 430 | * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed |
| 431 | c.mv/c.li if rs1 is zero. |
| 432 | |
| 433 | 2020-02-17 H.J. Lu <hongjiu.lu@intel.com> |
| 434 | |
| 435 | * i386-gen.c (cpu_flag_init): Replace CpuABM with |
| 436 | CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add |
| 437 | CPU_POPCNT_FLAGS. |
| 438 | (cpu_flags): Remove CpuABM. Add CpuPOPCNT. |
| 439 | * i386-opc.h (CpuABM): Removed. |
| 440 | (CpuPOPCNT): New. |
| 441 | (i386_cpu_flags): Remove cpuabm. Add cpupopcnt. |
| 442 | * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on |
| 443 | popcnt. Remove CpuABM from lzcnt. |
| 444 | * i386-init.h: Regenerated. |
| 445 | * i386-tbl.h: Likewise. |
| 446 | |
| 447 | 2020-02-17 Jan Beulich <jbeulich@suse.com> |
| 448 | |
| 449 | * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss): |
| 450 | Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/ |
| 451 | VexW1 instead of open-coding them. |
| 452 | * i386-tbl.h: Re-generate. |
| 453 | |
| 454 | 2020-02-17 Jan Beulich <jbeulich@suse.com> |
| 455 | |
| 456 | * i386-opc.tbl (AddrPrefixOpReg): Define. |
| 457 | (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx, |
| 458 | umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64 |
| 459 | templates. Drop NoRex64. |
| 460 | * i386-tbl.h: Re-generate. |
| 461 | |
| 462 | 2020-02-17 Jan Beulich <jbeulich@suse.com> |
| 463 | |
| 464 | PR gas/6518 |
| 465 | * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq, |
| 466 | vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms |
| 467 | into Intel syntax instance (with Unpsecified) and AT&T one |
| 468 | (without). |
| 469 | (vcvtneps2bf16): Likewise, along with folding the two so far |
| 470 | separate ones. |
| 471 | * i386-tbl.h: Re-generate. |
| 472 | |
| 473 | 2020-02-16 H.J. Lu <hongjiu.lu@intel.com> |
| 474 | |
| 475 | * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from |
| 476 | CPU_ANY_SSE4A_FLAGS. |
| 477 | |
| 478 | 2020-02-17 Alan Modra <amodra@gmail.com> |
| 479 | |
| 480 | * i386-gen.c (cpu_flag_init): Correct last change. |
| 481 | |
| 482 | 2020-02-16 H.J. Lu <hongjiu.lu@intel.com> |
| 483 | |
| 484 | * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove |
| 485 | CPU_ANY_SSE4_FLAGS. |
| 486 | |
| 487 | 2020-02-14 H.J. Lu <hongjiu.lu@intel.com> |
| 488 | |
| 489 | * i386-opc.tbl (movsx): Remove Intel syntax comments. |
| 490 | (movzx): Likewise. |
| 491 | |
| 492 | 2020-02-14 Jan Beulich <jbeulich@suse.com> |
| 493 | |
| 494 | PR gas/25438 |
| 495 | * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as |
| 496 | destination for Cpu64-only variant. |
| 497 | (movzx): Fold patterns. |
| 498 | * i386-tbl.h: Re-generate. |
| 499 | |
| 500 | 2020-02-13 Jan Beulich <jbeulich@suse.com> |
| 501 | |
| 502 | * i386-gen.c (cpu_flag_init): Move CpuSSE4a from |
| 503 | CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add |
| 504 | CPU_ANY_SSE4_FLAGS entry. |
| 505 | * i386-init.h: Re-generate. |
| 506 | |
| 507 | 2020-02-12 Jan Beulich <jbeulich@suse.com> |
| 508 | |
| 509 | * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form |
| 510 | with Unspecified, making the present one AT&T syntax only. |
| 511 | * i386-tbl.h: Re-generate. |
| 512 | |
| 513 | 2020-02-12 Jan Beulich <jbeulich@suse.com> |
| 514 | |
| 515 | * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants. |
| 516 | * i386-tbl.h: Re-generate. |
| 517 | |
| 518 | 2020-02-12 Jan Beulich <jbeulich@suse.com> |
| 519 | |
| 520 | PR gas/24546 |
| 521 | * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode. |
| 522 | * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into |
| 523 | Amd64 and Intel64 templates. |
| 524 | (call, jmp): Likewise for far indirect variants. Dro |
| 525 | Unspecified. |
| 526 | * i386-tbl.h: Re-generate. |
| 527 | |
| 528 | 2020-02-11 Jan Beulich <jbeulich@suse.com> |
| 529 | |
| 530 | * i386-gen.c (opcode_modifiers): Remove ShortForm entry. |
| 531 | * i386-opc.h (ShortForm): Delete. |
| 532 | (struct i386_opcode_modifier): Remove shortform field. |
| 533 | * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld, |
| 534 | fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub, |
| 535 | fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp, |
| 536 | ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq): |
| 537 | Drop ShortForm. |
| 538 | * i386-tbl.h: Re-generate. |
| 539 | |
| 540 | 2020-02-11 Jan Beulich <jbeulich@suse.com> |
| 541 | |
| 542 | * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip, |
| 543 | fucompi): Drop ShortForm from operand-less templates. |
| 544 | * i386-tbl.h: Re-generate. |
| 545 | |
| 546 | 2020-02-11 Alan Modra <amodra@gmail.com> |
| 547 | |
| 548 | * cgen-ibld.in (extract_normal): Set *valuep on all return paths. |
| 549 | * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c, |
| 550 | * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, |
| 551 | * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c, |
| 552 | * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate. |
| 553 | |
| 554 | 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> |
| 555 | |
| 556 | * arm-dis.c (print_insn_cde): Define 'V' parse character. |
| 557 | (cde_opcodes): Add VCX* instructions. |
| 558 | |
| 559 | 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> |
| 560 | Matthew Malcomson <matthew.malcomson@arm.com> |
| 561 | |
| 562 | * arm-dis.c (struct cdeopcode32): New. |
| 563 | (CDE_OPCODE): New macro. |
| 564 | (cde_opcodes): New disassembly table. |
| 565 | (regnames): New option to table. |
| 566 | (cde_coprocs): New global variable. |
| 567 | (print_insn_cde): New |
| 568 | (print_insn_thumb32): Use print_insn_cde. |
| 569 | (parse_arm_disassembler_options): Parse coprocN args. |
| 570 | |
| 571 | 2020-02-10 H.J. Lu <hongjiu.lu@intel.com> |
| 572 | |
| 573 | PR gas/25516 |
| 574 | * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64 |
| 575 | with ISA64. |
| 576 | * i386-opc.h (AMD64): Removed. |
| 577 | (Intel64): Likewose. |
| 578 | (AMD64): New. |
| 579 | (INTEL64): Likewise. |
| 580 | (INTEL64ONLY): Likewise. |
| 581 | (i386_opcode_modifier): Replace amd64 and intel64 with isa64. |
| 582 | * i386-opc.tbl (Amd64): New. |
| 583 | (Intel64): Likewise. |
| 584 | (Intel64Only): Likewise. |
| 585 | Replace AMD64 with Amd64. Update sysenter/sysenter with |
| 586 | Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter. |
| 587 | * i386-tbl.h: Regenerated. |
| 588 | |
| 589 | 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com> |
| 590 | |
| 591 | PR 25469 |
| 592 | * z80-dis.c: Add support for GBZ80 opcodes. |
| 593 | |
| 594 | 2020-02-04 Alan Modra <amodra@gmail.com> |
| 595 | |
| 596 | * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned. |
| 597 | |
| 598 | 2020-02-03 Alan Modra <amodra@gmail.com> |
| 599 | |
| 600 | * m32c-ibld.c: Regenerate. |
| 601 | |
| 602 | 2020-02-01 Alan Modra <amodra@gmail.com> |
| 603 | |
| 604 | * frv-ibld.c: Regenerate. |
| 605 | |
| 606 | 2020-01-31 Jan Beulich <jbeulich@suse.com> |
| 607 | |
| 608 | * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete. |
| 609 | (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label. |
| 610 | (OP_E_memory): Replace xmm_mdq_mode case label by |
| 611 | vex_scalar_w_dq_mode one. |
| 612 | * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar. |
| 613 | |
| 614 | 2020-01-31 Jan Beulich <jbeulich@suse.com> |
| 615 | |
| 616 | * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete. |
| 617 | (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode, |
| 618 | vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments. |
| 619 | (intel_operand_size): Drop vex_w_dq_mode case label. |
| 620 | |
| 621 | 2020-01-31 Richard Sandiford <richard.sandiford@arm.com> |
| 622 | |
| 623 | * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt. |
| 624 | Remove C_SCAN_MOVPRFX for SVE bfcvtnt. |
| 625 | |
| 626 | 2020-01-30 Alan Modra <amodra@gmail.com> |
| 627 | |
| 628 | * m32c-ibld.c: Regenerate. |
| 629 | |
| 630 | 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> |
| 631 | |
| 632 | * bpf-opc.c: Regenerate. |
| 633 | |
| 634 | 2020-01-30 Jan Beulich <jbeulich@suse.com> |
| 635 | |
| 636 | * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators. |
| 637 | (dis386): Use them to replace C2/C3 table entries. |
| 638 | (x86_64_table): Add X86_64_C2 and X86_64_C3 entries. |
| 639 | * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64 |
| 640 | ones. Use Size64 instead of DefaultSize on Intel64 ones. |
| 641 | * i386-tbl.h: Re-generate. |
| 642 | |
| 643 | 2020-01-30 Jan Beulich <jbeulich@suse.com> |
| 644 | |
| 645 | * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword |
| 646 | forms. |
| 647 | (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop |
| 648 | DefaultSize. |
| 649 | * i386-tbl.h: Re-generate. |
| 650 | |
| 651 | 2020-01-30 Alan Modra <amodra@gmail.com> |
| 652 | |
| 653 | * tic4x-dis.c (tic4x_dp): Make unsigned. |
| 654 | |
| 655 | 2020-01-27 H.J. Lu <hongjiu.lu@intel.com> |
| 656 | Jan Beulich <jbeulich@suse.com> |
| 657 | |
| 658 | PR binutils/25445 |
| 659 | * i386-dis.c (MOVSXD_Fixup): New function. |
| 660 | (movsxd_mode): New enum. |
| 661 | (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd. |
| 662 | (intel_operand_size): Handle movsxd_mode. |
| 663 | (OP_E_register): Likewise. |
| 664 | (OP_G): Likewise. |
| 665 | * i386-opc.tbl: Remove Rex64 and allow 32-bit destination |
| 666 | register on movsxd. Add movsxd with 16-bit destination register |
| 667 | for AMD64 and Intel64 ISAs. |
| 668 | * i386-tbl.h: Regenerated. |
| 669 | |
| 670 | 2020-01-27 Tamar Christina <tamar.christina@arm.com> |
| 671 | |
| 672 | PR 25403 |
| 673 | * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv. |
| 674 | * aarch64-asm-2.c: Regenerate |
| 675 | * aarch64-dis-2.c: Likewise. |
| 676 | * aarch64-opc-2.c: Likewise. |
| 677 | |
| 678 | 2020-01-21 Jan Beulich <jbeulich@suse.com> |
| 679 | |
| 680 | * i386-opc.tbl (sysret): Drop DefaultSize. |
| 681 | * i386-tbl.h: Re-generate. |
| 682 | |
| 683 | 2020-01-21 Jan Beulich <jbeulich@suse.com> |
| 684 | |
| 685 | * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and |
| 686 | Dword. |
| 687 | (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword. |
| 688 | * i386-tbl.h: Re-generate. |
| 689 | |
| 690 | 2020-01-20 Nick Clifton <nickc@redhat.com> |
| 691 | |
| 692 | * po/de.po: Updated German translation. |
| 693 | * po/pt_BR.po: Updated Brazilian Portuguese translation. |
| 694 | * po/uk.po: Updated Ukranian translation. |
| 695 | |
| 696 | 2020-01-20 Alan Modra <amodra@gmail.com> |
| 697 | |
| 698 | * hppa-dis.c (fput_const): Remove useless cast. |
| 699 | |
| 700 | 2020-01-20 Alan Modra <amodra@gmail.com> |
| 701 | |
| 702 | * arm-dis.c (print_insn_arm): Wrap 'T' value. |
| 703 | |
| 704 | 2020-01-18 Nick Clifton <nickc@redhat.com> |
| 705 | |
| 706 | * configure: Regenerate. |
| 707 | * po/opcodes.pot: Regenerate. |
| 708 | |
| 709 | 2020-01-18 Nick Clifton <nickc@redhat.com> |
| 710 | |
| 711 | Binutils 2.34 branch created. |
| 712 | |
| 713 | 2020-01-17 Christian Biesinger <cbiesinger@google.com> |
| 714 | |
| 715 | * opintl.h: Fix spelling error (seperate). |
| 716 | |
| 717 | 2020-01-17 H.J. Lu <hongjiu.lu@intel.com> |
| 718 | |
| 719 | * i386-opc.tbl: Add {vex} pseudo prefix. |
| 720 | * i386-tbl.h: Regenerated. |
| 721 | |
| 722 | 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 723 | |
| 724 | PR 25376 |
| 725 | * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. |
| 726 | (neon_opcodes): Likewise. |
| 727 | (select_arm_features): Make sure we enable MVE bits when selecting |
| 728 | armv8.1-m.main. Make sure we do not enable MVE bits when not selecting |
| 729 | any architecture. |
| 730 | |
| 731 | 2020-01-16 Jan Beulich <jbeulich@suse.com> |
| 732 | |
| 733 | * i386-opc.tbl: Drop stale comment from XOP section. |
| 734 | |
| 735 | 2020-01-16 Jan Beulich <jbeulich@suse.com> |
| 736 | |
| 737 | * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms. |
| 738 | (extractps): Add VexWIG to SSE2AVX forms. |
| 739 | * i386-tbl.h: Re-generate. |
| 740 | |
| 741 | 2020-01-16 Jan Beulich <jbeulich@suse.com> |
| 742 | |
| 743 | * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop |
| 744 | Size64 from and use VexW1 on SSE2AVX forms. |
| 745 | (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from |
| 746 | VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1. |
| 747 | * i386-tbl.h: Re-generate. |
| 748 | |
| 749 | 2020-01-15 Alan Modra <amodra@gmail.com> |
| 750 | |
| 751 | * tic4x-dis.c (tic4x_version): Make unsigned long. |
| 752 | (optab, optab_special, registernames): New file scope vars. |
| 753 | (tic4x_print_register): Set up registernames rather than |
| 754 | malloc'd registertable. |
| 755 | (tic4x_disassemble): Delete optable and optable_special. Use |
| 756 | optab and optab_special instead. Throw away old optab, |
| 757 | optab_special and registernames when info->mach changes. |
| 758 | |
| 759 | 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com> |
| 760 | |
| 761 | PR 25377 |
| 762 | * z80-dis.c (suffix): Use .db instruction to generate double |
| 763 | prefix. |
| 764 | |
| 765 | 2020-01-14 Alan Modra <amodra@gmail.com> |
| 766 | |
| 767 | * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short |
| 768 | values to unsigned before shifting. |
| 769 | |
| 770 | 2020-01-13 Thomas Troeger <tstroege@gmx.de> |
| 771 | |
| 772 | * arm-dis.c (print_insn_arm): Fill in insn info fields for control |
| 773 | flow instructions. |
| 774 | (print_insn_thumb16, print_insn_thumb32): Likewise. |
| 775 | (print_insn): Initialize the insn info. |
| 776 | * i386-dis.c (print_insn): Initialize the insn info fields, and |
| 777 | detect jumps. |
| 778 | |
| 779 | 2012-01-13 Claudiu Zissulescu <claziss@gmail.com> |
| 780 | |
| 781 | * arc-opc.c (C_NE): Make it required. |
| 782 | |
| 783 | 2012-01-13 Claudiu Zissulescu <claziss@gmail.com> |
| 784 | |
| 785 | * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo |
| 786 | reserved register name. |
| 787 | |
| 788 | 2020-01-13 Alan Modra <amodra@gmail.com> |
| 789 | |
| 790 | * ns32k-dis.c (Is_gen): Use strchr, add 'f'. |
| 791 | (print_insn_ns32k): Adjust ioffset for 'f' index_offset. |
| 792 | |
| 793 | 2020-01-13 Alan Modra <amodra@gmail.com> |
| 794 | |
| 795 | * wasm32-dis.c (print_insn_wasm32): Localise variables. Store |
| 796 | result of wasm_read_leb128 in a uint64_t and check that bits |
| 797 | are not lost when copying to other locals. Use uint32_t for |
| 798 | most locals. Use PRId64 when printing int64_t. |
| 799 | |
| 800 | 2020-01-13 Alan Modra <amodra@gmail.com> |
| 801 | |
| 802 | * score-dis.c: Formatting. |
| 803 | * score7-dis.c: Formatting. |
| 804 | |
| 805 | 2020-01-13 Alan Modra <amodra@gmail.com> |
| 806 | |
| 807 | * score-dis.c (print_insn_score48): Use unsigned variables for |
| 808 | unsigned values. Don't left shift negative values. |
| 809 | (print_insn_score32): Likewise. |
| 810 | * score7-dis.c (print_insn_score32, print_insn_score16): Likewise. |
| 811 | |
| 812 | 2020-01-13 Alan Modra <amodra@gmail.com> |
| 813 | |
| 814 | * tic4x-dis.c (tic4x_print_register): Remove dead code. |
| 815 | |
| 816 | 2020-01-13 Alan Modra <amodra@gmail.com> |
| 817 | |
| 818 | * fr30-ibld.c: Regenerate. |
| 819 | |
| 820 | 2020-01-13 Alan Modra <amodra@gmail.com> |
| 821 | |
| 822 | * xgate-dis.c (print_insn): Don't left shift signed value. |
| 823 | (ripBits): Formatting, use 1u. |
| 824 | |
| 825 | 2020-01-10 Alan Modra <amodra@gmail.com> |
| 826 | |
| 827 | * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned. |
| 828 | * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval. |
| 829 | |
| 830 | 2020-01-10 Alan Modra <amodra@gmail.com> |
| 831 | |
| 832 | * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG, |
| 833 | and XRREG value earlier to avoid a shift with negative exponent. |
| 834 | * m10200-dis.c (disassemble): Similarly. |
| 835 | |
| 836 | 2020-01-09 Nick Clifton <nickc@redhat.com> |
| 837 | |
| 838 | PR 25224 |
| 839 | * z80-dis.c (ld_ii_ii): Use correct cast. |
| 840 | |
| 841 | 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com> |
| 842 | |
| 843 | PR 25224 |
| 844 | * z80-dis.c (ld_ii_ii): Use character constant when checking |
| 845 | opcode byte value. |
| 846 | |
| 847 | 2020-01-09 Jan Beulich <jbeulich@suse.com> |
| 848 | |
| 849 | * i386-dis.c (SEP_Fixup): New. |
| 850 | (SEP): Define. |
| 851 | (dis386_twobyte): Use it for sysenter/sysexit. |
| 852 | (enum x86_64_isa): Change amd64 enumerator to value 1. |
| 853 | (OP_J): Compare isa64 against intel64 instead of amd64. |
| 854 | * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64 |
| 855 | forms. |
| 856 | * i386-tbl.h: Re-generate. |
| 857 | |
| 858 | 2020-01-08 Alan Modra <amodra@gmail.com> |
| 859 | |
| 860 | * z8k-dis.c: Include libiberty.h |
| 861 | (instr_data_s): Make max_fetched unsigned. |
| 862 | (z8k_lookup_instr): Make nibl_index and tabl_index unsigned. |
| 863 | Don't exceed byte_info bounds. |
| 864 | (output_instr): Make num_bytes unsigned. |
| 865 | (unpack_instr): Likewise for nibl_count and loop. |
| 866 | * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and |
| 867 | idx unsigned. |
| 868 | * z8k-opc.h: Regenerate. |
| 869 | |
| 870 | 2020-01-07 Shahab Vahedi <shahab@synopsys.com> |
| 871 | |
| 872 | * arc-tbl.h (llock): Use 'LLOCK' as class. |
| 873 | (llockd): Likewise. |
| 874 | (scond): Use 'SCOND' as class. |
| 875 | (scondd): Likewise. |
| 876 | (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit. |
| 877 | (scondd): Likewise. |
| 878 | |
| 879 | 2020-01-06 Alan Modra <amodra@gmail.com> |
| 880 | |
| 881 | * m32c-ibld.c: Regenerate. |
| 882 | |
| 883 | 2020-01-06 Alan Modra <amodra@gmail.com> |
| 884 | |
| 885 | PR 25344 |
| 886 | * z80-dis.c (suffix): Don't use a local struct buffer copy. |
| 887 | Peek at next byte to prevent recursion on repeated prefix bytes. |
| 888 | Ensure uninitialised "mybuf" is not accessed. |
| 889 | (print_insn_z80): Don't zero n_fetch and n_used here,.. |
| 890 | (print_insn_z80_buf): ..do it here instead. |
| 891 | |
| 892 | 2020-01-04 Alan Modra <amodra@gmail.com> |
| 893 | |
| 894 | * m32r-ibld.c: Regenerate. |
| 895 | |
| 896 | 2020-01-04 Alan Modra <amodra@gmail.com> |
| 897 | |
| 898 | * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value. |
| 899 | |
| 900 | 2020-01-04 Alan Modra <amodra@gmail.com> |
| 901 | |
| 902 | * crx-dis.c (match_opcode): Avoid shift left of signed value. |
| 903 | |
| 904 | 2020-01-04 Alan Modra <amodra@gmail.com> |
| 905 | |
| 906 | * d30v-dis.c (print_insn): Avoid signed overflow in left shift. |
| 907 | |
| 908 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
| 909 | |
| 910 | * aarch64-tbl.h (aarch64_opcode_table): Use |
| 911 | SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}. |
| 912 | |
| 913 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
| 914 | |
| 915 | * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD |
| 916 | forms of SUDOT and USDOT. |
| 917 | |
| 918 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
| 919 | |
| 920 | * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from |
| 921 | uzip{1,2}. |
| 922 | * opcodes/aarch64-dis-2.c: Re-generate. |
| 923 | |
| 924 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
| 925 | |
| 926 | * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit |
| 927 | FMMLA encoding. |
| 928 | * opcodes/aarch64-dis-2.c: Re-generate. |
| 929 | |
| 930 | 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com> |
| 931 | |
| 932 | * z80-dis.c: Add support for eZ80 and Z80 instructions. |
| 933 | |
| 934 | 2020-01-01 Alan Modra <amodra@gmail.com> |
| 935 | |
| 936 | Update year range in copyright notice of all files. |
| 937 | |
| 938 | For older changes see ChangeLog-2019 |
| 939 | \f |
| 940 | Copyright (C) 2020 Free Software Foundation, Inc. |
| 941 | |
| 942 | Copying and distribution of this file, with or without modification, |
| 943 | are permitted in any medium without royalty provided the copyright |
| 944 | notice and this notice are preserved. |
| 945 | |
| 946 | Local Variables: |
| 947 | mode: change-log |
| 948 | left-margin: 8 |
| 949 | fill-column: 74 |
| 950 | version-control: never |
| 951 | End: |