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12006-05-25 Richard Sandiford <richard@codesourcery.com>
2
3 * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
4 and fmovem entries. Put register list entries before immediate
5 mask entries. Use "l" rather than "L" in the fmovem entries.
6 * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
7 out from INFO.
8 (m68k_scan_mask): New function, split out from...
9 (print_insn_m68k): ...here. If no architecture has been set,
10 first try printing an m680x0 instruction, then try a Coldfire one.
11
122006-05-24 Nick Clifton <nickc@redhat.com>
13
14 * po/ga.po: Updated Irish translation.
15
162006-05-22 Nick Clifton <nickc@redhat.com>
17
18 * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
19
202006-05-22 Nick Clifton <nickc@redhat.com>
21
22 * po/nl.po: Updated translation.
23
242006-05-18 Alan Modra <amodra@bigpond.net.au>
25
26 * avr-dis.c: Formatting fix.
27
282006-05-14 Thiemo Seufer <ths@mips.com>
29
30 * mips16-opc.c (I1, I32, I64): New shortcut defines.
31 (mips16_opcodes): Change membership of instructions to their
32 lowest baseline ISA.
33
342006-05-09 H.J. Lu <hongjiu.lu@intel.com>
35
36 * i386-dis.c (grps): Update sgdt/sidt for 64bit.
37
382006-05-05 Julian Brown <julian@codesourcery.com>
39
40 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
41 vldm/vstm.
42
432006-05-05 Thiemo Seufer <ths@mips.com>
44 David Ung <davidu@mips.com>
45
46 * mips-opc.c: Add macro for cache instruction.
47
482006-05-04 Thiemo Seufer <ths@mips.com>
49 Nigel Stephens <nigel@mips.com>
50 David Ung <davidu@mips.com>
51
52 * mips-dis.c (mips_arch_choices): Add smartmips instruction
53 decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
54 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
55 MIPS64R2.
56 * mips-opc.c: fix random typos in comments.
57 (INSN_SMARTMIPS): New defines.
58 (mips_builtin_opcodes): Add paired single support for MIPS32R2.
59 Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
60 flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
61 FP_S and FP_D flags to denote single and double register
62 accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
63 Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
64 for MIPS32R2. Add SmartMIPS instructions. Add two-argument
65 variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
66 release 2 ISAs.
67 * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
68
692006-05-03 Thiemo Seufer <ths@mips.com>
70
71 * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
72
732006-05-02 Thiemo Seufer <ths@mips.com>
74 Nigel Stephens <nigel@mips.com>
75 David Ung <davidu@mips.com>
76
77 * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
78 (print_mips16_insn_arg): Force mips16 to odd addresses.
79
802006-04-30 Thiemo Seufer <ths@mips.com>
81 David Ung <davidu@mips.com>
82
83 * mips-opc.c (mips_builtin_opcodes): Add udi instructions
84 "udi0" to "udi15".
85 * mips-dis.c (print_insn_args): Adds udi argument handling.
86
872006-04-28 James E Wilson <wilson@specifix.com>
88
89 * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
90 error message.
91
922006-04-28 Thiemo Seufer <ths@mips.com>
93 David Ung <davidu@mips.com>
94 Nigel Stephens <nigel@mips.com>
95
96 * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
97 names.
98
992006-04-28 Thiemo Seufer <ths@mips.com>
100 Nigel Stephens <nigel@mips.com>
101 David Ung <davidu@mips.com>
102
103 * mips-dis.c (print_insn_args): Add mips_opcode argument.
104 (print_insn_mips): Adjust print_insn_args call.
105
1062006-04-28 Thiemo Seufer <ths@mips.com>
107 Nigel Stephens <nigel@mips.com>
108
109 * mips-dis.c (print_insn_args): Print $fcc only for FP
110 instructions, use $cc elsewise.
111
1122006-04-28 Thiemo Seufer <ths@mips.com>
113 Nigel Stephens <nigel@mips.com>
114
115 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
116 Map MIPS16 registers to O32 names.
117 (print_mips16_insn_arg): Use mips16_reg_names.
118
1192006-04-26 Julian Brown <julian@codesourcery.com>
120
121 * arm-dis.c (print_insn_neon): Disassemble floating-point constant
122 VMOV.
123
1242006-04-26 Nathan Sidwell <nathan@codesourcery.com>
125 Julian Brown <julian@codesourcery.com>
126
127 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
128 %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
129 Add unified load/store instruction names.
130 (neon_opcode_table): New.
131 (arm_opcodes): Expand meaning of %<bitfield>['`?].
132 (arm_decode_bitfield): New.
133 (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
134 Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
135 (print_insn_neon): New.
136 (print_insn_arm): Adjust print_insn_coprocessor call. Call
137 print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
138 (print_insn_thumb32): Likewise.
139
1402006-04-19 Alan Modra <amodra@bigpond.net.au>
141
142 * Makefile.am: Run "make dep-am".
143 * Makefile.in: Regenerate.
144
1452006-04-19 Alan Modra <amodra@bigpond.net.au>
146
147 * avr-dis.c (avr_operand): Warning fix.
148
149 * configure: Regenerate.
150
1512006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
152
153 * po/POTFILES.in: Regenerated.
154
1552006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
156
157 PR binutils/2454
158 * avr-dis.c (avr_operand): Arrange for a comment to appear before
159 the symolic form of an address, so that the output of objdump -d
160 can be reassembled.
161
1622006-04-10 DJ Delorie <dj@redhat.com>
163
164 * m32c-asm.c: Regenerate.
165
1662006-04-06 Carlos O'Donell <carlos@codesourcery.com>
167
168 * Makefile.am: Add install-html target.
169 * Makefile.in: Regenerate.
170
1712006-04-06 Nick Clifton <nickc@redhat.com>
172
173 * po/vi/po: Updated Vietnamese translation.
174
1752006-03-31 Paul Koning <ni1d@arrl.net>
176
177 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
178
1792006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
180
181 * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
182 logic to identify halfword shifts.
183
1842006-03-16 Paul Brook <paul@codesourcery.com>
185
186 * arm-dis.c (arm_opcodes): Rename swi to svc.
187 (thumb_opcodes): Ditto.
188
1892006-03-13 DJ Delorie <dj@redhat.com>
190
191 * m32c-asm.c: Regenerate.
192 * m32c-desc.c: Likewise.
193 * m32c-desc.h: Likewise.
194 * m32c-dis.c: Likewise.
195 * m32c-ibld.c: Likewise.
196 * m32c-opc.c: Likewise.
197 * m32c-opc.h: Likewise.
198
1992006-03-10 DJ Delorie <dj@redhat.com>
200
201 * m32c-desc.c: Regenerate with mul.l, mulu.l.
202 * m32c-opc.c: Likewise.
203 * m32c-opc.h: Likewise.
204
205
2062006-03-09 Nick Clifton <nickc@redhat.com>
207
208 * po/sv.po: Updated Swedish translation.
209
2102006-03-07 H.J. Lu <hongjiu.lu@intel.com>
211
212 PR binutils/2428
213 * i386-dis.c (REP_Fixup): New function.
214 (AL): Remove duplicate.
215 (Xbr): New.
216 (Xvr): Likewise.
217 (Ybr): Likewise.
218 (Yvr): Likewise.
219 (indirDXr): Likewise.
220 (ALr): Likewise.
221 (eAXr): Likewise.
222 (dis386): Updated entries of ins, outs, movs, lods and stos.
223
2242006-03-05 Nick Clifton <nickc@redhat.com>
225
226 * cgen-ibld.in (insert_normal): Cope with attempts to insert a
227 signed 32-bit value into an unsigned 32-bit field when the host is
228 a 64-bit machine.
229 * fr30-ibld.c: Regenerate.
230 * frv-ibld.c: Regenerate.
231 * ip2k-ibld.c: Regenerate.
232 * iq2000-asm.c: Regenerate.
233 * iq2000-ibld.c: Regenerate.
234 * m32c-ibld.c: Regenerate.
235 * m32r-ibld.c: Regenerate.
236 * openrisc-ibld.c: Regenerate.
237 * xc16x-ibld.c: Regenerate.
238 * xstormy16-ibld.c: Regenerate.
239
2402006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
241
242 * xc16x-asm.c: Regenerate.
243 * xc16x-dis.c: Regenerate.
244
2452006-02-27 Carlos O'Donell <carlos@codesourcery.com>
246
247 * po/Make-in: Add html target.
248
2492006-02-27 H.J. Lu <hongjiu.lu@intel.com>
250
251 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
252 Intel Merom New Instructions.
253 (THREE_BYTE_0): Likewise.
254 (THREE_BYTE_1): Likewise.
255 (three_byte_table): Likewise.
256 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
257 THREE_BYTE_1 for entry 0x3a.
258 (twobyte_has_modrm): Updated.
259 (twobyte_uses_SSE_prefix): Likewise.
260 (print_insn): Handle 3-byte opcodes used by Intel Merom New
261 Instructions.
262
2632006-02-24 David S. Miller <davem@sunset.davemloft.net>
264
265 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
266 (v9_hpriv_reg_names): New table.
267 (print_insn_sparc): Allow values up to 16 for '?' and '!'.
268 New cases '$' and '%' for read/write hyperprivileged register.
269 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
270 window handling and rdhpr/wrhpr instructions.
271
2722006-02-24 DJ Delorie <dj@redhat.com>
273
274 * m32c-desc.c: Regenerate with linker relaxation attributes.
275 * m32c-desc.h: Likewise.
276 * m32c-dis.c: Likewise.
277 * m32c-opc.c: Likewise.
278
2792006-02-24 Paul Brook <paul@codesourcery.com>
280
281 * arm-dis.c (arm_opcodes): Add V7 instructions.
282 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
283 (print_arm_address): New function.
284 (print_insn_arm): Use it. Add 'P' and 'U' cases.
285 (psr_name): New function.
286 (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
287
2882006-02-23 H.J. Lu <hongjiu.lu@intel.com>
289
290 * ia64-opc-i.c (bXc): New.
291 (mXc): Likewise.
292 (OpX2TaTbYaXcC): Likewise.
293 (TF). Likewise.
294 (TFCM). Likewise.
295 (ia64_opcodes_i): Add instructions for tf.
296
297 * ia64-opc.h (IMMU5b): New.
298
299 * ia64-asmtab.c: Regenerated.
300
3012006-02-23 H.J. Lu <hongjiu.lu@intel.com>
302
303 * ia64-gen.c: Update copyright years.
304 * ia64-opc-b.c: Likewise.
305
3062006-02-22 H.J. Lu <hongjiu.lu@intel.com>
307
308 * ia64-gen.c (lookup_regindex): Handle ".vm".
309 (print_dependency_table): Handle '\"'.
310
311 * ia64-ic.tbl: Updated from SDM 2.2.
312 * ia64-raw.tbl: Likewise.
313 * ia64-waw.tbl: Likewise.
314 * ia64-asmtab.c: Regenerated.
315
316 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
317
3182006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
319 Anil Paranjape <anilp1@kpitcummins.com>
320 Shilin Shakti <shilins@kpitcummins.com>
321
322 * xc16x-desc.h: New file
323 * xc16x-desc.c: New file
324 * xc16x-opc.h: New file
325 * xc16x-opc.c: New file
326 * xc16x-ibld.c: New file
327 * xc16x-asm.c: New file
328 * xc16x-dis.c: New file
329 * Makefile.am: Entries for xc16x
330 * Makefile.in: Regenerate
331 * cofigure.in: Add xc16x target information.
332 * configure: Regenerate.
333 * disassemble.c: Add xc16x target information.
334
3352006-02-11 H.J. Lu <hongjiu.lu@intel.com>
336
337 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
338 moves.
339
3402006-02-11 H.J. Lu <hongjiu.lu@intel.com>
341
342 * i386-dis.c ('Z'): Add a new macro.
343 (dis386_twobyte): Use "movZ" for control register moves.
344
3452006-02-10 Nick Clifton <nickc@redhat.com>
346
347 * iq2000-asm.c: Regenerate.
348
3492006-02-07 Nathan Sidwell <nathan@codesourcery.com>
350
351 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
352
3532006-01-26 David Ung <davidu@mips.com>
354
355 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
356 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
357 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
358 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
359 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
360
3612006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
362
363 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
364 ld_d_r, pref_xd_cb): Use signed char to hold data to be
365 disassembled.
366 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
367 buffer overflows when disassembling instructions like
368 ld (ix+123),0x23
369 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
370 operand, if the offset is negative.
371
3722006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
373
374 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
375 unsigned char to hold data to be disassembled.
376
3772006-01-17 Andreas Schwab <schwab@suse.de>
378
379 PR binutils/1486
380 * disassemble.c (disassemble_init_for_target): Set
381 disassembler_needs_relocs for bfd_arch_arm.
382
3832006-01-16 Paul Brook <paul@codesourcery.com>
384
385 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
386 f?add?, and f?sub? instructions.
387
3882006-01-16 Nick Clifton <nickc@redhat.com>
389
390 * po/zh_CN.po: New Chinese (simplified) translation.
391 * configure.in (ALL_LINGUAS): Add "zh_CH".
392 * configure: Regenerate.
393
3942006-01-05 Paul Brook <paul@codesourcery.com>
395
396 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
397
3982006-01-06 DJ Delorie <dj@redhat.com>
399
400 * m32c-desc.c: Regenerate.
401 * m32c-opc.c: Regenerate.
402 * m32c-opc.h: Regenerate.
403
4042006-01-03 DJ Delorie <dj@redhat.com>
405
406 * cgen-ibld.in (extract_normal): Avoid memory range errors.
407 * m32c-ibld.c: Regenerated.
408
409For older changes see ChangeLog-2005
410\f
411Local Variables:
412mode: change-log
413left-margin: 8
414fill-column: 74
415version-control: never
416End:
GDB Binutils - Deliverables
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