| | 1 | 2013-03-01 H.J. Lu <hongjiu.lu@intel.com> |
| | 2 | |
| | 3 | * i386-reg.tbl (riz): Add RegRex64. |
| | 4 | * i386-tbl.h: Regenerated. |
| | 5 | |
| | 6 | 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com> |
| | 7 | |
| | 8 | * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros. |
| | 9 | (aarch64_feature_crc): New static. |
| | 10 | (CRC): New macro. |
| | 11 | (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w, |
| | 12 | crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions. |
| | 13 | * aarch64-asm-2.c: Re-generate. |
| | 14 | * aarch64-dis-2.c: Ditto. |
| | 15 | * aarch64-opc-2.c: Ditto. |
| | 16 | |
| | 17 | 2013-02-27 Alan Modra <amodra@gmail.com> |
| | 18 | |
| | 19 | * rl78-decode.opc (rl78_decode_opcode): Fix typo. |
| | 20 | * rl78-decode.c: Regenerate. |
| | 21 | |
| | 22 | 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com> |
| | 23 | |
| | 24 | * rl78-decode.opc: Fix encoding of DIVWU insn. |
| | 25 | * rl78-decode.c: Regenerate. |
| | 26 | |
| | 27 | 2013-02-19 H.J. Lu <hongjiu.lu@intel.com> |
| | 28 | |
| | 29 | PR gas/15159 |
| | 30 | * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1. |
| | 31 | |
| | 32 | * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS. |
| | 33 | (cpu_flags): Add CpuSMAP. |
| | 34 | |
| | 35 | * i386-opc.h (CpuSMAP): New. |
| | 36 | (i386_cpu_flags): Add cpusmap. |
| | 37 | |
| | 38 | * i386-opc.tbl: Add clac and stac. |
| | 39 | |
| | 40 | * i386-init.h: Regenerated. |
| | 41 | * i386-tbl.h: Likewise. |
| | 42 | |
| | 43 | 2013-02-15 Markos Chandras <markos.chandras@imgtec.com> |
| | 44 | |
| | 45 | * metag-dis.c: Initialize outf->bytes_per_chunk to 4 |
| | 46 | which also makes the disassembler output be in little |
| | 47 | endian like it should be. |
| | 48 | |
| | 49 | 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com> |
| | 50 | |
| | 51 | * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name' |
| | 52 | fields to NULL. |
| | 53 | (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP. |
| | 54 | |
| | 55 | 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com> |
| | 56 | |
| | 57 | * mips-dis.c (is_compressed_mode_p): Only match symbols from the |
| | 58 | section disassembled. |
| | 59 | |
| | 60 | 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> |
| | 61 | |
| | 62 | * arm-dis.c: Update strht pattern. |
| | 63 | |
| | 64 | 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de> |
| | 65 | |
| | 66 | * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for |
| | 67 | single-float. Disable ll, lld, sc and scd for EE. Disable the |
| | 68 | trunc.w.s macro for EE. |
| | 69 | |
| | 70 | 2013-02-06 Sandra Loosemore <sandra@codesourcery.com> |
| | 71 | Andrew Jenner <andrew@codesourcery.com> |
| | 72 | |
| | 73 | Based on patches from Altera Corporation. |
| | 74 | |
| | 75 | * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and |
| | 76 | nios2-opc.c. |
| | 77 | * Makefile.in: Regenerated. |
| | 78 | * configure.in: Add case for bfd_nios2_arch. |
| | 79 | * configure: Regenerated. |
| | 80 | * disassemble.c (ARCH_nios2): Define. |
| | 81 | (disassembler): Add case for bfd_arch_nios2. |
| | 82 | * nios2-dis.c: New file. |
| | 83 | * nios2-opc.c: New file. |
| | 84 | |
| | 85 | 2013-02-04 Alan Modra <amodra@gmail.com> |
| | 86 | |
| | 87 | * po/POTFILES.in: Regenerate. |
| | 88 | * rl78-decode.c: Regenerate. |
| | 89 | * rx-decode.c: Regenerate. |
| | 90 | |
| | 91 | 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com> |
| | 92 | |
| | 93 | * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and |
| | 94 | ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2. |
| | 95 | * aarch64-asm.c (convert_xtl_to_shll): New function. |
| | 96 | (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by |
| | 97 | calling convert_xtl_to_shll. |
| | 98 | * aarch64-dis.c (convert_shll_to_xtl): New function. |
| | 99 | (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by |
| | 100 | calling convert_shll_to_xtl. |
| | 101 | * aarch64-gen.c: Update copyright year. |
| | 102 | * aarch64-asm-2.c: Re-generate. |
| | 103 | * aarch64-dis-2.c: Re-generate. |
| | 104 | * aarch64-opc-2.c: Re-generate. |
| | 105 | |
| | 106 | 2013-01-24 Nick Clifton <nickc@redhat.com> |
| | 107 | |
| | 108 | * v850-dis.c: Add support for e3v5 architecture. |
| | 109 | * v850-opc.c: Likewise. |
| | 110 | |
| | 111 | 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> |
| | 112 | |
| | 113 | * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI. |
| | 114 | * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise. |
| | 115 | * aarch64-opc.c (operand_general_constraint_met_p): For |
| | 116 | AARCH64_MOD_LSL, move the range check on the shift amount before the |
| | 117 | alignment check; change to call set_sft_amount_out_of_range_error |
| | 118 | instead of set_imm_out_of_range_error. |
| | 119 | * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL. |
| | 120 | (aarch64_opcode_table): Remove the OP enumerator from the asimdimm |
| | 121 | 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to |
| | 122 | SIMD_IMM_SFT. |
| | 123 | |
| | 124 | 2013-01-16 H.J. Lu <hongjiu.lu@intel.com> |
| | 125 | |
| | 126 | * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64. |
| | 127 | |
| | 128 | * i386-init.h: Regenerated. |
| | 129 | * i386-tbl.h: Likewise. |
| | 130 | |
| | 131 | 2013-01-15 Nick Clifton <nickc@redhat.com> |
| | 132 | |
| | 133 | * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE |
| | 134 | values. |
| | 135 | * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute. |
| | 136 | |
| | 137 | 2013-01-14 Will Newton <will.newton@imgtec.com> |
| | 138 | |
| | 139 | * metag-dis.c (REG_WIDTH): Increase to 64. |
| | 140 | |
| | 141 | 2013-01-10 Peter Bergner <bergner@vnet.ibm.com> |
| | 142 | |
| | 143 | * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries. |
| | 144 | * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK, |
| | 145 | XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines. |
| | 146 | (SH6): Update. |
| | 147 | <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.", |
| | 148 | "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.", |
| | 149 | "treclaim.", "tsr.">: Add POWER8 HTM opcodes. |
| | 150 | <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes. |
| | 151 | |
| | 152 | 2013-01-10 Will Newton <will.newton@imgtec.com> |
| | 153 | |
| | 154 | * Makefile.am: Add Meta. |
| | 155 | * configure.in: Add Meta. |
| | 156 | * disassemble.c: Add Meta support. |
| | 157 | * metag-dis.c: New file. |
| | 158 | * Makefile.in: Regenerate. |
| | 159 | * configure: Regenerate. |
| | 160 | |
| | 161 | 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com> |
| | 162 | |
| | 163 | * cr16-dis.c (make_instruction): Rename to cr16_make_instruction. |
| | 164 | (match_opcode): Rename to cr16_match_opcode. |
| | 165 | |
| | 166 | 2013-01-04 Juergen Urban <JuergenUrban@gmx.de> |
| | 167 | |
| | 168 | * mips-dis.c: Add names for CP0 registers of r5900. |
| | 169 | * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for |
| | 170 | instructions sq and lq. |
| | 171 | Add support for MIPS r5900 CPU. |
| | 172 | Add support for 128 bit MMI (Multimedia Instructions). |
| | 173 | Add support for EE instructions (Emotion Engine). |
| | 174 | Disable unsupported floating point instructions (64 bit and |
| | 175 | undefined compare operations). |
| | 176 | Enable instructions of MIPS ISA IV which are supported by r5900. |
| | 177 | Disable 64 bit co processor instructions. |
| | 178 | Disable 64 bit multiplication and division instructions. |
| | 179 | Disable instructions for co-processor 2 and 3, because these are |
| | 180 | not supported (preparation for later VU0 support (Vector Unit)). |
| | 181 | Disable cvt.w.s because this behaves like trunc.w.s and the |
| | 182 | correct execution can't be ensured on r5900. |
| | 183 | Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This |
| | 184 | will confuse less developers and compilers. |
| | 185 | |
| | 186 | 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com> |
| | 187 | |
| | 188 | * aarch64-opc.c (aarch64_print_operand): Change to print |
| | 189 | AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal |
| | 190 | in comment. |
| | 191 | * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag |
| | 192 | from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and |
| | 193 | OP_MOV_IMM_WIDE. |
| | 194 | |
| | 195 | 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com> |
| | 196 | |
| | 197 | * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP, |
| | 198 | PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM. |
| | 199 | |
| | 200 | 2013-01-02 H.J. Lu <hongjiu.lu@intel.com> |
| | 201 | |
| | 202 | * i386-gen.c (process_copyright): Update copyright year to 2013. |
| | 203 | |
| | 204 | 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com> |
| | 205 | |
| | 206 | * cr16-dis.c (match_opcode,make_instruction): Remove static |
| | 207 | declaration. |
| | 208 | (dwordU,wordU): Moved typedefs to opcode/cr16.h |
| | 209 | (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'. |
| | 210 | |
| | 211 | For older changes see ChangeLog-2012 |
| | 212 | \f |
| | 213 | Copyright (C) 2013 Free Software Foundation, Inc. |
| | 214 | |
| | 215 | Copying and distribution of this file, with or without modification, |
| | 216 | are permitted in any medium without royalty provided the copyright |
| | 217 | notice and this notice are preserved. |
| | 218 | |
| | 219 | Local Variables: |
| | 220 | mode: change-log |
| | 221 | left-margin: 8 |
| | 222 | fill-column: 74 |
| | 223 | version-control: never |
| | 224 | End: |
projects / deliverable / binutils-gdb.git / blame_incremental