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Add support for ARM's NOREAD section flag.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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CommitLineData
12015-12-14 Yoshinori Sato <ysato@users.sourceforge.jp>
2
3 * rx-deocde.opc: Add new instructions pattern.
4 * rx-deocde.c: Regenerate.
5 * rx-dis.c (register_name): Add new register.
6
72015-12-14 Matthew Wahab <matthew.wahab@arm.com>
8
9 * aarch64-asm-2.c: Regenerate.
10 * aarch64-dis-2.c: Regenerate.
11 * aarch64-opc-2.c: Regenerate.
12 * aarch64-tbl.h (QL_SSHIFT_H): New.
13 (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
14 and fcvtzu to the Adv.SIMD scalar shift by immediate group.
15
162015-12-14 Matthew Wahab <matthew.wahab@arm.com>
17
18 * aarch64-asm-2.c: Regenerate.
19 * aarch64-dis-2.c: Regenerate.
20 * aarch64-opc-2.c: Regenerate.
21 * aarch64-tbl.h (QL_VSHIFT_H): New.
22 (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
23 and fcvtzu to the Adv.SIMD shift by immediate group.
24
252015-12-14 Matthew Wahab <matthew.wahab@arm.com>
26
27 * aarch64-asm-2.c: Regenerate.
28 * aarch64-dis-2.c: Regenerate.
29 * aarch64-opc-2.c: Regenerate.
30 * aarch64-tbl.h (QL_SISD_PAIR_H): New.
31 (aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
32 fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.
33
342015-12-14 Matthew Wahab <matthew.wahab@arm.coM>
35
36 * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
37 and adjust calculation to ignore qualifier for type 2H.
38 * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".
39
402015-12-14 Matthew Wahab <matthew.wahab@arm.com>
41
42 * aarch64-asm-2.c: Regenerate.
43 * aarch64-dis-2.c: Regenerate.
44 * aarch64-opc-2.c: Regenerate.
45 * aarch64-tbl.h (QL_SIMD_IMM_H): New.
46 (aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
47 modified immediate group.
48
492015-12-14 Matthew Wahab <matthew.wahab@arm.com>
50
51 * aarch64-asm-2.c: Regenerate.
52 * aarch64-dis-2.c: Regenerate.
53 * aarch64-opc-2.c: Regenerate.
54 * aarch64-tbl.h (QL_XLANES_FP_H): New.
55 (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
56 fminnmv, fminv to the Adv.SIMD across lanes group.
57
582015-12-14 Matthew Wahab <matthew.wahab@arm.com>
59
60 * aarch64-asm-2.c: Regenerate.
61 * aarch64-dis-2.c: Regenerate.
62 * aarch64-opc-2.c: Regenerate.
63 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
64 fmls, fmul and fmulx to the scalar indexed element group.
65
662015-12-14 Matthew Wahab <matthew.wahab@arm.com>
67
68 * aarch64-asm-2.c: Regenerate.
69 * aarch64-dis-2.c: Regenerate.
70 * aarch64-opc-2.c: Regenerate.
71 * aarch64-tbl.h (QL_ELEMENT_FP_H): New.
72 (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
73 fmulx to the vector indexed element group.
74
752015-12-14 Matthew Wahab <matthew.wahab@arm.com>
76
77 * aarch64-asm-2.c: Regenerate.
78 * aarch64-dis-2.c: Regenerate.
79 * aarch64-opc-2.c: Regenerate.
80 * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
81 (QL_S_2SAMEH): New.
82 (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
83 fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
84 frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
85 fcvtzu and frsqrte to the scalar two register misc. group.
86
872015-12-14 Matthew Wahab <matthew.wahab@arm.com>
88
89 * aarch64-asm-2.c: Regenerate.
90 * aarch64-dis-2.c: Regenerate.
91 * aarch64-opc-2.c: Regenerate.
92 * aarch64-tbl.h (QL_V2SAMEH): New.
93 (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
94 fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
95 frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
96 fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
97 and fsqrt to the vector register misc. group.
98
992015-12-14 Matthew Wahab <matthew.wahab@arm.com>
100
101 * aarch64-asm-2.c: Regenerate.
102 * aarch64-dis-2.c: Regenerate.
103 * aarch64-opc-2.c: Regenerate.
104 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
105 fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
106 to the scalar three same group.
107
1082015-12-14 Matthew Wahab <matthew.wahab@arm.com>
109
110 * aarch64-asm-2.c: Regenerate.
111 * aarch64-dis-2.c: Regenerate.
112 * aarch64-opc-2.c: Regenerate.
113 * aarch64-tbl.h (QL_V3SAMEH): New.
114 (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
115 fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
116 fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
117 fcmgt, facgt and fminp to the vector three same group.
118
1192015-12-14 Matthew Wahab <matthew.wahab@arm.com>
120
121 * aarch64-tbl.h (aarch64_feature_simd_f16): New.
122 (SIMD_F16): New.
123
1242015-12-14 Matthew Wahab <matthew.wahab@arm.com>
125
126 * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
127 removed statement.
128 (aarch64_pstatefield_supported_p): Move feature checks for AT
129 registers ..
130 (aarch64_sys_ins_reg_supported_p): .. to here.
131
1322015-12-12 Alan Modra <amodra@gmail.com>
133
134 PR 19359
135 * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
136 (powerpc_opcodes): Remove single-operand mfcr.
137
1382015-12-11 Matthew Wahab <matthew.wahab@arm.com>
139
140 * aarch64-asm.c (aarch64_ins_hint): New.
141 * aarch64-asm.h (aarch64_ins_hint): Declare.
142 * aarch64-dis.c (aarch64_ext_hint): New.
143 * aarch64-dis.h (aarch64_ext_hint): Declare.
144 * aarch64-opc-2.c: Regenerate.
145 * aarch64-opc.c (aarch64_hint_options): New.
146 * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
147
1482015-12-11 Matthew Wahab <matthew.wahab@arm.com>
149
150 * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
151
1522015-12-11 Matthew Wahab <matthew.wahab@arm.com>
153
154 * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
155 pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
156 pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
157 pmscr_el2.
158 (aarch64_sys_reg_supported_p): Add architecture feature tests for
159 the new registers.
160
1612015-12-10 Matthew Wahab <matthew.wahab@arm.com>
162
163 * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
164 (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
165 feature test for "s1e1rp" and "s1e1wp".
166
1672015-12-10 Matthew Wahab <matthew.wahab@arm.com>
168
169 * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
170 (aarch64_sys_ins_reg_supported_p): New.
171
1722015-12-10 Matthew Wahab <matthew.wahab@arm.com>
173
174 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
175 with aarch64_sys_ins_reg_has_xt.
176 (aarch64_ext_sysins_op): Likewise.
177 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
178 (F_HASXT): New.
179 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
180 (aarch64_sys_regs_dc): Likewise.
181 (aarch64_sys_regs_at): Likewise.
182 (aarch64_sys_regs_tlbi): Likewise.
183 (aarch64_sys_ins_reg_has_xt): New.
184
1852015-12-10 Matthew Wahab <matthew.wahab@arm.com>
186
187 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
188 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
189 (aarch64_pstatefields): Add "uao".
190 (aarch64_pstatefield_supported_p): Add checks for "uao".
191
1922015-12-10 Matthew Wahab <matthew.wahab@arm.com>
193
194 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
195 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
196 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
197 (aarch64_sys_reg_supported_p): Add architecture feature tests for
198 new registers.
199
2002015-12-10 Matthew Wahab <matthew.wahab@arm.com>
201
202 * aarch64-asm-2.c: Regenerate.
203 * aarch64-dis-2.c: Regenerate.
204 * aarch64-tbl.h (aarch64_feature_ras): New.
205 (RAS): New.
206 (aarch64_opcode_table): Add "esb".
207
2082015-12-09 H.J. Lu <hongjiu.lu@intel.com>
209
210 * i386-dis.c (MOD_0F01_REG_5): New.
211 (RM_0F01_REG_5): Likewise.
212 (reg_table): Use MOD_0F01_REG_5.
213 (mod_table): Add MOD_0F01_REG_5.
214 (rm_table): Add RM_0F01_REG_5.
215 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
216 (cpu_flags): Add CpuOSPKE.
217 * i386-opc.h (CpuOSPKE): New.
218 (i386_cpu_flags): Add cpuospke.
219 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
220 * i386-init.h: Regenerated.
221 * i386-tbl.h: Likewise.
222
2232015-12-07 DJ Delorie <dj@redhat.com>
224
225 * rl78-decode.opc: Enable MULU for all ISAs.
226 * rl78-decode.c: Regenerate.
227
2282015-12-07 Alan Modra <amodra@gmail.com>
229
230 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
231 major opcode/xop.
232
2332015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
234
235 * arc-dis.c (special_flag_p): Match full mnemonic.
236 * arc-opc.c (print_insn_arc): Check section size to read
237 appropriate number of bytes. Fix printing.
238 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
239 arguments.
240
2412015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
242
243 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
244 <ldah>: ... to this.
245
2462015-11-27 Matthew Wahab <matthew.wahab@arm.com>
247
248 * aarch64-asm-2.c: Regenerate.
249 * aarch64-dis-2.c: Regenerate.
250 * aarch64-opc-2.c: Regenerate.
251 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
252 (QL_INT2FP_H, QL_FP2INT_H): New.
253 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
254 (QL_DST_H): New.
255 (QL_FCCMP_H): New.
256 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
257 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
258 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
259 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
260 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
261 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
262 fcsel.
263
2642015-11-27 Matthew Wahab <matthew.wahab@arm.com>
265
266 * aarch64-opc.c (half_conv_t): New.
267 (expand_fp_imm): Replace is_dp flag with the parameter size to
268 specify the number of bytes for the required expansion. Treat
269 a 16-bit expansion like a 32-bit expansion. Add check for an
270 unsupported size request. Update comment.
271 (aarch64_print_operand): Update to support 16-bit floating point
272 values. Update for changes to expand_fp_imm.
273
2742015-11-27 Matthew Wahab <matthew.wahab@arm.com>
275
276 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
277 (FP_F16): New.
278
2792015-11-27 Matthew Wahab <matthew.wahab@arm.com>
280
281 * aarch64-asm-2.c: Regenerate.
282 * aarch64-dis-2.c: Regenerate.
283 * aarch64-opc-2.c: Regenerate.
284 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
285 "rev64".
286
2872015-11-27 Matthew Wahab <matthew.wahab@arm.com>
288
289 * aarch64-asm-2.c: Regenerate.
290 * aarch64-asm.c (convert_bfc_to_bfm): New.
291 (convert_to_real): Add case for OP_BFC.
292 * aarch64-dis-2.c: Regenerate.
293 * aarch64-dis.c: (convert_bfm_to_bfc): New.
294 (convert_to_alias): Add case for OP_BFC.
295 * aarch64-opc-2.c: Regenerate.
296 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
297 to allow width operand in three-operand instructions.
298 * aarch64-tbl.h (QL_BF1): New.
299 (aarch64_feature_v8_2): New.
300 (ARMV8_2): New.
301 (aarch64_opcode_table): Add "bfc".
302
3032015-11-27 Matthew Wahab <matthew.wahab@arm.com>
304
305 * aarch64-asm-2.c: Regenerate.
306 * aarch64-dis-2.c: Regenerate.
307 * aarch64-dis.c: Weaken assert.
308 * aarch64-gen.c: Include the instruction in the list of its
309 possible aliases.
310
3112015-11-27 Matthew Wahab <matthew.wahab@arm.com>
312
313 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
314 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
315 feature test.
316
3172015-11-23 Tristan Gingold <gingold@adacore.com>
318
319 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
320
3212015-11-20 Matthew Wahab <matthew.wahab@arm.com>
322
323 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
324 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
325 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
326 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
327 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
328 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
329 cnthv_ctl_el2, cnthv_cval_el2.
330 (aarch64_sys_reg_supported_p): Update for the new system
331 registers.
332
3332015-11-20 Nick Clifton <nickc@redhat.com>
334
335 PR binutils/19224
336 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
337
3382015-11-20 Nick Clifton <nickc@redhat.com>
339
340 * po/zh_CN.po: Updated simplified Chinese translation.
341
3422015-11-19 Matthew Wahab <matthew.wahab@arm.com>
343
344 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
345 of MSR PAN immediate operand.
346
3472015-11-16 Nick Clifton <nickc@redhat.com>
348
349 * rx-dis.c (condition_names): Replace always and never with
350 invalid, since the always/never conditions can never be legal.
351
3522015-11-13 Tristan Gingold <gingold@adacore.com>
353
354 * configure: Regenerate.
355
3562015-11-11 Alan Modra <amodra@gmail.com>
357 Peter Bergner <bergner@vnet.ibm.com>
358
359 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
360 Add PPC_OPCODE_VSX3 to the vsx entry.
361 (powerpc_init_dialect): Set default dialect to power9.
362 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
363 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
364 extract_l1 insert_xtq6, extract_xtq6): New static functions.
365 (insert_esync): Test for illegal L operand value.
366 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
367 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
368 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
369 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
370 PPCVSX3): New defines.
371 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
372 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
373 <mcrxr>: Use XBFRARB_MASK.
374 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
375 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
376 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
377 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
378 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
379 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
380 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
381 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
382 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
383 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
384 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
385 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
386 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
387 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
388 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
389 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
390 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
391 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
392 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
393 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
394 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
395 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
396 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
397 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
398 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
399 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
400 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
401 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
402 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
403 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
404 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
405 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
406
4072015-11-02 Nick Clifton <nickc@redhat.com>
408
409 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
410 instructions.
411 * rx-decode.c: Regenerate.
412
4132015-11-02 Nick Clifton <nickc@redhat.com>
414
415 * rx-decode.opc (rx_disp): If the displacement is zero, set the
416 type to RX_Operand_Zero_Indirect.
417 * rx-decode.c: Regenerate.
418 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
419
4202015-10-28 Yao Qi <yao.qi@linaro.org>
421
422 * aarch64-dis.c (aarch64_decode_insn): Add one argument
423 noaliases_p. Update comments. Pass noaliases_p rather than
424 no_aliases to aarch64_opcode_decode.
425 (print_insn_aarch64_word): Pass no_aliases to
426 aarch64_decode_insn.
427
4282015-10-27 Vinay <Vinay.G@kpit.com>
429
430 PR binutils/19159
431 * rl78-decode.opc (MOV): Added offset to DE register in index
432 addressing mode.
433 * rl78-decode.c: Regenerate.
434
4352015-10-27 Vinay Kumar <vinay.g@kpit.com>
436
437 PR binutils/19158
438 * rl78-decode.opc: Add 's' print operator to instructions that
439 access system registers.
440 * rl78-decode.c: Regenerate.
441 * rl78-dis.c (print_insn_rl78_common): Decode all system
442 registers.
443
4442015-10-27 Vinay Kumar <vinay.g@kpit.com>
445
446 PR binutils/19157
447 * rl78-decode.opc: Add 'a' print operator to mov instructions
448 using stack pointer plus index addressing.
449 * rl78-decode.c: Regenerate.
450
4512015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
452
453 * s390-opc.c: Fix comment.
454 * s390-opc.txt: Change instruction type for troo, trot, trto, and
455 trtt to RRF_U0RER since the second parameter does not need to be a
456 register pair.
457
4582015-10-08 Nick Clifton <nickc@redhat.com>
459
460 * arc-dis.c (print_insn_arc): Initiallise insn array.
461
4622015-10-07 Yao Qi <yao.qi@linaro.org>
463
464 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
465 'name' rather than 'template'.
466 * aarch64-opc.c (aarch64_print_operand): Likewise.
467
4682015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
469
470 * arc-dis.c: Revamped file for ARC support
471 * arc-dis.h: Likewise.
472 * arc-ext.c: Likewise.
473 * arc-ext.h: Likewise.
474 * arc-opc.c: Likewise.
475 * arc-fxi.h: New file.
476 * arc-regs.h: Likewise.
477 * arc-tbl.h: Likewise.
478
4792015-10-02 Yao Qi <yao.qi@linaro.org>
480
481 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
482 argument insn type to aarch64_insn. Rename to ...
483 (aarch64_decode_insn): ... it.
484 (print_insn_aarch64_word): Caller updated.
485
4862015-10-02 Yao Qi <yao.qi@linaro.org>
487
488 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
489 (print_insn_aarch64_word): Caller updated.
490
4912015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
492
493 * s390-mkopc.c (main): Parse htm and vx flag.
494 * s390-opc.txt: Mark instructions from the hardware transactional
495 memory and vector facilities with the "htm"/"vx" flag.
496
4972015-09-28 Nick Clifton <nickc@redhat.com>
498
499 * po/de.po: Updated German translation.
500
5012015-09-28 Tom Rix <tom@bumblecow.com>
502
503 * ppc-opc.c (PPC500): Mark some opcodes as invalid
504
5052015-09-23 Nick Clifton <nickc@redhat.com>
506
507 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
508 function.
509 * tic30-dis.c (print_branch): Likewise.
510 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
511 value before left shifting.
512 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
513 * hppa-dis.c (print_insn_hppa): Likewise.
514 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
515 array.
516 * msp430-dis.c (msp430_singleoperand): Likewise.
517 (msp430_doubleoperand): Likewise.
518 (print_insn_msp430): Likewise.
519 * nds32-asm.c (parse_operand): Likewise.
520 * sh-opc.h (MASK): Likewise.
521 * v850-dis.c (get_operand_value): Likewise.
522
5232015-09-22 Nick Clifton <nickc@redhat.com>
524
525 * rx-decode.opc (bwl): Use RX_Bad_Size.
526 (sbwl): Likewise.
527 (ubwl): Likewise. Rename to ubw.
528 (uBWL): Rename to uBW.
529 Replace all references to uBWL with uBW.
530 * rx-decode.c: Regenerate.
531 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
532 (opsize_names): Likewise.
533 (print_insn_rx): Detect and report RX_Bad_Size.
534
5352015-09-22 Anton Blanchard <anton@samba.org>
536
537 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
538
5392015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
540
541 * sparc-dis.c (print_insn_sparc): Handle the privileged register
542 %pmcdper.
543
5442015-08-24 Jan Stancek <jstancek@redhat.com>
545
546 * i386-dis.c (print_insn): Fix decoding of three byte operands.
547
5482015-08-21 Alexander Fomin <alexander.fomin@intel.com>
549
550 PR binutils/18257
551 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
552 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
553 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
554 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
555 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
556 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
557 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
558 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
559 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
560 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
561 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
562 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
563 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
564 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
565 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
566 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
567 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
568 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
569 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
570 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
571 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
572 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
573 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
574 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
575 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
576 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
577 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
578 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
579 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
580 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
581 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
582 (vex_w_table): Replace terminals with MOD_TABLE entries for
583 most of mask instructions.
584
5852015-08-17 Alan Modra <amodra@gmail.com>
586
587 * cgen.sh: Trim trailing space from cgen output.
588 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
589 (print_dis_table): Likewise.
590 * opc2c.c (dump_lines): Likewise.
591 (orig_filename): Warning fix.
592 * ia64-asmtab.c: Regenerate.
593
5942015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
595
596 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
597 and higher with ARM instruction set will now mark the 26-bit
598 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
599 (arm_opcodes): Fix for unpredictable nop being recognized as a
600 teq.
601
6022015-08-12 Simon Dardis <simon.dardis@imgtec.com>
603
604 * micromips-opc.c (micromips_opcodes): Re-order table so that move
605 based on 'or' is first.
606 * mips-opc.c (mips_builtin_opcodes): Ditto.
607
6082015-08-11 Nick Clifton <nickc@redhat.com>
609
610 PR 18800
611 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
612 instruction.
613
6142015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
615
616 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
617
6182015-08-07 Amit Pawar <Amit.Pawar@amd.com>
619
620 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
621 * i386-init.h: Regenerated.
622
6232015-07-30 H.J. Lu <hongjiu.lu@intel.com>
624
625 PR binutils/13571
626 * i386-dis.c (MOD_0FC3): New.
627 (PREFIX_0FC3): Renamed to ...
628 (PREFIX_MOD_0_0FC3): This.
629 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
630 (prefix_table): Replace Ma with Ev on movntiS.
631 (mod_table): Add MOD_0FC3.
632
6332015-07-27 H.J. Lu <hongjiu.lu@intel.com>
634
635 * configure: Regenerated.
636
6372015-07-23 Alan Modra <amodra@gmail.com>
638
639 PR 18708
640 * i386-dis.c (get64): Avoid signed integer overflow.
641
6422015-07-22 Alexander Fomin <alexander.fomin@intel.com>
643
644 PR binutils/18631
645 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
646 "EXEvexHalfBcstXmmq" for the second operand.
647 (EVEX_W_0F79_P_2): Likewise.
648 (EVEX_W_0F7A_P_2): Likewise.
649 (EVEX_W_0F7B_P_2): Likewise.
650
6512015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
652
653 * arm-dis.c (print_insn_coprocessor): Added support for quarter
654 float bitfield format.
655 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
656 quarter float bitfield format.
657
6582015-07-14 H.J. Lu <hongjiu.lu@intel.com>
659
660 * configure: Regenerated.
661
6622015-07-03 Alan Modra <amodra@gmail.com>
663
664 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
665 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
666 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
667
6682015-07-01 Sandra Loosemore <sandra@codesourcery.com>
669 Cesar Philippidis <cesar@codesourcery.com>
670
671 * nios2-dis.c (nios2_extract_opcode): New.
672 (nios2_disassembler_state): New.
673 (nios2_find_opcode_hash): Use mach parameter to select correct
674 disassembler state.
675 (nios2_print_insn_arg): Extend to support new R2 argument letters
676 and formats.
677 (print_insn_nios2): Check for 16-bit instruction at end of memory.
678 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
679 (NIOS2_NUM_OPCODES): Rename to...
680 (NIOS2_NUM_R1_OPCODES): This.
681 (nios2_r2_opcodes): New.
682 (NIOS2_NUM_R2_OPCODES): New.
683 (nios2_num_r2_opcodes): New.
684 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
685 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
686 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
687 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
688 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
689
6902015-06-30 Amit Pawar <Amit.Pawar@amd.com>
691
692 * i386-dis.c (OP_Mwaitx): New.
693 (rm_table): Add monitorx/mwaitx.
694 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
695 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
696 (operand_type_init): Add CpuMWAITX.
697 * i386-opc.h (CpuMWAITX): New.
698 (i386_cpu_flags): Add cpumwaitx.
699 * i386-opc.tbl: Add monitorx and mwaitx.
700 * i386-init.h: Regenerated.
701 * i386-tbl.h: Likewise.
702
7032015-06-22 Peter Bergner <bergner@vnet.ibm.com>
704
705 * ppc-opc.c (insert_ls): Test for invalid LS operands.
706 (insert_esync): New function.
707 (LS, WC): Use insert_ls.
708 (ESYNC): Use insert_esync.
709
7102015-06-22 Nick Clifton <nickc@redhat.com>
711
712 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
713 requested region lies beyond it.
714 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
715 looking for 32-bit insns.
716 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
717 data.
718 * sh-dis.c (print_insn_sh): Likewise.
719 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
720 blocks of instructions.
721 * vax-dis.c (print_insn_vax): Check that the requested address
722 does not clash with the stop_vma.
723
7242015-06-19 Peter Bergner <bergner@vnet.ibm.com>
725
726 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
727 * ppc-opc.c (FXM4): Add non-zero optional value.
728 (TBR): Likewise.
729 (SXL): Likewise.
730 (insert_fxm): Handle new default operand value.
731 (extract_fxm): Likewise.
732 (insert_tbr): Likewise.
733 (extract_tbr): Likewise.
734
7352015-06-16 Matthew Wahab <matthew.wahab@arm.com>
736
737 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
738
7392015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
740
741 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
742
7432015-06-12 Peter Bergner <bergner@vnet.ibm.com>
744
745 * ppc-opc.c: Add comment accidentally removed by old commit.
746 (MTMSRD_L): Delete.
747
7482015-06-04 Peter Bergner <bergner@vnet.ibm.com>
749
750 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
751
7522015-06-04 Nick Clifton <nickc@redhat.com>
753
754 PR 18474
755 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
756
7572015-06-02 Matthew Wahab <matthew.wahab@arm.com>
758
759 * arm-dis.c (arm_opcodes): Add "setpan".
760 (thumb_opcodes): Add "setpan".
761
7622015-06-02 Matthew Wahab <matthew.wahab@arm.com>
763
764 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
765 macros.
766
7672015-06-02 Matthew Wahab <matthew.wahab@arm.com>
768
769 * aarch64-tbl.h (aarch64_feature_rdma): New.
770 (RDMA): New.
771 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
772 * aarch64-asm-2.c: Regenerate.
773 * aarch64-dis-2.c: Regenerate.
774 * aarch64-opc-2.c: Regenerate.
775
7762015-06-02 Matthew Wahab <matthew.wahab@arm.com>
777
778 * aarch64-tbl.h (aarch64_feature_lor): New.
779 (LOR): New.
780 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
781 "stllrb", "stllrh".
782 * aarch64-asm-2.c: Regenerate.
783 * aarch64-dis-2.c: Regenerate.
784 * aarch64-opc-2.c: Regenerate.
785
7862015-06-01 Matthew Wahab <matthew.wahab@arm.com>
787
788 * aarch64-opc.c (F_ARCHEXT): New.
789 (aarch64_sys_regs): Add "pan".
790 (aarch64_sys_reg_supported_p): New.
791 (aarch64_pstatefields): Add "pan".
792 (aarch64_pstatefield_supported_p): New.
793
7942015-06-01 Jan Beulich <jbeulich@suse.com>
795
796 * i386-tbl.h: Regenerate.
797
7982015-06-01 Jan Beulich <jbeulich@suse.com>
799
800 * i386-dis.c (print_insn): Swap rounding mode specifier and
801 general purpose register in Intel mode.
802
8032015-06-01 Jan Beulich <jbeulich@suse.com>
804
805 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
806 * i386-tbl.h: Regenerate.
807
8082015-05-18 H.J. Lu <hongjiu.lu@intel.com>
809
810 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
811 * i386-init.h: Regenerated.
812
8132015-05-15 H.J. Lu <hongjiu.lu@intel.com>
814
815 PR binutis/18386
816 * i386-dis.c: Add comments for '@'.
817 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
818 (enum x86_64_isa): New.
819 (isa64): Likewise.
820 (print_i386_disassembler_options): Add amd64 and intel64.
821 (print_insn): Handle amd64 and intel64.
822 (putop): Handle '@'.
823 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
824 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
825 * i386-opc.h (AMD64): New.
826 (CpuIntel64): Likewise.
827 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
828 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
829 Mark direct call/jmp without Disp16|Disp32 as Intel64.
830 * i386-init.h: Regenerated.
831 * i386-tbl.h: Likewise.
832
8332015-05-14 Peter Bergner <bergner@vnet.ibm.com>
834
835 * ppc-opc.c (IH) New define.
836 (powerpc_opcodes) <wait>: Do not enable for POWER7.
837 <tlbie>: Add RS operand for POWER7.
838 <slbia>: Add IH operand for POWER6.
839
8402015-05-11 H.J. Lu <hongjiu.lu@intel.com>
841
842 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
843 direct branch.
844 (jmp): Likewise.
845 * i386-tbl.h: Regenerated.
846
8472015-05-11 H.J. Lu <hongjiu.lu@intel.com>
848
849 * configure.ac: Support bfd_iamcu_arch.
850 * disassemble.c (disassembler): Support bfd_iamcu_arch.
851 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
852 CPU_IAMCU_COMPAT_FLAGS.
853 (cpu_flags): Add CpuIAMCU.
854 * i386-opc.h (CpuIAMCU): New.
855 (i386_cpu_flags): Add cpuiamcu.
856 * configure: Regenerated.
857 * i386-init.h: Likewise.
858 * i386-tbl.h: Likewise.
859
8602015-05-08 H.J. Lu <hongjiu.lu@intel.com>
861
862 PR binutis/18386
863 * i386-dis.c (X86_64_E8): New.
864 (X86_64_E9): Likewise.
865 Update comments on 'T', 'U', 'V'. Add comments for '^'.
866 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
867 (x86_64_table): Add X86_64_E8 and X86_64_E9.
868 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
869 (putop): Handle '^'.
870 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
871 REX_W.
872
8732015-04-30 DJ Delorie <dj@redhat.com>
874
875 * disassemble.c (disassembler): Choose suitable disassembler based
876 on E_ABI.
877 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
878 it to decode mul/div insns.
879 * rl78-decode.c: Regenerate.
880 * rl78-dis.c (print_insn_rl78): Rename to...
881 (print_insn_rl78_common): ...this, take ISA parameter.
882 (print_insn_rl78): New.
883 (print_insn_rl78_g10): New.
884 (print_insn_rl78_g13): New.
885 (print_insn_rl78_g14): New.
886 (rl78_get_disassembler): New.
887
8882015-04-29 Nick Clifton <nickc@redhat.com>
889
890 * po/fr.po: Updated French translation.
891
8922015-04-27 Peter Bergner <bergner@vnet.ibm.com>
893
894 * ppc-opc.c (DCBT_EO): New define.
895 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
896 <lharx>: Likewise.
897 <stbcx.>: Likewise.
898 <sthcx.>: Likewise.
899 <waitrsv>: Do not enable for POWER7 and later.
900 <waitimpl>: Likewise.
901 <dcbt>: Default to the two operand form of the instruction for all
902 "old" cpus. For "new" cpus, use the operand ordering that matches
903 whether the cpu is server or embedded.
904 <dcbtst>: Likewise.
905
9062015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
907
908 * s390-opc.c: New instruction type VV0UU2.
909 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
910 and WFC.
911
9122015-04-23 Jan Beulich <jbeulich@suse.com>
913
914 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
915 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
916 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
917 (vfpclasspd, vfpclassps): Add %XZ.
918
9192015-04-15 H.J. Lu <hongjiu.lu@intel.com>
920
921 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
922 (PREFIX_UD_REPZ): Likewise.
923 (PREFIX_UD_REPNZ): Likewise.
924 (PREFIX_UD_DATA): Likewise.
925 (PREFIX_UD_ADDR): Likewise.
926 (PREFIX_UD_LOCK): Likewise.
927
9282015-04-15 H.J. Lu <hongjiu.lu@intel.com>
929
930 * i386-dis.c (prefix_requirement): Removed.
931 (print_insn): Don't set prefix_requirement. Check
932 dp->prefix_requirement instead of prefix_requirement.
933
9342015-04-15 H.J. Lu <hongjiu.lu@intel.com>
935
936 PR binutils/17898
937 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
938 (PREFIX_MOD_0_0FC7_REG_6): This.
939 (PREFIX_MOD_3_0FC7_REG_6): New.
940 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
941 (prefix_table): Replace PREFIX_0FC7_REG_6 with
942 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
943 PREFIX_MOD_3_0FC7_REG_7.
944 (mod_table): Replace PREFIX_0FC7_REG_6 with
945 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
946 PREFIX_MOD_3_0FC7_REG_7.
947
9482015-04-15 H.J. Lu <hongjiu.lu@intel.com>
949
950 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
951 (PREFIX_MANDATORY_REPNZ): Likewise.
952 (PREFIX_MANDATORY_DATA): Likewise.
953 (PREFIX_MANDATORY_ADDR): Likewise.
954 (PREFIX_MANDATORY_LOCK): Likewise.
955 (PREFIX_MANDATORY): Likewise.
956 (PREFIX_UD_SHIFT): Set to 8
957 (PREFIX_UD_REPZ): Updated.
958 (PREFIX_UD_REPNZ): Likewise.
959 (PREFIX_UD_DATA): Likewise.
960 (PREFIX_UD_ADDR): Likewise.
961 (PREFIX_UD_LOCK): Likewise.
962 (PREFIX_IGNORED_SHIFT): New.
963 (PREFIX_IGNORED_REPZ): Likewise.
964 (PREFIX_IGNORED_REPNZ): Likewise.
965 (PREFIX_IGNORED_DATA): Likewise.
966 (PREFIX_IGNORED_ADDR): Likewise.
967 (PREFIX_IGNORED_LOCK): Likewise.
968 (PREFIX_OPCODE): Likewise.
969 (PREFIX_IGNORED): Likewise.
970 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
971 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
972 (three_byte_table): Likewise.
973 (mod_table): Likewise.
974 (mandatory_prefix): Renamed to ...
975 (prefix_requirement): This.
976 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
977 Update PREFIX_90 entry.
978 (get_valid_dis386): Check prefix_requirement to see if a prefix
979 should be ignored.
980 (print_insn): Replace mandatory_prefix with prefix_requirement.
981
9822015-04-15 Renlin Li <renlin.li@arm.com>
983
984 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
985 use it for ssat and ssat16.
986 (print_insn_thumb32): Add handle case for 'D' control code.
987
9882015-04-06 Ilya Tocar <ilya.tocar@intel.com>
989 H.J. Lu <hongjiu.lu@intel.com>
990
991 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
992 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
993 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
994 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
995 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
996 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
997 Fill prefix_requirement field.
998 (struct dis386): Add prefix_requirement field.
999 (dis386): Fill prefix_requirement field.
1000 (dis386_twobyte): Ditto.
1001 (twobyte_has_mandatory_prefix_: Remove.
1002 (reg_table): Fill prefix_requirement field.
1003 (prefix_table): Ditto.
1004 (x86_64_table): Ditto.
1005 (three_byte_table): Ditto.
1006 (xop_table): Ditto.
1007 (vex_table): Ditto.
1008 (vex_len_table): Ditto.
1009 (vex_w_table): Ditto.
1010 (mod_table): Ditto.
1011 (bad_opcode): Ditto.
1012 (print_insn): Use prefix_requirement.
1013 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
1014 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
1015 (float_reg): Ditto.
1016
10172015-03-30 Mike Frysinger <vapier@gentoo.org>
1018
1019 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
1020
10212015-03-29 H.J. Lu <hongjiu.lu@intel.com>
1022
1023 * Makefile.in: Regenerated.
1024
10252015-03-25 Anton Blanchard <anton@samba.org>
1026
1027 * ppc-dis.c (disassemble_init_powerpc): Only initialise
1028 powerpc_opcd_indices and vle_opcd_indices once.
1029
10302015-03-25 Anton Blanchard <anton@samba.org>
1031
1032 * ppc-opc.c (powerpc_opcodes): Add slbfee.
1033
10342015-03-24 Terry Guo <terry.guo@arm.com>
1035
1036 * arm-dis.c (opcode32): Updated to use new arm feature struct.
1037 (opcode16): Likewise.
1038 (coprocessor_opcodes): Replace bit with feature struct.
1039 (neon_opcodes): Likewise.
1040 (arm_opcodes): Likewise.
1041 (thumb_opcodes): Likewise.
1042 (thumb32_opcodes): Likewise.
1043 (print_insn_coprocessor): Likewise.
1044 (print_insn_arm): Likewise.
1045 (select_arm_features): Follow new feature struct.
1046
10472015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
1048
1049 * i386-dis.c (rm_table): Add clzero.
1050 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
1051 Add CPU_CLZERO_FLAGS.
1052 (cpu_flags): Add CpuCLZERO.
1053 * i386-opc.h: Add CpuCLZERO.
1054 * i386-opc.tbl: Add clzero.
1055 * i386-init.h: Re-generated.
1056 * i386-tbl.h: Re-generated.
1057
10582015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
1059
1060 * mips-opc.c (decode_mips_operand): Fix constraint issues
1061 with u and y operands.
1062
10632015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
1064
1065 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
1066
10672015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1068
1069 * s390-opc.c: Add new IBM z13 instructions.
1070 * s390-opc.txt: Likewise.
1071
10722015-03-10 Renlin Li <renlin.li@arm.com>
1073
1074 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
1075 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
1076 related alias.
1077 * aarch64-asm-2.c: Regenerate.
1078 * aarch64-dis-2.c: Likewise.
1079 * aarch64-opc-2.c: Likewise.
1080
10812015-03-03 Jiong Wang <jiong.wang@arm.com>
1082
1083 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
1084
10852015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
1086
1087 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
1088 arch_sh_up.
1089 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
1090 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
1091
10922015-02-23 Vinay <Vinay.G@kpit.com>
1093
1094 * rl78-decode.opc (MOV): Added space between two operands for
1095 'mov' instruction in index addressing mode.
1096 * rl78-decode.c: Regenerate.
1097
10982015-02-19 Pedro Alves <palves@redhat.com>
1099
1100 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
1101
11022015-02-10 Pedro Alves <palves@redhat.com>
1103 Tom Tromey <tromey@redhat.com>
1104
1105 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
1106 microblaze_and, microblaze_xor.
1107 * microblaze-opc.h (opcodes): Adjust.
1108
11092015-01-28 James Bowman <james.bowman@ftdichip.com>
1110
1111 * Makefile.am: Add FT32 files.
1112 * configure.ac: Handle FT32.
1113 * disassemble.c (disassembler): Call print_insn_ft32.
1114 * ft32-dis.c: New file.
1115 * ft32-opc.c: New file.
1116 * Makefile.in: Regenerate.
1117 * configure: Regenerate.
1118 * po/POTFILES.in: Regenerate.
1119
11202015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1121
1122 * nds32-asm.c (keyword_sr): Add new system registers.
1123
11242015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1125
1126 * s390-dis.c (s390_extract_operand): Support vector register
1127 operands.
1128 (s390_print_insn_with_opcode): Support new operands types and add
1129 new handling of optional operands.
1130 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1131 and include opcode/s390.h instead.
1132 (struct op_struct): New field `flags'.
1133 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1134 (dumpTable): Dump flags.
1135 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
1136 string.
1137 * s390-opc.c: Add new operands types, instruction formats, and
1138 instruction masks.
1139 (s390_opformats): Add new formats for .insn.
1140 * s390-opc.txt: Add new instructions.
1141
11422015-01-01 Alan Modra <amodra@gmail.com>
1143
1144 Update year range in copyright notice of all files.
1145
1146For older changes see ChangeLog-2014
1147\f
1148Copyright (C) 2015 Free Software Foundation, Inc.
1149
1150Copying and distribution of this file, with or without modification,
1151are permitted in any medium without royalty provided the copyright
1152notice and this notice are preserved.
1153
1154Local Variables:
1155mode: change-log
1156left-margin: 8
1157fill-column: 74
1158version-control: never
1159End:
GDB Binutils - Deliverables
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